Method of increasing process window for flash memory device ild fill
By forming arc-shaped sidewalls on the outside of the floating gate and control gate, the problem of voids during the ILD filling process of flash memory devices is solved, resulting in better filling effect and device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2022-09-23
- Publication Date
- 2026-06-02
AI Technical Summary
In floating-gate flash memory devices, as the process node shrinks, the size of the memory cell decreases, leading to a smaller spacing between control gates. This makes it difficult for the ILD to fill, easily forming voids and affecting device performance.
By forming arc-shaped sidewalls on the outside of the floating gate and control gate, and using etching and cleaning processes of oxide and nitride layers, the ILD filling process window is increased, resulting in a smooth memory cell morphology.
It effectively avoids the formation of voids during the ILD filling process, improves the filling effect of flash memory devices, and reduces leakage and erasure problems.
Smart Images
Figure CN115528036B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and in particular to a method for increasing the ILD fill process window of flash memory devices. Background Technology
[0002] In the manufacturing process of floating-gate flash memory devices, as the process node advances, the size of the memory cell shrinks accordingly. This reduction in cell size leads to a decrease in the spacing between control gates, resulting in a less smooth cell profile. Under these circumstances, complete filling of the ILD (interlayer dielectric layer) within the cell trench becomes extremely difficult, leading to voids (such as…) during the ILD filling process. Figure 1 (As shown). If a void occurs, there is a greater possibility of leakage between the selected and unselected word lines, which can also lead to erase problems. Summary of the Invention
[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for increasing the ILD filling process window of flash memory devices, in order to solve the problem of void defects generated in the ILD filling process of existing flash memory devices.
[0004] To achieve the above and other related objectives, the present invention provides a method for increasing the ILD fill process window of a flash memory device, the method comprising:
[0005] A semiconductor structure is provided, including a semiconductor substrate, a gate dielectric layer, word line polysilicon, a floating gate, and a control gate, wherein the gate dielectric layer is formed on the surface of the semiconductor substrate, the floating gate is formed on the surface of the gate dielectric layer and located on both sides of the word line polysilicon, and an intermediate dielectric layer, the control gate, and word line sidewalls are sequentially disposed above the floating gate.
[0006] An oxide layer is formed on the surface of the semiconductor structure, and a nitride layer is formed on the surface of the oxide layer;
[0007] The nitride layer and the oxide layer are etched by an etching process to form a first sidewall on the outside of the floating gate, the control gate, the intermediate dielectric layer and the word line sidewall;
[0008] The semiconductor structure on which the first sidewall is formed is cleaned using a first wet cleaning process;
[0009] Ion implantation is performed on the semiconductor substrate to form source and drain regions on both sides of the first sidewall;
[0010] The semiconductor structure having the source region and the drain region is cleaned using a second wet cleaning process.
[0011] Optionally, the thickness of the oxide layer ranges from [value missing].
[0012] Optionally, the thickness of the nitrided layer ranges from [value missing].
[0013] Optionally, both the first wet cleaning process and the second wet cleaning process use a mixture of HF solution, SPM solution and SC1 solution.
[0014] Optionally, the SPM solution is a mixture of concentrated sulfuric acid and hydrogen peroxide, and the ratio of concentrated sulfuric acid to hydrogen peroxide is 6:1 to 4:1.
[0015] Optionally, the SC1 solution is a mixture of ammonium hydroxide, hydrogen peroxide, and water.
[0016] Optionally, the semiconductor structure further includes a tunneling oxide layer formed between the word line polysilicon and the semiconductor substrate, the floating gate, the intermediate dielectric layer, the control gate, and the word line sidewalls.
[0017] Optionally, the semiconductor structure further includes a second sidewall formed on the outside of the tunneling oxide layer.
[0018] As described above, the method of increasing the ILD filling process window of the flash memory device of the present invention forms an arc-shaped sidewall on the outside of the control gate and the floating gate by utilizing oxide and nitride layers, making the morphology of the memory cell smoother, thereby increasing the ILD filling process window and avoiding the formation of voids in the flash memory device during the HDP (high-density plasma) filling process. Attached Figure Description
[0019] Figure 1 The image shown is a scanning electron microscope image of the voids created by ILD using existing methods.
[0020] Figure 2 The diagram shows a method for increasing the ILD filling process window of a flash memory device according to the present invention.
[0021] Figure 3 The diagram shown is a cross-sectional view of the semiconductor structure of the present invention.
[0022] Figure 4 The diagram shown is a cross-sectional view of the semiconductor structure after an oxide layer and a nitride layer are formed on the surface of the semiconductor structure according to the present invention.
[0023] Figure 5 The diagram shows a cross-sectional view of the semiconductor structure of the present invention after the formation of the first sidewall and the two cleaning processes.
[0024] Figure 6The image shown is a scanning electron microscope (SEM) image of the cross-sectional structure of the oxide and nitride layers after etching to form the first sidewall, as described in this invention.
[0025] Figure 7 The image shown is a scanning electron microscope (SEM) image of the semiconductor structure of the present invention after the formation of the first sidewall and the two cleaning processes.
[0026] Explanation of icon numbers
[0027] 100: Semiconductor structure; 101: Semiconductor substrate; 102: Gate dielectric layer; 103: Word line polysilicon; 104: Floating gate; 105: Control gate; 106: Intermediate dielectric layer; 107: Word line sidewall; 108: Tunneling oxide layer; 109: Second sidewall; 109a: Silicon oxide layer; 109b: Silicon nitride layer; 200: Oxide layer; 300: Nitride layer; 401: Source region; 402: Drain region Detailed Implementation
[0028] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0029] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0030] like Figure 2 As shown, this embodiment provides a method for increasing the ILD fill process window of a flash memory device, the method comprising:
[0031] A semiconductor structure 100 is provided, including a semiconductor substrate 101, a gate dielectric layer 102, a word line polysilicon 103, a floating gate 104, and a control gate 105. The gate dielectric layer 102 is formed on the surface of the semiconductor substrate 101, the floating gate 104 is formed on the surface of the gate dielectric layer 102 and located on both sides of the word line polysilicon 103, and an intermediate dielectric layer 106, the control gate 105, and a word line sidewall 107 are sequentially disposed above the floating gate 104.
[0032] An oxide layer 200 is formed on the surface of the semiconductor structure 100, and a nitride layer 300 is formed on the surface of the oxide layer 200;
[0033] The nitride layer 300 and the oxide layer 200 are etched by an etching process to form a first sidewall on the outside of the floating gate 104, the control gate 105, the intermediate dielectric layer 106 and the word line sidewall 107.
[0034] The semiconductor structure 100 on which the first sidewall is formed is cleaned using a first wet cleaning process;
[0035] Ion implantation is performed on the semiconductor substrate 101 to form a source region 401 and a drain region 402 on both sides of the first sidewall;
[0036] The semiconductor structure 100, on which the source region 401 and the drain region 402 are formed, is cleaned using a second wet cleaning process.
[0037] like Figure 3 As shown, in this embodiment, the sidewalls of the floating gate 104, the control gate 105, the intermediate dielectric layer 106, and the word line sidewall 107 on the side away from the word line polysilicon 107 have a certain angle α with the horizontal plane, and the angle α is greater than 90° and less than 120°. This method makes the morphology of the formed first sidewall smoother. In this embodiment, the intermediate dielectric layer 106 includes stacked silicon oxide layers, silicon nitride layers, and silicon oxide layers. The material of the word line sidewall 107 includes silicon oxide.
[0038] Specifically, the semiconductor structure 100 further includes a tunneling oxide layer 108 formed between the word line polysilicon 103 and the semiconductor substrate 101, the floating gate 104, the intermediate dielectric layer 106, the control gate 105, and the word line sidewall 107. In this embodiment, the tunneling oxide layer 108 is made of silicon oxide.
[0039] Specifically, the semiconductor structure 100 further includes a second sidewall 109 formed on the outside of the tunneling oxide layer 108.
[0040] In this embodiment, the second sidewall 109 includes a silicon oxide layer 109a and a silicon nitride layer 109b, wherein the silicon nitride layer 109b is formed between the tunneling oxide layer 108 and the silicon oxide layer 109a.
[0041] Specifically, the thickness of the oxide layer 200 ranges from [value missing]. Optionally, in this embodiment, the thickness of the oxide layer is Furthermore, the oxide layer 200 is made of silicon oxide.
[0042] Specifically, the thickness of the nitride layer 300 ranges from [value missing]. Optionally, in this embodiment, the thickness of the nitride layer is Furthermore, the nitride layer 300 is made of silicon nitride.
[0043] Specifically, both the first wet cleaning process and the second wet cleaning process use a mixture of HF solution, SPM solution and SC1 solution.
[0044] In this embodiment, when the semiconductor structure 100 with the first sidewall is cleaned using a mixture of HF solution, SPM solution and SC1 solution, the nitride layer 400 will not be etched away. Therefore, the first sidewall can be made to have an "arc" shape, which is beneficial for ILD HDP filling.
[0045] As an example, the SPM solution is a mixture of concentrated sulfuric acid and hydrogen peroxide, and the ratio of concentrated sulfuric acid to hydrogen peroxide is 6:1 to 4:1. In this embodiment, the SPM solution has a strong ability to remove organic matter.
[0046] As an example, SC1 solution is a mixture of ammonium hydroxide, hydrogen peroxide, and water. In this embodiment, the ratio of ammonium hydroxide, hydrogen peroxide, and water is 1:1.5:50, which can be used to remove heavy metals or precious metals.
[0047] In summary, the method for increasing the ILD filling process window of the flash memory device of the present invention, by utilizing oxide and nitride layers to form arc-shaped sidewalls on the outer side of the control gate and the floating gate, makes the morphology of the memory cell smoother, thereby increasing the ILD filling process window and avoiding the formation of voids in the flash memory device during HDP (high-density plasma) filling. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0048] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for increasing the ILD fill process window of a flash memory device, characterized in that, The method includes: A semiconductor structure is provided, including a semiconductor substrate, a gate dielectric layer, word line polysilicon, a floating gate, and a control gate, wherein the gate dielectric layer is formed on the surface of the semiconductor substrate, the floating gate is formed on the surface of the gate dielectric layer and located on both sides of the word line polysilicon, and an intermediate dielectric layer, the control gate, and word line sidewalls are sequentially disposed above the floating gate. An oxide layer is formed on the surface of the semiconductor structure, and a nitride layer is formed on the surface of the oxide layer; The nitride layer and the oxide layer are etched by an etching process to form an arc-shaped first sidewall on the outside of the floating gate, the control gate, the intermediate dielectric layer and the word line sidewall, thereby increasing the window for subsequent ILD filling processes. The semiconductor structure on which the first sidewall is formed is cleaned using a first wet cleaning process; Ion implantation is performed on the semiconductor substrate to form source and drain regions on both sides of the first sidewall; The semiconductor structure having the source region and the drain region is cleaned using a second wet cleaning process. Both the first and second wet cleaning processes use a mixture of HF solution, SPM solution and SCI solution. When the cleaning is performed using the mixture, the nitride layer is not etched, so that the first sidewall remains arc-shaped.
2. The method for increasing the ILD filling process window of a flash memory device according to claim 1, characterized in that, The thickness of the oxide layer ranges from 70 Å to 130 Å.
3. The method for increasing the ILD filling process window of a flash memory device according to claim 1, characterized in that, The thickness of the nitrided layer ranges from 300 Å to 500 Å.
4. The method for increasing the ILD filling process window of a flash memory device according to claim 1, characterized in that, The SPM solution is a mixture of concentrated sulfuric acid and hydrogen peroxide, and the ratio of concentrated sulfuric acid to hydrogen peroxide is 6:1 to 4:
1.
5. The method for increasing the ILD filling process window of a flash memory device according to claim 1, characterized in that, The SC1 solution is a mixture of ammonium hydroxide, hydrogen peroxide, and water.
6. The method for increasing the ILD filling process window of a flash memory device according to claim 1, characterized in that, The semiconductor structure further includes a tunneling oxide layer formed between the word line polysilicon and the semiconductor substrate, the floating gate, the intermediate dielectric layer, the control gate, and the word line sidewalls.
7. The method for increasing the ILD filling process window of a flash memory device according to claim 6, characterized in that, The semiconductor structure also includes a second sidewall formed on the outside of the tunneling oxide layer.