Gate dielectric for nanoscale transistors and methods of forming the same

Abstract

The present disclosure relates to gate dielectrics for nanostructure transistors and methods of forming the same. One method includes forming a plurality of semiconductor nanostructures including a lower semiconductor nanostructure and an uppermost semiconductor nanostructure positioned above the lower semiconductor nanostructure; forming an interface layer in contact with the plurality of semiconductor nanostructures; and depositing a high-k dielectric layer surrounding the interface layer. An uppermost high-k dielectric layer of the high-k dielectric layer surrounding the uppermost semiconductor nanostructure includes an uppermost horizontal portion overlying an uppermost horizontal portion of the uppermost semiconductor nanostructure, a lower horizontal portion underlied by the uppermost semiconductor nanostructure, and a sidewall portion positioned on sidewalls of the uppermost semiconductor nanostructure. A first one of the uppermost horizontal portion, the lower horizontal portion, and the sidewall portion has a first thickness. A second one of the uppermost horizontal portion, the lower horizontal portion, and the sidewall portion has a second thickness less than the first thickness.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to the gate dielectric of nanostructured transistors and methods for forming the same. Background Technology

[0002] Technological advancements in integrated circuit (IC) materials and design have resulted in generation after generation of ICs, each with smaller and more complex circuitry than its predecessors. Throughout IC development, functional density (e.g., the number of interconnect devices per chip area) has typically increased, while geometric dimensions have decreased. This shrinking process generally provides benefits by increasing manufacturing efficiency and reducing associated costs.

[0003] This shrinkage also increases the complexity of handling and manufacturing ICs, and achieving these advancements requires similar developments in IC handling and manufacturing. For example, gate-all-around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods for manufacturing GAA transistors are under development. Summary of the Invention

[0004] According to one aspect of this disclosure, a method is provided, comprising: forming a first plurality of semiconductor nanostructures, the first plurality of semiconductor nanostructures including: a first lower semiconductor nanostructure; and a first topmost semiconductor nanostructure located above the first lower semiconductor nanostructure; forming an interface layer on the first plurality of semiconductor nanostructures; and depositing a first high-k dielectric layer surrounding the interface layer, wherein the first topmost high-k dielectric layer surrounding the first topmost semiconductor nanostructure includes: a first topmost horizontal portion superimposed on the first topmost semiconductor nanostructure; a first bottom horizontal portion superimposed on the first topmost semiconductor nanostructure; and a first sidewall portion located on a sidewall of the first topmost semiconductor nanostructure, wherein a first portion selected from the first topmost horizontal portion, the first bottom horizontal portion, and the first sidewall portion has a first thickness, and a second portion selected from the first topmost horizontal portion, the first bottom horizontal portion, and the first sidewall portion has a second thickness different from the first thickness.

[0005] According to another aspect of this disclosure, a method is provided, comprising: forming a first plurality of semiconductor nanostructures including a first top semiconductor nanostructure; forming a second plurality of semiconductor nanostructures including a second top semiconductor nanostructure; depositing a first high-k dielectric layer surrounding the first top semiconductor nanostructure, wherein the first high-k dielectric layer is deposited using first process conditions; and depositing a second high-k dielectric layer surrounding the second top semiconductor nanostructure, wherein the second high-k dielectric layer is deposited using a second process condition different from the first process conditions, and wherein the first high-k dielectric layer comprises the same high-k dielectric material as the second high-k dielectric layer; forming a first gate electrode surrounding the first high-k dielectric layer; and forming a second gate electrode surrounding the second high-k dielectric layer, wherein the first gate electrode and the second gate electrode are formed using a common process.

[0006] According to another aspect of this disclosure, a structure is provided, comprising: a first plurality of semiconductor nanostructures, including: a first lower semiconductor nanostructure; and a first topmost semiconductor nanostructure located above the first lower semiconductor nanostructure; an interface layer surrounding the first topmost semiconductor nanostructure; and a first high-k dielectric layer surrounding the interface layer, wherein the first high-k dielectric layer includes: a first upper horizontal portion stacked on the first topmost semiconductor nanostructure and having a first thickness; a first bottom horizontal portion stacked on the first topmost semiconductor nanostructure and having a second thickness different from the first thickness; and a first sidewall portion located on the sidewall of the first topmost semiconductor nanostructure. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figures 1 to 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figures 12 to 28 , Figure 29A , Figure 29B , Figure 29C , Figure 30A and Figure 30BA view showing an intermediate stage in the formation of a nanostructured transistor according to some embodiments is shown.

[0009] Figures 31 to 33 The effect of adjusted gate dielectric layer thickness on the performance of nanostructured transistors according to some embodiments is illustrated.

[0010] Figure 34 A process flow for forming nanostructured transistors according to some embodiments is shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, this document uses spatially relevant terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature shown in the figure and another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those depicted in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein will be interpreted accordingly.

[0013] Nanostructured transistors (also known as nanosheet transistors or gate-all-around (GAA) transistors) and methods for their fabrication are provided. According to some embodiments, a gate dielectric is formed on a semiconductor nanostructure, which acts as the channel region of the transistor. The gate dielectric includes an interface layer and a high-k dielectric layer situated above the interface layer. Different process conditions are used to adjust the thickness of the high-k dielectric layer in portions above, below, at corners, and on the sidewalls of the nanosheet. By adjusting the thickness of the gate dielectric layer, the reliability and performance of the nanostructured transistor can be tuned and balanced based on requirements.

[0014] The embodiments discussed herein are intended to provide examples to enable the implementation or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Although the method embodiments may be discussed in a particular order of execution, other method embodiments may be executed in any logical order.

[0015] Figures 1 to 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figures 12 to 28 , Figure 29A , Figure 29B , Figure 29C , Figure 30A and Figure 30B A cross-sectional view is shown of an intermediate stage in the formation of a nanostructured transistor according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in… Figure 34 The process flow shown is as follows.

[0016] refer to Figure 1 The diagram shows a perspective view of wafer 10. Wafer 10 includes a multilayer structure comprising a multilayer stack 22 on a substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, etc., or other substrates and / or structures may be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium-on-insulator, etc. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments, substrate 20 may be doped as an n-type semiconductor substrate.

[0017] According to some embodiments, the multilayer stack 22 is formed via a series of deposition processes for depositing alternating materials. The corresponding processes are as follows: Figure 34 The process flow 200 is shown as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0018] According to some embodiments, the first semiconductor material of the first layer 22A is formed from or includes the following: SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is performed by epitaxial growth, and the corresponding deposition method may include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed as approximately... With the agreement The first thickness is within the range between [specific thicknesses]. However, any suitable thickness can be used, also within the range of the embodiments.

[0019] Once the first layer 22A has been deposited on the substrate 20, a second layer 22B is deposited on top of the first layer 22A. According to some embodiments, the second layer 22B is formed of or comprises a second semiconductor material (e.g., Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, etc.), wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon-germanium, the second layer 22B can be formed of silicon, and vice versa. It is understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0020] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, for example, the second layer 22A has a thickness in the range of about 4 nm to 7 nm, while the second layer 22B has a thickness in the range of about 8 nm to 12 nm.

[0021] Once the second layer 22B has been formed on top of the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the topmost layer required to form the multilayer stack 22 is formed. According to some embodiments, the thicknesses of the first layers 22A and the second layers 22B are the same or similar to each other. The thickness of the first layer 22A may also be the same as or different from the thickness of the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is a sacrificial layer and is removed in a subsequent process.

[0022] According to some embodiments, a number of pad oxide layers and hard mask layers (not shown) may be formed on the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0023] refer to Figure 2 A portion of the multilayer stack 22 and the underlying substrate 20 are patterned in one or more etching processes to form trenches 23. The corresponding processes are as follows: Figure 34 The process flow 200 shown is illustrated as process 204. Trench 23 extends into substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as multilayer stack 22'. Below multilayer stack 22', a portion of substrate 20 is retained and is hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layers 22A and 22B. Semiconductor layer 22A is hereinafter alternatively referred to as sacrificial layer, and semiconductor layer 22B is hereinafter alternatively referred to as nanostructure. The portion of multilayer stack 22' and the underlying substrate strip 20' is collectively referred to as semiconductor strip 24.

[0024] In the above embodiments, the GAA transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0025] Figure 3 The formation of isolation region 26 is shown; isolation region 26 is also referred to throughout the specification as a shallow trench isolation (STI) region. The corresponding process is as follows: Figure 34The process flow 200 is shown as process 206. STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermally oxidizing the surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer, formed, for example, using ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, etc. STI region 26 may also include a dielectric material situated on the liner oxide, wherein the dielectric material may be formed using flow chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, may then be performed to planarize the top surface of the dielectric material, and the remaining portion of the dielectric material constitutes STI region 26.

[0026] Then, the STI region 26 is recessed such that the top portion of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26, forming a protruding fin 28. The protruding fin 28 includes the top portion of the multilayer stack 22' and the substrate strip 20'. The recess of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. In the etching process, plasma can be generated. Argon gas can also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 26 is performed by a wet etching process. Etching chemicals can include, for example, HF.

[0027] refer to Figure 4 A dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 located on top of the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing surface portions of the protruding fins 28 to form an oxide layer, or by depositing a dielectric layer (e.g., a silicon oxide layer). The dummy gate electrode 34 may be formed using, for example, polycrystalline silicon or amorphous silicon, and may also use other materials (e.g., amorphous carbon).

[0028] Each dummy gate stack 30 may further include one or more hard mask layers 36 located above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon carbonoxynitride, or multiple layers thereof. The dummy gate stack 30 may span one or more protruding fins 28 and the STI region 26 between the protruding fins 28. The length direction of the dummy gate stack 30 is also perpendicular to the length direction of the protruding fins 28. The formation of the dummy gate stack 30 includes: forming a dummy gate dielectric layer; depositing a dummy gate electrode layer on the dummy gate dielectric layer; depositing one or more hard mask layers; and then patterning the formed layers by one or more patterning processes.

[0029] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of dielectric materials such as silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon carbonitride oxynitride (SiOCN), and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The formation process of the gate spacers 38 may include: depositing one or more dielectric layers, and then performing one or more anisotropic etching processes on the dielectric layers(one or more). The remaining portion of the dielectric layers(one or more) constitutes the gate spacers 38.

[0030] Figure 5A and Figure 5B It shows Figure 4 A cross-sectional view of the structure shown. Figure 5A It shows Figure 4 The reference cross section A1-A1 in the figure passes through the portion of the protruding fin 28 not covered by the dummy gate stack 30 and the gate spacer 38, and is parallel to the gate length direction. Figure 5B It shows Figure 4 The reference cross section BB is parallel to the length direction of the protruding fin 28.

[0031] refer to Figure 6A and Figure 6B The protruding fin 28 is made visible through an etching process. Figure 4 The portion of the gate not directly beneath the dummy gate stack 30 and gate spacer 38 is recessed to form a groove 42. The corresponding process is as follows: Figure 34The process flow 200 is shown as process 210. For example, dry etching can be performed using a mixture of C2F6, CF4, SO2, HBr, Cl2 and O2, or a mixture of HBr, Cl2, O2 and CH2F2, to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or may be lower (e.g., Figure 6B (As shown) The bottom of the multilayer semiconductor stack 22'. The etching can be anisotropic, such that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown. Figure 6B As shown.

[0032] refer to Figure 7A and Figure 7B The sacrificial semiconductor layer 22A is recessed laterally to form a lateral groove 41, which is recessed from the edges of the corresponding upper and lower nanostructures 22B. The corresponding process is as follows: Figure 34 The process flow 200 shown is illustrated as process 212.

[0033] Laterally recessing the sacrificial semiconductor layer 22A can be achieved using a wet etching process. This wet etching process uses an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon-germanium (SiGe)) than for the materials of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon-germanium and the nanostructure 22B is formed of silicon, an etchant such as hydrochloric acid (HCl) can be used to perform the wet etching process. The wet etching process can be performed using immersion processes, spraying processes, spin coating processes, etc.

[0034] According to an alternative embodiment, the sacrificial semiconductor layer 22A is recessed laterally by an isotropic dry etching process or a combination of dry etching and wet etching processes.

[0035] refer to Figure 8A and Figure 8B This forms the internal spacer 44. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 214. According to some embodiments, the formation of the internal spacer 44 includes depositing a conformal dielectric layer that extends to the lateral groove 41. Figure 7B Next, an etching process (also known as a spacer trimming process) is performed to trim the portion of the spacer layer outside the transverse groove 41, retaining the portion of the spacer layer within the transverse groove 41. The remaining portion of the spacer layer is referred to as the inner spacer 44. The inner spacer 44 may be a single-layer spacer or may include multiple sub-layers (e.g., two to three sub-layers).

[0036] refer to Figure 9A and 9B An epitaxial source / drain region 48 is formed in the groove 42. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 216. According to some embodiments, the source / drain region 48 can apply stress to the nanostructure 22B that serves as the channel for the corresponding GAA transistor, thereby improving performance. Depending on whether the resulting transistor is a p-type or n-type transistor, p-type or n-type impurities can be doped in situ during epitaxy. For example, when the resulting transistor is a p-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), etc., can be grown. Conversely, when the resulting transistor is an n-type transistor, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc., can be grown. After the groove 42 is filled with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to extend in the horizontal direction and can form a small facet. Further growth of the epitaxial region 48 may also cause adjacent epitaxial regions 48 to merge with each other. Alternatively, when the formation of the epitaxial region 48 is complete, the epitaxial regions 48 grown from different substrate strips 20' are separated from each other.

[0037] refer to Figure 10A and Figure 10B This forms a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 218. CESL 50 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 52 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 can be formed from an oxygen-containing dielectric material, which can be silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0038] CESL 50 and ILD 52 are planarized using a planarization process (e.g., CMP or mechanical polishing). According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, such as... Figure 10A As shown. According to an alternative embodiment, the planarization process may expose the hard mask 36 and stop on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the ILD 52 are flush within the process variation.

[0039] Next, the dummy gate electrode 34 and dummy gate dielectric 32 (and hard mask 36, if remaining) are removed in one or more etching processes to form a recess 58, as shown. Figure 11A and Figure 11B As shown. The corresponding process is as follows: Figure 34 The process flow 200 shown is illustrated as process 220.

[0040] The sacrificial layer 22A is then removed to extend the grooves 58 between the nanostructures 22B. The corresponding process is as follows: Figure 34 The process flow 200 shown is illustrated as process 220. The sacrificial layer 22A can be removed by performing an isotropic etching process (e.g., a wet etching process using an etchant that is selective for the material of the sacrificial layer 22A), while the nanostructure 22B, the substrate 20, and the STI region 26 remain relatively unetched compared to the sacrificial layer 22A.

[0041] Figures 12 to 26 A view is shown in the formation of a gate dielectric 68 according to some embodiments, the gate dielectric 68 including an interface layer 64 surrounding a nanostructure 22B and a high-k dielectric layer 66 located above the interface layer 64. Figure 12 The diagram shows portions of wafer 10 in different device regions. The structures shown in the different device regions are... Figure 11A The structure obtained from region 59 is basically the same.

[0042] The aforementioned process can be used to fabricate various nanostructured transistors, which can meet different reliability and performance requirements. In the subsequent discussion, four device regions are shown, each used to fabricate a nanostructured transistor. For example, Figure 12 Device regions 60A, 60B, 60C, and 60D are shown, and the structures shown are formed using the process discussed in the preceding figures. Each of device regions 60A, 60B, 60C, and 60D can be either a p-type transistor region (where p-type transistors will be formed) or an n-type transistor region (where n-type transistors will be formed) in any combination.

[0043] Throughout this specification, the portion of the gate dielectric (and the corresponding high-k dielectric layer) that covers and lies on the top surface of the nanostructure is referred to as the top (or upper) portion of the gate dielectric (and the high-k dielectric layer). The portion of the gate dielectric (and the corresponding high-k dielectric layer) that lies below and contacts the bottom surface of the nanostructure is referred to as the lower (or bottom) portion of the gate dielectric (and the high-k dielectric layer). The top (or upper) portion of the gate dielectric that lies above the topmost nanostructure 22B is referred to as the topmost portion of the gate dielectric. Similarly, corner portions and sidewall portions of the gate dielectric and the high-k dielectric layer can be implemented.

[0044] Device region 60A is a device region in which the high-k dielectric portion covering the topmost nanostructure 22B is formed to be thicker than other portions. Device region 60B is a device region in which the high-k dielectric portion covering the topmost nanostructure 22B is formed to be thinner than other portions. Device region 60C is a device region in which the thickness of the corner portions and sidewall portions is increased, wherein the sidewall portions are formed to be thicker than the corresponding top and bottom portions. Device region 60D is a device region in which the inner portions (the top portion facing upwards and the bottom portion facing downwards of the nanostructure 22B) are formed to be thinner than the topmost portion and may also be thinner than the sidewall portions.

[0045] like Figure 12 As shown, an interface layer (IL) 64 is formed and may include silicon oxide. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 222. The forming process may include an oxidation process. The oxidation process can be performed using oxygen, for example, by generating plasma from an oxygen-containing gas. The oxidation process may also include a chemical oxidation process. According to some embodiments, the thicknesses of the top, bottom, and sidewall portions of the IL 64 may be equal to or close to each other, for example, with a difference of less than about 20 percent or 10 percent.

[0046] Figures 13 to 26 The formation of high-k dielectric layers 66A, 66B, 66C, and 66D in device regions 60A, 60B, 60C, and 60D are illustrated, respectively. High-k dielectric layers 66A, 66B, 66C, and 66D are individually or collectively referred to as high-k dielectric layer 66. According to some embodiments, high-k dielectric layer 66 may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, combinations thereof, and / or multiple layers thereof.

[0047] The high-k dielectric layer 66 is deposited by a deposition process such as ALD or CVD. These deposition processes are generally considered to be conformal deposition processes. However, according to some embodiments of this disclosure, the process conditions can be adjusted to change the thickness of some portions (top portions (top / upper horizontal portions), bottom portions (bottom / lower horizontal portions), sidewall portions (vertical portions), and corner portions) to be greater than or less than the thickness of other portions.

[0048] Although high-k dielectric layers 66A, 66B, 66C, and 66D can be formed in different processes, the materials of high-k dielectric layers 66A, 66B, 66C, and 66D can be the same or can be different from each other in any combination. In the following discussion, the formation of HfO2 is discussed as an example of the material of high-k dielectric layer 66, but high-k dielectric layer 66 can also be formed from or include other types of high-k dielectric materials. Corresponding available precursors can also be realized.

[0049] Figures 13 to 16 , Figures 17 to 19 , Figures 20 to 22 ,as well as Figures 23 to 26 The formation of high-k dielectric layers 66 with different thickness profiles according to various embodiments is illustrated. Although the illustrated process flow shows the formation of four different thickness profiles in the same wafer and the same device die, the nanostructure transistors formed in one wafer and device die can be selected in any combination of single thickness profiles, two thickness profiles, three thickness profiles (instead of all shown thickness profiles), or four thickness profiles. Furthermore, when more than one thickness profile is used, the order in which the different thickness profiles are formed can be any available order different from the order shown.

[0050] Figures 13 to 16 A process for forming a high-k dielectric layer 66A in a device region 60A according to some embodiments is shown, wherein the thickness of the top portion of the high-k dielectric layer 66A above the topmost nanostructure 22B is greater than the thickness of the rest of the high-k dielectric layer 66A (including the bottom portion below, the top portion (below the topmost nanostructure 22B), and the sidewall portion).

[0051] According to some embodiments, the formation of the high-k dielectric layer 66A, including HfO2, employs tetra(ethylmethylamino)hafnium (TEMAH) as a hafnium precursor. H2O, O2, and / or O3 can be used as oxidants.

[0052] refer to Figure 13 This forms a hard mask 70A. The corresponding process is as follows: Figure 34The process flow 200 is shown as process 224. The hard mask 70A may include metal oxides, metal nitrides, metal oxynitrides, metal nitrides, metal oxycarbides, etc. The metal in the hard mask 70A may include Al, Zr, Ti, La, etc., or combinations thereof, and other metals may also be used. Metal-free materials may also be used to form the hard mask 70A.

[0053] According to some embodiments, the hard mask 70A can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.) to fill the gaps between the nanostructures 22B. The hard mask 70A is deposited in device regions 60A, 60B, 60C, and 60D.

[0054] Then, an etching mask 74A is formed on top of the hard mask 70A in device regions 60A, 60B, 60C, and 60D. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 226. The etching mask 74A may include a photoresist. The etching mask 74A is patterned and removed from device region 60A, and includes portions retained in device regions 60B, 60C, and 60D.

[0055] Then, etching process 72A is performed to remove a portion of the hard mask 70A within device region 60A, thereby exposing the corresponding portion of IL 64. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 228. After etching process 72A, the etching mask 74A is removed. The resulting structure is as follows. Figure 14 As shown.

[0056] refer to Figure 15 A high-k dielectric layer of 66A was deposited. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 230. According to some embodiments, the process conditions are adjusted such that the thickness T1A of the topmost portion of the high-k dielectric layer 66A above the topmost nanostructure 22B is greater than the thicknesses T1'A and T2'A of the bottom portion of the high-k dielectric layer 66A and the thickness T3A of the sidewall portion of the high-k dielectric layer 66A. Thickness T1A is also greater than the thickness T2A of the top portion of the high-k dielectric layer 66A below the topmost nanostructure 22B. For example, the thickness difference (T1A - T1'A) can be approximately... Within the range of approximately 2A. The ratio T1A / T1'A is greater than 1.0 and can be in the range of approximately 1.1 to approximately 2.0. In other words, thickness T1A is greater than thicknesses T1'A, T2A, T2'A, and T3A. Thicknesses T1'A, T2A, T2'A, and T3A can be equal to or different from each other.

[0057] According to some embodiments, a high-k dielectric layer 66A is deposited using an ALD process. To increase the thickness T1A of the topmost portion of the high-k dielectric layer 66A, the wafer temperature during the deposition process can be relatively high, for example, in the range of about 300°C to about 400°C. The chamber pressure of the deposition chamber performing the ALD process can also be relatively high, for example, in the range of about 3 Torr to about 4 Torr. The pulse duration for the hafnium precursor (assuming the high-k dielectric layer 66A includes hafnium oxide) (and possibly an oxidant) can be relatively long, for example, in the range of about 1 second to about 10 seconds. The purge time for the hafnium precursor (and possibly an oxidant) can also be relatively long, for example, in the range of about 1 second to about 5 seconds. A longer pulse duration can result in a larger high-k dielectric layer thickness, while a longer purge time can result in a smaller high-k dielectric layer thickness, and vice versa.

[0058] Throughout the specification, when the first process condition is described as relatively high / long, and the second process condition is described as relatively low / short, this may also mean that the first process condition is higher (or longer) than the second process condition. For example, when the first wafer temperature used to form the high-k dielectric layer 66A is relatively high, while the temperature used to form the high-k dielectric layer 66B is relatively low... Figure 18 When the temperature of the second wafer is relatively low, this may also mean that the temperature of the first wafer is higher than that of the second wafer. Similarly, when the first pulse time (or purge time) for forming the high-k dielectric layer 66A is relatively long, while the time for forming the high-k dielectric layer 66B is relatively long, this may also mean that the temperature of the first wafer is higher than that of the second wafer. Figure 18 When the second pulse time (or purge time) is relatively short, it may also mean that the first pulse time (or purge time) is longer than the second pulse time (or purge time).

[0059] Then, the hard mask 70A is removed by an etching process, resulting in the structure shown below. Figure 16 As shown. The corresponding process is as follows: Figure 34 The process flow 200 shown is illustrated as process 232. Removing the hard mask 70A may include: forming a patterned etch mask (not shown) to cover device region 60A while leaving device regions 60B, 60C and 60D open, etching a portion of the high-k dielectric layer 66A above a portion of the hard mask 70A, etching the hard mask 70A, and removing the patterned etch mask.

[0060] In some cases, it is advantageous to make the top portion of the high-k dielectric layer 66A thicker. For example, increasing the top portion of the high-k dielectric layer 66A can improve yield and reliability. These embodiments can be adopted when a subsequent dipole introduction process is used, which may include etching / cleaning processes that could lead to yield and reliability issues.

[0061] Figures 17 to 19 The formation of a high-k dielectric layer 66B in device region 60B is shown. The corresponding process is as follows: Figure 34 The process flow 200 shown is illustrated as process 234. Furthermore, Figures 20 to 22 The formation of a high-k dielectric layer 66C in device region 60C is shown, and Figures 23 to 26 The formation of a high-k dielectric layer 66D in device region 60D is shown. Unless otherwise stated, the materials, structure, and fabrication processes of the components in these processes are consistent with those in the reference numerals. Figures 12 to 16 The similar components indicated by similar reference numerals in the discussed processes are substantially identical. Throughout this specification, details regarding materials, structure, and fabrication processes provided for one device region can be applied to other device regions where applicable.

[0062] refer to Figure 17 A hard mask 70B is deposited and patterned, forming an etch mask 74B. The portion of the etch mask 74B within device region 60B is removed, while portions within device regions 60A, 60C, and 60D are retained. Next, an etching process 72B is performed to remove the hard mask 70B from device region 60B. Then, the etch mask 74B is removed, resulting in the structure shown below. Figure 18 As shown.

[0063] Figure 18 The deposition of a high-k dielectric layer 66B according to some embodiments is also illustrated. Process conditions are adjusted such that the thickness T1B of the topmost portion of the high-k dielectric layer 66B above the topmost nanostructure 22B is less than the thicknesses T1'B and T2'B of the bottom portions of the high-k dielectric layer 66B and the thickness T3B of the sidewall portions of the high-k dielectric layer 66B. Thickness T1B is also less than the thickness T2B of the top portion of the high-k dielectric layer 66B below the topmost nanostructure 22B. For example, the thickness difference (T1'B - T1B) can be approximately... With the agreement The ratio T1'B / T1B can be between approximately 1.1 and approximately 2. In other words, the thickness T1B decreases to be less than the thicknesses T1'B, T2B, T2'B, and T3B. The thicknesses T1'B, T2B, T2'B, and T3B can be equal to or different from each other.

[0064] According to some embodiments, relationship T1B may also exist. <T1A( Figure 15 ) and T1'B>=T1'A.

[0065] According to some embodiments, to reduce the thickness T1B, the wafer temperature can be relatively low, for example, in the range of about 200°C to about 300°C. The chamber pressure of the deposition chamber performing the ALD process is relatively low, for example, in the range of about 1 Torr to about 3 Torr. The pulse time for the hafnium precursor (assuming the high-k dielectric layer 66B includes hafnium oxide) and possible oxidant can be relatively short, for example, in the range of about 0.1 seconds to about 3 seconds. The purge time for the precursor and possible oxidant can be relatively short, for example, in the range of about 0.1 seconds to about 2 seconds.

[0066] Then, the hard mask 70B is removed by an etching process, resulting in the structure shown below. Figure 19 As shown. Removing the hard mask 70B may include: forming a patterned etch mask (not shown) to cover device region 60B while leaving device regions 60A, 60C and 60D open, etching the portion of the high-k dielectric layer 66B above the portion of the hard mask 70B, etching the hard mask, and removing the etch mask.

[0067] In some cases, it is advantageous to make the top portion of the high-k dielectric layer 66B thinner. These embodiments can be adopted in situations where a dipole introduction process is not used and there are no concerns about yield and reliability.

[0068] Figures 20 to 22 The formation of a high-k dielectric layer 66C according to some embodiments is shown. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 236. (See reference) Figure 20 A hard mask 70C is deposited and patterned, and an etch mask 74C is formed. A portion of the etch mask 74C in device region 60C is removed, while portions in device regions 60A, 60B, and 60D are retained. Next, an etch process 72C is performed to remove the hard mask 70C in device region 60C. Then, the etch mask 74C is removed, resulting in the structure shown below. Figure 21 As shown.

[0069] Figure 21 The deposition of a high-k dielectric layer 66C according to some embodiments is also shown. Process conditions are adjusted such that the thickness T3C of the sidewall portion of the high-k dielectric layer 66C is greater than the thicknesses T1C, T1'C, T2C, and T2'C. For example, the thickness differences (T3C-T1C), (T3C-T1'C), (T3C-T2C), and (T3C-T2'C) can be greater than approximately And can be in about With the agreement The thickness ratios T3C / T1C, T3C / T1'C, T3C / T2C, and T3C / T2'C can be greater than about 1.1 and can be in the range between about 1.1 and about 2.0.

[0070] According to some embodiments, the relationship T3C>T3A can also exist. Figure 15 ), T3C>T3B( Figure 18 T1C <T1A( Figure 15 ), and T1C>T1B ( Figure 18 ).

[0071] According to some embodiments, to increase the sidewall thickness T3C and corner thickness T4C, the wafer temperature can be relatively high, for example, in the range of about 300°C to about 400°C. The chamber pressure of the deposition chamber performing the ALD process is relatively high, for example, in the range of about 3 Torr to about 4 Torr. The pulse duration for the hafnium precursor (assuming the high-k dielectric layer 66C includes hafnium oxide) and possible oxidants can be relatively long, for example, in the range of about 1 second to about 10 seconds. The purge time for the hafnium precursor and possible oxidants can be relatively long, for example, in the range of about 1 second to about 5 seconds.

[0072] Then, the hard mask 70C is removed by an etching process, resulting in the structure shown below. Figure 22 As shown.

[0073] In some cases, it is advantageous to make the sidewall and corner portions of the high-k dielectric layer 66C thicker. For example, increasing the sidewall and corner portions of the high-k dielectric layer can improve yield and reliability. These embodiments can be adopted when a dipole is introduced into the process, and the corresponding etching / cleaning process may cause yield and reliability issues.

[0074] Figures 23 to 26 The formation of a high-k dielectric layer 66D according to some embodiments is shown. The corresponding process is as follows: Figure 34 The process flow shown in the diagram 200 is illustrated as process 238. (Reference) Figure 23 A hard mask 70D is deposited and patterned, and an etch mask 74D is formed. A portion of the etch mask 74D in device region 60D is removed, while portions in device regions 60A, 60B, and 60C are retained. Next, an etch process 72D is performed to remove the hard mask 70D in device region 60D. Then, the etch mask 74D is removed, resulting in the structure shown below. Figure 24 As shown.

[0075] Figure 25The deposition of a high-k dielectric layer 66D according to some embodiments is illustrated. Process conditions were adjusted such that the internal thicknesses T1'D, T2D, and T2'D of the inner portions of the high-k dielectric layer 66C were reduced to less than the thicknesses T1D and T3D. Throughout the specification, the portion of the high-k dielectric layer facing upwards or downwards towards the nanostructure 22B is referred to as the inner portion, and its thicknesses T1'D, T2D, and T2'D are referred to as the inner thicknesses. Thicknesses T1D and T3D can be greater than the inner thicknesses T1'D, T2D, and T2'D, with a thickness difference greater than approximately And can be in about With the agreement The thickness ratio (T1D or T3D) / (T1'D or T2D or T2'D) can be greater than about 1.1 and can be in the range between about 1.1 and about 2.0. The internal thicknesses T1'D, T2D, and T2'D can be less than about 1.1.

[0076] According to some embodiments, the relationship T1'D may also exist. <T1'A( Figure 15 T1D <T1A( Figure 15 ) and T3D=T3A( Figure 15 ), T1'D <T1'B( Figure 18 T1D>T1B Figure 18 ) and T3D=T3B( Figure 18 ), and T1'D <T1'C( Figure 21 ) and T1D=T1C( Figure 21 ).

[0077] According to some embodiments, in order to reduce the internal thicknesses T1'D, T2D, and T2'D, the wafer temperature can be relatively high, for example, in the range of about 300°C to about 400°C. The chamber pressure of the deposition chamber performing the ALD process is relatively high, for example, in the range of about 3 Torr to about 4 Torr. The pulse time for the precursor (assuming the high-k dielectric layer 66B includes hafnium oxide) and possibly the oxidant can be relatively short, for example, in the range of about 0.1 seconds to about 3 seconds. The purge time for the precursor can be relatively short, for example, in the range of about 0.1 seconds to about 0.2 seconds.

[0078] In some cases, it is advantageous to make the inner portion of the high-k dielectric layer 66D thinner. For example, reducing the inner thickness of the high-k dielectric layer can improve device performance (e.g., current). Furthermore, reducing the inner thickness of the high-k dielectric layer makes it easier to fill the dipole film (not shown) in subsequent processes, allowing the dipole film to fill all the spaces between the nanostructures 22B.

[0079] Then, the hard mask 70D is removed by etching, resulting in the structure shown below. Figure 26 As shown. In Figure 26 In the middle, IL 64 and the corresponding overlying high-k dielectric layers 66A, 66B, 66C and 66D together form the gate dielectrics 68A, 68B, 68C and 68D.

[0080] Figure 27 An embodiment is shown in which a dipole film 75 is formed to dope dipole dopants into high-k dielectric layers 66A and 66C, thereby adjusting the threshold voltage of the corresponding nanostructured transistors in device regions 66A and 66C. In other embodiments, the dipole doping process is omitted. The dipole film 75 may include an n-type dipole dopant, which can lower the threshold voltage of the n-type nanostructured transistor and increase the threshold voltage of the p-type nanostructured transistor. Alternatively, the dipole film 75 may include a p-type dipole dopant, which can increase the threshold voltage of the n-type nanostructured transistor and decrease the threshold voltage of the p-type nanostructured transistor. Reference Figure 27 In the process of forming the dipole film 75, an etching mask 71 is formed in device regions 60B and 60D, while the etching mask 71 in device regions 60A and 60C is removed to form the dipole film 75. After the etching process is performed, the etching mask 71 in device regions 60B and 60D is removed.

[0081] Figure 27 Further illustrated is an annealing process 73 used to drive / introduce dipole dopant from dipole film 75 into / introduce high-k dielectric layers 66A and 66C. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 240. According to an alternative embodiment, the dipole doping process is omitted. The dipole film 75 is removed after the annealing process is completed. Figure 28 The resulting structure is shown. The high-k dielectric layers 66A and 66C are less likely to be damaged during the etching of the dipole film 75 due to their thicker top or sidewall / corner portions.

[0082] Figure 29A and Figure 29B The diagram shows a cross-section of wafer 10 after the formation of IL 64 and the high-k dielectric layer 66 as discussed in the foregoing embodiments. The gate dielectric 68 shown represents... Figure 28 The gate dielectrics shown are 68A, 68B, 68C, and 68D.

[0083] Figure 29C A perspective view of a portion of the nanostructure 22B and the corresponding high-k dielectric 66 is shown. It will be understood that certain features are not shown in the figure. From Figure 29CIt can be seen that a thicker gate dielectric 68 (due to a thicker high-k dielectric layer 66) is desirable for improving yield and reliability, but undesirable for improving device performance. Conversely, a thinner gate dielectric 68 is desirable for improving device performance, but undesirable for improving yield and reliability. Therefore, the embodiments of this disclosure can be used to meet different needs.

[0084] Then the gate electrode 70 is formed, such as Figure 30A and Figure 30B As shown. The corresponding process is as follows: Figure 34 The process flow 200 is shown as process 242. Gate dielectric 68 and gate electrode 70 together form an alternative gate stack 72. In the formation process of gate electrode 70, a conductive layer is first formed over a high-k dielectric layer 66 to fill the remaining portion of the trench 58, followed by a planarization process (e.g., CMP or mechanical polishing) to remove excess material. Gate electrode 70 may include a metallic material such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. This forms a nanostructure transistor 74, and nanostructure transistors 74A, 74B, 74C, and 74D may be represented, having, for example... Figure 28 The gate dielectrics shown are 68A, 68B, 68C, and 68D.

[0085] Figures 31 to 33 This diagram schematically illustrates the effect of adjusting the thickness of different portions of the high-k dielectric layer on device performance, as well as yield and reliability (referred to as yield / reliability). The X-axis represents thickness, and the Y-axis represents device performance or yield / reliability. Line 82 represents device performance and shows that device performance decreases as the thickness of the high-k dielectric layer increases. Line 84 represents yield / reliability and shows that yield / reliability improves as the thickness of the high-k dielectric layer increases.

[0086] Figure 31 The X-axis in the figure shows the high-k dielectric layer 66A ( Figure 15 The thickness of the top portion of the nanostructure transistor with a conformal high-k dielectric layer. The yield / reliability and device performance of the nanostructure transistor with a thickness equal to TCon will be located at the position where the thickness is equal to TCon, while the top portion of the high-k dielectric layer of the 66A nanostructure transistor 74A is thicker. Figure 30A and Figure 30B The yield / reliability and device performance of ) will be located at a thickness equal to T1A ( Figure 15 The location of the nanostructure transistor 74A will be understood to be that while it reduces device performance, it improves yield / reliability.

[0087] Figure 32 The X-axis in the figure shows the high-k dielectric layer 66C ( Figure 21 The thickness of the corner / sidewall portion of the nanostructure transistor with a conformal high-k dielectric layer. The yield / reliability and device performance of the nanostructure transistor with a thickness equal to TCon will be at the position where the high-k dielectric layer 66C has a thicker corner / sidewall portion than the nanostructure transistor 74C. Figure 30A and Figure 30B The yield / reliability and device performance will be at the level of thickness equal to T3C / T4C ( Figure 21 The location of the nanostructure transistor 74C will be understood to be that while it reduces device performance, it improves yield / reliability.

[0088] Figure 33 The X-axis in the figure shows the high-k dielectric layer 66D ( Figure 25 The thickness of the internal portion of the nanostructure transistor with a conformal high-k dielectric layer. The yield / reliability and device performance of the nanostructure transistor with a thickness equal to TCon will be located at the position where the thickness is equal to TCon, while the internal portion of the high-k dielectric layer 66D is thinner in the nanostructure transistor 74D ( Figure 30A and Figure 30B The yield / reliability and device performance will be located within an internal thickness equal to T1'D ( Figure 25 The location of the nanostructure transistor 74D will be understood to be a factor. It improves device performance but reduces yield / reliability.

[0089] The embodiments of this disclosure have several advantageous features. By employing different process conditions to adjust the profile of the high-k dielectric layer, nanostructured transistors can be tuned to meet different requirements, such as improving yield and reliability, or enhancing device performance.

[0090] According to some embodiments of the present disclosure, a method includes: forming a first plurality of semiconductor nanostructures, the first plurality of semiconductor nanostructures including: a first lower semiconductor nanostructure; and a first topmost semiconductor nanostructure located above the first lower semiconductor nanostructure; forming an interface layer in contact with the first plurality of semiconductor nanostructures; and depositing a first high-k dielectric layer surrounding the interface layer, wherein the first topmost high-k dielectric layer surrounding the first topmost semiconductor nanostructure includes: a first topmost horizontal portion superimposed on the first topmost semiconductor nanostructure; a first bottom horizontal portion superimposed on the first topmost semiconductor nanostructure; and a first sidewall portion located on the sidewall of the first topmost semiconductor nanostructure, wherein a first portion selected from the first topmost horizontal portion, the first bottom horizontal portion, and the first sidewall portion has a first thickness, and a second portion selected from the first topmost horizontal portion, the first bottom horizontal portion, and the first sidewall portion has a second thickness different from the first thickness.

[0091] In one embodiment, the second thickness is less than the first thickness. In one embodiment, depositing the first high-k dielectric layer includes an atomic layer deposition process. In one embodiment, the thinner first portion is a first topmost horizontal portion, and the thicker second portion is a first bottom horizontal portion. In one embodiment, the first sidewall portion has the same thickness as the first bottom horizontal portion.

[0092] In one embodiment, the method further includes: forming a second plurality of semiconductor nanostructures, the second plurality of semiconductor nanostructures including: a second lower semiconductor nanostructure; and a second topmost semiconductor nanostructure located above the second lower semiconductor nanostructure; and depositing a second high-k dielectric layer surrounding the second plurality of semiconductor nanostructures, wherein the second topmost high-k dielectric layer surrounding the second topmost semiconductor nanostructure includes: a second topmost horizontal portion superimposed on the second topmost semiconductor nanostructure; and a second bottom horizontal portion superimposed on the second topmost semiconductor nanostructure, wherein the second topmost horizontal portion is thicker than the first topmost horizontal portion.

[0093] In one embodiment, the second bottom horizontal portion is thinner than the second top horizontal portion. In one embodiment, the first portion is a first sidewall portion, and the second portion is the first bottom horizontal portion. In one embodiment, the method further includes: forming a source / drain region located adjacent to and in contact with the first plurality of semiconductor nanostructures; and forming a gate electrode over a first high-k dielectric layer. In one embodiment, the first high-k dielectric layer comprises hafnium oxide. In one embodiment, the interface layer comprises silicon oxide.

[0094] According to some embodiments of this disclosure, a method includes: forming a first plurality of semiconductor nanostructures including a first top semiconductor nanostructure; forming a second plurality of semiconductor nanostructures including a second top semiconductor nanostructure; depositing a first high-k dielectric layer surrounding the first top semiconductor nanostructure, wherein the first high-k dielectric layer is deposited using first process conditions; and depositing a second high-k dielectric layer surrounding the second top semiconductor nanostructure, wherein the second high-k dielectric layer is deposited using a second process condition different from the first process conditions, and wherein the first high-k dielectric layer includes the same high-k dielectric material as the second high-k dielectric layer; forming a first gate electrode surrounding the first high-k dielectric layer; and forming a second gate electrode surrounding the second high-k dielectric layer, wherein the first gate electrode and the second gate electrode are formed using a common process.

[0095] In one embodiment, the method further includes: forming a first interface layer on a first topmost semiconductor nanostructure before forming a first high-k dielectric layer; and forming a second interface layer on a second topmost semiconductor nanostructure before forming a second high-k dielectric layer, wherein the first interface layer and the second interface layer are formed in the same formation process.

[0096] In one embodiment, the first process conditions include a first wafer temperature and a first chamber pressure, and the second process conditions include: a second wafer temperature higher than the first wafer temperature; and a second chamber pressure higher than the first chamber pressure. In one embodiment, the first high-k dielectric layer includes: a first top horizontal portion overlaid with a first top semiconductor nanostructure; and a first bottom horizontal portion overlaid with the first top semiconductor nanostructure, wherein the first top horizontal portion is thinner than the first bottom horizontal portion.

[0097] In one embodiment, the second high-k dielectric layer includes: a second top horizontal portion overlaid with a second top semiconductor nanostructure; and a second bottom horizontal portion overlaid with the second top semiconductor nanostructure, wherein the second top horizontal portion is thicker than the second bottom horizontal portion. In one embodiment, both the first high-k dielectric layer and the second high-k dielectric layer are deposited using an atomic layer deposition process.

[0098] According to some embodiments of this disclosure, a structure includes: a first plurality of semiconductor nanostructures, including: a first lower semiconductor nanostructure; and a first topmost semiconductor nanostructure located above the first lower semiconductor nanostructure; an interface layer surrounding the first topmost semiconductor nanostructure; and a first high-k dielectric layer surrounding the interface layer, wherein the first high-k dielectric layer includes: a first upper horizontal portion stacked on the first topmost semiconductor nanostructure and having a first thickness; a first bottom horizontal portion stacked on the first topmost semiconductor nanostructure and having a second thickness different from the first thickness; and a first sidewall portion located on the sidewall of the first topmost semiconductor nanostructure.

[0099] In one embodiment, the first thickness is less than the second thickness. In another embodiment, the structure further includes: a second plurality of semiconductor nanostructures, including: a second lower semiconductor nanostructure; and a second topmost semiconductor nanostructure located above the second lower semiconductor nanostructure; and a second high-k dielectric layer surrounding the second topmost semiconductor nanostructure, wherein the second high-k dielectric layer includes: a second upper horizontal portion stacked on the second topmost semiconductor nanostructure and having a third thickness; and a second bottom horizontal portion stacked on the second topmost semiconductor nanostructure and having a fourth thickness less than the third thickness. In one embodiment, the first upper horizontal portion is thinner than the first sidewall portion.

[0100] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method comprising: Forming a first plurality of semiconductor nanostructures, the first plurality of semiconductor nanostructures comprising: The first lower semiconductor nanostructure; and The first topmost semiconductor nanostructure is located above the first lower semiconductor nanostructure; An interface layer is formed on the first plurality of semiconductor nanostructures; and A first high-k dielectric layer is deposited surrounding the interface layer, wherein the first high-k dielectric layer surrounding the first topmost semiconductor nanostructure comprises: The first top horizontal portion of the first top semiconductor nanostructure is superimposed; The first bottom horizontal portion is covered by the first topmost semiconductor nanostructure; and A first sidewall portion located on the sidewall of the first topmost semiconductor nanostructure, wherein a first portion selected from the first topmost horizontal portion, the first bottom horizontal portion and the first sidewall portion has a first thickness, and a second portion selected from the first topmost horizontal portion, the first bottom horizontal portion and the first sidewall portion has a second thickness different from the first thickness.

2. The method according to claim 1, wherein, The second thickness is less than the first thickness.

3. The method according to claim 1, wherein, The thinner first portion is the first topmost horizontal portion, and the thicker second portion is the first bottom horizontal portion.

4. The method according to claim 3, wherein, The first sidewall portion has the same thickness as the first bottom horizontal portion.

5. The method according to claim 3, further comprising: Forming a second plurality of semiconductor nanostructures, the second plurality of semiconductor nanostructures comprising: The second lower semiconductor nanostructure; and The second, topmost semiconductor nanostructure is located above the second lower semiconductor nanostructure; and A second high-k dielectric layer is deposited surrounding the second plurality of semiconductor nanostructures, wherein the second high-k dielectric layer surrounding the second topmost semiconductor nanostructure comprises: The second top horizontal portion of the superimposed second top semiconductor nanostructure; and A second bottom horizontal portion is superimposed on the second topmost semiconductor nanostructure, wherein the second topmost horizontal portion is thicker than the first topmost horizontal portion.

6. The method according to claim 5, wherein, The second bottom horizontal portion is thinner than the second top horizontal portion.

7. The method according to claim 1, wherein, The first part is the first sidewall portion, and the second part is the first bottom horizontal portion.

8. The method according to claim 1, further comprising: A source / drain region is formed next to and in contact with the first plurality of semiconductor nanostructures; as well as A gate electrode is formed on the first high-k dielectric layer.

9. A method comprising: Forming a plurality of semiconductor nanostructures, including a first topmost semiconductor nanostructure; Forming a second plurality of semiconductor nanostructures, including a second topmost semiconductor nanostructure; A first high-k dielectric layer is deposited surrounding the first topmost semiconductor nanostructure, wherein the first high-k dielectric layer is deposited using first process conditions; and A second high-k dielectric layer is deposited around the second topmost semiconductor nanostructure, wherein the second high-k dielectric layer is deposited using a second process condition different from the first process condition, and wherein the first high-k dielectric layer comprises the same high-k dielectric material as the second high-k dielectric layer. A first gate electrode is formed surrounding the first high-k dielectric layer; and A second gate electrode is formed around the second high-k dielectric layer, wherein the first gate electrode and the second gate electrode are formed using a common process.

10. A structure comprising: The first plurality of semiconductor nanostructures include: The first lower semiconductor nanostructure; and The first topmost semiconductor nanostructure is located above the first lower semiconductor nanostructure; The interface layer surrounding the first topmost semiconductor nanostructure; and A first high-k dielectric layer surrounding the interface layer, wherein the first high-k dielectric layer comprises: A first upper horizontal portion that overlaps the first topmost semiconductor nanostructure and has a first thickness; A first bottom horizontal portion, covered by the first topmost semiconductor nanostructure and having a second thickness different from the first thickness; and The first sidewall portion located on the sidewall of the first topmost semiconductor nanostructure.

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