Semiconductor structure and method of forming the same

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin standing on the substrate, along the extension direction of the fin, the fin includes a channel region, the channel region is used to form a stacked work function layer; forming a gate dielectric layer conformally covering the top and sidewall of the fin in the channel region; forming a first work function layer conformally covering the gate dielectric layer in the channel region; forming a filling layer on the first work function layer between adjacent fins, the filling layer exposes at least the first work function layer on the top of the fin, the Fermi level of the material of the filling layer is closer to the Fermi level of the fin than the Fermi level of the material of the stacked work function layer; forming a second work function layer covering the first work function layer and the filling layer, the second work function layer and the first work function layer are used to constitute the stacked work function layer. The second work function layer is located on the top of the first work function layer and the filling layer, which reduces the probability of generating void defects in the second work function layer and improves the uniformity of the threshold voltage of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] The primary semiconductor device in integrated circuits, especially very large-scale integrated circuits (VLSI), is the metal-oxide-semiconductor field-effect transistor (MOS transistor). With the continuous development of integrated circuit manufacturing technology, semiconductor device technology nodes are constantly shrinking, and the geometric dimensions of semiconductor structures are shrinking according to Moore's Law. When the size of semiconductor structures shrinks to a certain extent, various second-order effects caused by the physical limitations of semiconductor structures emerge, making it increasingly difficult to scale down the feature sizes of semiconductor structures proportionally. Among these challenges in semiconductor manufacturing, the most significant is addressing the problem of high leakage current in semiconductor structures. High leakage current in semiconductor structures is mainly caused by the continuous reduction in the thickness of the traditional gate dielectric layer.

[0003] The current proposed solution is to use a high-k gate dielectric material instead of the traditional silicon dioxide gate dielectric material, and to use a metal as the gate electrode to avoid the Fermi level pinning effect and boron permeation effect between the high-k gate dielectric material and the traditional gate electrode material. The introduction of a high-k metal gate reduces the leakage current of the semiconductor structure. However, the high-k metal gate includes a work function layer, which can easily cause performance problems during fabrication. Therefore, although the introduction of a high-k metal gate can improve the electrical performance of the semiconductor structure to some extent, the existing methods for forming the work function layer still need improvement. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, including a base and fins protruding from the substrate, wherein the fins include a channel region along the extending direction of the fins, the channel region being used to form a stacked work function layer; a gate dielectric layer conformally covering the top and sidewalls of the fins in the channel region; a first work function layer conformally covering the gate dielectric layer; a fill layer located on the first work function layer between adjacent fins, the fill layer at least exposing the first work function layer at the top of the fins, the material Fermi level of the fill layer being closer to the Fermi level of the fins than the material Fermi level of the stacked work function layer; and a second work function layer covering the first work function layer and the fill layer, the second work function layer and the first work function layer being used to form a stacked work function layer.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin protruding from the substrate, wherein along the extending direction of the fin, the fin includes a channel region, the channel region being used to form a stacked work function layer; forming a gate dielectric layer conformally covering the top and sidewalls of the fin in the channel region; forming a first work function layer conformally covering the gate dielectric layer in the channel region; forming a fill layer on the first work function layer between adjacent fins, the fill layer at least exposing the first work function layer at the top of the fin, the material Fermi level of the fill layer being closer to the Fermi level of the fin than the material Fermi level of the stacked work function layer; and forming a second work function layer covering the first work function layer and the fill layer, the second work function layer and the first work function layer being used to constitute a stacked work function layer.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a semiconductor structure in which the channel region of a fin is used to form a stacked work function layer. A first work function layer conformally covers the gate dielectric layer of the channel region. A fill layer is located on the first work function layer between adjacent fins, and the fill layer at least exposes the first work function layer at the top of the fin. The Fermi level of the fill layer is closer to the Fermi level of the fin than the Fermi level of the work function layer. A second work function layer covers the first work function layer and the fill layer. The second and first work function layers constitute a stacked work function layer. Since the channel region is used to form a stacked work function layer (i.e., including multiple work function layers), as the number of work function layers increases between adjacent fins, the space available for forming each work function layer gradually decreases. This makes the stacked work function layer between adjacent fins prone to void defects. In this embodiment of the invention, compared to the scheme where the second work function layer is located between adjacent fins, the filling layer is located on the first work function layer, occupying the space between adjacent fins. The second work function layer is located on top of the first work function layer and the filling layer. This reduces the distance from the bottom of the second work function layer to the top of the fin between adjacent fins, thus reducing the probability of void defects in the second work function layer. This improves the non-uniformity of void defects in the second work function layer and correspondingly improves the performance uniformity of the second work function layer, which in turn helps to improve the uniformity of the device threshold voltage. Furthermore, since the Fermi level of the filling layer is closer to the Fermi level of the fin than the Fermi level of the stacked work function layer, the filling layer has a smaller impact on the work function of the stacked work function layer. Therefore, the presence of the filling layer has a smaller impact on the device threshold voltage. In summary, the performance of the semiconductor structure is improved.

[0009] In the forming method provided by this embodiment of the invention, the channel region of the fin is used to form a stacked work function layer. After forming a first work function layer that conformally covers the gate dielectric layer in the channel region, a fill layer is formed on the first work function layer between adjacent fins. The fill layer at least exposes the first work function layer at the top of the fin. The Fermi level of the material in the fill layer is closer to the Fermi level of the fin than the Fermi level of the material in the work function layer. A second work function layer is formed that covers the first work function layer and the fill layer. The second work function layer and the first work function layer constitute a stacked work function layer. Since the channel region is used to form a stacked work function layer (i.e., including multiple work function layers), as the number of work function layers increases between adjacent fins, the space used to form each work function layer gradually decreases. This makes it easy for void defects to occur in the stacked work function layer between adjacent fins. In this embodiment of the invention, after forming the first work function layer, a filling layer occupies the space between adjacent fins, and the second work function layer is formed on top of the first work function layer and the filling layer. This reduces the distance from the bottom of the second work function layer to the top of the fin between adjacent fins, thus reducing the probability of void defects in the second work function layer. This improves the non-uniformity of void defects in the second work function layer and correspondingly improves the performance uniformity of the second work function layer, which in turn helps to improve the uniformity of the device threshold voltage. Furthermore, since the Fermi level of the filling layer is closer to the Fermi level of the fin than the Fermi level of the stacked work function layer, the filling layer has a smaller impact on the work function of the stacked work function layer. Therefore, the presence of the filling layer has a smaller impact on the device threshold voltage. In summary, the performance of the semiconductor structure is improved. Attached Figure Description

[0010] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figure 5 and Figure 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 7 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons for this need to improve performance using a semiconductor structure formation method as an example.

[0014] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 A substrate (not shown) is provided, including a substrate 10 and fins 13 protruding from the substrate 10, the substrate including an NMOS region 10N (e.g., Figure 1 (a) shown) and PMOS region 10P (as shown in) Figure 1 (b) As shown, the fin 13 of the PMOS region 10P is used to form a stacked work function layer.

[0016] refer to Figure 2 A first work function layer 31 is formed to conformally cover part of the top and part of the sidewalls of the fin 13.

[0017] refer to Figure 3 Remove the first work function layer 31 located in the NMOS region 10N.

[0018] refer to Figure 4 After removing the first work function layer 31 located in the NMOS region 10N, a conformal fin 13 covering the NMOS region 10N and a second work function layer 32 of the first work function layer 31 are formed. The second work function layer 32 is used to form the work function layer of the NMOS region 10N, and the first work function layer 31 and the second work function layer 32 are used to form the stacked work function layer of the PMOS region 10P.

[0019] Because a stacked work function layer is formed in the PMOS region 10P, the space available for forming each work function layer gradually decreases between adjacent fins 13 as the number of work function layers increases. This makes the stacked work function layers between adjacent fins 13 prone to void defects. In other words, after forming the first work function layer 31, the remaining space between adjacent fins 13 is small. Therefore, when forming the second work function layer 32, void defects are easily generated in the second work function layer 32 located between adjacent fins 13 (e.g., void defects). Figure 4 (b) As shown by the dashed circle, the morphology of the void defect is randomly generated, and the position and size of the void defect cannot be precisely controlled. Therefore, it is easy to cause the non-uniformity of the void defect, which leads to large fluctuations in the threshold voltage of the device (i.e., the threshold voltage of the PMOS device) and affects the performance of the semiconductor structure.

[0020] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and fins protruding from the substrate, wherein the fins include a channel region along an extension direction of the fins, the channel region being used to form a stacked work function layer; forming a conformally conformally covering the top and sidewalls of the fins in the channel region; forming a conformally conformally covering the gate dielectric layer in the channel region; forming a fill layer on the first work function layer between adjacent fins, the fill layer at least exposing the first work function layer at the top of the fins, wherein the material Fermi level of the fill layer is closer to the Fermi level of the fins than the material Fermi level of the stacked work function layer; and forming a second work function layer covering the first work function layer and the fill layer, the second work function layer and the first work function layer constituting a stacked work function layer.

[0021] In the forming method provided by this embodiment of the invention, the channel region of the fin is used to form a stacked work function layer. After forming a first work function layer that conformally covers the gate dielectric layer in the channel region, a fill layer is formed on the first work function layer between adjacent fins. The fill layer at least exposes the first work function layer at the top of the fin. The Fermi level of the material in the fill layer is closer to the Fermi level of the fin than the Fermi level of the material in the work function layer. A second work function layer is formed that covers the first work function layer and the fill layer. The second work function layer and the first work function layer constitute a stacked work function layer. Since the channel region is used to form a stacked work function layer (i.e., including multiple work function layers), as the number of work function layers increases between adjacent fins, the space used to form each work function layer gradually decreases. This makes it easy for void defects to occur in the stacked work function layer between adjacent fins. In this embodiment of the invention, after forming the first work function layer, a filling layer occupies the space between adjacent fins, and the second work function layer is formed on top of the first work function layer and the filling layer. This reduces the distance from the bottom of the second work function layer to the top of the fin between adjacent fins, thus reducing the probability of void defects in the second work function layer. This improves the non-uniformity of void defects in the second work function layer and correspondingly improves the performance uniformity of the second work function layer, which in turn helps to improve the uniformity of the device threshold voltage. Furthermore, since the Fermi level of the filling layer is closer to the Fermi level of the fin than the Fermi level of the stacked work function layer, the filling layer has a smaller impact on the work function of the stacked work function layer. Therefore, the presence of the filling layer has a smaller impact on the device threshold voltage. In summary, the performance of the semiconductor structure is improved.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figure 5 and Figure 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, wherein, Figure 6 This is a top view of the fin.

[0024] The semiconductor structure includes: a substrate (not shown), including a substrate 101 and a fin 131 protruding from the substrate 101, wherein along the extending direction of the fin 131, the fin 131 includes a channel region 131c (e.g., Figure 6 As shown, the channel region 131c is used to form a stacked work function layer 341; the gate dielectric layer 201 conformally covers the top and sidewalls of the fin 131 of the channel region 131c; the first work function layer 311 conformally covers the gate dielectric layer 201; the filler layer 331 is located on the first work function layer 311 between adjacent fins 131, the filler layer 331 at least exposes the first work function layer 311 on the top of the fin 131, the material Fermi level of the filler layer 331 is closer to the Fermi level of the fin 131 than the material Fermi level of the stacked work function layer 341; the second work function layer 321 covers the first work function layer 311 and the filler layer 331, the second work function layer 321 and the first work function layer 311 are used to form the stacked work function layer 341.

[0025] Since the channel region 131c is used to form a stacked work function layer 341 (i.e., including multiple work function layers), the space used to form each work function layer gradually decreases between adjacent fins 131 as the number of work function layers increases. This makes the stacked work function layer 341 between adjacent fins 131 prone to void defects. Compared to the scheme where the second work function layer is located between adjacent fins, in this embodiment of the invention, the filling layer 331 is located on the first work function layer 311, occupying the space between adjacent fins 131, and the second work function layer 321 is located on top of the first work function layer 311 and the filling layer 331. This reduces the distance from the bottom of the second work function layer 321 to the top of the fin 131 between adjacent fins 131, thus reducing the probability of void defects in the second work function layer 321 and improving the second work function... The non-uniformity of void defects in the multilayer 321 improves the performance uniformity of the second work function layer 321, which in turn helps to improve the uniformity of the device threshold voltage. Furthermore, since the Fermi level of the material of the filling layer 331 is closer to the Fermi level of the fin 131 than the Fermi level of the material of the stacked work function layer 341, the filling layer 331 has a smaller impact on the work function of the stacked work function layer 341. Therefore, the presence of the filling layer 331 has a smaller impact on the device threshold voltage. In summary, the performance of the semiconductor structure is improved.

[0026] The substrate provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure has a three-dimensional structure. In this embodiment, the semiconductor structure includes a FinFET or a fully enclosed (GAA) transistor.

[0027] The substrate includes an NMOS region 101N (such as...). Figure 5 (a) shown) and PMOS region 101P (as shown in) Figure 5 (b) shown) are used to form NMOS transistors and PMOS transistors, respectively.

[0028] In this embodiment, taking the semiconductor structure as a fin field-effect transistor as an example, the substrate includes a substrate 101 and a fin 131 protruding from the substrate 101.

[0029] In this embodiment, the substrate 101 is made of silicon. In other embodiments, the substrate may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 101 may be suitable for process requirements or easy to integrate.

[0030] The fin 131 is used to provide a channel for the fin field-effect transistor.

[0031] In this embodiment, the fin 131 and the substrate 101 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.

[0032] In this embodiment, the material of the fin 131 is the same as the material of the substrate 101, and the material of the fin 131 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0033] In this embodiment, along the extending direction of the fin 131, the fin 131 includes a channel region 131c (e.g., ...). Figure 6 (As shown).

[0034] The fin portion 131 of the channel region 131c is used as the channel of the fin field-effect transistor, and the channel region 131c is also used to form a stacked work function layer 341.

[0035] In this embodiment, the stacked work function layer 341 is located in the PMOS region 101P. The stacked work function layer 341 includes multiple work function layers. The work function layers are used to adjust the threshold voltage of the transistor. The stacked work function layer 341 is used to adjust the threshold voltage of the PMOS transistor.

[0036] In this embodiment, the semiconductor structure further includes an isolation layer 111 located on the substrate 101 and covering part of the sidewall of the fin 131.

[0037] The isolation layer 111 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 111 is usually formed between NMOS transistors and PMOS transistors.

[0038] The insulating layer 111 is made of an insulating material. As an example, the insulating layer 111 is made of silicon oxide.

[0039] In this embodiment, in the NMOS region 101N, the gate dielectric layer 201 is located between the second work function layer 321 and the fin 131, and in the PMOS region 101P, the gate dielectric layer 201 is located between the first work function layer 311 and the fin 131.

[0040] In this embodiment, the gate dielectric layer 201 conformally covers the top and sidewalls of the fin 131 of the channel region 131c, as well as the top of the isolation layer 111.

[0041] The gate dielectric layer 201 is made of one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 201 is made of a high-k dielectric material, wherein a high-k dielectric material is a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k gate dielectric layer is made of materials such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0042] The first work function layer 311 is used to adjust the threshold voltage of the transistor.

[0043] In this embodiment, the channel region 131C in the PMOS region 101P is used to form the stacked work function layer 341. Therefore, the first work function layer 311 is located in the PMOS region 101P and is used to form the stacked work function layer 341 of the PMOS region 101P. The stacked work function layer 341 of the PMOS region 101P is used to adjust the threshold voltage of the PMOS transistor.

[0044] In this embodiment, the first work function layer 311 is made of a P-type work function material, used as the work function layer of a PMOS transistor to adjust the threshold voltage of the PMOS transistor. The P-type work function material includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. As an example, the first work function layer 311 is made of TiN.

[0045] In this embodiment, the filling layer 331 is located in the PMOS region 101P. The filling layer 331 is used to fill the space enclosed by the first work function layer 311 between adjacent fins 131 in the structure of the stacked work function layer 341, so as to reduce the height of the second work function layer 321 between adjacent fins 131, thereby reducing the probability of void defects in the second work function layer 321.

[0046] In this embodiment, the channel region 131c in the PMOS region 101P is used to form the stacked work function layer 341. Therefore, the filling layer 331 exposes at least the first work function layer 311 on the top of the fin 131, so that the first work function layer 311 and the second work function layer 321 are in contact, which is beneficial to the control of the threshold voltage of the transistor by the stacked work function layer 341.

[0047] In this embodiment, the top of the filling layer 331 is lower than or flush with the top of the first work function layer 311, thereby ensuring that the first work function layer 311 on the top of the fin 131 can be exposed, so that the second work function layer 321 can contact the first work function layer 311.

[0048] It should be noted that the top of the filling layer 331 should not be too high. If the top of the filling layer 331 is too high, it will fill too much space, thereby replacing too much of the second work function layer 321. This could excessively weaken the control capability of the second work function layer 321 over the threshold voltage of the transistor, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the top of the filling layer 331 is lower than or flush with the top of the first work function layer 311.

[0049] In this embodiment, the Fermi level of the material of the filling layer 331 is closer to the Fermi level of the fin 131 than the Fermi level of the material of the stacked work function layer 341. Therefore, the filling layer 331 has a smaller impact on the work function of the stacked work function layer 341. Thus, even if void defects are generated in the filling layer 331 during the formation of the filling layer 331, the presence of the filling layer 331 has a smaller impact on the device threshold voltage, thereby improving the performance of the semiconductor structure.

[0050] In this embodiment, the filling layer 331 is made of a conductive material.

[0051] The conductive material does not easily add additional resistance between the first work function layer 311 and the second work function layer 321, which helps to ensure the conductivity of the stacked work function layer 341.

[0052] In this embodiment, the material of the filling layer 331 includes tungsten.

[0053] In this embodiment, the fin 131 is made of silicon. The Fermi level of the tungsten is close to that of silicon, and the tungsten has good conductivity. Therefore, the tungsten material can have a small impact on the work function of the stacked work function layer 341 and does not easily increase the resistance.

[0054] The second work function layer 321 is used to adjust the threshold voltage of the transistor.

[0055] In this embodiment, the second work function layer 321 covers the first work function layer 311 and the fill layer 331 of the PMOS region 101P, and is used to form the stacked work function layer 341 of the PMOS region 101P. The stacked work function layer 341 of the PMOS region 101P is used to adjust the threshold voltage of the PMOS transistor.

[0056] In this embodiment, the second work function layer 321 is also located in the NMOS region 101N and is used as the work function layer of the NMOS region 101N. The second work function layer 321 in the NMOS region 101N is used to adjust the threshold voltage of the NMOS transistor.

[0057] In this embodiment, the second work function layer 321 covers the first work function layer 311 and the fill layer 331 of the PMOS region 101P, and the second work function layer 321 and the first work function layer 311 are used together to form a stacked work function layer 341.

[0058] In this embodiment, the second work function layer 321 covers the top and sidewalls of the fin 131 of the channel region 131c, and the second work function layer 321 is used to form the work function layer of the NMOS region 101N.

[0059] Specifically, in the NMOS region 101N, the second work function layer 321 covers the gate dielectric layer 201.

[0060] As an example, in the NMOS region 101N, the second work function layer 321 fills between adjacent fins 131 of the channel region 131c and covers the gate dielectric layer 201.

[0061] In this embodiment, the material of the second work function layer is an N-type work function material, used as the work function layer of the NMOS transistor. The N-type work function material includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. As an example, the material of the second work function layer 321 is TiAl.

[0062] In this embodiment, the semiconductor structure further includes a metal gate electrode layer 501 covering the second work function layer 321.

[0063] The metal gate electrode layer 501 is used to form a metal gate structure with the work function layer.

[0064] Specifically, in the PMOS region 101P, the metal gate electrode layer 501, the first work function layer 311, and the second work function layer 321 constitute the metal gate structure of the PMOS transistor, and in the NMOS region 101N, the metal gate electrode layer 501 and the second work function layer 321 constitute the metal gate structure of the NMOS transistor.

[0065] The metal gate electrode layer 501 is used to bring out the electrical properties of the metal gate structure. In this embodiment, the material of the metal gate electrode layer 501 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0066] Figures 7 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0067] Reference Figure 7 and Figure 8 , Figure 8 yes Figure 7 A top view of any fin, providing a substrate (not shown), including a substrate 100 and a fin 130 protruding from the substrate 100, the fin 130 including a channel region 130c (e.g., along the extending direction of the fin 130) Figure 8 As shown in the figure, the channel region 130c is used to form a stacked work function layer.

[0068] The substrate provides the basis for the process operations of forming the semiconductor structure. The semiconductor structure has a three-dimensional structure. In this embodiment, the semiconductor structure includes a FinFET or a fully enclosed (GAA) transistor.

[0069] The substrate includes an NMOS region 100N (e.g., ... Figure 7 (a) shown) and PMOS region 100P (as shown in) Figure 7 (b) shown) are used to form NMOS transistors and PMOS transistors, respectively.

[0070] In this embodiment, taking the semiconductor structure as a fin field-effect transistor as an example, the substrate includes a substrate 100 and a fin 130 protruding from the substrate 100.

[0071] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate 101 may be made of a material suitable for process requirements or easy to integrate.

[0072] The fin 130 is used to provide a channel for the fin field-effect transistor.

[0073] In this embodiment, the fin 130 and the substrate 100 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.

[0074] In this embodiment, the material of the fin 130 is the same as the material of the substrate 100, and the material of the fin 130 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0075] In this embodiment, along the extending direction of the fin 130, the fin 130 includes a channel region 130c (e.g., ...). Figure 8 (As shown).

[0076] The fin 130 of the channel region 130c is used as a channel for a fin field-effect transistor, and the channel region 130c is also used to form a stacked work function layer.

[0077] In this embodiment, the channel region 130c in the PMOS region 100P is used to form the stacked work function layer, which includes multiple work function layers. The work function layers are used to adjust the threshold voltage of the transistor, and the stacked work function layers are used to adjust the threshold voltage of the PMOS transistor.

[0078] In this embodiment, during the step of providing the substrate, an isolation layer 110 is also formed on the substrate, located on the substrate 100, and covering part of the sidewall of the fin 130.

[0079] The isolation layer 110 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 110 is usually formed between NMOS transistors and PMOS transistors.

[0080] The insulating layer 110 is made of an insulating material. As an example, the insulating layer 110 is made of silicon oxide.

[0081] In this embodiment, in the step of raising the substrate, an interlayer dielectric layer 120 is formed on the substrate 110, and a gate opening 140 is formed in the interlayer dielectric layer 120. The gate opening 140 spans the fin 130 and exposes the top and sidewalls of the channel region 130c of the fin 130.

[0082] The interlayer dielectric layer 120 is used to achieve isolation between adjacent devices.

[0083] The gate opening 140 is used to provide space for the subsequent formation of the metal gate structure.

[0084] The material of the interlayer dielectric layer 120 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0085] The gate opening 140 is used to provide space for the subsequent formation of the device gate structure. The gate opening 140 exposes the top and sidewalls of the channel region 130c of the fin 130, and is used to prepare for the formation of the first work function layer 310.

[0086] Continue to refer to Figure 7A gate dielectric layer 200 conformally covers the top and sidewalls of the fin 130 in the channel region 130c.

[0087] In this embodiment, the gate dielectric layer 200 conformally covers the top and sidewalls of the fin 130 of the channel region 130c, as well as the top of the isolation layer 110.

[0088] Specifically, the gate dielectric layer 200 is formed in the gate opening 140, and the gate dielectric layer 200 also conformally covers the sidewall of the gate opening 140.

[0089] The gate dielectric layer 200 is made of one or more of the following materials: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 200 is made of a high-k dielectric material, wherein a high-k dielectric material is a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k gate dielectric layer material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0090] In this embodiment, the gate dielectric layer 200 includes a gate oxide layer (not shown) and a high-k gate dielectric layer (not shown) covering the gate oxide layer. As an example, the material of the gate oxide layer is silicon oxide, and the material of the high-k gate dielectric layer is HfO2.

[0091] refer to Figure 9 A first work function layer 310 is formed in the channel region 130c to conformally cover the gate dielectric layer 200.

[0092] The first work function layer 310 is used to form a stacked work function layer in the future.

[0093] In this embodiment, the channel region 130C in the PMOS region 100P is used to form the stacked work function layer. Therefore, in the step of forming the first work function layer 310 that conformally covers the top and sidewalls of the fin 130 in the channel region 130c, the first work function layer 310 is formed in the PMOS region 100P.

[0094] The first work function layer 310 is formed in the PMOS region 100P and is used to subsequently form the stacked work function layers of the PMOS region 100P. The first work function layer 310 is used to adjust the threshold voltage of the PMOS transistor.

[0095] In this embodiment, the gate openings 140 of both the NMOS region 100N and the PMOS region 100P are exposed in the environment in which the first work function layer 310 is formed. Therefore, in the step of forming the first work function layer 310, the first work function layer 310 is also formed in the NMOS region 100N.

[0096] Furthermore, in the same subsequent step, a first work function layer 310 is formed in the PMOS region 100P and the NMOS region 100N. Other film layers will then be formed in the NMOS region 100N. The first work function layer 310 in the NMOS region 100N is removed in the same step as the other film layers, which reduces the number of photomasks and saves process costs.

[0097] In this embodiment, the first work function layer 310 is formed using atomic layer deposition (ALD).

[0098] The first work function layer 310 formed by atomic layer deposition has good thickness uniformity and good step coverage capability, which enables the first work function layer 310 to cover the bottom and sidewalls of the fin 130 of the channel region 130c in a good conformal manner.

[0099] In this embodiment, the first work function layer 310 is made of a P-type work function material, used as the work function layer of a PMOS transistor to adjust the threshold voltage of the PMOS transistor. The P-type work function material includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. As an example, the first work function layer 310 is made of TiN.

[0100] In this embodiment, in the step of forming a first work function layer 310 that conformally covers the gate dielectric layer 200, the first work function layer 310 conformally covers the fin 130 in the gate opening 140 and the bottom of the gate opening 140.

[0101] Reference Figures 10 to 12 A filling layer 330 is formed on the first work function layer 310 between adjacent fins 130. The filling layer 330 exposes at least the first work function layer 310 on the top of the fin 130. The material Fermi level of the filling layer 330 is closer to the Fermi level of the fin 130 than the material Fermi level of the stacked work function layers.

[0102] It should be noted that a second work function layer needs to be formed on the first work function layer 310 and the filling layer 330.

[0103] Since the channel region 130c is used to form a stacked work function layer (i.e., including multiple work function layers), between adjacent fins 130, as the number of work function layers increases, the space used to form each work function layer gradually decreases. This makes the stacked work function layers between adjacent fins 130 prone to void defects. In this embodiment of the invention, after forming the first work function layer 310, a filling layer 330 occupies the space between adjacent fins 130. The second work function layer is formed on top of the first work function layer 310 and the filling layer 330. This reduces the distance from the bottom of the second work function layer to the top of the fin 130 between adjacent fins 130, thus reducing the probability of void defects in the second work function layer. This improves the non-uniformity of void defects in the second work function layer and correspondingly improves the performance uniformity of the second work function layer, which in turn helps to improve the uniformity of the device threshold voltage. Furthermore, since the Fermi level of the filling layer 330 is closer to the Fermi level of the fin 130 than the material Fermi level of the stacked work function layer, the filling layer 330 has a smaller impact on the work function of the stacked work function layer. Therefore, the presence of the filling layer 330 has a smaller impact on the device threshold voltage. In summary, the performance of the semiconductor structure is improved.

[0104] In this embodiment, the channel region 130c in the PMOS region 100P is used to form the stacked work function layer. Therefore, the filling layer 330 exposes at least the first work function layer 310 on the top of the fin 130, so that the first work function layer 310 and the second work function layer are in contact, which is beneficial to the control of the threshold voltage of the transistor by the stacked work function layer.

[0105] In this embodiment, in the step of forming a filling layer 330 on the first work function layer 310 between adjacent fins 130, the filling layer 330 is formed in the PMOS region 100P. The filling layer 330 is used to fill the remaining space between adjacent fins 130 in the structure of the stacked work function layer, so as to reduce the height of the second work function layer between adjacent fins 130, thereby reducing the probability of void defects in the second work function layer.

[0106] In this embodiment, the remaining space of the gate openings 140 of the NMOS region 100N and the PMOS region 100P is exposed to the environment in which the filling layer 330 is formed. Therefore, in the PMOS region 100P and the NMOS region 100N, the filling layer 330 is formed on the first work function layer 310 between adjacent fins 130.

[0107] Furthermore, in the same subsequent step, the filling layer 330 and the first work function layer 310 in the NMOS region 100N are removed, reducing the number of photomasks and saving process costs.

[0108] In this embodiment, the process for forming the filling layer 330 includes atomic layer deposition or fluidized chemical vapor deposition.

[0109] The atomic layer deposition process or the fluidized chemical vapor deposition process has a good deposition effect, the formed filling layer 330 has good uniformity, and the atomic layer deposition process or the fluidized chemical vapor deposition process has a good gap filling ability, which can form a high-quality filling layer 330 and reduce the voids in the filling layer 330.

[0110] In this embodiment, the top of the filling layer 330 is lower than or flush with the top of the first work function layer 310, thereby ensuring that the first work function layer 310 on the top of the fin 130 can be exposed, so that the second work function layer can contact the first work function layer 310.

[0111] It should be noted that the top of the filling layer 330 cannot be too high. If the top of the filling layer 330 is too high, it will fill too much space, thereby replacing too much of the second work function layer. This could excessively weaken the control capability of the second work function layer over the threshold voltage of the transistor, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the top of the filling layer 330 is lower than or flush with the top of the first work function layer 310.

[0112] In this embodiment, the Fermi level of the material of the filling layer 330 is closer to the Fermi level of the fin 130 than the Fermi level of the material of the stacked work function layer. Therefore, the filling layer 330 has a smaller impact on the work function of the stacked work function layer. Thus, even if void defects are generated in the filling layer 330 during the formation of the filling layer 330, the presence of the filling layer 330 has a smaller impact on the device threshold voltage, thereby improving the performance of the semiconductor structure.

[0113] In this embodiment, the filling layer 330 is made of a conductive material.

[0114] The conductive material does not easily add additional resistance between the first work function layer 310 and the second work function layer, which helps to ensure the conductivity of the stacked work function layers.

[0115] In this embodiment, the material of the filling layer 330 includes tungsten.

[0116] In this embodiment, the fin 130 is made of silicon. The Fermi level of the tungsten is close to that of silicon, and the tungsten has good conductivity. Therefore, the tungsten material can satisfy the requirement of having little impact on the work function of the stacked work function layer and not easily increasing the additional resistance.

[0117] Specifically, refer to Figure 10 The step of forming the filling layer 330 includes: forming an initial filling layer 300 on the first work function layer 310, wherein the initial filling layer 300 fills the remaining space between adjacent fins 130, and the initial filling layer 300 covers the first work function layer 310 located on top of the fins 130.

[0118] The initial fill layer 300 is used to form the fill layer 330.

[0119] In this embodiment, the process for forming the initial filling layer 300 includes atomic layer deposition or flowable chemical vapor deposition.

[0120] The atomic layer deposition process or the fluidized chemical vapor deposition process has a good deposition effect, the initial filling layer 300 formed has good uniformity, and the atomic layer deposition process or the fluidized chemical vapor deposition process has a good gap filling ability, which can form a high-quality initial filling layer 300 and reduce void defects in the initial filling layer 300.

[0121] In this embodiment, in the step of forming an initial filling layer 300 on the first work function layer 310, an initial filling layer 300 that conformally covers the first work function layer 310 is formed in the remaining space between adjacent fins 130, and the initial filling layers 300 located on opposite sidewalls of the first work function layer 310 are in contact with each other.

[0122] Therefore, during the deposition of the initial filler layer 300, the bottom and sidewalls of the first work function layer 310 are used as the deposition base. The initial filler layer 300 is first formed on the bottom and sidewalls of the first work function layer 310. As the deposition thickness increases, the initial filler layers 300 located on opposite sidewalls of the first work function layer 310 come into contact, which helps to reduce the probability of void defects in the initial filler layer 300. Accordingly, in this embodiment, atomic layer deposition is used to form the initial filler layer 300.

[0123] The initial filler layer 300 is made of tungsten and is used to directly form the filler layer 330.

[0124] Continue to refer to Figure 10 The initial fill layer 330 is flattened.

[0125] The step of flattening the initial fill layer 330 is used to prepare for the subsequent definition of the height of the fill layer 330.

[0126] Specifically, the initial filler layer 330 is planarized using a chemical mechanical polishing process.

[0127] As an example, the initial fill layer 330 is planarized to expose the top of the first work function 310, thereby ensuring that the first work function layer 310 on the top of the fin 130 can be exposed, so that the second work function layer can contact the first work function layer 310.

[0128] refer to Figure 11 After planarizing the initial fill layer 300, a portion of the initial fill layer 300 is etched back, leaving the remaining thickness of the initial fill layer 300 between adjacent fins 130 as fill layer 330.

[0129] The initial fill layer 300, which is etched back to a certain thickness, is used to form the fill layer 330 and to define the height of the fill layer 330.

[0130] It should be noted that the initial filling layer 300, which is etched back to a certain thickness, forms a filling layer 330. On the basis that the second work function layer subsequently formed on the filling layer 330 is less likely to produce void defects, the height of the filling layer 330 is made as small as possible. This reduces the impact of the scheme of forming a filling layer 330 between adjacent fins 130 to replace part of the second work function layer on the threshold voltage of the device.

[0131] Reference Figure 11 and Figure 12 The formation method further includes: removing the first work function layer 310 located in the NMOS region 100N.

[0132] The first work function layer 310 located in the NMOS region 100N is removed to provide space for the subsequent formation of the second work function layer in the NMOS region 100N.

[0133] In this embodiment, before removing the first work function layer 310 located in the NMOS region 100N, the formation method further includes: removing the filling layer 330 in the NMOS region 100N.

[0134] The fill layer 330 in the NMOS region 100N is removed to expose the second work function layer in the NMOS region 100N, thereby preparing for the removal of the second work function layer in the NMOS region 100N to ensure the normal performance of the NMOS transistor.

[0135] Specifically, refer to Figure 11The step of removing the first work function layer 310 and the fill layer 330 located in the NMOS region 100N includes: forming a mask layer 400 in the PMOS region 100P that covers the first work function layer 310 and the fill layer 330.

[0136] The mask layer 400 is used as an etching mask to remove the first work function layer 310 and the fill layer 330 located in the NMOS region 100N.

[0137] In this embodiment, the mask layer 400 is a non-metallic mask layer, and the material of the mask layer 400 includes one or more of silicon oxide and silicon nitride, that is, the mask layer 400 can be a single-layer structure or a stacked structure. As an example, the material of the mask layer 400 is silicon nitride, that is, the mask layer 300 is a single-layer structure.

[0138] Specifically, the mask layer 400 is formed using a chemical vapor deposition process.

[0139] refer to Figure 12 Using the mask layer 400 as a mask, the filling layer 330 and the first work function layer 310 of the NMOS region 100N are removed.

[0140] By removing the fill layer 330 and the first work function layer 310 of the NMOS region 100N, the gate opening 140 of the NMOS region 100N is exposed, providing space for the subsequent formation of the second work function layer. Furthermore, the same mask layer 400 is used as the mask (i.e., a single photomask is shared). Removing the fill layer 330 and the first work function layer 310 of the NMOS region 100N in the same process simplifies the process flow, improves process efficiency, and saves process costs.

[0141] In this embodiment, a dry etching process is used to remove the first work function layer 310 and the fill layer 330 located in the NMOS region 100N.

[0142] The dry etching process has anisotropic etching characteristics. Therefore, by selecting the dry etching process, it is beneficial to reduce damage to other film layers during the removal of the first work function layer 310 and the filling layer 330 located in the NMOS region 100N.

[0143] In this embodiment, after removing the filling layer 330 and the first work function layer 310 of the NMOS region 100N, the mask layer 400 is removed.

[0144] The mask layer 400 is removed to prepare for subsequent process steps.

[0145] refer to Figure 13A second work function layer 320 is formed, covering the first work function layer 310 and the fill layer 330. The second work function layer 320 and the first work function layer 310 are used to form a stacked work function layer 340.

[0146] In the PMOS region 100P, the second work function layer 320 is used to form the stacked work function layer 340 of the PMOS region 100P, and the second work function layer 320 and the first work function layer 310 in the PMOS region 100P are used together to adjust the threshold voltage of the PMOS transistor.

[0147] In the NMOS region 100N, the second work function layer 320 is used to form the work function layer of the NMOS region 100N. The second work function layer 320 in the NMOS region 100N is used to adjust the threshold voltage of the NMOS transistor.

[0148] In this embodiment, in the step of forming a second work function layer 320 covering the first work function layer 310 and the fill layer 330, the second work function layer 320 covers the first work function layer 310 and the fill layer 330 of the PMOS region 100P, and the second work function layer 320 and the first work function layer 310 are used together to form a stacked work function layer 340.

[0149] In this embodiment, in the step of forming a second work function layer 320 covering the first work function layer 310 and the fill layer 330, in the NMOS region 100N, the second work function layer 320 also covers the gate dielectric layer 200, and the second work function layer 320 is used to constitute the work function layer of the NMOS region 100N.

[0150] As an example, in the NMOS region 100N, the second work function layer 320 fills the gate opening 140 and covers the gate dielectric layer 200.

[0151] In this embodiment, the material of the second work function layer 320 is an N-type work function material, used as the work function layer of the NMOS transistor. The N-type work function material includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. As an example, the material of the second work function layer 320 is TiAl.

[0152] refer to Figure 14 The forming method further includes: forming a metal gate electrode layer 500 covering the second work function layer 320.

[0153] The metal gate electrode layer 500 is used to form a metal gate structure with the work function layer.

[0154] Specifically, in the PMOS region 100P, the metal gate electrode layer 500, the first work function layer 310, and the second work function layer 320 constitute the metal gate structure of the PMOS transistor, and in the NMOS region 100N, the metal gate electrode layer 500 and the second work function layer 320 constitute the metal gate structure of the NMOS transistor.

[0155] The metal gate electrode layer 500 is used to draw out the electrical properties of the metal gate structure. In this embodiment, the material of the metal gate electrode layer 500 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0156] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a substrate and a fin protruding from the substrate, wherein the fin includes a channel region along the extending direction of the fin, the channel region being used to form a stacked work function layer; A gate dielectric layer conformally covers the top and sidewalls of the fins in the channel region; The first work function layer conformally covers the gate dielectric layer; A filling layer is located on the first work function layer between adjacent fins, the filling layer at least exposes the first work function layer at the top of the fins, and the material Fermi level of the filling layer is closer to the Fermi level of the fins than the material Fermi level of the stacked work function layers; The second work function layer covers the first work function layer and the fill layer, and the second work function layer and the first work function layer are used to form a stacked work function layer.

2. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a PMOS region, and the channel region in the PMOS region is used to form the stacked work function layer; The first work function layer is located in the PMOS region; The filling layer is located in the PMOS region; The second work function layer covers the first work function layer and the fill layer of the PMOS region.

3. The semiconductor structure as described in claim 2, characterized in that, The substrate also includes an NMOS region; The material of the first work function layer is a P-type work function material; The second work function layer is also located in the NMOS region and covers the gate dielectric layer. The material of the second work function layer is an N-type work function material.

4. The semiconductor structure as described in claim 1, characterized in that, The top of the filling layer is lower than or flush with the top of the first function layer.

5. The semiconductor structure as described in claim 1, characterized in that, The filling layer is made of a conductive material.

6. The semiconductor structure as described in claim 5, characterized in that, The filling layer is made of tungsten.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

8. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a metal gate electrode layer covering the second work function layer.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a fin protruding from the substrate, wherein the fin includes a channel region along the extension direction of the fin, the channel region being used to form a stacked work function layer; A conformal gate dielectric layer is formed in the channel region, covering the top and sidewalls of the fin; A first work function layer is formed in the channel region to conformally cover the gate dielectric layer; A filling layer is formed on the first work function layer between adjacent fins, the filling layer at least exposing the first work function layer at the top of the fins, and the material Fermi level of the filling layer is closer to the Fermi level of the fins than the material Fermi level of the stacked work function layers; A second work function layer is formed that covers the first work function layer and the fill layer. The second work function layer and the first work function layer are used to constitute a stacked work function layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing a substrate, the substrate includes a PMOS region, and the channel region in the PMOS region is used to form the stacked work function layer; In the step of forming a first work function layer that conformally covers the top and sidewalls of the fin in the channel region, the first work function layer is formed in the PMOS region; In the step of forming a fill layer on the first work function layer between adjacent fins, the fill layer is formed in the PMOS region; In the step of forming a second work function layer covering the first work function layer and the fill layer, the second work function layer covers the first work function layer and the fill layer of the PMOS region.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the filling layer includes: forming an initial filling layer on the first work function layer, the initial filling layer filling the remaining space between adjacent fins, and the initial filling layer covering the first work function layer located on top of the fins; Flatten the initial fill layer; After planarizing the initial fill layer, a portion of the initial fill layer thickness is etched back, leaving the remaining thickness of the initial fill layer between adjacent fins as the fill layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming an initial filling layer on the first work function layer, an initial filling layer that conformally covers the first work function layer is formed in the remaining space between adjacent fins, and the initial filling layers located on opposite sidewalls of the first work function layer are in contact with each other.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing a substrate, the substrate further includes an NMOS region; In the step of forming a first work function layer that conformally covers the gate dielectric layer in the channel region, the material of the first work function layer is a P-type work function material; In the step of forming a second work function layer covering the first work function layer and the fill layer, in the NMOS region, the second work function layer also covers the gate dielectric layer, and the material of the second work function layer is an N-type work function material.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the first work function layer, the first work function layer is also formed in the NMOS region; The formation method further includes: removing the first work function layer located in the NMOS region.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, Before removing the first work function layer located in the NMOS region, the filling layer is formed on the first work function layer between adjacent fins in the PMOS region and the NMOS region; Before removing the first work function layer located in the NMOS region, the formation method further includes: removing the filling layer in the NMOS region.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The step of removing the first work function layer and the fill layer located in the NMOS region includes: forming a mask layer covering the first work function layer and the fill layer in the PMOS region; Using the mask layer as a mask, the filling layer and the first work function layer of the NMOS region are removed; After removing the fill layer and the first work function layer of the NMOS region, the mask layer is removed.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The first work function layer and the fill layer located in the NMOS region are removed using a dry etching process.

18. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process for forming the filling layer includes atomic layer deposition or flowable chemical vapor deposition.

19. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the filling layer, the top of the filling layer is lower than or flush with the top of the first work function layer.

20. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before forming a first work function layer that conformally covers the fin, the method further includes: forming an interlayer dielectric layer on the substrate, wherein a gate opening is formed in the interlayer dielectric layer, the gate opening spans the fin and exposes the top and sidewalls of the channel region of the fin; In the step of forming a first work function layer that conformally covers the fin, the first work function layer conformally covers the fin exposed by the gate opening and the bottom of the gate opening.

21. The method for forming a semiconductor structure as described in claim 9, characterized in that, The forming method further includes: forming a metal gate electrode layer covering the second work function layer.

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