P-epitaxial bcd-on-soi integration technology and complementary bipolar devices
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING ZHONGKE YUXIN ELECTRONICS
- Filing Date
- 2026-03-13
- Publication Date
- 2026-06-23
Smart Images
Figure CN122269798A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuits, specifically to P-epitaxial BCD-on-SOI integration technology and complementary bipolar transistor devices. Background Technology
[0002] With the rapid development of automobiles, computers and industrial automation, bulk silicon BCD (Bipolar-CMOS-DMOS) technology has been widely adopted, enabling chip designers to flexibly and reliably integrate power, analog and digital signal processing circuits on a single chip.
[0003] BCD-on-SOI technology combines the highly attractive characteristics of SOI (Silicon-on-Insulator) and DTI (Deep Trench Isolation). Compared to bulk silicon BCD processes, dielectric isolation offers advantages such as low parasitic substrate capacitance, no leakage current paths, and smaller isolation distances between high-voltage devices. Therefore, the new BCD-on-SOI technology exhibits high robustness. It can cover a wider operating temperature range and also provides higher EMI immunity.
[0004] In the fields of medical equipment and precision instruments, bipolar transistors (BJTs) have become the best choice due to their excellent amplification and matching performance. However, in the development of bipolar integrated circuits, the load power has been continuously increasing. The increase in load power has reached the safety limits set by system heat dissipation (power dissipation) and rated power. The insulating oxide layer and the silicon layer on top of it in SOI processes limit the process integration of bipolar transistors.
[0005] Solving the technical challenges of integrating complementary bipolar transistors in BCD-on-SOI technology has always been a difficult and hot topic of concern for scientists and engineers. Summary of the Invention
[0006] The purpose of this invention is to provide a method for manufacturing P-epitaxial BCD-on-SOI integration technology and complementary bipolar transistor devices, comprising the following steps:
[0007] Step 1) Form an N-type buried layer and a P-type buried layer on a P-type substrate silicon wafer;
[0008] Step 2) Generate SOI (Silicon Insulator On Wafer) with P-type epitaxial silicon as the device layer;
[0009] Step 3) Grow the thermo-oxidative liner layer;
[0010] Step 4) Deposit a low-stress silicon nitride dielectric layer;
[0011] Step 5) Deposit a silicon dioxide dielectric layer;
[0012] Step 6) Expose and etch the isolation trench;
[0013] Step 7) Grow the sidewall liner silica layer;
[0014] Step 8) Deposit polycrystalline silicon to fill the isolation trench, the polycrystalline silicon film serving as a composite isolation medium;
[0015] Step 9) Remove excess polysilicon;
[0016] Step 10) Grow an oxide medium layer;
[0017] Step 11) On the N-type buried layer, a deep trench is created by photomask exposure and plasma dry etching, which penetrates the insulating oxide layer of the SOI wafer to the substrate.
[0018] Step 12) Grow the sidewall liner silica layer;
[0019] Step 13) Remove the silica medium lining the sidewalls of the deep trench;
[0020] Step 14) In-situ doping and filling of the N-type silicon film is performed using RPCVD;
[0021] Step 15) Remove excess N-type silicon;
[0022] Step 16) On the P-type buried layer, a deep trench is formed by photomask exposure and plasma dry etching, which will penetrate the insulating oxide layer of the SOI wafer to the substrate.
[0023] Step 17) Grow the sidewall liner silica layer;
[0024] Step 18) Remove the silica medium lining the sidewalls of the deep trench;
[0025] Step 19) P-type silicon film is filled by in-situ doping using RPCVD;
[0026] Step 20) Remove excess P-type silicon;
[0027] Step 21) Complete the required N-type collector region implantation, P-type base region implantation, N-type collector-side well implantation, N-type drain-side well implantation for VDMOS transistors, N-type interconnect implantation and well drive-in of the substrate silicon wafer under SOI insulation according to the requirements of Bipolar-CMOS-DMOS process devices;
[0028] Step 22) Complete the required N-type base region implantation, P-type collector-side well implantation, SOI-insulated substrate silicon wafer P-type interconnect implantation, and well drive-up for PNP transistors according to the requirements of Bipolar-CMOS-DMOS process devices;
[0029] Step 23) Complete the fabrication of the active region, isolation region, gate oxide, MOS source-drain ohmic contact, and Bipolar collector-base-emitter ohmic contact according to the requirements of the Bipolar-CMOS-DMOS process device;
[0030] Step 24) Deposit LPTEOS and USG silica films and planarize them using CMP process;
[0031] Step 25) Use an exposure etching process to form contact holes and complete the tungsten plug and metal interconnect structure.
[0032] Furthermore, in step 1), the N-type buried layer and the P-type buried layer formed on the P-type substrate silicon wafer are respectively an arsenic buried layer and a boron buried layer.
[0033] Furthermore, an N-type external collector region is formed in the annular deep trench dielectric isolation region to interconnect with the N-type buried layer of the substrate silicon wafer.
[0034] Furthermore, a P-type external collector region is formed in the annular deep trench dielectric isolation region to interconnect with the P-type buried layer of the substrate silicon wafer.
[0035] Furthermore, N-type epitaxy is formed in the annular deep trench dielectric isolation region, and low-resistance interconnection is achieved by side-well N-type injection.
[0036] Furthermore, the annular deep trench dielectric isolation region forms a P-type epitaxial layer, and low-resistance interconnection is achieved by side-well P-type injection.
[0037] Furthermore, the N-type buried layer and the P-type buried layer on the surface of the P-type substrate silicon wafer (101) form an ESD self-protection structure for the PN junction diode.
[0038] Furthermore, in step 1), ion implantation technology is used to form N-type and P-type buried layers;
[0039] In step 2), a thermal bonding technique is used to generate an SOI (Silicon-on-Insulator) wafer;
[0040] In step 3), the thermo-oxidative liner layer is grown using the thermo-oxidative method;
[0041] In step 4), a low-stress silicon nitride dielectric layer is deposited using low-pressure chemical vapor deposition (LPCVD).
[0042] In step 5), a silicon dioxide dielectric layer is deposited using low-pressure chemical vapor deposition (LPCVD).
[0043] In step 6), isolation trenches are etched using plasma dry etching.
[0044] Step 7) In the process of growing a sidewall liner silica layer using the thermo-oxidative method;
[0045] In step 8), polycrystalline silicon is deposited into a filling isolation trench using low-pressure chemical vapor deposition technology.
[0046] Furthermore, in step 10), a polysilicon back-etching process is used to remove excess polysilicon;
[0047] In step 12), a deep trench is created using photomask exposure and plasma dry etching.
[0048] In step 13), a sidewall liner silica layer is grown using thermal oxidation.
[0049] In step 15), an N-type silicon film layer is filled by in-situ doping using RPCVD;
[0050] In step 17), a deep trench is created using photomask exposure and plasma dry etching.
[0051] In step 18), a sidewall liner silica layer is grown using thermal oxidation.
[0052] In step 20), RPCVD is used to in-situ dope-fill the P-type silicon film.
[0053] In step 21), excess P-type silicon is removed using a silicon etch-back process.
[0054] The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar transistor devices manufactured using the method mainly consist of a P-type substrate silicon wafer, an N-type buried layer, a P-type buried layer, an insulating silicon dioxide buried layer, a P-type device layer, a dielectric isolation trench region, an N-type epitaxial layer, a P-type epitaxial layer, a gate dielectric layer, a polycrystalline thin film, an oxide thin film, a tungsten plug, and a metal thin film layer.
[0055] The P-type substrate silicon wafer is located at the bottom; the N-type buried layer and the P-type buried layer are formed on the surface of the substrate silicon wafer.
[0056] An insulating silicon dioxide buried layer is formed between the substrate silicon wafer and the device layer silicon wafer.
[0057] The N-type epitaxial layer is formed in the N-type buried layer of the substrate and the N-type vertical side well trench region of the device layer;
[0058] The P-type epitaxial layer is formed in the P-type buried layer of the substrate and the P-type vertical side well region of the device layer;
[0059] The polycrystalline isolation film is located in the middle of the isolation trench;
[0060] The tungsten plug and the metal interconnect film have a planar structure;
[0061] NMOS and PMOS form a complementary structure;
[0062] Vertical NPN and vertical PNP form a complementary architecture;
[0063] The N-type buried layer of the SOI substrate silicon wafer in the NPN external collector region and the P-type buried layer of the substrate silicon wafer in the PNP external collector region form a PN junction ESD protection structure.
[0064] The technical effects of this invention are undeniable. This invention not only solves the problem of integrating complementary bipolar transistors with BCD-on-SOI process technology, but also solves the problem of high-density standard device integration, and solves the problems of parasitic capacitance and floating potential effect of substrate-buried oxide-device layer in BCD-on-SOI all-dielectric isolation process.
[0065] This invention employs a deep trench dielectric isolation region, followed by N-type side-well implantation after trench etching, forming a low-resistance interconnect structure with the N-type buried layer of the substrate. This structure enables planar lead-out of the collector of the vertical NPN transistor, reduces parasitic capacitance, improves device characteristic frequency and other performance characteristics, and enhances the reliability of P-type epitaxial BCD-on-SOI process integrated circuits.
[0066] This invention employs a deep trench dielectric isolation region, followed by P-type sidewell implantation after trench etching, forming a low-resistance interconnect structure with the P-type buried layer of the substrate. This structure enables planar lead-out of the vertical PNP transistor collector and simultaneously achieves a complementary process architecture with NPN transistors, reducing circuit design complexity and increasing the coverage of P-type epitaxial BCD-on-SOI integrated circuits.
[0067] This invention forms a PN junction ESD protection structure by using the N-type buried layer of the SOI substrate silicon wafer in the NPN external collector region and the P-type buried layer of the substrate silicon wafer under SOI insulation in the PNP external collector region. This reduces the parasitic resistance of the NPN and PNP external collectors, reduces the influence of substrate noise, and effectively improves the ESD self-protection capability of complementary bipolar transistors on the P-epitaxial BCD-on-SOI process platform. Attached Figure Description
[0068] Figure 1 A cross-sectional view of silicon-on-insulator (SOI) grown using thermal bonding technology after forming N-type and P-type buried layer structures on a P-type substrate.
[0069] Figure 2 To complete the structural cross-section diagram after the deep trench isolation DTI is manufactured;
[0070] Figure 3 A cross-sectional view showing the completion of deep trench etching and N-type and P-type epitaxial filling;
[0071] Figure 4 To complete the N-type and P-type side-well injection, active region and isolation region fabrication profiles;
[0072] Figure 5A cross-sectional view to complete the integration of complementary vertical NPN and PNP devices;
[0073] Figure 6 A cross-sectional view showing the integration of VD-NMOS and PMOS devices;
[0074] Figure 7 This is a cross-sectional view of Example 1, showing the P-epitaxial BCD-on-SOI integration technology and complementary bipolar transistor device.
[0075] Figure 8 This refers to P-epitaxial BCD-on-SOI integration technology and complementary bipolar transistor devices;
[0076] In the diagram, 101 represents a P-type base;
[0077] 102, silicon dioxide layer;
[0078] 103, deep trench isolation polycrystalline filled dielectric layer;
[0079] 104, N-type collector-side well in the device layer;
[0080] 105, Insulating silica buried layer;
[0081] 106, P-type device layer on insulator;
[0082] 107, P-type buried layer;
[0083] 108, P-type collector-side well in device layer;
[0084] 201, VNMOS drain, VNPN collector N-type epitaxial-N-side well interconnect low-resistivity layer;
[0085] 202, P-body region of VNMOS and VNPN transistors;
[0086] 203, VPNP external collector region base P-type buried layer - device P-type epitaxial layer - P-type side well interconnect low-resistivity layer;
[0087] 204, ILD dielectric layer between device and metal layer 1;
[0088] 205, Tungsten plug structure for contact holes between device and metal layer 1;
[0089] 206, First layer interconnect metal layer region. Detailed Implementation
[0090] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.
[0091] Example 1:
[0092] See Figures 1 to 7 The P-epitaxial BCD-on-SOI integration technology and the fabrication method of complementary bipolar transistor devices include the following steps:
[0093] Step 1) Form an N-type buried layer and a P-type buried layer 107 on the P-type substrate silicon wafer 101;
[0094] Step 2) Generate SOI on-insulator wafer, with device layer 106 being P-type epitaxial silicon;
[0095] Before bonding, corresponding to the N-type and P-type buried layers of the substrate silicon wafer in step 1), a buried layer of the same doping type is formed at the bottom of device layer 106.
[0096] Step 3) Grow the thermo-oxidative liner layer;
[0097] Step 4) Deposit a low-stress silicon nitride dielectric layer;
[0098] Step 5) Deposit a silicon dioxide dielectric layer;
[0099] Step 6) Expose and etch the isolation trench;
[0100] Step 7) Grow the sidewall liner silica layer 102;
[0101] Step 8) Deposit polysilicon to fill the isolation trench, the polysilicon film 103 serving as a composite isolation medium;
[0102] Step 9) Remove excess polysilicon;
[0103] Step 10) Grow an oxide medium layer;
[0104] Step 11) On the N-type buried layer, a deep trench is created by photomask exposure and plasma dry etching, which penetrates the insulating oxide layer of the SOI wafer to the substrate.
[0105] Step 12) Grow the sidewall liner silica layer;
[0106] Step 13) Remove the silica medium lining the sidewalls of the deep trench;
[0107] Step 14) The N-type silicon film is filled by in-situ doping using RPCVD, and a low-resistivity layer 201 for the VNMOS drain and VNPN collector N-type epitaxial-side well interconnect is formed.
[0108] Step 15) Remove excess N-type silicon;
[0109] Step 16) On the P-type buried layer, a deep trench is formed by photomask exposure and plasma dry etching, which will penetrate the insulating oxide layer of the SOI wafer to the substrate.
[0110] Step 17) Grow the sidewall liner silica layer;
[0111] Step 18) Remove the silica medium lining the sidewalls of the deep trench;
[0112] Step 19) P-type silicon film layer is filled by in-situ doping using RPCVD to form a low-resistivity layer 203 for substrate P-type buried layer-device P-type epitaxial layer-side well interconnect.
[0113] Step 20) Remove excess P-type silicon;
[0114] Step 21) Complete the required N-type collector region implantation, P-type base region implantation, N-type collector-side well 104 implantation for NPN transistors, N-type drain-side well implantation for VDMOS transistors, N-type interconnect implantation and well drive-in of the substrate silicon wafer under SOI insulation according to the requirements of Bipolar-CMOS-DMOS process devices;
[0115] Step 22) Complete the N-type base region implantation, P-type collector-side well 108 implantation, SOI-insulated substrate silicon wafer P-type interconnect implantation and well drive-in according to the Bipolar-CMOS-DMOS process device requirements to form the P-body region 202 of VNMOS and VNPN transistors;
[0116] Step 23) Complete the fabrication of the active region, isolation region, gate oxide, MOS source-drain ohmic contact, and Bipolar collector-base-emitter ohmic contact according to the requirements of the Bipolar-CMOS-DMOS process device;
[0117] Step 24) Deposit LPTEOS and USG silicon dioxide thin films and planarize them using CMP process to form ILD dielectric layer 204 between device-metal layer 1;
[0118] Step 25) Use an exposure etching process to form contact holes and complete the fabrication of the tungsten plug and metal interconnect structure 205.
[0119] Example 2:
[0120] The P-epitaxial BCD-on-SOI integration technology and the manufacturing method of complementary bipolar transistor devices are the same as in Example 1. Further, in step 1), the N-type buried layer and the P-type buried layer formed on the P-type substrate silicon wafer are arsenic buried layer and boron buried layer, respectively.
[0121] Example 3:
[0122] The P-epitaxial BCD-on-SOI integration technology and the manufacturing method of complementary bipolar transistor devices are the same as any one of Examples 1-2. Further, an N-type external collector region is formed in the annular deep trench dielectric isolation region to interconnect with the N-type buried layer of the base silicon wafer.
[0123] Example 4:
[0124] The P-type epitaxial BCD-on-SOI integration technology and the manufacturing method of complementary bipolar transistor devices are the same as any one of Examples 1-3. Further, a P-type external collector region is formed in the annular deep trench dielectric isolation region to interconnect with the P-type buried layer of the substrate silicon wafer.
[0125] Example 5:
[0126] The P-type epitaxial BCD-on-SOI integration technology and the manufacturing method of complementary bipolar transistor devices are the same as any one of Examples 1-4. Furthermore, an N-type epitaxial layer is formed in the annular deep trench dielectric isolation region, and a side-well N-type injection is used to achieve low-resistance interconnection.
[0127] Example 6:
[0128] The P-type epitaxial BCD-on-SOI integration technology and the manufacturing method of complementary bipolar transistor devices are the same as any one of Examples 1-5. Furthermore, the P-type epitaxial layer formed by the annular deep trench dielectric isolation region is used to achieve low-resistance interconnection by side-well P-type injection.
[0129] Example 7:
[0130] The P-type epitaxial BCD-on-SOI integration technology and the manufacturing method of complementary bipolar transistor devices are the same as any one of Examples 1-6. Furthermore, the N-type buried layer and the P-type buried layer on the surface of the P-type substrate silicon wafer 101 form an ESD self-protection structure for a PN junction diode.
[0131] Example 8:
[0132] The P-epitaxial BCD-on-SOI integration technology and the manufacturing method of complementary bipolar transistor devices are the same as any one of Examples 1-7. Further, in step 1), ion implantation technology is used to form an N-type buried layer and a P-type buried layer.
[0133] In step 2), a thermal bonding technique is used to generate an SOI (Silicon-on-Insulator) wafer;
[0134] In step 3), the thermo-oxidative liner layer is grown using the thermo-oxidative method;
[0135] In step 4), a low-stress silicon nitride dielectric layer is deposited using low-pressure chemical vapor deposition (LPCVD).
[0136] In step 5), a silicon dioxide dielectric layer is deposited using low-pressure chemical vapor deposition (LPCVD).
[0137] In step 6), isolation trenches are etched using plasma dry etching.
[0138] Step 7) In the process of growing a sidewall liner silica layer using the thermo-oxidative method;
[0139] In step 8), polycrystalline silicon is deposited into a filling isolation trench using low-pressure chemical vapor deposition technology.
[0140] Example 9:
[0141] The P-epitaxial BCD-on-SOI integration technology and the manufacturing method of complementary bipolar transistor devices are the same as any one of Examples 1-8. Further, in step 10), a polysilicon back-etching process is used to remove excess polysilicon.
[0142] In step 12), a deep trench is created using photomask exposure and plasma dry etching.
[0143] In step 13), a sidewall liner silica layer is grown using thermal oxidation.
[0144] In step 15), an N-type silicon film layer is filled by in-situ doping using RPCVD;
[0145] In step 17), a deep trench is created using photomask exposure and plasma dry etching.
[0146] In step 18), a sidewall liner silica layer is grown using thermal oxidation.
[0147] In step 20), RPCVD is used to in-situ dope-fill the P-type silicon film.
[0148] In step 21), excess P-type silicon is removed using a silicon etch-back process.
[0149] Example 10:
[0150] The P-epitaxial BCD-on-SOI integration technology and the manufacturing method of complementary bipolar transistor devices are the same as any one of Examples 1-9. Further, in step 5), a T3 nanometer silicon dioxide dielectric layer is deposited, where T3 = 40nm polycrystalline + 80nm-240nm silicon nitride.
[0151] Example 11:
[0152] The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar transistor device fabricated using any one of the methods described in Examples 1-9 have the following main film layers: P-type substrate silicon wafer, N-type buried layer, P-type buried layer, insulating silicon dioxide buried layer 105, P-type device layer, dielectric isolation trench region, N-type epitaxy, P-type epitaxy, gate dielectric layer, polycrystalline thin film, oxide thin film, tungsten plug and metal thin film layer;
[0153] The P-type substrate silicon wafer is located at the bottom; the N-type buried layer and the P-type buried layer are formed on the surface of the substrate silicon wafer.
[0154] An insulating silicon dioxide buried layer is formed between the substrate silicon wafer and the device layer silicon wafer.
[0155] The N-type epitaxial layer is formed in the N-type buried layer of the substrate and the N-type vertical side well trench region of the device layer;
[0156] The P-type epitaxial layer is formed in the P-type buried layer of the substrate and the P-type vertical side well region of the device layer;
[0157] The polycrystalline isolation film is located in the middle of the isolation trench;
[0158] The tungsten plug and the metal interconnect film have a planar structure;
[0159] NMOS and PMOS form a complementary structure;
[0160] Vertical NPN and vertical PNP form a complementary architecture;
[0161] The N-type buried layer of the SOI substrate silicon wafer in the NPN external collector region and the P-type buried layer of the substrate silicon wafer in the PNP external collector region form a PN junction ESD protection structure.
[0162] Example 11:
[0163] The P-epitaxial BCD-on-SOI integration technology and complementary bipolar transistor devices mainly include the following steps:
[0164] 1) An N-type (arsenic) buried layer and a P-type (boron) buried layer are formed on a P-type substrate silicon wafer using ion implantation technology;
[0165] Forming N-type buried layers and P-type buried layers on a P-type substrate is beneficial for vertical isolation of DMOS devices, reducing substrate noise, and improving circuit accuracy.
[0166] 2) SOI (Silicon Insulator On Wafer) is generated using thermal bonding technology, and the device layer is a P-type silicon epitaxial layer;
[0167] 3) The thermo-oxidative liner layer is grown using the thermo-oxidative method;
[0168] 4) Low-stress silicon nitride dielectric layers are deposited using low-pressure chemical vapor deposition (LCV) technology;
[0169] 5) A silica dielectric layer is deposited using low-pressure chemical vapor deposition (LCV) technology;
[0170] 6) Expose and etch isolation trenches using plasma dry etching;
[0171] 7) The sidewall liner silica layer is grown using the thermo-oxidative method;
[0172] 8) Polycrystalline silicon is deposited in the isolation trench using low-pressure chemical vapor deposition technology, and the polycrystalline silicon film serves as the composite isolation medium;
[0173] 10) Use a polysilicon etch-back process to remove excess polysilicon;
[0174] 11) An oxide medium layer was grown using a thermo-oxidative method;
[0175] 12) On the N-type buried layer, a deep trench is created by photomask exposure and plasma dry etching, which penetrates the insulating oxide layer of the SOI wafer to the substrate.
[0176] 13) A silica layer is grown by thermal oxidation to line the sidewalls;
[0177] 14) Wet cleaning method is used to remove the silica media from the sidewall lining of the deep tank;
[0178] 15) In-situ doping and filling of N-type silicon films was performed using RPCVD;
[0179] Using in-situ doping during N-type epitaxy growth via RPCVD is beneficial for uniform impurity distribution in this critical layer and improves device performance.
[0180] 16) Use silicon etch-back process to remove excess N-type silicon;
[0181] 17) On the P-type buried layer, a deep trench is formed by photomask exposure and plasma dry etching, which penetrates the insulating oxide layer of the SOI wafer to the substrate.
[0182] 18) A silica layer is grown using thermal oxidation to line the sidewalls;
[0183] 19) Wet cleaning was used to remove the silica media from the sidewall lining of the deep tank;
[0184] 20) P-type silicon films were filled using in-situ doping via RPCVD;
[0185] Using in-situ doping during P-type epitaxy growth via RPCVD is beneficial for uniform impurity distribution in this critical layer and improves device performance.
[0186] 21) Use silicon etch-back process to remove excess P-type silicon;
[0187] 22) Complete the required N-type collector region implantation, P-type base region implantation, N-type collector-side well implantation for NPN transistors, N-type drain-side well implantation for VDMOS transistors, N-type interconnect implantation and well drive-in of the substrate silicon wafer under SOI insulation according to the requirements of Bipolar-CMOS-DMOS process devices;
[0188] Employing a dual-polycrystalline self-aligned structure with a polycrystalline external base region and a polycrystalline emitter region, the complementary bipolar transistor achieves higher frequencies, lower base-emitter parasitic capacitance, and superior device performance.
[0189] Polycrystalline base region technology is compatible with MOS gate polycrystalline technology.
[0190] 23) Complete the required N-type base region injection, P-type collector-side well injection, SOI-insulated substrate silicon wafer P-type interconnect injection, and well drive-up for PNP transistors according to the requirements of Bipolar-CMOS-DMOS process devices;
[0191] 24) Complete the fabrication of the active region, isolation region, gate oxide, MOS source-drain ohmic contact, and Bipolar collector-base-emitter ohmic contact according to the requirements of Bipolar-CMOS-DMOS process devices;
[0192] 25) Deposit LPTEOS and USG silica thin films and planarize them using CMP process;
[0193] 26) Contact holes are formed using an exposure etching process to complete the tungsten plug and metal interconnect structure. The first interconnect metal layer region in the structure is shown in 206.
Claims
1. A method for manufacturing P-epitaxial BCD-on-SOI integrated technology and complementary bipolar transistor devices, characterized in that, Includes the following steps: Step 1) Form an N-type buried layer and a P-type buried layer on a P-type substrate silicon wafer; Step 2) Generate SOI (Silicon Insulator On Wafer) with P-type epitaxial silicon as the device layer; Step 3) Grow the thermo-oxidative liner layer; Step 4) Deposit a low-stress silicon nitride dielectric layer; Step 5) Deposit a silicon dioxide dielectric layer; Step 6) Expose and etch the isolation trench; Step 7) Grow the sidewall liner silica layer; Step 8) Deposit polycrystalline silicon to fill the isolation trench, the polycrystalline silicon film serving as a composite isolation medium; Step 9) Remove excess polysilicon; Step 10) Grow an oxide medium layer; Step 11) On the N-type buried layer, a deep trench is created by photomask exposure and plasma dry etching, which penetrates the insulating oxide layer of the SOI wafer to the substrate. Step 12) Grow the sidewall liner silica layer; Step 13) Remove the silica medium lining the sidewalls of the deep trench; Step 14) In-situ doping and filling of the N-type silicon film is performed using RPCVD; Step 15) Remove excess N-type silicon; Step 16) On the P-type buried layer, a deep trench is formed by photomask exposure and plasma dry etching, which will penetrate the insulating oxide layer of the SOI wafer to the substrate. Step 17) Grow the sidewall liner silica layer; Step 18) Remove the silica medium lining the sidewalls of the deep trench; Step 19) P-type silicon film is filled by in-situ doping using RPCVD; Step 20) Remove excess P-type silicon; Step 21) Complete the required N-type collector region implantation, P-type base region implantation, N-type collector-side well implantation, N-type drain-side well implantation for VDMOS transistors, N-type interconnect implantation and well drive-in of the substrate silicon wafer under SOI insulation according to the requirements of Bipolar-CMOS-DMOS process devices; Step 22) Complete the required N-type base region implantation, P-type collector-side well implantation, SOI-insulated substrate silicon wafer P-type interconnect implantation, and well drive-up for PNP transistors according to the requirements of Bipolar-CMOS-DMOS process devices; Step 23) Complete the fabrication of the active region, isolation region, gate oxide, MOS source-drain ohmic contact, and Bipolar collector-base-emitter ohmic contact according to the requirements of the Bipolar-CMOS-DMOS process device; Step 24) Deposit LPTEOS and USG silica films and planarize them using CMP process; Step 25) Use an exposure etching process to form contact holes and complete the tungsten plug and metal interconnect structure.
2. The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar junction device according to claim 1, characterized in that: In step 1), the N-type buried layer and the P-type buried layer formed on the P-type substrate silicon wafer (101) are arsenic buried layer and boron buried layer, respectively.
3. The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar junction device according to claim 1, characterized in that: In step 11), an N-type external collector region is formed in the annular deep trench dielectric isolation region to interconnect with the N-type buried layer of the substrate silicon wafer.
4. The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar junction device according to claim 1, characterized in that: In step 16), a P-type external collector region is formed in the annular deep trench dielectric isolation region to interconnect with the P-type buried layer of the substrate silicon wafer.
5. The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar transistor device according to claim 1, characterized in that: In step 14), an N-type epitaxial layer is formed in the annular deep trench dielectric isolation region, and low-resistance interconnection is achieved by side-well N-type injection.
6. The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar junction device according to claim 1, characterized in that: In step 19), the annular deep trench dielectric isolation region forms a P-type epitaxial layer, and low-resistance interconnection is achieved by side-well P-type injection.
7. The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar junction device according to claim 1, characterized in that: In step 1), the N-type buried layer and the P-type buried layer on the surface of the P-type substrate silicon wafer (101) form the ESD self-protection structure of the PN junction diode.
8. The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar junction device according to claim 1, characterized in that: In step 1), ion implantation technology is used to form N-type and P-type buried layers; In step 2), a thermal bonding technique is used to generate an SOI (Silicon-on-Insulator) wafer; In step 3), the thermo-oxidative liner layer is grown using the thermo-oxidative method; In step 4), a low-stress silicon nitride dielectric layer is deposited using low-pressure chemical vapor deposition (LPCVD). In step 5), a silicon dioxide dielectric layer is deposited using low-pressure chemical vapor deposition (LPCVD). In step 6), isolation trenches are etched using plasma dry etching. Step 7) In the process of growing a sidewall liner silica layer using the thermo-oxidative method; In step 8), polycrystalline silicon is deposited into a filling isolation trench using low-pressure chemical vapor deposition technology.
9. The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar junction device according to claim 1, characterized in that: In step 10), excess polysilicon is removed using a polysilicon etch-back process; In step 12), a deep trench is created using photomask exposure and plasma dry etching. In step 13), a sidewall liner silica layer is grown using thermal oxidation. In step 15), an N-type silicon film layer is filled by in-situ doping using RPCVD; In step 17), a deep trench is created using photomask exposure and plasma dry etching. In step 18), a sidewall liner silica layer is grown using thermal oxidation. In step 20), RPCVD is used to in-situ dope-fill the P-type silicon film. In step 21), excess P-type silicon is removed using a silicon etch-back process.
10. The P-epitaxial BCD-on-SOI integrated technology and complementary bipolar transistor device manufactured using the method according to any one of claims 1 to 9, characterized in that: The main film layers are P-type substrate silicon wafer, N-type buried layer, P-type buried layer, insulating silicon dioxide buried layer, P-type device layer, dielectric isolation trench region, N-type epitaxial layer, P-type epitaxial layer, gate dielectric layer, polycrystalline thin film, oxide thin film, tungsten plug and metal thin film layer; The P-type substrate silicon wafer is located at the bottom; the N-type buried layer and the P-type buried layer are formed on the surface of the substrate silicon wafer. An insulating silicon dioxide buried layer is formed between the substrate silicon wafer and the device layer silicon wafer. The N-type epitaxial layer is formed in the N-type buried layer of the substrate and the N-type vertical side well trench region of the device layer; The P-type epitaxial layer is formed in the P-type buried layer of the substrate and the P-type vertical side well region of the device layer; The polycrystalline isolation film is located in the middle of the isolation trench; The tungsten plug and the metal interconnect film have a planar structure; NMOS and PMOS form a complementary structure; Vertical NPN and vertical PNP form a complementary architecture; The N-type buried layer of the SOI substrate silicon wafer in the NPN external collector region and the P-type buried layer of the substrate silicon wafer in the PNP external collector region form a PN junction ESD protection structure.