Light-emitting substrate and display panel

Abstract

Provided in the present application are a light-emitting substrate and a display panel. The light-emitting substrate has a light-emitting region and a border region located outside the light-emitting region, and a first insulating layer of the light-emitting substrate comprises a first via hole located in the light-emitting region and a second via hole located in the border region. By means of arranging a metal barrier portion inside the second via hole of the border region, an invasion path of water vapor is blocked, thereby ameliorating the problem in existing OLED devices of black spots appearing on an OLED device after same is subjected to a reliability test.

Description

Light-emitting substrate and display panel TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a light-emitting substrate and a display panel. BACKGROUND

[0002] In recent years, the organic light emitting diode (OLED) device has attracted more attention due to its active light-emitting, high light-emitting brightness, high resolution, wide viewing angle, fast response speed, low energy consumption and flexible characteristics. For the OLED device, high temperature and high humidity reliability test is necessary after the completion of the module process, such as the reliability test of the OLED device in the environment of 85℃ and 85% humidity. However, after the reliability test of the OLED device, black spots appear on the OLED device, which seriously affects the quality of the OLED device. SUMMARY

[0003] The present application provides a light-emitting substrate and a display panel to alleviate the technical problem of black spots appearing on the OLED device after the reliability test of the existing OLED device.

[0004] The technical scheme provided by the present application is as follows:

[0005] In a first aspect, the present application provides a light-emitting substrate having a light-emitting area and a frame area outside the light-emitting area; the light-emitting substrate includes a substrate and a plurality of light-emitting units arranged in an array on the substrate and located in the light-emitting area, each light-emitting unit including at least one first transistor, the first transistor including a first active layer disposed on the substrate and a first source and a first drain disposed on a side of the first active layer away from the substrate; the light-emitting substrate further includes:

[0006] A first insulating layer is disposed on a side of the first active layer close to the first source or the first drain, the first insulating layer including a first via in the light-emitting area and a second via in the frame area, at least one of the first source and the first drain being connected to the first active layer through the corresponding first via;

[0007] A metal barrier is disposed in the second via, and in the perspective of the light-emitting substrate, the metal barrier overlaps the second via.

[0008] In a second aspect, the embodiments of the present application also provide a display panel, comprising a light-emitting substrate, the light-emitting substrate having a light-emitting area and a frame area outside the light-emitting area; the light-emitting substrate comprising a substrate and a plurality of light-emitting units arranged in an array on the substrate and located in the light-emitting area, each of the light-emitting units comprising at least one first transistor, the first transistor comprising a first active layer disposed on the substrate and a first source and a first drain disposed on a side of the first active layer away from the substrate; the light-emitting substrate further comprising:

[0009] a first insulating layer disposed on a side of the first active layer close to the first source or the first drain, the first insulating layer comprising a first via in the light-emitting area and a second via in the frame area, at least one of the first source and the first drain being connected to the first active layer through the corresponding first via;

[0010] a metal barrier disposed in the second via, and in a perspective view of the light-emitting substrate, the metal barrier overlaps the second via. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0012] FIG. 1 is a schematic diagram of a partial cross-sectional structure of an OLED device in the related art.

[0013] FIG. 2 is a schematic diagram of a first partial planar structure of a light-emitting substrate provided by the embodiments of the present application.

[0014] FIG. 3 is a schematic diagram of a first partial film layer structure of a light-emitting substrate provided by the embodiments of the present application.

[0015] FIG. 4 is a schematic diagram of a second partial film layer structure of a light-emitting substrate provided by the embodiments of the present application.

[0016] FIG. 5 is a schematic diagram of a third partial film layer structure of a light-emitting substrate provided by the embodiments of the present application.

[0017] FIG. 6 is a schematic diagram of a fourth partial film layer structure of a light-emitting substrate provided by the embodiments of the present application.

[0018] FIG. 7 is a schematic diagram of a fifth partial film layer structure of a light-emitting substrate provided by the embodiments of the present application.

[0019] FIG. 8 is a second partial plan view of a light-emitting substrate according to an embodiment of the present application. Embodiments of the present application

[0020] The following description of the embodiments is provided as an example to illustrate particular embodiments that can be used to implement the present application. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inward], [outward], [lateral] and the like, are only the directions with reference to the accompanying drawings. Therefore, the directional terms used are used to illustrate and understand the present application, and are not used to limit the present application. In the drawings, similar elements are denoted by the same reference numerals. In the drawings, the thicknesses of some layers and regions are exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.

[0021] After the reliability test is performed on the existing OLED device, the problem of black spots appearing on the OLED device, the inventors of the present application found in the research that through analysis of the black spot defect, no film peeling problem was found in the black spot area, and through further analysis, it was found that in the process of performing the reliability test on the OLED device, the water vapor in the high temperature and high humidity environment would penetrate the substrate, and the water vapor penetrating the substrate would pass through the via in the frame area and enter the light-emitting area of the OLED device, thereby causing the black spots to appear on the OLED device after the reliability test is performed on the OLED device.

[0022] Specifically, referring to FIG. 1, FIG. 1 is a partial cross-sectional structure schematic diagram of an OLED device in the related art, the OLED device has a light-emitting area AA' and a frame area NA' located outside the light-emitting area AA', and the OLED device includes a substrate 10' and a first transistor 21' located on one side of the substrate 10'. The first transistor 21' includes a first active layer 211' and a source electrode 212' and a drain electrode 213'. The OLED device further includes a first insulating layer 30' between the first active layer 211' and the source electrode 212' and the drain electrode 213', and a second insulating layer 60' covering the source electrode 212' and the drain electrode 213'. The first insulating layer 30' is an inorganic layer, and the second insulating layer 60' is an organic layer. A first via 31' is disposed on the first insulating layer 30' in the light-emitting area AA', and the source electrode 212' and the drain electrode 213' are connected to the first active layer 211' through the corresponding first via 31'.

[0023] In the process of forming the first via hole 31', due to the influence of exposure, the first via hole 31' formed in the middle region and the peripheral edge region of the light emitting region AA' is not uniform in size, and the size of the first via hole 31' formed in the peripheral edge region of the light emitting region AA' is smaller than that of the first via hole 31' formed in the middle region. In order to make the size of the first via hole 31' formed in the whole light emitting region AA' uniform, a second via hole 32' can be formed on the first insulating layer 30' located in the frame region NA', the second via hole 32' is a dummy via hole and is not used for connection between structures, and the second via hole 32' is filled with a second insulating layer 60'.

[0024] However, in the process of reliability test of the OLED device, water vapor in the high temperature and high humidity environment can penetrate the substrate substrate 10', and the water vapor penetrating the substrate substrate 10' can enter the light emitting region AA' of the OLED device through the second via hole 32' in the frame region NA'. This is because the substrate layer 11' of the substrate substrate 10' is an organic material, although the barrier layer 12' formed of inorganic material is also provided on the substrate substrate 10', the barrier performance of the barrier layer 12' is limited and cannot completely block the water vapor from penetrating, and in the process of forming the second via hole 32', micro-cracks may be caused in the barrier layer 12' below the second via hole 32', weakening the barrier performance of the barrier layer 12' at this position, so that the water vapor can enter and penetrate the barrier layer 12' from the substrate layer 11' to the second via hole 32'. The second insulating layer 60' filled in the second via hole 32' is an organic material, so that the water vapor can enter the light emitting region AA' along the second insulating layer 60' in the second via hole 32', causing part of the light emitting pixels in the light emitting region AA' to fail and produce black spots. Thus, after the inventor's unremitting efforts, the cause of the black spot is found.

[0025] Therefore, the application provides a light emitting substrate and a display panel to solve the above problems.

[0026] In an embodiment, the application provides a light emitting substrate having a light emitting region and a frame region located outside the light emitting region; the light emitting substrate comprises a substrate substrate and a plurality of light emitting units arranged in an array on the substrate substrate and located in the light emitting region, each of the light emitting units comprising at least one first transistor, the first transistor comprising a first active layer disposed on the substrate substrate and a first source electrode and a first drain electrode disposed on a side of the first active layer away from the substrate substrate; the light emitting substrate further comprises:

[0027] A first insulating layer is disposed on a side of the first active layer close to the first source electrode or the first drain electrode, and the first insulating layer includes a first via hole in the light emitting region and a second via hole in the frame region, and at least one of the first source electrode and the first drain electrode is connected to the first active layer through the corresponding first via hole.

[0028] A metal barrier is disposed in the second via hole, and the metal barrier overlaps the second via hole in a perspective view of the light emitting substrate.

[0029] In an embodiment, the light emitting substrate further includes an auxiliary barrier between the first insulating layer and the substrate, and the second via hole exposes part of the auxiliary barrier, and the metal barrier is connected to the auxiliary barrier.

[0030] In an embodiment, the auxiliary barrier is disposed in the same layer as the first active layer.

[0031] In an embodiment, the first transistor further includes a first gate electrode disposed in alignment with the first active layer, and the auxiliary barrier is disposed in the same layer as the first gate electrode.

[0032] In an embodiment, each light emitting unit further includes a second transistor connected to the first transistor, and the second transistor includes a second active layer, a second source electrode, and a second drain electrode, the first insulating layer is further disposed on a side of the second active layer close to the second source electrode or the second drain electrode, and the auxiliary barrier is disposed in the same layer as the second active layer.

[0033] In an embodiment, the first transistor is a polysilicon transistor, and the second transistor is an oxide transistor, the first insulating layer further includes a third via hole in the light emitting region, and at least one of the second source electrode and the second drain electrode is connected to the second active layer through the corresponding third via hole, and the depth of the third via hole is less than or equal to the depth of the first via hole.

[0034] In an embodiment, the frame region includes a first frame region and a second frame region on opposite sides of the light emitting region, a binding region is disposed in the first frame region, and the second via hole is located in the second frame region.

[0035] In an embodiment, the aperture of the first via hole is larger than the aperture of the second via hole.

[0036] In an embodiment, the substrate includes at least one substrate layer and at least one barrier layer, and the barrier layer is between the substrate layer and the first transistor.

[0037] In an embodiment, the metal barrier is disposed in the same layer as the first source electrode or the first drain electrode.

[0038] In an embodiment, each of the light emitting units further comprises a first electrode connected to the first transistor, the first electrode is located on a side of the first transistor away from the substrate, and the metal barrier is disposed in the same layer as one of the first electrode, the first source electrode, and the first drain electrode.

[0039] In an embodiment, the present application further provides a display panel comprising the light emitting substrate of any one of the foregoing embodiments.

[0040] In the light emitting substrate and the display panel provided by the embodiments of the present application, the light emitting substrate has a light emitting area and a frame area located outside the light emitting area, the first insulating layer of the light emitting substrate comprises a first via located in the light emitting area and a second via located in the frame area, at least one of the first source electrode and the first drain electrode of the first transistor is connected to the first active layer through the corresponding first via, the metal barrier is disposed in the second via, and the metal barrier overlaps the second via in the perspective of the front view of the light emitting substrate. By disposing the metal barrier in the second via of the frame area, the metal barrier can block the water vapor penetrating through the substrate from penetrating through the second via in the reliability test, so as to block the invasion path of the water vapor, and improve the problem of black spots appearing on the OLED device after the reliability test of the existing OLED device.

[0041] The light emitting substrate and the display panel of the present application will be described in detail below in combination with the accompanying drawings and specific embodiments.

[0042] Please refer to FIG. 2 and FIG. 3, FIG. 2 is a first partial planar structure schematic diagram of the light emitting substrate provided by the embodiments of the present application, and FIG. 3 is a first partial film layer structure schematic diagram of the light emitting substrate provided by the embodiments of the present application. Referring to FIG. 2, the light emitting substrate 100 has a light emitting area AA and a frame area NA located outside the light emitting area AA. The light emitting substrate 100 comprises a substrate 10 and a plurality of light emitting units 20 arranged in an array on the substrate 10 and located in the light emitting area AA.

[0043] Referring to FIGS. 2 and 3, each of the light emitting units 20 includes at least one first transistor 21 including a first active layer 211 disposed on the substrate 10 and a first source 212 and a first drain 213 disposed on a side of the first active layer 211 away from the substrate 10. The light emitting substrate 100 further includes a first insulating layer 30 and a metal barrier 40. The first insulating layer 30 is disposed on a side of the first active layer 211 close to the first source 212 or the first drain 213, and includes a first via 31 in the light emitting area AA and a second via 32 in the non-active area NA, at least one of the first source 212 and the first drain 213 being connected to the first active layer 211 through the corresponding first via 31. The metal barrier 40 is disposed in the second via 32, and overlaps the second via 32 in a perspective view of the light emitting substrate 100.

[0044] In the present embodiment, by disposing the metal barrier 40 in the second via 32 in the non-active area NA, the metal barrier 40 can block the water vapor penetrating the substrate 10 from passing through the second via 32 in the reliability test, so as to block the invasion path of the water vapor, and improve the problem of black spots appearing on the OLED device after the existing OLED device is subjected to the reliability test.

[0045] Specifically, with continued reference to FIG. 3, the substrate 10 includes at least one substrate layer and at least one barrier layer between the substrate layer and the first transistor 21. For example, the substrate 10 includes a first substrate layer 11 and a first barrier layer 12 disposed in layers, and the first barrier layer 12 is between the first substrate layer 11 and the first transistor 21. Optionally, the substrate 10 can further include a second substrate layer 13 and a second barrier layer 14, and the second barrier layer 14 is between the first substrate layer 11 and the second substrate layer 13, and the second substrate layer 13 is on a side of the first substrate layer 11 away from the first barrier layer 12. The material of the first substrate layer 11 is the same as that of the second substrate layer 13, such as both being organic materials such as polyimide (PI). The material of the second barrier layer 14 is the same as that of the first barrier layer 12, such as both being inorganic materials such as silicon oxide and silicon nitride.

[0046] The first transistor 21 is disposed on the substrate 10, and more particularly, the first transistor 21 is disposed on the side of the first barrier layer 12 away from the first substrate layer 11. The first transistor 21 includes a first active layer 211, a first source 212, a first drain 213, and a first gate 214. The first active layer 211 includes a channel region 2111 and a source region 2112 and a drain region 2113 located on opposite sides of the channel region 2111. The first source 212 is connected to the source region 2112 of the first active layer 211, and the first drain 213 is connected to the drain region 2113 of the first active layer 211. The first gate 214 is disposed in register with the first active layer 211, and more particularly, the first gate 214 is disposed in register with the channel region 2111 of the first active layer 211.

[0047] Optionally, the first source 212 and the first drain 213 are disposed in the same layer. It should be noted that "disposed in the same layer" in the present application means that in the preparation process, a film layer formed of the same material is patterned to obtain at least two different structures, and the at least two different structures are disposed in the same layer. For example, in the present embodiment, the first source 212 and the first drain 213 are obtained by patterning a same metal film layer, and thus the first source 212 and the first drain 213 are disposed in the same layer. Of course, in other embodiments, the first source 212 and the first drain 213 can also be disposed in different layers.

[0048] Optionally, the first source 212 and the first drain 213 can be formed as a plurality of layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material having high corrosion resistance. For example, the first source 212 and the first drain 213 can be a three-layer structure of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, or the like.

[0049] The first gate 214 is located on the side of the first active layer 211 close to the substrate 10, or the first gate 214 can also be located on the side of the first active layer 211 away from the substrate 10. In this embodiment, the first gate 214 is located on the side of the first active layer 211 away from the substrate 10. The first gate 214 is also located between the first active layer 211 and the first source 212. The first gate 214 can be formed as a plurality of layers or a single layer including a low-resistance material such as Al, Ti, Mo, Cu, Ni or an alloy thereof, or a material with high corrosion resistance, such as Ti, Mo and other metal materials. The material of the first active layer 211 includes a semiconductor material such as amorphous silicon (a-Si) or polycrystalline silicon (p-Si), such as low-temperature polycrystalline silicon (LTPS).

[0050] The first insulating layer 30 is located between the first source 212, the first drain 213 and the first gate 214. The material of the first insulating layer 30 includes inorganic materials such as silicon oxide and silicon nitride. The light-emitting substrate 100 further includes a first gate insulating layer 50 located between the first gate 214 and the first active layer 211, and a second insulating layer 60 located on the side of the first transistor 21 away from the substrate 10. The first gate insulating layer 50 covers the surface of the first active layer 211 and the substrate 10. The material of the first gate insulating layer 50 includes inorganic materials such as silicon oxide and silicon nitride. The second insulating layer 60 covers the surface of the first source 212, the first drain 213 and the first insulating layer 30. The second insulating layer 60 is an organic layer. The material of the second insulating layer 60 includes organic materials such as polyacrylate or polyimide, and silica.

[0051] The first insulating layer 30 is provided with a first via 31 and a second via 32. Specifically, the first via 31 is provided on the first insulating layer 30 located in the light-emitting area AA, and the second via 32 is provided on the first insulating layer 30 located in the frame area NA. The first via 31 penetrates the first insulating layer 30 and the first gate insulating layer 50 to expose part of the first active layer 211. The first source 212 is connected to the source region 2112 of the first active layer 211 through the corresponding first via 31, and the first drain 213 is connected to the drain region 2113 of the first active layer 211 through the corresponding first via 31.

[0052] The metal barrier 40 is arranged in the second via hole 32, the depth of the second via hole 32 is greater than the depth of the first via hole 31, and the second via hole 32 penetrates the first insulating layer 30 and the first gate insulating layer 50. Of course, in other embodiments, due to the influence of etching process, over-etching may occur when forming the second via hole 32, so that the second via hole 32 also penetrates part of the first barrier layer 12, that is, the second via hole 32 also penetrates part of the substrate 10, and at this time, the metal barrier 40 is also located in the substrate 10.

[0053] In the perspective of the light-emitting substrate 100, the metal barrier 40 overlaps the second via hole 32, that is, the orthographic projection of the metal barrier 40 on the substrate 10 overlaps the orthographic projection of the second via hole 32 on the substrate 10. Among them, the orthographic projection of the second via hole 32 on the substrate 10 falls within the range of the orthographic projection of the metal barrier 40 on the substrate 10. In other words, the orthographic projection of the metal barrier 40 on the substrate 10 completely covers the orthographic projection of the second via hole 32 on the substrate 10, so that the metal barrier 40 completely covers the inner wall of the second via hole 32. For example, the metal barrier 40 fills the entire second via hole 32, so that the second via hole 32 is filled with the metal barrier 40.

[0054] The material of the metal barrier 40 is metal or metal oxide. Because the material of metal or metal oxide is relatively dense, compared with inorganic materials and organic materials, it has good water vapor barrier performance. Therefore, by arranging the metal barrier 40 in the second via hole 32, water vapor can be prevented from entering the light-emitting area AA through the second via hole 32, so as to block the invasion path of water vapor, thereby avoiding the problem of black spots caused by water vapor penetrating the substrate 10 and entering the light-emitting area AA through the second via hole 32 during high-temperature and high-humidity reliability tests, and improving the problem of black spots appearing on the OLED device after the reliability test of the existing OLED device.

[0055] Optionally, the metal barrier 40 is arranged in the same layer as the first source electrode 212 or the first drain electrode 213. That is, during the process of forming the first source electrode 212 and the first drain electrode 213 in the light-emitting area AA, the metal barrier 40 is formed in the frame area NA, so that the metal barrier 40 is formed under the same process condition as the first source electrode 212 and the first drain electrode 213. In this way, while improving the problem of black spots, no additional process steps are added.

[0056] In an embodiment, continuing to refer to FIGS. 2 and 3, the frame area NA includes a first frame area BSA and a second frame area TSA located on opposite sides of the light emitting area AA, a binding area BDA is arranged in the first frame area BSA, and the binding area BDA is used to bind a driving IC or the like. The second via hole 32 is located in the second frame area TSA.

[0057] In an embodiment, the arrangement rule of the second via hole 32 is the same as that of the first via hole 31, and the aperture of the first via hole 31 is larger than that of the second via hole 32, so as to improve the uniformity of the first via hole 31 in the light emitting area AA.

[0058] In an embodiment, referring to FIGS. 2 to 4, FIG. 4 is a schematic diagram of a second partial film structure of a light emitting substrate 100 provided by an embodiment of the present application. Referring to FIG. 4, different from the above embodiments, the light emitting substrate 100 further includes an auxiliary barrier portion 70, the auxiliary barrier portion 70 is located between the first insulating layer 30 and the substrate substrate 10, the second via hole 32 exposes part of the auxiliary barrier portion 70, and the metal barrier portion 40 is connected with the auxiliary barrier portion 70.

[0059] In a perspective view of the light emitting substrate 100, the auxiliary barrier portion 70 overlaps with the second via hole 32, that is, the orthographic projection of the auxiliary barrier portion 70 on the substrate substrate 10 overlaps with the orthographic projection of the second via hole 32 on the substrate substrate 10. Among them, the orthographic projection of the second via hole 32 on the substrate substrate 10 falls within the range of the orthographic projection of the auxiliary barrier portion 70 on the substrate substrate 10. In other words, the orthographic projection of the auxiliary barrier portion 70 on the substrate substrate 10 completely covers the orthographic projection of the second via hole 32 on the substrate substrate 10.

[0060] The water vapor transmission rate of the auxiliary barrier portion 70 is less than the water vapor transmission rate of the inorganic material, and / or the etching rate of the auxiliary barrier portion 70 is less than the etching rate of the inorganic material. For example, the water vapor transmission rate of the auxiliary barrier portion 70 is less than the water vapor transmission rate of the substrate substrate 10, so as to further enhance the water vapor blocking performance of the metal barrier portion 40 and further improve the black spot problem; the etching rate of the auxiliary barrier portion 70 is less than the etching rate of the first insulating layer 30, so as to avoid over-etching of the inorganic layer in the process of forming the second via hole 32, so that a relatively thick inorganic layer can be reserved below the second via hole 32, the water vapor blocking effect is improved, and the black spot problem is further improved.

[0061] Optionally, the auxiliary barrier 70 is arranged in the same layer as the first active layer 211. That is, the auxiliary barrier 70 is formed in the non-active area NA in the process of forming the first active layer 211, so that the auxiliary barrier 70 is formed in the same process condition as the first active layer 211. Thus, the black spot problem is improved without additional process steps. Since the etching rate of the first active layer 211 is less than that of the inorganic material, the etching rate of the auxiliary barrier 70 arranged in the same layer as the first active layer 211 is also less than that of the inorganic material. Thus, when the second via hole 32 is formed, the auxiliary barrier 70 can protect the inorganic layer (i.e., the first barrier layer 12) below it from over-etching and micro-cracks. Other descriptions are as described above and will not be repeated here.

[0062] In an embodiment, please refer to FIGS. 2-5, and FIG. 5 is a schematic diagram of a third partial film structure of the light-emitting substrate 100 provided in the embodiment. As shown in FIG. 5, different from the above-described embodiments, the first transistor 21 further includes a first gate 214 arranged in alignment with the first active layer 211, and the auxiliary barrier 70 is arranged in the same layer as the first gate 214. The first gate 214 is located on the side of the first active layer 211 away from the substrate 10, for example, the first gate 214 is located between the first active layer 211 and the first source electrode 212.

[0063] Since the material of the first gate 214 is metal, the material of the auxiliary barrier 70 arranged in the same layer as the first gate 214 is also metal. The metal material has a relatively dense material quality and has better water vapor blocking performance than inorganic and organic materials. That is, the water vapor transmission rate of the auxiliary barrier 70 is less than that of the inorganic material, thereby further enhancing the water vapor blocking performance of the metal barrier 40. Moreover, when the dry etching is used to form the second via hole 32, the etching rate of the metal material is less than that of the inorganic material, that is, the etching rate of the auxiliary barrier 70 is less than that of the inorganic material. Thus, when the first insulating layer 30 is etched to form the second via hole 32, the inorganic layer below the auxiliary barrier 70 is not etched due to the blocking of the auxiliary barrier 70, thereby retaining a larger thickness of the inorganic layer, and the inorganic layer below the auxiliary barrier 70 also does not have micro-cracks. At this time, the depth of the second via hole 32 is less than that of the first via hole 31. Other descriptions are as described above and will not be repeated here.

[0064] In an embodiment, referring to FIGS. 2-6, FIG. 6 is a fourth partial film layer structure diagram of the light-emitting substrate 100 provided in the embodiment. Referring to FIG. 6, different from the above-mentioned embodiments, each of the light-emitting units 20 further comprises a first electrode 22 connected with the first transistor 21, the first electrode 22 is located on a side of the first transistor 21 away from the substrate 10, and the metal barrier portion 40 is arranged in the same layer as one of the first electrode 22, the first source electrode 212 and the first drain electrode 213.

[0065] Specifically, the metal barrier portion 40 is arranged in the same layer as the first electrode 22. That is, in the process of forming the first electrode 22 in the light-emitting area AA, the metal barrier portion 40 is formed in the frame area NA, so that the metal barrier portion 40 and the first electrode 22 are formed under the same process condition. In this way, the black spot problem is improved without additional process steps. Optionally, the first electrode 22 is a transparent conductive thin film, such as indium tin oxide (ITO) and the like. Of course, in order to improve the light extraction efficiency of the light-emitting substrate 100, the first electrode 22 can also be a reflective electrode, such as the first electrode 22 can be a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a combination thereof, and a single layer or multiple layers formed of ITO, IZO, ZnO or In2O3.

[0066] Since the first electrode 22 is formed of metal or metal oxide, the metal barrier portion 40 in the same layer as the first electrode 22 is also formed of metal or metal oxide. The material of metal or metal oxide is dense, and has better water vapor blocking performance than inorganic or organic materials. Therefore, by arranging the metal barrier portion 40 in the second via hole 32, the water vapor can be blocked from penetrating the second via hole 32 into the light-emitting area AA, so as to block the invasion path of water vapor, thereby avoiding the problem of black spots caused by water vapor penetrating the substrate 10 and the second via hole 32 into the light-emitting area AA during high temperature and high humidity reliability test, and improving the problem of black spots on the OLED device after the reliability test of the existing OLED device.

[0067] Of course, the light-emitting substrate 100 further comprises a second electrode and a light-emitting device which emits light under the joint action of the first electrode 22 and the second electrode, wherein the first electrode 22 is an anode and the second electrode is a cathode. The light-emitting device can be a light-emitting layer formed by an organic light-emitting material, which is located between the first electrode 22 and the second electrode; or the light-emitting device can also be a Light-Emitting Diode (LED) chip, a Micro Light-Emitting Diode (Micro-LED) chip or a Mini Light-Emitting Diode (Mini-LED) chip. For other descriptions, please refer to the above embodiments, which will not be repeated here.

[0068] In an embodiment, please refer to FIGS. 2-7, and FIG. 7 is a schematic diagram of a fifth partial film layer structure of the light-emitting substrate 100 provided in the embodiment. Referring to FIG. 7, different from the above embodiments, each of the light-emitting units 20 further comprises a second transistor 23 connected with the first transistor 21, the second transistor 23 comprises a second active layer 231, a second source electrode 232 and a second drain electrode 233, the first insulating layer 30 is further located on a side of the second active layer 231 close to the second source electrode 232 or the second drain electrode 233, and the auxiliary barrier portion 70 is arranged in the same layer as the second active layer 231.

[0069] Optionally, the first transistor 21 is a polysilicon transistor, and the second transistor 23 is an oxide transistor; the first insulating layer 30 further comprises a third via hole 33 located in the light-emitting area AA, and at least one of the second source electrode 232 and the second drain electrode 233 is connected with the second active layer 231 through a corresponding third via hole 33; wherein the depth of the third via hole 33 is less than or equal to the depth of the first via hole 31.

[0070] Specifically, the first transistor 21 further includes a third electrode 215 located on the side of the first gate 214 away from the first active layer 211, and the third electrode 215 is arranged in alignment with the first gate 214. The second transistor 23 further includes a second gate 234 and a third gate 235, and the third gate 235 is arranged in the same layer as the third electrode 215. The second active layer 231 is located on the side of the third gate 235 away from the substrate 10, and the second gate 234 is located on the side of the second active layer 231 away from the third gate 235. The second source 232 is arranged in the same layer as the second drain 233, and the second source 232 is also arranged in the same layer as the first source 212, and the first source 212 is arranged in the same layer as the first drain 213. The second drain 233 is connected with the second active layer 231 through the third via hole 33, and the second drain 233 is also connected with the first active layer 211 through the corresponding first via hole 31, so as to realize the connection between the second drain 233 and the first source 212, and further realize the connection between the second transistor 23 and the first transistor 21.

[0071] The light-emitting substrate 100 further includes a third insulating layer 80 located between the third electrode 215 and the first gate 214, a second gate insulating layer 90 located between the third gate 235 and the second active layer 231, and a third gate insulating layer 91 located between the second active layer 231 and the second gate 234. The third insulating layer 80, the second gate insulating layer 90, and the third gate insulating layer 91 are all inorganic layers, such as inorganic layers formed of inorganic materials such as silicon oxide and silicon nitride. The materials of the third electrode 215, the second gate 234, and the third gate 235 can be the same as the material of the first gate 214.

[0072] The material of the second active layer 231 includes metal oxide semiconductor materials such as indium gallium zinc oxide (IGZO). Since the water vapor permeability of metal oxide is less than the water vapor permeability of inorganic materials, and the etching rate of metal oxide is less than the etching rate of inorganic materials, the water vapor permeability of the auxiliary barrier portion 70 arranged in the same layer as the second active layer 231 is less than the water vapor permeability of inorganic materials, and the etching rate of the auxiliary barrier portion 70 is less than the etching rate of inorganic materials, so that the auxiliary barrier portion 70 can protect the inorganic layer below it.

[0073] Of course, in some other embodiments, the auxiliary barrier portion 70 can also be arranged in the same layer as the metal layer such as the second gate 234 or the third gate 235, which will not be illustrated one by one here. For other descriptions, please refer to the above embodiments, which will not be described here.

[0074] In an embodiment, please refer to FIG. 2 to FIG. 8, FIG. 8 is a second partial planar structure schematic diagram of the light-emitting substrate 100 provided by the embodiment of the present application. Referring to FIG. 8, different from the above-mentioned embodiment, the second via hole 32 is also arranged in the first bezel area BSA, and the number of the second via hole 32 in the first bezel area BSA is less than the number of the second via hole 32 in the second bezel area TSA, so as to avoid that the second via hole 32 occupies too much area in the first bezel area BSA and affects the arrangement of the bonding area BDA.

[0075] Optionally, the bezel area NA further includes a third bezel area LSA and a fourth bezel area RSA connected between the first bezel area BSA and the second bezel area TSA, the second via hole 32 is also arranged in the third bezel area LSA and the fourth bezel area RSA, and the number of the second via hole 32 in the third bezel area LSA is less than the number of the second via hole 32 in the second bezel area TSA, and the number of the second via hole 32 in the fourth bezel area RSA is less than the number of the second via hole 32 in the second bezel area TSA, so as to reduce the area of the third bezel area LSA and the fourth bezel area RSA, and further realize narrow frame. Other descriptions please refer to the above-mentioned embodiment, which will not be repeated here.

[0076] Based on the same inventive concept, the embodiment of the present application further provides a display panel, which includes the light-emitting substrate 100 of any one of the above-mentioned embodiments. The display panel includes an organic light-emitting diode (OLED) display panel, a light-emitting diode (LED) display panel, a micro light-emitting diode (Micro-LED) display panel, or a mini light-emitting diode (Mini-LED) display panel, etc.

[0077] According to the above-mentioned embodiments, it can be known that:

[0078] The application provides a light-emitting substrate and a display panel, wherein the light-emitting substrate has a light-emitting area and a frame area outside the light-emitting area; a first insulating layer of the light-emitting substrate includes a first via hole in the light-emitting area and a second via hole in the frame area; at least one of a first source electrode and a first drain electrode of a first transistor is connected to a first active layer through the corresponding first via hole; a metal barrier is arranged in the second via hole; and the metal barrier overlaps the second via hole in the perspective of the light-emitting substrate. The metal barrier can block the penetration of water vapor through the second via hole in the reliability test, so as to block the invasion path of the water vapor, and improve the problem of black spots on the OLED device after the reliability test of the existing OLED device.

[0079] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0080] The above describes the embodiments of the application in detail, and the principle and implementation mode of the application are described by applying specific examples; the above embodiment is only used to help understand the technical solution and core idea of the application; those skilled in the art should understand that the technical solution recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and the modification or replacement does not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the application.

Claims

1. A light emitting substrate having a light emitting region and a frame region outside the light emitting region; the light emitting substrate comprises a substrate substrate and a plurality of light emitting units arranged in an array in the light emitting region, each of the light emitting units comprising at least one first transistor, the first transistor comprising a first active layer disposed on the substrate substrate and a first source and a first drain disposed on a side of the first active layer away from the substrate substrate; the light emitting substrate further comprises: a first insulating layer disposed on a side of the first active layer close to the first source or the first drain, the first insulating layer comprising a first via in the light emitting region and a second via in the frame region, at least one of the first source and the first drain being connected to the first active layer through the corresponding first via; and a metal barrier disposed in the second via, and in a perspective view of the light emitting substrate, the metal barrier overlaps the second via. The light emitting substrate further comprises an auxiliary barrier between the first insulating layer and the substrate substrate, the second via exposing part of the auxiliary barrier, and the metal barrier is connected to the auxiliary barrier.

2. The light-emitting substrate according to claim 1, wherein The auxiliary barrier is disposed in the same layer as the first active layer.

3. The light-emitting substrate of claim 2, wherein, The first transistor further comprises a first gate disposed in alignment with the first active layer, and the auxiliary barrier is disposed in the same layer as the first gate.

4. The light-emitting substrate of claim 2, wherein, Each of the light emitting units further comprises a second transistor connected to the first transistor, the second transistor comprising a second active layer, a second source and a second drain, the first insulating layer further being disposed on a side of the second active layer close to the second source or the second drain, and the auxiliary barrier being disposed in the same layer as the second active layer.

5. The light-emitting substrate of claim 2, wherein, The first transistor is a polysilicon transistor, and the second transistor is an oxide transistor; the first insulating layer further comprises a third via in the light emitting region, at least one of the second source and the second drain being connected to the second active layer through the corresponding third via, and a depth of the third via is less than or equal to a depth of the first via.

6. The light-emitting substrate of claim 5, wherein, The frame region comprises a first frame region and a second frame region located on opposite sides of the light emitting region, a binding region is disposed in the first frame region, and the second via is located in the second frame region.

7. The light-emitting substrate of claim 1, wherein, An aperture of the first via is larger than an aperture of the second via.

8. The light-emitting substrate of claim 7, wherein, The substrate substrate comprises at least one substrate layer and at least one barrier layer, and the barrier layer is located between the substrate layer and the first transistor.

9. The light emitting substrate of claim 1, wherein, The metal barrier is disposed in the same layer as the first source or the first drain.

10. The light emitting substrate of claim 1, wherein, Each of the light emitting units further comprises a first electrode connected to the first transistor, the first electrode being located on a side of the first transistor away from the substrate substrate, and the metal barrier is disposed in the same layer as one of the first electrode, the first source and the first drain.

11. The light emitting substrate of claim 1, wherein, ​ 12.A display panel, comprising a light-emitting substrate having a light-emitting region and a frame region outside the light-emitting region; the light-emitting substrate comprises a substrate and a plurality of light-emitting units arranged in an array in the light-emitting region, each of the light-emitting units comprising at least one first transistor, the first transistor comprising a first active layer disposed on the substrate and a first source and a first drain disposed on a side of the first active layer away from the substrate; the light-emitting substrate further comprises: a first insulating layer disposed on a side of the first active layer close to the first source or the first drain, the first insulating layer comprising a first via in the light-emitting region and a second via in the frame region, at least one of the first source and the first drain being connected to the first active layer through the corresponding first via; and a metal barrier disposed in the second via, the metal barrier overlapping the second via in a perspective view of the light-emitting substrate. The light-emitting substrate further comprises an auxiliary barrier between the first insulating layer and the substrate, the second via exposing part of the auxiliary barrier, the metal barrier being connected to the auxiliary barrier. The auxiliary barrier is disposed in the same layer as the first active layer. The first transistor further comprises a first gate disposed in alignment with the first active layer, the auxiliary barrier being disposed in the same layer as the first gate.

13. The display panel of claim 12, wherein, Each of the light-emitting units further comprises a second transistor connected to the first transistor, the second transistor comprising a second active layer, a second source and a second drain, the first insulating layer further being disposed on a side of the second active layer close to the second source or the second drain, the auxiliary barrier being disposed in the same layer as the second active layer.

14. The display panel of claim 13, wherein, The first transistor is a polysilicon transistor, and the second transistor is an oxide transistor; the first insulating layer further comprises a third via in the light-emitting region, at least one of the second source and the second drain being connected to the second active layer through the corresponding third via; wherein the depth of the third via is less than or equal to the depth of the first via.

15. The display panel of claim 13, wherein, The frame region comprises a first frame region and a second frame region on opposite sides of the light-emitting region, the first frame region having a binding region disposed therein, and the second via being disposed in the second frame region.

16. The display panel of claim 13, wherein, The aperture of the first via is larger than the aperture of the second via.

17. The display panel of claim 16, wherein, Each of the light-emitting units further comprises a first electrode connected to the first transistor, the first electrode being disposed on a side of the first transistor away from the substrate, the metal barrier being disposed in the same layer as one of the first electrode, the first source and the first drain.

18. The display panel of claim 12, wherein, ​ 19. The display panel of claim 18, wherein, ​ 20. The display panel of claim 12, wherein, ​

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