Display panel and display apparatus

Abstract

A display panel. The display panel comprises a passivation layer (34), wherein the passivation layer (34) is provided with a water vapor release port (341). The orthographic projection of the water vapor release port (341) on a base substrate (1) at least overlaps the orthographic projection of a first alignment mark on the base substrate (1), such that water vapor in a planarization layer group (217) located on the side of the passivation layer (34) close to the base substrate (1) can be effectively released, a first alignment mark (41) can be prevented from peeling off from the passivation layer (34), the first alignment mark (41) can be prevented from being eroded, and the calibration accuracy of the first alignment mark (41) for a mask can be accurately ensured, thereby guaranteeing the accuracy of alignment between the mask and a film layer that has been formed on the base substrate (1). Further provided in the present disclosure is a display apparatus comprising the display panel.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410703867.7, filed May 31, 2024, entitled “Display panel and display device,” the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0004] In order to ensure the alignment accuracy of the mask plate and the film layer formed on the substrate, an alignment mark is usually arranged in the peripheral area, and the setting position of the mask plate is calibrated through the alignment mark.

[0005] In order to prevent water and oxygen from eroding the alignment mark, a passivation layer is usually covered on the side of the alignment mark away from the substrate. Since the passivation layer has a strong ability to isolate water and oxygen, the water in the lower layer cannot be effectively released, which causes the alignment mark to easily peel off from the passivation layer above.

[0006] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0007] The present disclosure aims to overcome the problem that the alignment mark easily peels off from the passivation layer, and provides a display panel and a display device.

[0008] According to one aspect of the present disclosure, a display panel is provided, having a display area and a peripheral area located at the periphery of the display area, the display panel comprising a substrate, a planarization layer group, a first source-drain conductive layer, and a passivation layer, the planarization layer group being arranged on one side of the substrate; the first source-drain conductive layer being arranged on the side of the planarization layer group away from the substrate, the first source-drain conductive layer comprising a first alignment mark, the first alignment mark being located in the peripheral area; the passivation layer being arranged on the side of the first source-drain conductive layer away from the substrate, the passivation layer being provided with a water vapor release port, and the orthogonal projection of the water vapor release port on the substrate at least overlaps the orthogonal projection of the first alignment mark on the substrate.

[0009] In one embodiment of this disclosure, the planarization layer group has an easy-peel region located around the first alignment mark, and the orthographic projection of the water vapor release port on the substrate overlaps with the orthographic projections of the first alignment mark and the easy-peel region on the substrate.

[0010] In one embodiment of this disclosure, the orthographic projection of the first alignment mark and the easily peelable area on the substrate is located within the orthographic projection of the moisture release port on the substrate, exposing the side of the first alignment mark away from the substrate, the side of the first alignment mark, and the side of the easily peelable area away from the substrate.

[0011] In one embodiment of this disclosure, the moisture release port includes a first moisture release hole and a second moisture release hole. The orthographic projection of the first moisture release hole on the substrate overlaps with the orthographic projection of the first alignment mark on the substrate, and the orthographic projection of the second moisture release hole on the substrate overlaps with the orthographic projection of the easily peelable area on the substrate.

[0012] In one embodiment of this disclosure, the first alignment mark includes a first alignment portion and a second alignment portion, the first alignment portion and the second alignment portion intersect each other, the first alignment portion extends along a first direction, the second alignment portion extends along a second direction, the second direction is perpendicular to the first direction, and the first moisture release hole includes a first strip portion and a second strip portion connected end to end, the first strip portion and the first alignment portion are parallel to each other, and the second strip portion and the second alignment portion are parallel to each other.

[0013] In one embodiment of this disclosure, the passivation layer is provided with four first water vapor release holes, the first alignment portions of the four first water vapor release holes are spaced apart and symmetrical along a second direction, and the second alignment portions of the four first water vapor release holes are spaced apart and symmetrical along a first direction.

[0014] In one embodiment of this disclosure, an easy-peeling area is formed around each of the first water vapor release holes, and the four easy-peeling areas are respectively provided with a plurality of second water vapor release holes arranged in an array.

[0015] In one embodiment of this disclosure, the display panel further includes a partition layer, a plurality of pixel electrodes, a pixel defining layer, and a light-emitting material layer. The partition layer is disposed on the same layer as the passivation layer and is located in the display area. The plurality of pixel electrodes are disposed on the side of the passivation layer away from the substrate. The pixel defining layer is disposed on the side of the pixel electrodes away from the substrate, and the pixel defining layer has pixel openings that expose each of the pixel electrodes. The light-emitting material layer is disposed on the side of the pixel defining layer away from the substrate. A partition groove is provided between two adjacent pixel openings, and the light-emitting material layer is partitioned in the partition groove. The partition groove penetrates the pixel defining layer and passes through at least a portion of the partition layer.

[0016] In one embodiment of this disclosure, the partition groove includes a first groove segment and a second groove segment sequentially disposed along a direction away from the substrate. The first groove segment penetrates the partition layer, and the second groove segment penetrates the pixel defining layer. The orthographic projection of the first groove segment on the substrate is located within the orthographic projection of the second groove segment on the substrate.

[0017] In one embodiment of this disclosure, the display panel further includes a transistor layer disposed between the first source-drain conductive layer and the substrate. The transistor layer includes at least one transistor. The first source-drain conductive layer includes a first source conductive portion and a first drain conductive portion. The first source conductive portion and the second drain conductive portion are located in the display area. The first source conductive portion is connected to the source of the transistor, and the first drain conductive portion is connected to the drain of the transistor. The pixel electrode is connected to the first drain conductive portion.

[0018] In one embodiment of this disclosure, the display panel further includes a second source / drain conductive layer and a third source / drain conductive layer. The second source / drain conductive layer is disposed between the first source / drain conductive layer and the transistor layer, and the third source / drain conductive layer is disposed between the second source / drain conductive layer and the transistor layer. The planarization layer group includes a second planarization layer and a first planarization layer. The second planarization layer is located away from the first source / drain conductive layer and the third source / drain conductive layer. The first planarization layer is disposed between the second source / drain conductive layer and the third source / drain conductive layer. The second source / drain conductive layer includes a second source conductive portion and a second drain conductive portion. The third source / drain conductive layer covers... The transistor includes a third source conductive portion and a third drain conductive portion. The first source conductive portion is connected to the second source conductive portion through a first via on the second planarization layer. The first drain conductive portion is connected to the second drain conductive portion through a second via on the second planarization layer. The second source conductive portion is connected to the third source conductive portion through a third via on the first planarization layer. The second drain conductive portion is connected to the third drain conductive portion through a fourth via on the first planarization layer. The third source conductive portion is connected to the source of the transistor through a fifth via. The third drain conductive portion is connected to the drain of the transistor through a sixth via.

[0019] In one embodiment of this disclosure, the display panel further includes a third planarization layer disposed between the passivation layer and the first source / drain conductive layer, and the pixel electrode is connected to the first drain conductive portion through a seventh via on the third planarization layer.

[0020] In one embodiment of this disclosure, the transistor layer includes a first active layer, a second active layer, a first gate, a second gate, and a third gate. The first active layer is disposed on one side of the substrate, and the first gate is disposed on the side of the first active layer away from the substrate. The orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the channel region of the first active layer on the substrate to form a first transistor. The second gate is disposed on the side of the first gate away from the substrate, the second active layer is disposed on the side of the second gate away from the substrate, and the third gate is disposed on the side of the second gate away from the substrate. The second gate and the third gate overlap with the orthographic projection of the channel region of the second active layer on the substrate to form a second transistor. The material of the first active layer is low-temperature polycrystalline silicon, and the material of the second active layer is indium gallium zinc oxide.

[0021] According to another aspect of this disclosure, a display device is provided, including a display panel provided in one aspect of this disclosure.

[0022] The display panel disclosed herein includes a passivation layer, which has a moisture release port. The orthographic projection of the moisture release port on the substrate overlaps at least with the orthographic projection of the first alignment mark on the substrate, so that moisture in the planarization layer group located on the side of the passivation layer closer to the substrate can be effectively released. This can prevent peeling between the first alignment mark and the passivation layer, avoid erosion of the first alignment mark, and accurately ensure the calibration accuracy of the first alignment mark with the mask, thereby ensuring the alignment accuracy of the mask and the film layer formed on the substrate.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 is a cross-sectional schematic diagram of the display panel according to an embodiment of this disclosure.

[0026] Figure 2 is a schematic diagram of the peripheral area of ​​the display panel according to an embodiment of the present disclosure when the exposure machine performs alignment by the seventh alignment mark during the formation of the patterned first active layer.

[0027] Figure 3 is a schematic diagram of the peripheral area of ​​the display panel according to an embodiment of the present disclosure when the exposure machine aligns the patterned first gate using the sixth alignment mark.

[0028] Figure 4 is a schematic diagram of the peripheral area of ​​the display panel according to an embodiment of the present disclosure when the exposure machine aligns with the fifth alignment mark during the formation of the patterned second gate.

[0029] Figure 5 is a schematic diagram of the peripheral area of ​​the display panel according to an embodiment of this disclosure when the exposure machine aligns with the fourth alignment mark during the formation of the patterned second active layer.

[0030] Figure 6 is a schematic diagram of the peripheral area of ​​the display panel according to an embodiment of the present disclosure when the exposure machine aligns the patterned third gate using the fourth alignment mark.

[0031] Figure 7 is a schematic diagram of the peripheral area of ​​the display panel involved in this embodiment of the present disclosure when the exposure machine aligns with the fourth alignment mark during the formation of vias on the first interlayer dielectric layer.

[0032] Figure 8 is a schematic diagram of the peripheral area of ​​the display panel involved in the embodiments of this disclosure when the exposure machine performs alignment by the sixth alignment mark during the formation of the patterned third source and drain conductive layer.

[0033] Figure 9 is a schematic diagram of the peripheral area of ​​the display panel involved in this embodiment of the present disclosure when the exposure machine aligns with the third alignment mark during the formation of the protective layer.

[0034] Figure 10 is a schematic diagram of the peripheral area of ​​the display panel involved in this embodiment of the present disclosure when a via is formed on the second planarization layer and the exposure machine is aligned with the third alignment mark.

[0035] Figure 11 is a schematic diagram of the peripheral area of ​​the display panel according to an embodiment of the present disclosure when the exposure machine can perform alignment by a third alignment mark during the formation of a patterned second source / drain conductive layer.

[0036] Figure 12 is a schematic diagram of the peripheral area of ​​the display panel involved in this embodiment of the present disclosure when a via is formed on the first planarization layer and the exposure machine is aligned with the second alignment mark.

[0037] Figure 13 is a schematic diagram of the peripheral area of ​​the display panel involved in the embodiments of this disclosure when the exposure machine aligns the patterned first source and drain conductive layer using the second alignment mark.

[0038] Figure 14 is a schematic diagram of the peripheral area of ​​the display panel involved in this embodiment of the present disclosure when a via is formed in the third planarization layer and the exposure machine is aligned with the first alignment mark.

[0039] Figure 15 is a schematic diagram of the peripheral area of ​​the display panel according to an embodiment of the present disclosure when the exposure machine aligns the patterned pixel electrodes using the first alignment mark.

[0040] Figure 16 is a schematic diagram of the peripheral area of ​​the display panel involved in this embodiment of the present disclosure when the exposure machine aligns with the sixth alignment mark during the formation of the pixel defining layer.

[0041] Figure 17 is a schematic diagram showing the positional relationship of multiple display areas and multiple alignment marks on the entire substrate according to an embodiment of this disclosure.

[0042] Figure 18 is a partial cross-sectional schematic diagram of the peripheral area of ​​the display panel according to an embodiment of the present disclosure when the first alignment mark is on the first planarization layer.

[0043] Figure 19 is a partial cross-sectional schematic diagram of the peripheral area of ​​the display panel involved in the embodiments of this disclosure when the passivation layer covers the first alignment mark.

[0044] Figure 20 is a partial cross-sectional schematic diagram of the peripheral area of ​​the display panel involved in this embodiment of the present disclosure when a water vapor release port is provided on the passivation layer.

[0045] Figure 21 is a planar schematic diagram of the water vapor release port on the passivation layer involved in this embodiment of the present disclosure when the first alignment mark and the easily peelable area located around the first alignment mark are directly removed.

[0046] Figure 22 is a planar schematic diagram of the water vapor release port on the passivation layer in the present disclosure embodiment when the water vapor release port includes a first water vapor release hole and a second water vapor release hole.

[0047] In the diagram: 100 - Display area; 200 - Peripheral area; 1 - Substrate; 2 - Driving circuit layer; 21 - First transistor; 22 - Second transistor; 201 - Light-shielding layer; 202 - First buffer layer; 203 - First active layer; 204 - Second active layer; 205 - First gate insulating layer; 206 - Second gate insulating layer; 207 - Third gate insulating layer; 208 - First gate layer; 2081 - First gate; 209 - Second gate layer; 2091 - Second gate. 210-Third gate layer, 2101-Third gate, 211-First interlayer dielectric layer, 212-Second interlayer dielectric layer, 213-Protective layer, 214-First source / drain conductive layer, 2141-First source conductive portion, 2142-First drain conductive portion, 215-Second source / drain conductive layer, 2151-Second source conductive portion, 2152-Second drain conductive portion, 216-Third source / drain conductive layer, 2161-Third source conductive portion, 2162-Third drain conductive layer Electrical components, 217-Planarization layer group, 2171-First planarization layer, 2172-Second planarization layer, 218-Third planarization layer, 3-Light-emitting layer, 31-Pixel defining layer, 311-Pixel opening, 32-Light-emitting unit, 321-Pixel electrode, 322-Light-emitting material layer, 323-Common electrode, 33-Partition layer, 34-Passivation layer, 341-Moisture release port, 3411-First moisture release hole, 3412-Second moisture release hole, 3413- First strip, 3414-Second strip, 35-Partition groove, 351-First groove segment, 352-Second groove segment, 36-First cover layer, 37-Second cover layer, 4-Alignment mark, 41-First alignment mark, 411-First alignment part, 412-Second alignment part, 42-Second alignment mark, 43-Third alignment mark, 44-Fourth alignment mark, 45-Fifth alignment mark, 46-Sixth alignment mark, 47-Seventh alignment mark, 5-Full-surface substrate. Detailed Implementation

[0048] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0049] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0050] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0051] As shown in Figures 1 and 17, to prevent crosstalk between different light-emitting units 32 and affect the display effect, a barrier layer is usually set in the display area 100 of the display panel to separate the light-emitting material layer 322. To ensure the alignment accuracy of the mask and the film layer formed on the substrate 1, alignment marks 4 are usually set in the peripheral area 200 to align and calibrate the setting position of the mask. The alignment marks 4 are located in the peripheral area 200 of the display panel, making them susceptible to water and oxygen erosion. The material of the barrier layer is SiNx. Therefore, it is considered that a passivation layer 34 is formed on the side of the first alignment mark 41 away from the substrate 1 to isolate water and oxygen while forming the barrier layer. However, the planarization layer group 217 under the first alignment mark 41 is an organic layer. The moisture in the planarization layer group 217 cannot be effectively released, which makes it easy for the first alignment mark 41 and the passivation layer 34 to peel off.

[0052] Based on this, the present disclosure provides a display panel. As shown in Figures 1 to 22, the display panel has a display area 100 and a peripheral area 200 located around the display area 100. The display panel includes a substrate 1, a first source / drain conductive layer 214, and a passivation layer 34. A planarization layer group 217 is disposed on one side of the substrate 1. The first source / drain conductive layer 214 is disposed on the side of the planarization layer group 217 away from the substrate 1. The first source / drain conductive layer 214 includes a first alignment mark 41, which is located in the peripheral area 200. The passivation layer 34 is disposed on the side of the first source / drain conductive layer 214 away from the substrate 1. The passivation layer 34 has a moisture release port 341. The orthographic projection of the moisture release port 341 on the substrate 1 overlaps at least with the orthographic projection of the first alignment mark 41 on the substrate 1.

[0053] The passivation layer 34 is provided with a moisture release port 341. The orthographic projection of the moisture release port 341 on the substrate 1 overlaps at least with the orthographic projection of the first alignment mark 41 on the substrate 1, so that the moisture in the planarization layer group 217 located on the side of the passivation layer 34 close to the substrate 1 can be effectively released. This can prevent the first alignment mark 41 from peeling off from the passivation layer 34, avoid the first alignment mark 41 from being eroded, and accurately ensure the calibration accuracy of the first alignment mark 41 with the mask, thereby ensuring the alignment accuracy of the mask and the film layer formed on the substrate 1.

[0054] The display panel involved in the embodiments of this disclosure will be described in detail below with reference to specific examples.

[0055] As shown in Figure 1, a display panel generally includes a substrate 1, a driving circuit layer 2, and a light-emitting layer 3. The driving circuit layer 2 is disposed on one side of the substrate 1, and the light-emitting layer 3 is disposed on the side of the driving circuit layer 2 away from the substrate 1. In addition, the display panel may also include a buffer layer disposed between the substrate 1 and the driving circuit layer 2.

[0056] The substrate 1 can be an inorganic material or an organic material. For example, in one embodiment of this disclosure, the substrate 1 can be made of glass materials such as soda-lime glass, quartz glass, or sapphire glass, or it can be made of metal materials such as stainless steel, aluminum, or nickel.

[0057] In another embodiment of this disclosure, the substrate 1 may also be a flexible substrate 1, for example, the material of the substrate 1 may be polyimide (PI). The substrate 1 may also be a composite of multiple materials. For example, in one embodiment of this disclosure, the substrate 1 may include a bottom film, a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer stacked sequentially.

[0058] In the display area 100, the driving circuit layer 2 includes a transistor layer. The transistor layer may include a first buffer layer 202, a second buffer layer, a first active layer 203, a second active layer 204, a first gate insulating layer 205, a second gate insulating layer 206, a third gate insulating layer 207, a first gate layer 208, a second gate layer 209, a third gate layer 210, a first interlayer dielectric layer 211, and a second interlayer dielectric layer 212. The first buffer layer 202 is disposed on one side of the substrate 1. The first active layer is disposed on the side of the first buffer layer 202 away from the substrate 1. The first gate insulating layer 205 is disposed on the side of the first active layer 203 away from the substrate 1. The first gate layer 208 is disposed on the side of the first gate insulating layer 205 away from the substrate 1. The second gate insulating layer 206 is disposed on the side of the first gate layer 208 away from the substrate 1. The second gate layer 209 is disposed on the side of the second gate insulating layer 206 away from the substrate 1. The first interlayer dielectric layer 211... Layer 211 is disposed on the side of the second gate layer 209 away from the substrate 1, the second buffer layer is disposed on the side of the first interlayer dielectric layer 211 away from the substrate 1, the second active layer 204 is disposed on the side of the second buffer layer away from the substrate 1, the third gate insulating layer 207 is disposed on the side of the second active layer 204 away from the substrate 1, the third gate layer 210 is disposed on the side of the third gate insulating layer 207 away from the substrate 1, and the second interlayer dielectric layer 212 is disposed on the side of the third gate layer 210 away from the substrate 1.

[0059] Both the first active layer 203 and the second active layer 204 may include a channel region. The first gate layer 208 includes a first gate 2081, the orthographic projection of the first gate 2081 on the substrate 1 overlaps with the orthographic projection of the channel region of the first active layer 203 on the substrate 1, forming a first transistor 21. The second gate layer 209 includes a second gate 2091, and the third gate layer 210 includes a third gate 2101, the second gate 2091 and the third gate 2101 overlap with the orthographic projection of the channel region of the second active layer 204 on the substrate 1, forming a second transistor 22. The material of the first active layer 203 is low-temperature polysilicon (LTPS), and the material of the second active layer 204 is indium gallium zinc oxide (IGZO). Therefore, the first transistor 21 is a low-temperature polysilicon thin-film transistor, and the second transistor 22 is an oxide thin-film transistor. The transistor layer may also include a light-shielding layer 201, which is located between the first buffer layer 202 and the substrate 1. The light-shielding layer 201 may overlap with the channel region of the first active layer 203 to shield the light irradiating the first transistor 21, thereby stabilizing the electrical characteristics of the first transistor 21.

[0060] The driving circuit layer 2 may further include a first source / drain conductive layer 214, a second source / drain conductive layer 215, a third source / drain conductive layer 216, a protective layer 213, and a planarization layer group 217. The planarization layer group 217 includes a second planarization layer 2172 and a first planarization layer 2171. The third source / drain metal layer is disposed on the surface of the second interlayer dielectric layer 212 away from the substrate 1. The protective layer 213 is disposed on the side of the third source / drain metal layer away from the substrate 1. The first planarization layer 2171 is disposed on the side of the protective layer 213 away from the substrate 1. The second source / drain conductive layer 215 is disposed on the side of the first planarization layer 2171 away from the substrate 1. The second planarization layer 2172 is disposed on the side of the second source / drain conductive layer 215 away from the substrate 1. The first source / drain conductive layer 214 is disposed on the side of the second planarization layer 2172 away from the substrate 1. The driving circuit layer 2 may also include a third planarization layer 218, which is disposed on the side of the first source / drain conductive layer 214 away from the substrate 1.

[0061] The first active layer 203 has two doped regions of different doping types on both sides of its channel region, which are the source and drain of the first transistor 21, respectively. The second active layer 204 has two doped regions of different doping types on both sides of its channel region, which are the source and drain of the second transistor 22, respectively. The first source-drain conductive layer 214 includes a first source conductive portion 2141 and a first drain conductive portion 2142. The second source-drain conductive layer 215 includes a second source conductive portion 2151 and a second drain conductive portion 2152. The third source-drain conductive layer 216 includes a third source conductive portion 2161 and a third drain conductive portion 2162. The first source conductive portion 2141 is connected to the second source conductive portion 2151 through a first via on the second planarization layer 2172. The first drain conductive portion 2142 is connected to the second drain conductive portion 2162 through the second planarization layer 2172. The second via on layer 2172 is connected to the second drain conductive portion 2152. The second source conductive portion 2151 is connected to the third source conductive portion 2161 through the third via on the first planarization layer 2171. The second drain conductive portion 2152 is connected to the third drain conductive portion 2162 through the fourth via on the first planarization layer 2171. The third source conductive portion 2161 is connected to the source of the transistor through the fifth via. The third drain conductive portion 2162 is connected to the drain of the transistor through the sixth via.

[0062] The light-emitting layer 3 includes a pixel defining layer 31, which is disposed on the side of the third planarization layer 218 away from the array substrate. The pixel defining layer 31 has multiple pixel openings 311. The light-emitting layer 3 may include multiple light-emitting units 32, each disposed within a different pixel opening 311. Each light-emitting unit 32 may include a pixel electrode 321, a light-emitting material layer 322, and a common electrode 323. The pixel electrode 321 is located on the surface of the third planarization layer 218 away from the substrate 1. The pixel electrode 321 is connected to the first drain conductive portion 2142 through a seventh via on the third planarization layer 218. The light-emitting material layer 322 is disposed on the side of the pixel electrode 321 and pixel defining layer away from the substrate 1, and the common electrode 323 is disposed on the side of the light-emitting material layer 322 away from the substrate 1. The pixel electrode 321 and the common electrode 323 can drive the light-emitting element to emit light to display an image.

[0063] The common electrode 323 can serve as the cathode, and the pixel electrode 321 can serve as the anode. Light emission can be driven by applying a signal to the pixel electrode 321; the specific light emission principle will not be detailed here. The light emission element may contain electroluminescent organic light-emitting materials and can be formed using processes such as vapor deposition. For example, the light emission element may include a hole injection layer, a hole transport layer, a light generation layer, an electron transport layer, and an electron injection layer sequentially stacked on the pixel electrode 321 layer. It should be noted that, depending on the emitted color, the light emission element may include a red light emission element, a green light emission element, and a blue light emission element.

[0064] Because the light-emitting material layer 322 protects multiple sub-light-emitting layers 3 groups connected in series, and a charge-generation layer (CGL) is provided between two adjacent sub-light-emitting layers 3 groups, the charge-generation layer is a common layer with strong conductivity, which can easily cause lateral leakage and crosstalk between two adjacent light-emitting units 32. In order to minimize the crosstalk problem, a partition layer 33 is provided on the side of the pixel electrode 321 near the substrate 1, and a partition groove 35 is provided in the part of the partition layer 33 and the pixel definition layer between two adjacent pixel openings 311, so that the light-emitting material layer 322 is isolated in the partition groove 35. The common electrode 323 can break in the partition groove 35, or it can remain intact, without affecting the display effect. The partition groove 35 includes a first groove segment 351 and a second groove segment 352 arranged sequentially along the direction away from the substrate 1. The first groove segment 351 penetrates the partition layer 33, and the second groove segment 352 penetrates the pixel defining layer 31. The orthographic projection of the first groove segment 351 on the substrate 1 is located within the orthographic projection of the second groove segment 352 on the substrate 1.

[0065] As shown in Figures 2 to 16, during the manufacturing process of the display panel, in order to ensure the alignment accuracy between the mask and the film layers already formed on the substrate 1, so that the mask patterns of each film layer fall on the corresponding positions on the substrate 1 after the masking process is completed, alignment marks 4 are usually set in the peripheral area 200. The alignment marks 4 are used to calibrate the setting position of the mask. It should be noted that the peripheral area 200 is set around the outer periphery of the display area 100. Alignment mark 4 may include a first alignment mark 41, a second alignment mark 42, a third alignment mark 43, a fourth alignment mark 44, a fifth alignment mark 45, a sixth alignment mark 46, and a seventh alignment mark 47. The first alignment mark 41 is located in the first source-drain conductive layer 214 and may be disposed in the same layer and with the same material as the first source conductive portion 2141 and the first drain conductive portion 2142. The second alignment mark 42 is located in the second source-drain conductive layer 215. The third alignment mark 43 is located in the third source-drain conductive layer 216. The fourth alignment mark 44 is disposed in the same layer and with the second gate 2091. The fifth alignment mark 45 is disposed in the same layer and with the first gate 2081. The sixth alignment mark 46 is disposed in the same layer and with the first active layer 203. The seventh alignment mark 47 is disposed in the same layer and with the light-shielding layer 201.

[0066] The first buffer layer 202 is transparent. During the formation of the patterned first active layer 203, the exposure machine aligns the layers using the seventh alignment mark 47. During the formation of the patterned first gate 2081, the first gate insulating layer 205 is transparent, and the exposure machine aligns it using the sixth alignment mark 46. During the formation of the patterned second gate 2091, the exposure machine aligns it with the fifth alignment mark 45. At this point, the second gate layer 209 has completed film deposition, and the entire second gate layer 209 formed by film deposition will form a first alignment protrusion at the position directly opposite the fifth alignment mark 45. The second active layer 204 is transparent. During the formation of the patterned second active layer 204, the exposure machine aligns it with the fourth alignment mark 44. When forming the patterned third gate 2101, the exposure machine can also align it using the fourth alignment mark 44. At this time, the third gate layer 210 has completed film deposition, and the entire third gate layer 210 formed by film deposition will form a second alignment protrusion at the position directly opposite the fourth alignment mark 44. The first interlayer dielectric layer 211 is transparent. When forming vias on the first interlayer dielectric layer 211, the exposure machine aligns with the fourth alignment mark 44.

[0067] When forming the patterned third source / drain conductive layer 216, the exposure machine can also be aligned using the sixth alignment mark 46. At this point, the third source / drain conductive layer 216 has completed film deposition, and the entire third source / drain conductive layer 216 formed by film deposition will form a third alignment protrusion at the position directly opposite to the sixth alignment mark 46. The protective layer 213 is transparent, and the exposure machine is aligned with the third alignment mark 43 when forming the protective layer 213. The second planarization layer 2172 is transparent, and the exposure machine is aligned with the third alignment mark 43 when forming vias on the second planarization layer 2172. When forming the patterned second source / drain conductive layer 215, the exposure machine can be aligned using the third alignment mark 43. At this point, the second source / drain conductive layer 215 has completed film deposition, and the entire second source / drain conductive layer 215 formed by film deposition will form a fourth alignment protrusion at the position directly opposite to the third alignment mark 43. The first planarization layer 2171 is transparent. When forming vias on the first planarization layer 2171, the exposure machine aligns with the second alignment mark 42. When forming the patterned first source / drain conductive layer 214, the exposure machine can align using the second alignment mark 42. At this time, the first source / drain conductive layer 214 has completed film deposition, and the entire first source / drain conductive layer 214 formed by film deposition will form a fifth alignment protrusion at the position directly opposite the second alignment mark 42. The third planarization layer 218 is transparent. When forming vias on the third planarization layer 218, the exposure machine aligns with the first alignment mark 41.

[0068] When forming the patterned pixel electrode 321, the exposure machine can align it using the first alignment mark 41. At this time, the pixel electrode 321 layer has completed film deposition. The entire pixel electrode 321 layer formed by film deposition will form a sixth alignment protrusion at the position directly opposite to the first alignment mark 41. The first gate insulating layer 205, the second gate insulating layer 206, the pixel defining layer 31, the first interlayer dielectric layer 211, the second interlayer dielectric layer 212, the second planarization layer 2172, the first planarization layer 2171, the third planarization layer 218, and the pixel defining layer 31 are transparent. When forming the pixel defining layer 31, the exposure machine aligns it with the sixth alignment mark 46. As shown in Figure 1, the first alignment mark 41 is disposed on the side of the first planarization layer 2171 away from the substrate 1. The passivation layer 34 covers the first alignment mark 41. The passivation layer 34 is provided with a first cover layer 36 on the side away from the substrate 1. The first cover layer 36 is provided with a second cover layer 37 on the side away from the substrate 1. The first cover layer 36 is disposed in the same layer and with the same material as the pixel electrode 321. The second cover layer 37 is disposed in the same layer and with the same material as the common electrode 323.

[0069] As shown in Figure 17, during the fabrication of the display panel, multiple display areas 100 are formed on a substrate 5, and the driving circuit layer 2 and the light-emitting layer 3 of each display panel are formed in different display areas 100. To ensure alignment accuracy, a certain number of alignment marks 4 need to be set in the first direction and the second direction respectively. In this embodiment, a row of alignment marks 4 can be set at both ends of the substrate 5 along the second direction, and two sets of alignment marks 4 are set between the two rows of alignment marks 4 at intervals along the second direction. Each set of alignment marks 4 may include three adjacent rows of alignment marks 4. Eleven columns of alignment marks 4 are set along the first direction, wherein two columns of alignment marks 4 are located at both ends of the substrate 5 along the first direction, and the remaining columns of alignment marks 4 are located between two adjacent columns of display areas 100 along the first direction.

[0070] As shown in Figures 18 to 22, to prevent the first alignment mark 41 from being eroded by water and oxygen, a passivation layer 34 is provided between the pixel electrode 321 layer and the first alignment mark 41, covering the first alignment mark 41. The passivation layer 34 is provided with a water vapor release port 341, the orthographic projection of the water vapor release port 341 on the substrate 1 overlapping with the orthographic projection of the first alignment mark 41 on the substrate 1. Water vapor between the passivation layer 34 and the first alignment mark 41 can escape through the water vapor release port 341, greatly reducing the possibility of peeling between the passivation layer 34 and the first alignment mark 41.

[0071] Because the passivation layer 34 has a strong ability to isolate water and oxygen, the moisture between the second planarization layer 2172 and the passivation layer 34 cannot be effectively released. During the high-temperature process of forming the pixel electrode 321, the movement of water vapor at the contact surface between the first alignment mark 41 and the passivation layer 34 intensifies, eventually leading to the peeling off of the passivation layer 34. Therefore, the coverage area of ​​the water vapor release port 341 can be expanded so that the orthographic projection of the water vapor release port 341 on the substrate 1 overlaps with the orthographic projections of the first alignment mark 41 and the easily peelable area on the substrate 1.

[0072] As shown in Figure 21, the first alignment mark 41 is cross-shaped, including a first alignment portion 411 and a second alignment portion 412. The first alignment portion 411 extends along a first direction, and the second alignment portion 412 extends along a second direction. The first direction and the second direction are perpendicular to each other, and the first alignment portion 411 and the second alignment portion 412 intersect each other. The first alignment mark 41 and the easily peelable area located around the first alignment mark 41 can be directly removed. That is, the orthographic projection of the first alignment mark 41 on the substrate 1 and the orthographic projection of the easily peelable area on the substrate 1 are both located within the orthographic projection of the moisture release port 341 on the substrate 1. The pixel electrode 321 and the common electrode 323 are directly covered on the side of the first alignment mark 41 and the second planarization layer 2172 away from the substrate 1.

[0073] As shown in Figure 22, four first moisture release holes 3411 can also be provided on the passivation layer 34. Each first moisture release hole 3411 includes a first strip-shaped portion 3413 and a second strip-shaped portion 3414 connected end-to-end. The first strip-shaped portion 3413 is parallel to the first alignment portion 411, and the second strip-shaped portion 3414 is parallel to the second alignment portion 412. The first alignment portions 411 of the four first moisture release holes 3411 are spaced apart and symmetrical along a second direction, and the second alignment portions 412 of the four first moisture release holes 3411 are spaced apart and symmetrical along a first direction. Four easily peelable areas are formed around the first alignment mark 41. Each of the four easily peelable areas is provided with a plurality of arrayed second moisture release holes 3412. The plurality of second moisture release holes 3412 are arranged in multiple rows along the first direction and in multiple columns along the second direction. It can be understood that the plurality of second moisture release holes 3412 are arranged in a rectangular array.

[0074] This disclosure also provides a display device, which may include the display panel mentioned above in this disclosure. The specific structure and beneficial effects of the display panel have been described in detail above, and therefore will not be repeated here.

[0075] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts, such as the casing, circuit board, power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0076] Display devices can be traditional electronic devices, such as mobile phones, computers, televisions, and video recorders, or emerging wearable devices, such as virtual reality devices and augmented reality devices, which will not be listed here.

[0077] It should be noted that the above embodiments are interconnected and can be combined to form other solutions. The solutions disclosed herein are not limited to those described in the above embodiments. Those skilled in the art will readily conceive of other embodiments of this disclosure upon considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims. 。

Claims

1. A display panel having a display area and a peripheral area located peripherally of the display area, wherein, The display panel comprises: a substrate substrate; a planarization layer group arranged on one side of the substrate substrate; a first source-drain conductive layer arranged on a side of the planarization layer group away from the substrate substrate, the first source-drain conductive layer comprising a first alignment mark, the first alignment mark being located in the peripheral area; a passivation layer arranged on a side of the first source-drain conductive layer away from the substrate substrate, the passivation layer being provided with a water vapor release port, a normal projection of the water vapor release port on the substrate substrate at least overlapping a normal projection of the first alignment mark on the substrate substrate.

2. The display panel of claim 1, wherein, The planarization layer group has a peelable area, the peelable area being arranged in the periphery of the first alignment mark, and a normal projection of the water vapor release port on the substrate substrate and a normal projection of the first alignment mark and the peelable area on the substrate substrate both overlapping.

3. The display panel of claim 2, wherein, The normal projection of the first alignment mark and the peelable area on the substrate substrate is located within the normal projection of the water vapor release port on the substrate substrate, exposing a side of the first alignment mark away from the substrate substrate, a side of the first alignment mark, and a side of the peelable area away from the substrate substrate.

4. The display panel of claim 2, wherein, The water vapor release port comprises a first water vapor release hole and a second water vapor release hole, a normal projection of the first water vapor release hole on the substrate substrate overlapping a normal projection of the first alignment mark on the substrate substrate, and a normal projection of the second water vapor release hole on the substrate substrate overlapping a normal projection of the peelable area on the substrate substrate.

5. The display panel of claim 4, wherein, The first alignment mark comprises a first alignment portion and a second alignment portion, the first alignment portion and the second alignment portion intersecting each other, the first alignment portion extending in a first direction, and the second alignment portion extending in a second direction, the second direction being perpendicular to the first direction, the first water vapor release hole comprising a first strip portion and a second strip portion connected end to end, the first strip portion being parallel to the first alignment portion, and the second strip portion being parallel to the second alignment portion.

6. The display panel of claim 5, wherein, The passivation layer is provided with four first water vapor release holes, the first alignment portions of the four first water vapor release holes being spaced apart and symmetrical in the second direction, and the second alignment portions of the four first water vapor release holes being spaced apart and symmetrical in the first direction.

7. The display panel of claim 5 or 6, wherein, The periphery of each first water vapor release hole forms a peelable area, and the four peelable areas are respectively provided with a plurality of arrayed second water vapor release holes.

8. The display panel of claim 1, wherein, The display panel further comprises: a partition layer arranged in the same layer as the passivation layer and located in the display area; a plurality of pixel electrodes arranged on a side of the passivation layer away from the substrate substrate; a pixel definition layer arranged on a side of the pixel electrode away from the substrate substrate, the pixel definition layer being provided with pixel openings exposing the pixel electrodes; a light-emitting material layer arranged on a side of the pixel definition layer away from the substrate substrate; a partition groove is arranged between adjacent two pixel openings, the light-emitting material layer is partitioned in the partition groove, the partition groove penetrates through the pixel definition layer and at least part of the partition layer.

9. The display panel of claim 8, wherein, The partition groove comprises a first groove segment and a second groove segment arranged in sequence in a direction away from the substrate base plate, the first groove segment penetrates the partition layer, and the second groove segment penetrates the pixel definition layer, and a projection of the first groove segment on the substrate base plate is located in a projection of the second groove segment on the substrate base plate.

10. The display panel of claim 8, wherein, The display panel further comprises a transistor layer arranged between the first source-drain conductive layer and the substrate base plate, the transistor layer comprising at least one transistor, the first source-drain conductive layer comprising a first source conductive part and a first drain conductive part, the first source conductive part and the second drain conductive part being located in the display area, the first source conductive part being connected to the source of the transistor, the first drain conductive part being connected to the drain of the transistor, and the pixel electrode being connected to the first drain conductive part.

11. The display panel of claim 10, wherein, The display panel further comprises a second source-drain conductive layer and a third source-drain conductive layer, the second source-drain conductive layer being arranged between the first source-drain conductive layer and the transistor layer, and the third source-drain conductive layer being arranged between the second source-drain conductive layer and the transistor layer, the planarization layer group comprising a second planarization layer and a first planarization layer, the second planarization layer being away from between the first source-drain conductive layer and the second source-drain conductive layer, and the first planarization layer being arranged between the second source-drain conductive layer and the third source-drain conductive layer, the second source-drain conductive layer comprising a second source conductive part and a second drain conductive part, the third source-drain conductive layer comprising a third source conductive part and a third drain conductive part, the first source conductive part being connected to the second source conductive part through a first via hole on the second planarization layer, the first drain conductive part being connected to the second drain conductive part through a second via hole on the second planarization layer, the second source conductive part being connected to the third source conductive part through a third via hole on the first planarization layer, the second drain conductive part being connected to the third drain conductive part through a fourth via hole on the first planarization layer, the third source conductive part being connected to the source of the transistor through a fifth via hole, and the third drain conductive part being connected to the drain of the transistor through a sixth via hole.

12. The display panel of claim 11, wherein, The display panel further comprises a third planarization layer arranged between the passivation layer and the first source-drain conductive layer, and the pixel electrode is connected to the first drain conductive part through a seventh via hole on the third planarization layer.

13. The display panel of claim 11, wherein, The transistor layer comprises a first active layer, a second active layer, a first gate, a second gate and a third gate, the first active layer is arranged on one side of the substrate, the first gate is arranged on the side of the first active layer away from the substrate, the first gate is overlapped with the channel region of the first active layer on the substrate to form a first transistor, the second gate is arranged on the side of the first gate away from the substrate, the second active layer is arranged on the side of the second gate away from the substrate, the third gate is arranged on the side of the second gate away from the substrate, the second gate and the third gate are overlapped with the channel region of the second active layer on the substrate to form a second transistor, the material of the first active layer is low-temperature polysilicon, and the material of the second active layer is indium gallium zinc oxide.

14. A display device, wherein, The display panel comprises the display panel of any one of claims 1 to 13.

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