Data packet forwarding method, gateway device, storage medium and program

Abstract

Provided in the embodiments of the present disclosure are a data packet forwarding method, a gateway device, a storage medium and a program. The gateway device comprises a plurality of processors and a network card provided with a programmable chip, wherein the plurality of processors comprise a control processor and a plurality of data processors. The control processor sends to the programmable chip a scheduling mode setting instruction including a first scheduling mode, determines weighted round-robin values of the plurality of data processors on the basis of loads of the plurality of data processors, and sends the weighted round-robin values of the plurality of data processors to the programmable chip. The programmable chip receives a data packet sent by a source-end device, and determines, on the basis of the first scheduling mode and the weighted round-robin values of the plurality of data processors, a first data processor, the number of round-robin cycles of which has reached a corresponding weighted round-robin value, and the programmable chip then distributes the data packet to the first data processor for processing, receives the processed data packet fed back by the first data processor, and sends the processed data packet to a destination-end device. The solution can reduce the forwarding delay of data packets.

Description

[0001] This disclosure relates to the field of network technology, and more particularly to a packet forwarding method, gateway device, storage medium, and program. Background: The communication traffic carried on the Internet is constantly growing and changing. Among them, the transmission of "elephant flows" consumes more network resources. An elephant flow refers to network traffic that lasts a long time and has a large data volume. For example, an elephant flow, which accounts for about 5% of the network traffic, may account for about 40% of the network bandwidth. Common examples of elephant flows include virtual machine migration, data migration, and data processing in distributed databases. In scenarios such as data centers, there is often a need to forward elephant flows. For example, a gateway device in a data center may forward an elephant flow received from a switch to a corresponding cloud server. Currently, in gateway devices, the processor (usually a CPU) can use the Data Plane Development Kit (DPDK) application to accelerate packet processing. In simple terms, DPDK applications run in the operating system's user space, utilizing their own data plane library for packet sending and receiving, bypassing the kernel-mode protocol stack to improve packet processing efficiency. A single CPU handles a large volume of packets, and since this CPU is a general-purpose processor with limited processing power and may also need to handle other tasks, the packet forwarding performance remains low despite the acceleration provided by the DPDK application. This invention discloses a packet forwarding method, gateway device, storage medium, and program to reduce packet forwarding latency.In a first aspect, embodiments of this disclosure provide a data packet forwarding method applied to a programmable chip in a network interface card (NIC). The NIC is located in a gateway device, which includes multiple processors, including a control processor and multiple data processors. The method includes: receiving a scheduling mode setting instruction containing a first scheduling mode sent by the control processor, and a weighted round-robin value of the multiple data processors, wherein the weighted round-robin value of the multiple data processors is determined by the control processor based on the load of the multiple data processors; receiving a first data packet sent by a source device; determining a first data processor whose round-robin count has reached a corresponding weighted round-robin value based on the first scheduling mode and the weighted round-robin value of the multiple data processors; distributing the first data packet to the first data processor for processing; receiving a first processed data packet fed back by the first data processor; and sending the first processed data packet to a corresponding destination device. Secondly, embodiments of this disclosure provide a data packet forwarding device applied to a programmable chip in a network interface card (NIC). The NIC is located in a gateway device, which includes multiple processors, including a control processor and multiple data processors. The device includes: a first receiving module configured to receive a scheduling mode setting instruction containing a first scheduling mode sent by the control processor, and weighted polling values ​​of the multiple data processors, wherein the weighted polling values ​​of the multiple data processors are determined by the control processor based on the load of the multiple data processors; a second receiving module configured to receive a first data packet sent by a source device; a determining module configured to determine a first data processor whose polling count has reached a corresponding weighted polling value based on the first scheduling mode and the weighted polling values ​​of the multiple data processors; a first sending module configured to distribute the first data packet to the first data processor for processing; the first receiving module is further configured to receive a first processed data packet fed back by the first data processor; and the second sending module configured to send the first processed data packet to a corresponding destination device. Thirdly, embodiments of this disclosure provide a non-transitory machine-readable storage medium storing executable code. When the executable code is executed by a programmable chip in a gateway device, the programmable chip can at least implement the packet forwarding method as described in the first aspect. Fourthly, embodiments of this disclosure provide a computer program product comprising a computer program that, when executed by a programmable chip in a gateway device, enables the programmable chip to at least implement the packet forwarding method as described in the first aspect.Fifthly, this disclosure provides a data packet forwarding method applied to a control processor among multiple processors in a gateway device. The gateway device includes the multiple processors and a network interface card (NIC). The NIC includes a programmable chip. The multiple processors include the control processor and multiple data processors. The method includes: sending a scheduling mode setting instruction containing a first scheduling mode to the programmable chip; determining the load of the multiple data processors and determining a weighted round-robin value for the multiple data processors based on their loads; sending the weighted round-robin value to the programmable chip, so that when the programmable chip receives a first data packet sent by a source device, it determines, based on the first scheduling mode and the weighted round-robin value of the multiple data processors, the first data processor whose round-robin count has reached the corresponding weighted round-robin value, and distributes the first data packet to the first data processor for processing. Sixthly, embodiments of this disclosure provide a data packet forwarding apparatus applied to a control processor among multiple processors in a gateway device. The gateway device includes the multiple processors and a network interface card (NIC). The NIC includes a programmable chip. The multiple processors include the control processor and multiple data processors. The apparatus includes: a sending module configured to send a scheduling mode setting instruction containing a first scheduling mode to the programmable chip; a determining module configured to determine the load of the multiple data processors and determine a weighted polling value of the multiple data processors based on the load of the multiple data processors; the sending module is further configured to send the weighted polling value of the multiple data processors to the programmable chip, so that when the programmable chip receives a first data packet sent by a source device, based on the first scheduling mode and the weighted polling value of the multiple data processors, it determines a first data processor whose polling count has reached the corresponding weighted polling value, and distributes the first data packet to the first data processor for processing. In a seventh aspect, embodiments of this disclosure provide a non-transitory machine-readable storage medium storing executable code, which, when executed by a processor of a gateway device, enables the processor to at least implement the packet forwarding method as described in the fifth aspect. In an eighth aspect, embodiments of this disclosure provide a computer program product comprising a computer program, which, when executed by a processor of a gateway device, enables the processor to at least implement the packet forwarding method as described in the fifth aspect.Ninthly, embodiments of this disclosure provide a gateway device, including: a plurality of processors, the plurality of processors including a control processor and a plurality of data processors; a network interface card (NIC), the NIC including a programmable chip, the NIC being communicatively connected to the plurality of processors; the control processor is configured to: send a scheduling mode setting instruction including a first scheduling mode to the programmable chip, and determine the load of the plurality of data processors, and determine a weighted polling value of the plurality of data processors based on the load of the plurality of data processors, and send the weighted polling value of the plurality of data processors to the programmable chip; the programmable chip is configured to: receive a first data packet sent by a source device, determine a first data processor whose polling count has reached a corresponding weighted polling value based on the first scheduling mode and the weighted polling value of the plurality of data processors, distribute the first data packet to the first data processor for processing, receive a first processed data packet fed back by the first data processor, and send the first processed data packet to a corresponding destination device. Tenthly, this disclosure provides a network interface card (NIC) including a programmable chip. The NIC is communicatively connected to multiple processors in a gateway device, including a control processor and multiple data processors. The NIC is located in the gateway device. The programmable chip is configured to receive a scheduling mode setting instruction including a first scheduling mode sent by the control processor and a weighted polling value of the multiple data processors; receive a first data packet sent by a source device; determine a first data processor whose polling count has reached a corresponding weighted polling value based on the first scheduling mode and the weighted polling value of the multiple data processors; distribute the first data packet to the first data processor for processing; and receive a first processed data packet fed back by the first data processor and send the first processed data packet to a corresponding destination device. The weighted polling value of the multiple data processors is determined by the control processor based on the load of the multiple data processors. The gateway device provided in this disclosure includes multiple processors and a NIC with an internal programmable chip, thereby leveraging the inherent high-speed parallel processing advantage of the programmable chip to achieve high-speed forwarding of data packets sent by the source device to the destination device. The gateway device comprises multiple processors, including a control processor that primarily provides control functions and multiple data processors that process data packets. Based on this configuration, efficient packet forwarding can be achieved through a combination of hardware and software. The software refers to the control program running on the control processor, while the hardware refers to the hardware language code programmed into the programmable chip.Specifically, the control processor sends a scheduling mode setting instruction, including a first scheduling mode (such as a weighted round-robin mode), to the programmable chip. It also determines the load of multiple data processors, determines a weighted round-robin value for each data processor based on their load, and sends this weighted round-robin value to the programmable chip. Thus, upon receiving the first data packet from the source device, the programmable chip, based on the first scheduling mode and the weighted round-robin value, determines the first data processor whose round-robin count has reached the corresponding weighted round-robin value, and distributes the first data packet to that first data processor for processing. Upon receiving the first processed data packet from the first data processor, the programmable chip sends the processed data packet to the corresponding destination device. In the aforementioned gateway device architecture, by coordinating the hardware and software of the control processor and the programmable chip to load-balance the distribution of data packets received by the network interface card to different data processors, the frequency of data packet distribution to high-load data processors can be reduced, achieving balanced utilization of data processor resources and reducing the packet forwarding latency caused by high data processor load. Brief Description of the Drawings To more clearly illustrate the technical solutions in the embodiments of this disclosure, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Figure 1 is a schematic diagram of the composition of a gateway device provided in an embodiment of this disclosure; Figure 2 is a schematic diagram of one working process of a gateway device provided in an embodiment of this disclosure; Figure 3 is a schematic diagram of another working process of a gateway device provided in an embodiment of this disclosure; Figure 4 is a flowchart of a data packet forwarding method provided in an embodiment of this disclosure; Figure 5 is a flowchart of a data packet forwarding method provided in an embodiment of this disclosure; Figure 6 is a structural schematic diagram of a data packet forwarding device provided in an embodiment of this disclosure; Figure 7 is a structural schematic diagram of a data packet forwarding device provided in an embodiment of this disclosure. Detailed Description of the Embodiments To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the embodiments of this disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are some embodiments of this disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this disclosure.It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse. The following describes some embodiments of this disclosure in detail with reference to the accompanying drawings. Where there is no conflict between the embodiments, the following embodiments and features in the embodiments can be combined with each other. In addition, the timing of the steps in the following method embodiments is only an example and not a strict limitation. First, some concepts involved in the embodiments of this disclosure are explained. Gateway device: This can be a gateway-type forwarding node in application scenarios such as data centers, and is the convergence point of traffic. Field-Programmable Gate Array (FPGA): This is a programmable chip, a reconfigurable integrated circuit at the hardware level. Gini coefficient: The Gini coefficient is used as an indicator to measure the degree of imbalance (or inequality) in CPU load distribution. The Gini coefficient value ranges from 0 to 1, where 0 represents complete equality and 1 represents complete inequality. Instructions per clock (IPC): The number of instructions a CPU can execute per clock cycle. Round Robin (RR) algorithm: In the packet distribution process described below, this refers to distributing packets to various CPUs in a round-robin fashion. Weighted Round Robin (WRR) algorithm: Adds weights to the simple round-robin scheduling algorithm. To cope with high bandwidth consumption network traffic such as elephant flows, currently, in gateway devices, CPUs can use DPDK applications to accelerate packet forwarding. Furthermore, currently, a single elephant flow is centrally processed by one CPU (i.e., one CPU core). Because CPUs are general-purpose processors with limited processing power and may also need to handle other tasks, packet forwarding performance remains unsatisfactory despite acceleration by DPDK applications.In view of this, this disclosure provides a new network interface card (NIC) structure, which includes a programmable chip, such as an FPGA, to achieve high-speed forwarding of data packets from source devices to destination devices by leveraging its high-speed parallel processing capabilities. In summary, the programmable chip in the NIC can receive data packets corresponding to various network traffic streams sent by one or more source devices, distribute them to different CPUs for processing, such as encapsulating packet headers and performing security checks on the data packets. Finally, the programmable chip receives the processed data packets from each CPU and forwards them to the corresponding destination devices. This network traffic distribution protects the CPUs and prevents excessive load on a single CPU's data packet processing tasks. The NIC has load balancing and data packet ordering features. The following section describes the composition structure of the gateway device provided in this disclosure embodiment with reference to Figure 1. Figure 1 is a schematic diagram of the gateway device provided in this disclosure embodiment. As shown in Figure 1, the gateway device includes multiple processors and a NIC, with the NIC containing a programmable chip. In this context, multiple processors typically refer to multiple CPUs, such as CPU0, CPU1, CPU2, ..., CPUn illustrated in Figure 1. The programmable chip is, for example, the FPGA chip illustrated in Figure 1, but is not limited to this; other dedicated integrated circuits can also be used. The following explanation uses CPUs as the processors and FPGA chips as the programmable chip. In summary, for any network traffic sent from any source device, the FPGA chip receives the data packets corresponding to that network traffic (data packet reception), and sequentially distributes different data packets to different CPUs for processing (data packet distribution). This includes processes such as packet header encapsulation and security checks. The FPGA chip then receives the processed data packets from each CPU and forwards them to the corresponding destination device. In practical applications, the source device can be a switch, and the destination device can be a cloud server. The multiple CPUs process the data packets by running software programs, which is the software layer, while the FPGA chip is the hardware layer, and the code related to the data packet forwarding logic programmed into it is also hardware code. This process combines hardware and software (multiple CPUs and FPGA chip). This enables high-speed forwarding of data packets.Taking a source device illustrated in Figure 1 as an example, this source device continuously outputs data packets, which are received sequentially by the FPGA chip. The currently received data packet is called the first data packet. Based on a set scheduling mode, the first data packet is distributed, for example, to CPU1. CPU1 processes the first data packet to obtain the first processed data packet, which is then fed back to the FPGA chip. The FPGA chip sends the first processed data packet to the corresponding destination device. The first data packet consists of two parts: a header and payload data. The header includes the source IP address and source port number corresponding to the source device, as well as the destination IP address and destination port number corresponding to the destination device, and also includes fields such as the protocol number, from which the destination device can be identified.

[0002] In addition to providing the aforementioned data packet reception, distribution, and transmission functions, FPGAs also provide order-keeping detection and timeout detection functions. Specifically, assuming the FPGA chip receives data packets a and b sequentially sent by the source device as shown in Figure 1, it first distributes data packet a to CPU1, and then distributes data packet b to CPU2. Normally, according to the order of data packet distribution, the FPGA chip should first receive the processed data packet a' (the processing result of data packet a) from CPU1, and then receive the processed data packet b' (the processing result of data packet b) from CPU2. However, due to the different processing delays of CPU1 and CPU2, it may receive the processed data packet b' first. In this case, the FPGA chip will not directly send the processed data packet b' to the destination device, but will wait for the processed data packet a' to arrive before sequentially sending both processed data packets a' and b' to the destination device. This ensures that the corresponding processed data packets are sent to the corresponding destination devices according to the order of data packet reception. In practical applications, each data packet has a corresponding sequence number, which determines the order of data packets: the first received data packet has a smaller sequence number. Regarding the timeout detection function, if after receiving a processed data packet b', a set time is waited, and if the processed data packet a' is not received within that time, then the wait will cease, and the processed data packet b' will be sent to the destination device. If the processed data packet a' is received later, it will be sent to the destination device immediately. During the data packet reception, distribution, and transmission process of the FPGA chip, the distribution of different data packets to different CPUs can employ a scheduling mode, such as the Redirect Response (RR) mode. In RR mode, whenever a data packet corresponding to an elephant stream is received from the source device, the elephant stream can be distributed across various CPUs by distributing the data packets one by one, reducing the impact of the elephant stream on a single CPU and preventing excessive load on a single CPU. Taking CPU1, CPU2-CPUn as an example, each CPU is polled sequentially. When a data packet is received, it is distributed to CPU1. When the next data packet is received, it is distributed to CPU2, and so on. However, in actual gateway devices, in addition to the data packet processing logic described above, there are still a large number of other task processing logics on the CPUs, and the task processing threads and their overhead ratios differ on each CPU. Distributing a large number of data packets to high-load CPUs will introduce high processing latency, resulting in longer forwarding latency for these data packets.Furthermore, since data packets need to be forwarded in order, meaning they are sent to the destination device according to the order they are received, even if some low-load CPUs have already processed the distributed data packets, the FPGA chip still needs to wait for the high-load CPU to finish processing the earlier distributed data packets before it can send them to the destination device normally. This affects the forwarding latency of all data packets. Therefore, this disclosure provides a data packet forwarding method based on CPU load, reducing the data packet distribution frequency of high-load CPUs, achieving balanced utilization of overall CPU resources in the gateway device, solving the high latency problem of data packet forwarding caused by high CPU load, and ensuring ordered forwarding of data packets. In this embodiment, the multiple CPUs in the gateway device are divided into different functional types. The CPU that mainly provides control functions is called the control CPU, and the CPU used to process data packets is called the data CPU. Based on the composition of this gateway device, efficient data packet forwarding can be achieved through hardware and software collaboration. The software mainly refers to the software program that controls the CPU and provides control functions, while the hardware refers to the hardware language code burned into the FPGA chip, which mainly completes the functions of receiving, distributing, and sending data packets. The software also includes software programs that provide data processing functions and run on the data CPUs. In the gateway device architecture shown in Figure 1, for example, CPU0 can be set as the control CPU, and CPU1-CPUn can be set as multiple data CPUs. Figure 2 is a schematic diagram of the working process of a gateway device provided in an embodiment of this disclosure. As shown in Figure 2, the control CPU includes CPU0, and the data CPUs include CPU1-CPUn. The control CPU sends a scheduling mode setting instruction containing a first scheduling mode (e.g., WRR) to the FPGA chip. The FPGA chip writes the first scheduling mode into its local first register. The control CPU determines the load of the multiple data CPUs, i.e., calculates the load of each data CPU, and determines the weighted polling value of the multiple data CPUs based on the load of the multiple data CPUs, i.e., calculates the weighted polling value of each data CPU. The weighted polling value of the multiple data CPUs is then sent to the FPGA chip, and the FPGA chip writes the weighted polling value of the multiple data CPUs into its local second register.

[0003] The FPGA chip receives the first data packet sent by the source device. Based on the first scheduling mode and the weighted polling value of multiple data CPUs, it determines the first data CPU that has reached the corresponding weighted polling value after a certain number of polling attempts. The first data packet is then distributed to the first data CPU for processing. The FPGA receives the first processed data packet from the first data CPU and sends it to the corresponding destination device. In practical applications, the gateway device can provide a scheduling mode setting interface. The first scheduling mode can be manually input, and the CPU can receive this setting information and issue a scheduling mode setting instruction containing the first scheduling mode to the FPGA chip. The FPGA then writes the first scheduling mode into its local first register used for storing scheduling modes. In other words, the FPGA chip receives data packets, reads the received data, and writes the first scheduling mode (WRR) into the first register. The following example uses WRR as the first scheduling mode; other scheduling modes based on CPU load can also be applied. In practical applications, the control CPU can periodically calculate the load of each data CPU, thereby periodically determining the weighted polling value of each data CPU in different periods. The calculated weighted polling value for each data CPU in the current period is then sent to the FPGA chip for storage in the second register. It is understandable that for a data CPU, its load is calculated every set period, and since the load is dynamically changing, the weighted polling value calculated for that data CPU in each period is also dynamically changing. The weighted polling value of each data CPU can be the load weighting metric used when employing WRR mode. The following describes how the control CPU calculates the load of each data CPU at a certain calculation moment determined based on the set period. Optionally, the control CPU obtains at least one load metric corresponding to each of the multiple data CPUs, and determines the load of the multiple data CPUs based on this metric. The load metric may include at least one of the following: utilization (C), IPC (I), response time (T), number of running threads (N), and cache usage (S). The CPU load for any given data can be calculated as: (a*C+b*T+c*N) / (d*l + e*S), where a, b, c, d, and e are set coefficients.In practical applications, taking a cycle length of Z as an example, if the last load calculation was performed at time t1, then the next load calculation will be performed at time t2 = t1 + Z. The control CPU can read the log files generated by the gateway device and retrieve the various load metrics corresponding to each data CPU at time t2, thus completing the load calculation for each CPU in this cycle. Calculating the data CPU load using these multiple load metrics allows the load calculation results to more accurately reflect the true load situation of the data CPUs. In practical applications, the aforementioned set coefficients can be obtained based on testing. The testing process can be as follows: under a certain initial load condition for each data CPU, different test data packets are continuously distributed to different data CPUs, and the load of each data CPU is recalculated according to the above calculation formula. During the calculation process, the value of the set coefficients is adjusted, with the ultimate goal of balancing the load of each data CPU. Therefore, setting appropriate set coefficients can not only reflect the differences in load among different data CPUs but also ultimately help achieve load balancing among the data CPUs. Because the weighted round-robin (WRR) scheduling process calculates the weighted round-robin value based on the load of each data CPU, it can be understood that the higher the load of a data CPU, the lower its weighted round-robin value, and the fewer data packets it receives, thus ultimately achieving load balancing across multiple data CPUs. After calculating the load of each data CPU for the current period, the control CPU can determine the weighted round-robin value for each data CPU based on the load calculation results. Optionally, the control CPU can take the reciprocal of the load of each data CPU, amplify the lowest reciprocal to one, determine the corresponding amplification factor, and amplify the other reciprocals by this factor to obtain the weighted round-robin value for each data CPU. If the result of multiplying other reciprocals by the amplification factor is not an integer, it can be rounded to the nearest integer. The method for determining the weighted round-robin value is not limited to this; other methods based on load to determine the weighted round-robin value are also acceptable, as long as they conform to the rule that the higher the load, the lower the weighted round-robin value. Assuming the data CPUs include CPU1, CPU2, and CPU3, their reciprocals of load are 0.1, 0.8, and 1, respectively. It can be understood that the higher the load, the smaller the reciprocal of the load.Amplifying 0.1 to 1 requires a 10-fold amplification, resulting in a weighted polling value of 1 for CPU1. Amplifying 0.8 by the same factor yields 8, so the weighted polling value for CPU2 is 8. Similarly, the weighted polling value for CPU3 is 10. The reason for amplifying the lowest reciprocal value to one is that in weighted polling scheduling modes such as WRR, the lower limit for the number of polls is one. The weighted polling value of a data CPU serves as a weight indicator for data packet distribution to it. The larger the value, the more polls are needed before a data packet is distributed to that data CPU. Assuming a data CPU's weighted polling value is X, it means that only one data packet is distributed to that data CPU after X polls. In practical applications, optionally, in this embodiment, the FPGA chip can maintain a queue for each data CPU. Data packets distributed to a data CPU can be sent to its corresponding queue, and the data CPU can read the data packet from the queue for processing. Therefore, the weighted polling value of each data CPU can also be regarded as the weighted polling value of its corresponding queue.

[0004] The FPGA chip receives the weighted polling values ​​of each data CPU sent by the control CPU and stores them in its local second register. As shown in Figure 2, when the FPGA chip receives the first data packet sent by a source device, it reads the scheduling mode from the first register: the first scheduling mode, such as WRR mode. If the read scheduling mode is determined to be the first scheduling mode, it reads the weighted polling value corresponding to each data CPU from the second register. Thus, using WRR mode, based on the read weighted polling values ​​of each data CPU, the first data CPU to distribute the first data packet is determined, and the first data packet is distributed to the first data CPU. In other words, the FPGA chip can perform data packet distribution in WRR mode, including reading and comparison.

[0005] The FPGA chip can trigger a scheduling event each time it receives a data packet. The scheduling process upon receiving the first data packet can be as follows: Based on the order of multiple data CPUs, starting with the next data CPU after the data CPU that last received the data packet, poll each data CPU and perform the following processing: Increment the first polling count value corresponding to the currently polled target data CPU by one to obtain the second polling count value. If the second polling count value is greater than or equal to the weighted polling value corresponding to the target data CPU, then the target data CPU is determined as the first data processor. Here, the first polling count value is the polling count value updated when the target data CPU was last polled, and the polling count value corresponding to the first data CPU is cleared. If the second polling count value is less than the weighted polling value corresponding to the target data CPU, then poll the next data CPU after the target data CPU.

[0006] In the FPGA chip, a polling count variable `index` is maintained for each data CPU. Each time a data CPU is polled, the corresponding polling count is incremented by one (i.e., `index+1`). When the incremented `index` equals the weighted polling value for that data CPU, the `index` is reset to zero. Therefore, the initial value of `index` is zero. The sorting of the multiple data CPUs can be based on the numerical order assigned to each data CPU in the gateway device. Taking the multiple data CPUs illustrated in Figure 2 as an example, assuming the sorting result of the multiple data CPUs is CPU1, CPU2, ..., CPUn, and the weighted polling values ​​of these n data CPUs are L1, L2...Ln... oFor ease of description, assume that after the FPGA chip receives the weighted polling values ​​of each data CPU sent by the control CPU for the first time, the first data packet received is data packet a1. Then, it first polls CPU1, and the polling count value index of CPU1 is incremented by one from the initial value of 0: index+1=1. This increment is compared with the weighted polling value L1 corresponding to CPU1. If it is less than L1, it means that this round of polling did not hit CPU1, and the next data CPU is polled: CPU2o. If L1=1, that is, if the increment is equal to the weighted polling value L1 corresponding to CPU1, then CPU1 is hit, and data packet a1 is distributed to CPU1o. Here, it is assumed that L1=1, and data packet a1 is distributed to CPU1. Next, assuming the FPGA chip receives the next data packet a2 sent by the source device, and assuming the results read from the first and second registers by the FPGA chip have not changed, then the FPGA chip will begin polling from the next data CPU (CPU2) after CPU1, which last distributed data packet a1. Similarly, the polling count value index of CPU2 is incremented by one: index+1 o The index incremented by one at this point is actually the update result of the last time CPU2 was polled. Since we assume CPU2 is being polled for the first time, index = 0, and the incremented result is 1. This incremented result is compared with the weighted polling value L2 corresponding to CPU2. If it is less than L2, the polling continues to the next data CPU: CPU3. O If L2=1, meaning the result of adding one is equal to the weighted polling value L2 corresponding to CPU2, then CPU2 is hit, and data packet a2 is distributed to CPU2. O The following assumes that the FPGA chip receives data packet bi from the source device, and that the previous data packet was distributed to CPU2. Furthermore, assuming that polling starts from CPU3 according to the sorting result, and the result of incrementing the index corresponding to CPU3 by one is greater than or equal to the weighted polling value L3' corresponding to CPU3, then data packet bi is distributed to CPU3. OAmong them, the weighted polling value L3' is the new weighted polling value corresponding to CPU3 received by the FPGA chip. As mentioned above, the control CPU can periodically determine the load of each data CPU, and thus periodically determine the weighted polling value of each data CPU. For example, at time t1, the control CPU sends the weighted polling values ​​L1, L2...Ln to the FPGA chip's CPU1, CPU2-CPUn. At time t2, one period later, the control CPU sends the weighted polling values ​​L1', L2'...*' to the FPGA chip's CPU1, CPU2-CPUn. In the example above, assuming that when the FPGA chip starts scheduling data packet bi, it reads L1', L2'...*' from the second register, and assuming that L3=5 and L3'=3 for CPU3, and that at this time, the index for CPU3 is 4, which is already greater than L3', then after incrementing index by 1, the updated result is 5, which is greater than L3'. At this point, CPU3 is hit, data packet bi is distributed to CPU3, and then index is cleared, i.e., index=0. This is understandable. After distributing different data packets to different data CPUs, the FPGA chip also ensures that the data packets are sent to the destination device in the correct order based on the functions of order preservation detection and timeout detection. Additionally, it should be noted that in an optional embodiment, the FPGA chip can distribute complete data packets or packet header information to the data CPU. Therefore, the processing performed by the CPU can be either encapsulation processing only on the packet header information or other processing on the entire data packet, such as data verification. The processing required by the data CPU varies depending on the actual application scenario. In the above scheme, by setting the aforementioned FPGA chip in the network card of the gateway device, and through the hardware and software collaboration between the FPGA chip and multiple CPUs in the gateway device, load-balanced distribution of data packets to different data CPUs is achieved based on the data CPU load and WRR mode, so as to fully utilize the capabilities of the data CPUs, achieve high-speed forwarding of data packets, and reduce forwarding latency. Figure 3 is a schematic diagram of another working process of the gateway device provided in this embodiment. As shown in Figure 3, the control CPU, including CPU0, can also determine the load balancing index values ​​corresponding to multiple data CPUs. That is, calculate the load balance index value. If the load balance index value is greater than the set threshold, send a scheduling mode adjustment command containing the second scheduling mode to the FPGA chip.Therefore, when the FPGA chip receives the second data packet sent by the source device, it determines the second data CPU based on the second scheduling mode, distributes the second data packet to the second data CPU for processing, receives the second processed data packet fed back by the second data CPU, and sends the second processed data packet to the corresponding destination device. The FPGA chip can receive and read data packets, and write the second scheduling mode (RR) into the first register. Then, it can distribute data packets: in RR mode, the packets are distributed to CPU1, CPU2, ..., CPUn in the data CPU. The second scheduling mode is a fallback mode of the first scheduling mode. That is, from the perspective of priority, the second scheduling mode has a lower priority than the first scheduling mode. It is a fallback or fallback scheduling mode when the first scheduling mode is unavailable. Optionally, the second scheduling mode includes RR mode or Receiver Scaling (RSS) mode. In simple terms, RSS mode is based on the five-tuple or six-tuple contained in the header information of the data packet. Data packets corresponding to the same 5-tuple or 6-tuple are distributed to the same data CPU for processing. The 5-tuple includes five fields: source IP, source port, destination IP, destination port, and protocol number. The 6-tuple is based on the 5-tuple, with the addition of a Virtual Local Area Network Identifier (VXLAN Network Identifier, or VNI for short). oIn practical applications, the control CPU can launch a thread to periodically calculate the aforementioned load balancing metric. When the calculated load balancing metric value in a certain period exceeds a set threshold, it triggers a scheduling mode adjustment instruction (including a second scheduling mode) to the FPGA chip. This causes the FPGA chip to change the scheduling mode in its first register to the second scheduling mode, meaning that subsequent packet distribution will use the second scheduling mode. The load balancing metric measures the fairness of the data CPUs, i.e., the balance of the load. In practical applications, metrics such as the GI coefficient, Paret efficiency, equal chance method, and Lorenz curve can be used as this load balancing metric. The calculation methods for these metrics can be found in existing related technologies and will not be elaborated here. Taking the GI coefficient as an example, the lower the calculated GI coefficient value (less than a set threshold), the more balanced the usage of the data CPUs. Weighted distribution of packets according to the first scheduling mode can further reduce this value, so the first scheduling mode continues to be used. Conversely, if the calculated Gini coefficient value exceeds a set threshold, a fallback mechanism is triggered: falling back to RR mode or RSS mode. In practical applications, the choice between RR and RSS modes can be determined based on the degree to which the load balancing index value exceeds the set threshold. When the exceedance is minor (e.g., the difference is less than a preset value), RR mode can be used; when the exceedance is severe (e.g., the difference is greater than a preset value), RSS mode can be used. Alternatively, the control CPU can optionally determine the load balancing index values ​​corresponding to multiple data CPUs based on their utilization rates. Of course, other indicators besides utilization can also be used for calculation; there are no specific restrictions. In the above scheme, the FPGA chip uses the WRR (Weighted Redirect) mode to perform weighted distribution of data packets to the data CPU based on the load of the data CPU, and provides load balancing indicators to ensure that the functions of basic scheduling modes such as RR mode are not affected. That is, when the WRR mode cannot effectively balance the load of each data CPU, the scheduling mode can be rolled back to ensure the normal distribution of data packets to the data CPU. Figure 4 is a flowchart of a data packet forwarding method provided by an embodiment of this disclosure. This data packet forwarding method is applied to a programmable chip in a gateway device. The gateway device includes multiple processors and network interface cards (NICs). The programmable chip is located in the NIC, and the multiple processors include a control processor and multiple data processors. As shown in Figure 4, the method may include the following steps:

[0007] 401. Receive a scheduling mode setting instruction containing a first scheduling mode and a weighted polling value of multiple data processors sent by the control processor, wherein the weighted polling value of the multiple data processors is determined by the control processor based on the load of the multiple data processors.

[0008] 402. Receive the first data packet sent by the source device.

[0009] 403. Based on the first scheduling mode and the weighted polling value of multiple data processors, determine the first data processor whose polling count has reached the corresponding weighted polling value, and distribute the first data packet to the first data processor for processing. Optionally, determining the first data processor whose polling count has reached the corresponding weighted polling value based on the first scheduling mode and the weighted polling value of multiple data processors includes: based on the sorting of multiple data processors, polling each data processor starting from the next data processor after the data processor that last distributed the data packet, and performing the following processing: incrementing the first polling count value corresponding to the currently polled target data processor by one to update and obtain the second polling count value; if the second polling count value is greater than or equal to the weighted polling value corresponding to the target data processor, then determining the target data processor as the first data processor, and clearing the polling count value corresponding to the first data processor, wherein the first polling count value is the polling count value updated when the target data processor was last polled.

[0010] 404. Receive the first processed data packet fed back by the first data processor, and send the first processed data packet to the corresponding destination device. Optionally, the method further includes: receiving a scheduling mode adjustment instruction containing a second scheduling mode sent by the control processor, the scheduling mode adjustment instruction being sent by the control processor when it determines that the load balancing index value corresponding to multiple data processors is greater than a set threshold; receiving the second data packet sent by the source device; determining the second data processor based on the second scheduling mode; distributing the second data packet to the second data processor for processing; receiving the second processed data packet fed back by the second data processor; and sending the second processed data packet to the corresponding destination device. The specific processing procedure of the programmable chip can be referred to the relevant description in the foregoing embodiments, and will not be repeated here. Figure 5 is a flowchart of a data packet forwarding method provided by an embodiment of this disclosure. This data packet forwarding method is applied to the control processor among multiple processors in a gateway device. The gateway device includes multiple processors and a network interface card (NIC). The NIC includes a programmable chip. The multiple processors include a control processor and multiple data processors. As shown in Figure 5, the method may include the following steps:

[0011] 501. Send the scheduling mode setting instruction containing the first scheduling mode to the programmable chip.

[0012] 502. Determine the load of multiple data processors, and determine the weighted polling value of multiple data processors based on the load of multiple data processors.

[0013] 503. The weighted round-robin values ​​of multiple data processors are sent to the programmable chip, so that when the programmable chip receives a first data packet sent by the source device, it determines the first data processor whose round-robin count has reached the corresponding weighted round-robin value based on the first scheduling mode and the weighted round-robin values ​​of the multiple data processors, and distributes the first data packet to the first data processor for processing. Optionally, the method further includes: determining the load balancing index value corresponding to the multiple data processors; if the load balancing index value is greater than a set threshold, sending a scheduling mode adjustment instruction containing a second scheduling mode to the programmable chip, so that when the programmable chip receives a second data packet sent by the source device, it determines the second data processor based on the second scheduling mode and distributes the second data packet to the second data processor for processing. Optionally, determining the load balancing index value corresponding to the multiple data processors includes: determining the load balancing index value corresponding to the multiple data processors based on the utilization rate of the multiple data processors. Optionally, determining the weighted polling value of the multiple data processors based on their loads includes: taking the reciprocal of the loads of each data processor, amplifying the lowest reciprocal to one, determining the corresponding amplification factor, and amplifying the other reciprocals by the amplification factor to obtain the weighted polling value of the multiple data processors. The specific processing procedure of the control processor can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here. This disclosure provides a network interface card (NIC), as described above, which includes a programmable chip. The NIC is communicatively connected to multiple processors in a gateway device, including a control processor and multiple data processors. The NIC is located in the gateway device. As described above, the programmable chip is configured to receive a scheduling mode setting instruction containing a first scheduling mode and a weighted polling value of multiple data processors sent by a control processor; receive a first data packet sent by a source device; determine a first data processor whose polling count has reached the corresponding weighted polling value based on the first scheduling mode and the weighted polling value of the multiple data processors; distribute the first data packet to the first data processor for processing; and receive a first processed data packet fed back by the first data processor and send the first processed data packet to the corresponding destination device; wherein the weighted polling value of the multiple data processors is determined by the control processor based on the load of the multiple data processors.In addition, the programmable chip is also used to: receive a scheduling mode adjustment instruction containing a second scheduling mode sent by a control processor; receive a second data packet sent by a source device; determine a second data processor based on the second scheduling mode; distribute the second data packet to the second data processor for processing; receive a second processed data packet fed back by the second data processor; and send the second processed data packet to the corresponding destination device. The scheduling mode adjustment instruction is sent by the control processor when it determines that the load balancing index values ​​corresponding to multiple data processors are greater than a set threshold. The specific processing procedure of the programmable chip can be referred to the relevant descriptions in the foregoing embodiments, and will not be repeated here. The following will describe in detail one or more embodiments of the data packet forwarding apparatus of this disclosure. Those skilled in the art will understand that these apparatuses can all be configured using commercially available hardware components through the steps taught in this solution. Figure 6 is a schematic diagram of a data packet forwarding device provided in an embodiment of this disclosure. This device is applied to a programmable chip in a network interface card (NIC). The NIC is located in a gateway device, which includes multiple processors, including a control processor and multiple data processors. As shown in Figure 6, the device includes: a first receiving module 11, a second receiving module 12, a determining module 13, a first sending module 14, and a second sending module 15. The first receiving module 11 is used to receive a scheduling mode setting instruction containing a first scheduling mode sent by the control processor, and a weighted polling value of the multiple data processors. The weighted polling value of the multiple data processors is determined by the control processor based on the load of the multiple data processors. The second receiving module 12 is used to receive a first data packet sent by a source device. The determining module 13 is used to determine the first data processor whose polling count has reached the corresponding weighted polling value based on the first scheduling mode and the weighted polling value of the multiple data processors. The first sending module 14 is used to distribute the first data packet to the first data processor for processing. The first receiving module 11 is further configured to receive the first processed data packet fed back by the first data processor. The second sending module 15 is configured to send the first processed data packet to the corresponding destination device. The device shown in Figure 6 can execute the steps performed by the programmable chip in the foregoing embodiments. For detailed execution process and technical effects, please refer to the description in the foregoing embodiments, which will not be repeated here.Figure 7 is a schematic diagram of a data packet forwarding device provided in an embodiment of this disclosure. This device is applied to a control processor among multiple processors in a gateway device. The gateway device includes multiple processors and a network interface card (NIC). The NIC includes a programmable chip. The multiple processors include a control processor and multiple data processors. As shown in Figure 7, the device includes: a sending module 21 and a determining module 22. The sending module 21 is used to send a scheduling mode setting instruction containing a first scheduling mode to the programmable chip. The determining module 22 is used to determine the load of the multiple data processors and determine the weighted polling value of the multiple data processors based on the load of the multiple data processors. The sending module 21 is also used to send the weighted polling value of the multiple data processors to the programmable chip, so that when the programmable chip receives a first data packet sent by the source device, based on the first scheduling mode and the weighted polling value of the multiple data processors, it determines the first data processor whose polling count has reached the corresponding weighted polling value, and distributes the first data packet to the first data processor for processing. The device shown in Figure 7 can execute the steps of the control processor in the foregoing embodiments. Detailed execution processes and technical effects are described in the foregoing embodiments and will not be repeated here. Furthermore, this disclosure provides a non-transitory machine-readable storage medium storing executable code. When the executable code is executed by the programmable chip of the gateway device, the programmable chip can at least implement the packet forwarding method provided in the foregoing embodiments. Additionally, this disclosure provides a non-transitory machine-readable storage medium storing executable code. When the executable code is executed by the processor of the gateway device (the control processor mentioned above), the processor can at least implement the packet forwarding method provided in the foregoing embodiments. The device embodiments described above are merely illustrative. The network elements described as separate components may or may not be physically separate. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort. Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of a necessary general-purpose hardware platform, or it can be implemented by a combination of hardware and software.Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a computer product. This disclosure can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of this disclosure, and not to limit them; although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure. Industrial Applicability The gateway device provided by the embodiments of this disclosure includes multiple processors and a network card with a programmable chip inside, thereby leveraging the inherent high-speed parallel processing advantage of the programmable chip to achieve high-speed forwarding of data packets sent by the source device to the destination device. Among them, the multiple processors include a processor that mainly provides control functions—a control processor—and multiple processors for processing data packets—data processors. Based on the composition of this gateway device, efficient packet forwarding can be achieved through hardware and software collaboration. The software refers to the control program running on the processor, providing control functions, while the hardware refers to the hardware language code burned into the programmable chip. Specifically, the control processor sends a scheduling mode setting instruction, including a first scheduling mode (such as a weighted round-robin mode), to the programmable chip. It also determines the load of multiple data processors, determines a weighted round-robin value for each data processor based on its load, and sends this weighted round-robin value to the programmable chip. Thus, upon receiving the first data packet from the source device, the programmable chip, based on the first scheduling mode and the weighted round-robin values ​​of the multiple data processors, determines the first data processor whose polling count has reached the corresponding weighted round-robin value, and distributes the first data packet to the first data processor for processing. Upon receiving the first processed data packet from the first data processor, the programmable chip sends the processed data packet to the corresponding destination device. In the aforementioned gateway device architecture, by controlling the hardware and software collaboration of the processor and programmable chip to load balance the distribution of data packets received by the network card to different data processors, the data packet distribution frequency of high-load data processors can be reduced, the balanced utilization of data processor resources can be achieved, and the degree of data packet forwarding delay caused by high data processor load can be reduced.

Claims

Claims 1. A gateway device, comprising: Multiple processors, including a control processor and multiple data processors; A network interface card (NIC), wherein the NIC includes a programmable chip, and the NIC is communicatively connected to the plurality of processors respectively; The control processor is configured to: send a scheduling mode setting instruction including a first scheduling mode to the programmable chip; and determine the load of the plurality of data processors, determine a weighted polling value of the plurality of data processors based on the load of the plurality of data processors, and send the weighted polling value of the plurality of data processors to the programmable chip; the programmable chip is configured to: receive a first data packet sent by a source device; determine a first data processor whose polling count has reached the corresponding weighted polling value based on the first scheduling mode and the weighted polling value of the plurality of data processors; distribute the first data packet to the first data processor for processing; receive a first processed data packet fed back by the first data processor; and send the first processed data packet to the corresponding destination device.

2. The gateway device according to claim 1, wherein, The programmable chip is specifically used for: based on the sorting of the plurality of data processors, polling each data processor starting from the next data processor after the data processor that last distributed the data packet, and performing the following processing: incrementing the first polling count value corresponding to the currently polled target data processor by one to update and obtain the second polling count value; if the second polling count value is greater than or equal to the weighted polling value corresponding to the target data processor, then determining the target data processor as the first data processor, wherein the first polling count value is the polling count value updated when the target data processor was last polled; and clearing the polling count value corresponding to the first data processor.

3. The gateway device according to claim 2, wherein, The programmable chip is further configured to: if the second polling count is less than the weighted polling value corresponding to the target data processor, then poll the next data processor of the target data processor.

4. The gateway device according to claim 1, wherein, The control processor is further configured to: determine the load balancing index value corresponding to the plurality of data processors; if the load balancing index value is greater than a set threshold, send a scheduling mode adjustment instruction containing a second scheduling mode to the programmable chip; the programmable chip is further configured to: receive a second data packet sent by the source device; determine a second data processor based on the second scheduling mode; distribute the second data packet to the second data processor for processing; receive a second processed data packet fed back by the second data processor; and send the second processed data packet to the corresponding destination device.

5. The gateway device according to claim 4, wherein, The second scheduling mode includes either polling scheduling mode or receiver scaling mode.

6. The gateway device according to claim 4, wherein, The control processor is specifically used to: determine the load balancing index value corresponding to the plurality of data processors based on the utilization rate of the plurality of data processors.

7. The gateway device according to any one of claims 1-6, wherein, The control processor is specifically used to: acquire at least one load metric corresponding to each of the plurality of data processors, and determine the load of the plurality of data processors based on the at least one load metric corresponding to each of the plurality of data processors.

8. The gateway device according to any one of claims 1-6, wherein, The control processor is specifically used to: take the reciprocal of the load of the plurality of data processors, amplify the lowest reciprocal to one, determine the corresponding amplification factor, and amplify the other reciprocals by the amplification factor to obtain the weighted polling value of the plurality of data processors.

9. The gateway device according to any one of claims 1-6, wherein, The programmable chip is further configured to: sequentially receive the first data packet and the third data packet sent by the source device; distribute the first data packet to the first data processor and the third data packet to the third data processor; and if the third processed data packet fed back by the third data processor is received first, then wait for the first processed data packet to arrive, and sequentially send the first processed data packet and the third processed data packet to the destination device.

10. The gateway device according to claim 9, wherein, The programmable chip is further configured to: if the first processed data packet is not received after a set waiting period, then send the third processed data packet to the destination device.

1. A network interface card (NIC), comprising a programmable chip, the NIC being communicatively connected to multiple processors in a gateway device, the multiple processors including a control processor and multiple data processors, the NIC being located in the gateway device; the programmable chip being configured to receive a scheduling mode setting instruction including a first scheduling mode sent by the control processor and weighted polling values ​​of the multiple data processors; receive a first data packet sent by a source device; determine a first data processor whose polling count has reached a corresponding weighted polling value based on the first scheduling mode and the weighted polling values ​​of the multiple data processors; distribute the first data packet to the first data processor for processing; and receive a first processed data packet fed back by the first data processor; and send the first processed data packet to a corresponding destination device; wherein... The weighted polling value of the plurality of data processors is determined by the control processor based on the load of the plurality of data processors.

12. The network interface card according to claim 11, wherein, The programmable chip is further configured to: receive a scheduling mode adjustment instruction containing a second scheduling mode sent by the control processor; receive a second data packet sent by the source device; determine a second data processor based on the second scheduling mode; distribute the second data packet to the second data processor for processing; receive a second processed data packet fed back by the second data processor; and send the second processed data packet to the corresponding destination device. The scheduling mode adjustment instruction is sent by the control processor when it determines that the load balancing index value corresponding to the plurality of data processors is greater than a set threshold.

13. A packet forwarding method, applied to a programmable chip in a network interface card (NIC), the NIC being located in a gateway device, the gateway device including multiple processors, the multiple processors including a control processor and multiple data processors, the method comprising: The system receives a scheduling mode setting instruction containing a first scheduling mode from the control processor, as well as a weighted polling value of the plurality of data processors, wherein the weighted polling value of the plurality of data processors is determined by the control processor based on the load of the plurality of data processors.

18. Receive a first data packet sent by the source device; Based on the first scheduling mode and the weighted polling value of the plurality of data processors, determine the first data processor whose polling count has reached the corresponding weighted polling value; Distribute the first data packet to the first data processor for processing; Receive a first processed data packet fed back by the first data processor; Send the first processed data packet to the corresponding destination device.

14. The method according to claim 13, wherein, The step of determining the first data processor whose polling count has reached the corresponding weighted polling value based on the first scheduling mode and the weighted polling value of the plurality of data processors includes: based on the sorting of the plurality of data processors, polling each data processor starting from the next data processor after the data processor that last distributed the data packet, and performing the following processing: incrementing the first polling count value corresponding to the currently polled target data processor by one to update it to obtain a second polling count value; if the second polling count value is greater than or equal to the weighted polling value corresponding to the target data processor, then determining the target data processor as the first data processor, wherein the first polling count value is the polling count value updated when the target data processor was last polled; and clearing the polling count value corresponding to the first data processor.

15. The method according to claim 13, wherein, The method further includes: receiving a scheduling mode adjustment instruction containing a second scheduling mode sent by the control processor, wherein the scheduling mode adjustment instruction is sent by the control processor when it determines that the load balancing index value corresponding to the plurality of data processors is greater than a set threshold; receiving a second data packet sent by the source device; determining a second data processor based on the second scheduling mode; distributing the second data packet to the second data processor for processing; receiving a second processed data packet fed back by the second data processor; and sending the second processed data packet to the corresponding destination device.

16. A packet forwarding method, applied to a control processor among multiple processors in a gateway device, the gateway device including the multiple processors and a network interface card (NIC), the NIC including a programmable chip, the multiple processors including the control processor and multiple data processors, the method comprising: Send a scheduling mode setting instruction, including the first scheduling mode, to the programmable chip; Determine the load of the plurality of data processors, and determine the weighted polling value of the plurality of data processors based on the load of the plurality of data processors; The weighted polling values ​​of the plurality of data processors are sent to the programmable chip, so that when the programmable chip receives the first data packet sent by the source device, it determines the first data processor whose polling count has reached the corresponding weighted polling value based on the first scheduling mode and the weighted polling values ​​of the plurality of data processors, and distributes the first data packet to the first data processor for processing.

17. The method according to claim 16, wherein, The method further includes: determining the load balancing index values ​​corresponding to the plurality of data processors; 19 If the load balancing index value is greater than the set threshold, a scheduling mode adjustment instruction containing a second scheduling mode is sent to the programmable chip, so that when the programmable chip receives the second data packet sent by the source device, it determines the second data processor based on the second scheduling mode and distributes the second data packet to the second data processor for processing.

18. The method according to claim 17, wherein, Determining the load balancing index value corresponding to the plurality of data processors includes: determining the load balancing index value corresponding to the plurality of data processors based on the utilization rate of the plurality of data processors.

19. The method according to any one of claims 16-18, wherein, The step of determining the weighted polling value of the plurality of data processors based on their loads includes: taking the reciprocal of the loads of the plurality of data processors; amplifying the lowest reciprocal to one and determining the corresponding amplification factor; and amplifying the other reciprocals by the amplification factor to obtain the weighted polling value of the plurality of data processors.

20. A non-transitory machine-readable storage medium storing executable code, wherein when the executable code is executed by a programmable chip in a gateway device, the programmable chip performs the packet forwarding method as described in any one of claims 13-15.

21. A non-transitory machine-readable storage medium storing executable code, wherein when the executable code is executed by a processor of a gateway device, the processor performs the packet forwarding method as described in any one of claims 16-19.

22. A computer program product, comprising: A computer program, when executed by a programmable chip in a gateway device, causes the programmable chip processor to perform the packet forwarding method as described in any one of claims 13-15.

23. A computer program product, comprising: A computer program, when executed by the processor of a gateway device, causes the processor to perform the packet forwarding method as described in any one of claims 16-19.

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