Display substrate and manufacturing method therefor, and display panel

Abstract

Embodiments of the present disclosure relate to the technical field of display, and provide a display substrate and a manufacturing method therefor, and a display panel, used for improving the efficiency of a display panel. A light-emitting device comprises a substrate, an insulating film group, a reflective layer, a pixel defining layer, and a plurality of first trenches; the insulating film group comprises a first passivation layer and a plurality of planarization layers that are stacked; the surface of the insulating film group away from the substrate comprises a plurality of first grooves arranged in a first direction; the reflective layer covers the sidewalls and bottom walls of the first grooves; the pixel defining layer is located on the side of the reflective layer away from the insulating film group and comprises a plurality of pixel openings; each first groove among the plurality of first grooves surrounds a corresponding pixel opening; each first trench penetrates from the pixel defining layer to a first planarization layer; the first passivation layer comprises a first pattern, the part of the first pattern extending out from the sidewall of each first trench is close to the surface of the substrate, and a gap is formed between said part and the bottom of the first trench. The display substrate is used for a display apparatus.

Description

Display substrate, preparation method thereof and display panel

[0001] This application claims priority to Chinese Patent Application No. 202410876627.7, filed on July 1, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular to a display substrate, a preparation method thereof and a display panel. BACKGROUND

[0003] OLED (Organic Light Emitting Diode) display panels are widely used in display screens such as mobile phones, tablets and vehicle displays due to their advantages of full solid state, fast response speed and wide operating temperature range. SUMMARY

[0004] In one aspect, a display substrate is provided. The display substrate includes a substrate, an insulating film group, a reflective layer, a pixel definition layer and a plurality of first trenches. The insulating film group is located on one side of the substrate and includes a first passivation layer and a plurality of flat layers stacked. The plurality of flat layers includes a first flat layer. The first passivation layer is located on a side of the first flat layer away from the substrate and in contact with the first flat layer. A surface of the insulating film group away from the substrate includes a plurality of first grooves arranged along a first direction. The first direction intersects a stacking direction of the plurality of flat layers. The reflective layer is located on a side of the insulating film group away from the substrate and covers sidewalls and a bottom wall of the first grooves. The pixel definition layer is located on a side of the reflective layer away from the insulating film group and includes a plurality of pixel openings. Each of the plurality of first grooves surrounds one of the pixel openings. The first trench is formed through the pixel definition layer to the first flat layer and is located between two adjacent first grooves of the plurality of first grooves. The first passivation layer includes a first pattern, the first pattern includes a portion extending from a sidewall of the first trench, and a surface of the portion of the first pattern extending from the sidewall of the first trench, which is close to the surface of the substrate, has a gap with a bottom of the first trench.

[0005] In some embodiments, the first flat layer includes a second pattern. The sidewall of the first groove includes a surface of the first pattern, or the sidewall of the first groove includes a surface of the first pattern and a surface of the second pattern.

[0006] In some embodiments, the first passivation layer includes a plurality of first openings arranged along the first direction, and the first openings constitute at least part of the first grooves.

[0007] In some embodiments, in the case where the first openings constitute the first grooves, a dimension of the first passivation layer along a second direction ranges from 0.5 μm to 1.5 μm, and the second direction is the stacking direction of the plurality of flat layers.

[0008] In some embodiments, when the first openings constitute a part of the first recesses, the first planar layer comprises a plurality of first sub-recesses connected with the plurality of first openings, the first sub-recesses constituting the rest of the first recesses except the first openings. Alternatively, the first planar layer comprises a plurality of second openings connected with the plurality of first openings, the second openings constituting the rest of the first recesses except the first openings. The bottom surface of the first trenches is closer to the substrate than the bottom surface of the first recesses.

[0009] In some embodiments, when the first planar layer comprises the plurality of first sub-recesses, the first planar layer has a dimension in the second direction ranging from 1.5 μm to 3.0 μm, the second direction being the stacking direction of the plurality of planar layers.

[0010] In some embodiments, the first planar layer further comprises a plurality of third openings arranged in the first direction, and the first pattern and the reflective layer are sequentially arranged on the sidewalls and the bottom wall of the third openings.

[0011] In some embodiments, the pixel definition layer further comprises a first portion located on the side of the first passivation layer close to the substrate, the surface of the first portion close to the substrate is flush with the bottom surface of the first trenches, and the edge portion of the first portion overlaps with the edge portion of the first passivation layer.

[0012] In some embodiments, the insulating film group further comprises a second planar layer located on the side of the first planar layer away from the first passivation layer, and the display substrate further comprises a first source-drain metal layer located on the side of the second planar layer away from the first planar layer.

[0013] In some embodiments, the display substrate further comprises a third planar layer. The third planar layer is arranged on the side of the first passivation layer away from the first planar layer, and comprises a plurality of fourth openings arranged in the first direction, and the plurality of fourth openings are multiplexed as the plurality of first recesses.

[0014] In some embodiments, the insulating film group further comprises a second planar layer, and the display substrate further comprises a first source-drain metal layer. The second planar layer and the first source-drain metal layer are located between the first planar layer and the third planar layer, and the second planar layer is farther away from the substrate than the first source-drain metal layer. The surface of the first source-drain metal layer close to the substrate is closer to the substrate than the surface of the first passivation layer close to the substrate. The second planar layer further comprises a second portion located on the side of the first passivation layer close to the substrate, and the edge portion of the second portion overlaps with the edge portion of the first passivation layer.

[0015] In some embodiments, the display substrate further comprises a first source-drain metal layer. The first source-drain metal layer is located on the side of the first planar layer close to the substrate, and the surface of the first source-drain metal layer away from the substrate is closer to the substrate than the surface of the first trench close to the substrate.

[0016] In some embodiments, the first passivation layer has no overlap with the projection of the reflective layer on the substrate; the surface of the portion of the reflective layer covering the bottom wall of the first groove, which is close to the substrate, is closer to the substrate than the surface of the first passivation layer, which is close to the substrate.

[0017] In some embodiments, the reflective layer is in contact with the first passivation layer. The third planar layer further comprises a third portion located on the side of the first passivation layer close to the substrate; the edge portion of the third portion overlaps with the edge portion of the first passivation layer.

[0018] In some embodiments, the pixel definition layer comprises a fourth portion located on the side of the first passivation layer close to the substrate, and the side surface of the fourth portion constitutes part of the sidewall of the first trench.

[0019] In some embodiments, the portion of the first pattern protruding from the sidewall of the first trench is away from the surface of the substrate and has a first distance from the bottom surface of the first trench along the second direction. The surface of the insulating film group away from the surface of the substrate has a second distance from the bottom surface of the first groove along the second direction. The first distance is less than or equal to the second distance; the second direction is the stacking direction of the multilayer planar layer.

[0020] In another aspect, a preparation method of a display substrate is provided. The preparation method comprises: forming a substrate. Forming an insulating film group on one side of the substrate; the insulating film group comprises a first passivation layer and a multilayer planar layer stacked; the multilayer planar layer comprises a first planar layer; the first passivation layer is located on the side of the first planar layer away from the substrate and is in contact with the first planar layer. The surface of the insulating film group away from the substrate comprises a plurality of first grooves arranged along a first direction; the first direction intersects with the stacking direction of the multilayer planar layer. Forming a reflective layer on the side of the insulating film group away from the substrate, the reflective layer covering the sidewall and the bottom wall of the first groove. Forming a pixel definition layer on the side of the reflective layer away from the substrate; the pixel definition layer comprises a plurality of pixel openings; each of the plurality of first grooves surrounds one pixel opening. Forming a plurality of first trenches, the first trench penetrating through the pixel definition layer to the first planar layer; the first trench is located between two adjacent first grooves in the plurality of first grooves. The first passivation layer comprises a first pattern, the first pattern comprising a portion protruding from the sidewall of the first trench, and the portion of the first pattern protruding from the sidewall of the first trench has a gap between the surface close to the substrate and the bottom of the first trench.

[0021] In some embodiments, forming the insulating film group comprises forming an initial planar layer, and forming an initial passivation layer on a side of the initial planar layer distal to the substrate. Forming the plurality of first trenches comprises patterning the initial passivation layer using an etching process. In the process of patterning the initial passivation layer, the etching parameters are controlled such that a portion of the initial planar layer proximal to the initial passivation layer is removed to form a portion of the first trench on a side of the initial passivation layer proximal to the substrate, and form a portion of the first pattern extending from a sidewall of the first trench with a gap from a bottom of the first trench.

[0022] In another aspect, a display panel is provided. The display panel comprises a plurality of light emitting devices and a display substrate as described in any of the above embodiments. The light emitting device is located in a pixel opening.

[0023] In some embodiments, the light emitting device comprises at least two light emitting layers and a charge generation unit located between the two adjacent light emitting layers. In the light emitting device, the charge generation units of the plurality of light emitting devices are of the same layer and material, and constitute a common unit. The common unit comprises a fifth portion and a sixth portion. The fifth portion is located on a side of the portion of the first pattern extending from the sidewall of the first trench along a second direction. The sixth portion is located in the first trench and on a side of the portion of the first pattern along the second direction. The second direction is the stacking direction of the plurality of planar layers. In the second direction, there is a gap between the fifth portion and the sixth portion. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0025] FIG. 1A is a structural diagram of a display panel according to some embodiments;

[0026] FIG. 1B is a partial enlarged view of M in FIG. 1A;

[0027] FIG. 1C is a focused ion beam-transmission electron microscope diagram of a display panel according to some embodiments;

[0028] FIG. 2 is a structural diagram of a display panel according to further embodiments;

[0029] FIG. 3 is a structural diagram of a display substrate according to some embodiments;

[0030] FIG. 4 is a structural diagram of a display substrate according to further embodiments;

[0031] FIG. 5 is a structural diagram of a display substrate according to still other embodiments;

[0032] FIG. 6 is a structural diagram of a display substrate according to still other embodiments;

[0033] FIG. 7 is a structural diagram of a display substrate according to still other embodiments;

[0034] FIG. 8 is a structural diagram of a display substrate according to still other embodiments;

[0035] FIG. 9 is a structural diagram of a display substrate according to still other embodiments;

[0036] FIG. 10 is a flowchart of a manufacturing process of a display substrate according to some embodiments;

[0037] FIG. 11A is a step diagram of a manufacturing method of a display substrate according to some embodiments;

[0038] FIG. 11B is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0039] FIG. 11C is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0040] FIG. 11D is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0041] FIG. 11E is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0042] FIG. 11F is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0043] FIG. 11G is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0044] FIG. 11H is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0045] FIG. 12A is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0046] FIG. 12B is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0047] FIG. 12C is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0048] FIG. 12D is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0049] FIG. 13A is a step diagram of a manufacturing method of a display substrate according to still other embodiments;

[0050] FIG. 13B is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0051] FIG. 13C is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0052] FIG. 13D is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0053] FIG. 13E is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0054] FIG. 13F is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0055] FIG. 13G is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0056] FIG. 14A is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0057] FIG. 14B is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0058] FIG. 14C is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0059] FIG. 14D is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0060] FIG. 14E is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0061] FIG. 14F is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0062] FIG. 15A is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0063] FIG. 15B is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0064] FIG. 15C is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0065] FIG. 15D is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0066] FIG. 15E is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0067] FIG. 15F is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0068] FIG. 15G is a step diagram of a method of manufacturing a display substrate according to still other embodiments;

[0069] FIG. 16A is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0070] FIG. 16B is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0071] FIG. 16C is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0072] FIG. 16D is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0073] FIG. 16E is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0074] FIG. 17A is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0075] FIG. 17B is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0076] FIG. 17C is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0077] FIG. 17D is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0078] FIG. 17E is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0079] FIG. 17F is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0080] FIG. 17G is a step diagram of a method of manufacturing a display substrate according to yet some embodiments;

[0081] FIG. 18 is a structural diagram of a display panel according to yet some embodiments. DETAILED DESCRIPTION

[0082] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0083] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed both to cover the containing feature or features and additional feature or features not described. In describing some embodiments, the use of "connect" or "connected" can be used. The term "connect" shall be construed broadly, for example, "connect" can be fixed connections, detachable connections, or integral; can be directly connected, or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited by the content herein.

[0084] Hereinafter, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0085] In describing some embodiments, the use of "connect" or "connected" can be used. The term "connect" shall be construed broadly, for example, "connect" can be fixed connections, detachable connections, or integral; can be directly connected, or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited by the content herein.

[0086] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0087] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0088] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

[0089] Additionally, the use of "based on" means open and inclusive, as "based on" one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0090] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0091] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0092] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present.

[0093] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples of exemplary embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0094] It should be noted that, for example, 11-1 appearing in the drawings of the present disclosure indicates that the component 11 belongs to the component 1, for example, 111-110 appearing in FIG. 4 indicates that the substrate 111 belongs to the base 110, and other similar notations appearing in the drawings follow the above description. For example, 1 / 2 appearing in the drawings of the present disclosure indicates that both the structure 1 and the structure 2 can refer to the structure, for example, 121a / 121 appearing in FIG. 3 indicates that both the first pattern 121a and the first passivation layer 121 can refer to the structure. Other similar notations appearing in the drawings follow the above description.

[0095] As shown in FIG. 1A, some embodiments of the present disclosure provide a display panel 200, which includes a plurality of light emitting devices 210 and a display substrate 100.

[0096] The display panel 200 described above can be, for example, an OLED (Organic Light Emitting Diode) display panel 200.

[0097] The display panel 200 described above can be any display panel that displays both motion (e.g., video) and still (e.g., still images) and both text and graphics. More specifically, it is contemplated that the display panel 200 of the described embodiments can be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projections, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry) and the like.

[0098] In some examples, as shown in FIG. 1A, the display panel 200 further includes an encapsulation layer 220 located on a side of the plurality of light emitting devices 210 away from the display substrate 100.

[0099] In some examples, the encapsulation layer 220 includes a first sub-layer 221, a second sub-layer 222, and a third sub-layer 223 arranged in sequence in a direction away from the plurality of light emitting devices 210. The materials of the first sub-layer 221 and the third sub-layer 223 are, for example, inorganic materials; and the material of the second sub-layer 222 is, for example, an organic material.

[0100] By such an arrangement, the encapsulation layer 220 can cover the light emitting device 210, encapsulating the light emitting device 210 to avoid water vapor and oxygen in the external environment from entering the light emitting device 210, damaging the organic material in the light emitting device 210 and causing the service life of the display panel 200 to be shortened.

[0101] Exemplarily, the plurality of light emitting devices 210 can be arranged along a first direction X, which intersects the thickness direction of the display substrate 100. For example, the first direction X is arranged perpendicularly to the thickness direction of the display substrate 100.

[0102] In some examples, as shown in FIG. 2, the plurality of light emitting devices 210 includes a first light emitting device 210A for emitting first color light, a second light emitting device 210B for emitting second color light, and a third light emitting device 210C for emitting third color light. In this way, the brightness (gray scale) of the first light emitting device 210A, the second light emitting device 210B, and the third light emitting device 210C can be adjusted respectively, and a full-color display of the display panel 200 can be achieved through color combination and superposition. Exemplarily, the first color light is blue light; the second color light is green light; and the third color light is red light.

[0103] In some examples, the plurality of light emitting devices 210 further includes a fourth light emitting device (not shown in the figure) for emitting white light.

[0104] It should be noted that FIG. 2 is a simplified schematic diagram obtained after removing other film layers in the display panel 200 except the film layers related to the light emitting device 210.

[0105] In some embodiments, as shown in FIG. 1A and FIG. 2, the light emitting device 210 includes an anode 211 and a cathode 212 arranged opposite to each other along the thickness direction of the display substrate 100, and a plurality of light emitting functional layers arranged between the anode 211 and the cathode 212, the plurality of light emitting functional layers being arranged along the thickness direction of the display substrate 100. The plurality of light emitting functional layers includes at least one light emitting layer 213.

[0106] In some examples, as shown in FIG. 1A, the anode 211 can be located on the side of the plurality of light emitting functional layers close to the display substrate 100, and the cathode 212 can be located on the side of the plurality of light emitting functional layers away from the display substrate 100. In other examples, the anode 211 can be located on the side of the plurality of light emitting functional layers away from the display substrate 100, and the cathode 212 can be located on the side of the plurality of light emitting functional layers close to the display substrate 100.

[0107] In some examples, the light-emitting device 210 includes one light-emitting layer 213. In this case, the light-emitting device 210 is a single-layer light-emitting device (e.g., a single OLED light-emitting device). In other examples, as shown in FIGS. 1A and 2, the light-emitting device 210 includes a plurality of (e.g., two) light-emitting layers 213 arranged along the thickness direction of the display substrate 100. In this case, the light-emitting device 210 is a tandem light-emitting device (e.g., a tandem OLED light-emitting device). The tandem light-emitting device has the advantages of longer lifetime, lower power consumption, and higher efficiency.

[0108] In some embodiments, as shown in FIGS. 1A and 2, when the light-emitting device 210 includes a plurality of light-emitting layers 213, the plurality of light-emitting functional layers further include a charge generation unit 214 located between two adjacent light-emitting layers 213.

[0109] In some examples, as shown in FIG. 2, the charge generation unit 214 includes an electron generation layer 2141 (also referred to as an N-CGL) and a hole generation layer 2142 (also referred to as a P-CGL) arranged in a stack. The electron generation layer 2141 is closer to the anode 211 than the hole generation layer 2142.

[0110] In some embodiments, as shown in FIGS. 1A and 2, to improve the light-emitting efficiency of the light-emitting device 210, the plurality of light-emitting functional layers further include a hole transport functional layer 215 located on the side of the light-emitting layer 213 closer to the anode 211, and / or an electron transport functional layer 216 located on the side of the light-emitting layer 213 closer to the cathode 212. The hole transport functional layer 215 includes, for example, at least one of a hole injection layer 2151 (HIL), a hole transport layer 2152 (HTL), and an electron blocking layer 2153 (EBL) arranged in a stack. The electron transport functional layer 216 includes, for example, at least one of an electron injection layer 2161 (EIL), an electron transport layer 2162 (ETL), and a hole blocking layer 2163 (EBL) arranged in a stack.

[0111] In some embodiments, as shown in FIG. 1A, the cathode 212 of the plurality of light emitting devices 210 can be an integral layer structure, i.e., the cathode 212 can be a common electrode shared by the plurality of light emitting devices 210. The electron generation layer 2141 of the plurality of light emitting devices 210 can also be an integral layer structure, i.e., the electron generation layer 2141 can be a common film layer shared by the plurality of light emitting devices 210. The hole injection layer 2151, the hole transport layer 2152, the electron blocking layer 2153, the electron injection layer 2161, the electron transport layer 2162, the hole blocking layer 2163, and the hole generation layer 2142 can also be common film layers shared by the plurality of light emitting devices 210, which will not be described here.

[0112] As described in the background, in the field of organic semiconductors, OLED light emitting devices have the advantages of self-emission, large viewing angle, large contrast, fast response speed, wide operating temperature range, and can be prepared into flexible products. Moreover, compared with liquid crystal displays (LCD), OLED display panels containing OLED light emitting devices also have the advantages of not requiring a backlight source, a thin panel thickness, and a light weight.

[0113] With the increasing demand for long-life, low-power products such as AUTO (vehicle-mounted modules), notebooks (NB) & foldable panels, single OLED display panels cannot meet the demand. Therefore, in order to meet the demand for long-life, low-power products, it is necessary to apply Tandem OLED display panels in the above products.

[0114] In some implementations, the electron generation layer and the hole generation layer in the Tandem OLED light emitting device are common film layers. Due to the high doping concentration, lateral leakage is easy to occur, which causes color crosstalk phenomenon when a single sub-pixel is lit, i.e., the adjacent sub-pixels are also lit, resulting in poor color purity of the light emitted by the Tandem OLED light emitting device, poor display effect, and limitation of the application of the Tandem OLED light emitting device.

[0115] In yet some implementations, the light emitted by the light emitting device includes a portion emitted from the front surface of the light emitting device and a portion emitted from the side surface of the light emitting device. The light emitted from the front surface of the light emitting device is emitted from the sub-pixel region to form effective emitted light, while the portion emitted from the side surface of the light emitting device can not emit light from the sub-pixel region, resulting in low light emission efficiency of the display panel.

[0116] Based on this, some embodiments of the present disclosure propose a display substrate 100 to solve one or more of the above problems. As shown in FIGS. 3-9, the display substrate 100 includes a base 110, an insulating film group 120, a reflective layer 130, a pixel defining layer 140, and a plurality of first grooves 150.

[0117] The insulating film group 120 is located on one side of the base 110 and includes a first passivation layer 121 and a plurality of planar layers 122 stacked together; the plurality of planar layers 122 includes a first planar layer 122A; the first passivation layer 121 is located on a side of the first planar layer 122A away from the base 110 and is in contact with the first planar layer 122A; a surface of the insulating film group 120 away from the base 110 includes a plurality of first grooves 160 arranged along a first direction X; the first direction X intersects with a stacking direction of the plurality of planar layers 122.

[0118] The reflective layer 130 is located on a side of the insulating film group 120 away from the base 110 and covers the side walls and bottom walls of the first grooves 160. The pixel defining layer 140 is located on a side of the reflective layer 130 away from the insulating film group 120 and includes a plurality of pixel openings Q1; each of the plurality of first grooves 160 surrounds one of the pixel openings Q1.

[0119] The first groove 150 is penetrated by the pixel defining layer 140 to the first planar layer 122A and is located between two adjacent first grooves 160 among the plurality of first grooves 160. The first passivation layer 121 includes a first pattern 121a, the first pattern 121a includes a portion G extending from the side wall of the first groove 150, and the portion G of the first pattern 121a extending from the side wall of the first groove 150 is close to the surface of the base 110 and has a gap E between the bottom of the first groove 150.

[0120] In some examples, as shown in FIGS. 3-9, the base 110 includes a substrate 111.

[0121] Exemplarily, the substrate 111 can be a rigid substrate. For example, the rigid substrate can be a glass substrate or a Polymethyl Methacrylate (PMMA) substrate, etc.

[0122] Exemplarily, the substrate 111 can be a flexible substrate. For example, the flexible substrate can be a Polyethylene Terephthalate (PET) substrate, a Polyethylene Naphthalate Two Formic Acid Glycol Ester (PEN) substrate, or a Polyimide (PI) substrate, etc.

[0123] Exemplarily, the substrate 111 can be a single-layer structure, or can also be a stacked structure. As shown in FIGS. 3-9, when the substrate 111 is a stacked structure, the substrate 111 includes, for example, a first polyimide layer PI1, a first barrier layer Barrier1, a second polyimide layer PI2, and a second barrier layer Barrier2, which are sequentially stacked in a direction close to the insulating film group 120. Of course, the substrate 111 can also be other forms of stacked structures.

[0124] In some examples, as shown in FIGS. 3-9, the base 110 further includes a plurality of backplane film layers disposed between the substrate 111 and the insulating film group 120. The plurality of backplane film layers include any combination of one or more of a buffer layer Buffer, a shielding layer LS, an active layer AL, a gate metal layer Gate, a gate insulating layer GI, a source-drain metal layer SD, a passivation layer PVX, and an interlayer dielectric layer ILD. Among these backplane film layers, some are continuous whole-layer film layers, some are patterned film layers, some are located in the display area, some extend from the display area to the peripheral area, some include a portion located in the display area and a portion located in the peripheral area, and the two portions are separated.

[0125] Among them, the gate metal layer Gate, the source-drain metal layer SD, and the shielding layer LS are conductive film layers, and the materials of these conductive film layers are, for example, aluminum (Al), silver (Ag), copper (Cu), or chromium (Cr), etc. The gate insulating layer GI, the interlayer dielectric layer ILD, and the passivation layer PVX are insulating film layers, and the materials of these insulating film layers are, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0126] For example, as shown in FIGS. 3-9, the plurality of backplane film layers include, sequentially stacked in a direction away from the substrate 111, a shielding layer LS, a first buffer layer Buffer1 (for example, Buffer-S), a second buffer layer Buffer2 (for example, Buffer-L), a first active layer AL1, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, a third buffer layer Buffer3 (for example, Buffer-O), a second active layer AL2, a third gate insulating layer GI3 (for example, GI3-O), a third gate metal layer Gate3, an interlayer dielectric layer ILD (for example, O-ILD-O), a second source-drain metal layer SD1, and a second passivation layer PVX. In some examples, as shown in FIGS. 3-8, the plurality of backplane film layers further include a fourth planarization layer PLN disposed on a side of the second passivation layer PVX away from the substrate 111.

[0127] The material of the first active layer AL1 is, for example, polysilicon (Poly). The material of the second active layer AL2 is, for example, low temperature polysilicon (LTPS). The second source-drain metal layer SD1 is a patterned film layer, and includes a pattern coupled with the shielding layer LS, a pattern coupled with the first active layer AL1, and a pattern coupled with the second active layer AL2.

[0128] It should be understood that these backplane film layers can constitute part of the film layer structure of the pixel driving circuit, and thus the display substrate 100 can include a plurality of pixel driving circuits for driving a plurality of light emitting devices 210 to emit light.

[0129] In some embodiments, the light emitting device 210 is located in one pixel opening Q1. Thus, the pixel defining layer 140 can be used to position the location of each light emitting device 210, facilitating the subsequent preparation of various light emitting functional layers in the light emitting device 210.

[0130] In some examples, the display substrate 100 further includes a spacer layer located on the side of the pixel defining layer 140 away from the reflective layer 130; the spacer layer includes a plurality of spacers PS arranged at intervals. The spacers PS can be used to support the FMM (Fine Metal Mask) when evaporating the light emitting material.

[0131] Here, the insulating film group 120 includes a first passivation layer 121 and a plurality of planar layers 122 arranged in layers. For example, similar to the aforementioned gate insulating layer GI, interlayer dielectric layer ILD, and passivation layer PVX, the first passivation layer 121 and the plurality of planar layers 122 can be insulating film layers, and the material of the first passivation layer 121 and the plurality of planar layers 122 is, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0132] The surface of the aforementioned insulating film group 120 away from the substrate 110 (hereinafter referred to as the first surface) includes a plurality of first recesses 160 arranged along the first direction X; it can be understood that the first surface is formed with a plurality of first recesses 160 with openings facing away from the substrate 110, so that the sidewalls and bottom walls of the plurality of first recesses 160 can constitute part of the first surface.

[0133] It is to be noted that the first surface is patterned to form the plurality of first recesses 160 is not limited herein. For example, as shown in FIGS. 5-9, the plurality of first recesses 160 can be formed by patterning one or more layers of the insulating film group 120 away from the substrate 110. For another example, as shown in FIGS. 3 and 4, the plurality of recessed structures can be formed in the region where the plurality of first recesses 160 are to be formed by patterning one or more layers of the insulating film group 120 at a middle position, and the insulating film group 120 at a side away from the substrate 110 of the plurality of recessed structures is continued with the topography of the plurality of recessed structures to form the plurality of first recesses 160.

[0134] Here, the reflection layer 130 covers the sidewalls and the bottom wall of the first recess 160 means that the reflection layer 130 includes a portion covering the sidewalls and the bottom wall of the first recess 160. Of course, in addition to the portion covering the sidewalls and the bottom wall of the first recess 160, the reflection layer 130 can also include a portion covering other parts of the first surface except the first recess 160, as shown in FIGS. 3-9.

[0135] In some examples, as shown in FIGS. 3-9, the portion of the reflection layer 130 covering the bottom wall of the first recess 160 is reused as the anode 211. By such arrangement, on the one hand, the reflection layer 130 and the anode 211 can be formed simultaneously, which can simplify the manufacturing process of the display panel 200. On the other hand, the anode 211 can have certain reflection performance, so that the anode 211 can be used to reflect the part of the light emitted by the light-emitting layer 131 towards the anode 211, thereby improving the light extraction efficiency of the light-emitting device 210.

[0136] For example, the material of the reflection layer 130 includes a magnesium-silver alloy, and the mass ratio of magnesium to silver in the magnesium-silver alloy can be in the range of 1:9-2:8.

[0137] In some examples, as shown in FIGS. 3-9, the material of the pixel defining layer 140 covers the portion of the reflection layer 130 away from the sidewalls of the first recess 160, and at this time, the material of the pixel defining layer 140 is in contact with the portion of the reflection layer 130 covering the sidewalls of the first recess 160. In this case, the sidewalls of the pixel opening Q1 are formed by the sidewalls of the pixel defining layer 140. At this time, the light emitted by the light-emitting device 210 can pass through the material of the pixel defining layer 140 and be emitted to the surface of the reflection layer 130.

[0138] The display substrate 100 includes a plurality of first grooves 150. In some embodiments, the first grooves 150 are arc-shaped grooves, and the plurality of arc-shaped grooves can be divided into a plurality of groups of arc-shaped grooves, and each group of arc-shaped grooves surrounds one first recess 160. Here, the first grooves 150 are arc-shaped grooves means that the cross section of the first grooves 150 parallel to the first direction X is arc-shaped.

[0139] As can be appreciated, when the reflective layer 130 covers the sidewalls and the bottom wall of the first recess 160, the portion of the reflective layer 130 covering the sidewalls and the bottom wall of the first recess 160 can continue the concave topography of the plurality of first recesses 160, so that the reflective layer 130 can include a plurality of reflective cup structures 130a. Moreover, when each first recess 160 surrounds a pixel opening Q1, the reflective cup structure 130a can surround the pixel opening Q1, so that, as shown in FIGS. 3-9, the light emitted from the side of the light emitting device 210 can be reflected on the surface of the reflective cup structure 130a and then emitted from the pixel opening Q1. In this way, the light emitting efficiency of the light emitting device 210 can be improved, and the light emitting efficiency of the display panel 200 can be improved.

[0140] On the other hand, when the first trench 150 penetrates through the pixel defining layer 140 to the first planar layer 122A, the common film layer (e.g., the electron generating layer 2141 and / or the hole generating layer 2142) of the plurality of light emitting devices 210 can be formed in the first trench 150, and when the first trench 150 is located between two adjacent first recesses 160 and the portion G of the first pattern 121a extending from the sidewall of the first trench 150 is close to the surface of the substrate 110 and has a gap E with the bottom of the first trench 150, when the common film layer is formed at the first trench 150, the common film layer formed on the portion G of the first pattern 121a extending from the sidewall of the first trench 150 is disconnected from the common film layer formed in the first trench 150 (see FIG. 1A), so that the transmission of the lateral current between the adjacent light emitting devices 210 can be reduced, and the color crosstalk phenomenon can be avoided. In this way, the light emitting device 210 included in the display panel 200 can be a series type light emitting device, so that the light emitting efficiency and the service life of the display panel 200 can be improved, and the power consumption of the display panel 200 can be reduced.

[0141] In some embodiments, the material of the plurality of light emitting functional layers and the material of the encapsulation layer 220 are filled in the first trench 150. For example, as shown in FIG. 1A, the portion of the first trench 150 located between the first passivation layer 121 and the first planar layer 122A can be divided into a portion 151 (hereinafter referred to as the first portion 151) located beside the portion G of the first pattern 121a extending from the sidewall of the first trench 150 and a remaining portion 152 (hereinafter referred to as the second portion 152) other than the first portion 151. The first portion 151 is filled with the material of the first sub-layer 221 of the encapsulation layer 220, and the second portion 152 is filled with the material of the light emitting functional layer. In this case, the material of the first sub-layer 221 located in the first portion 151 can form a barrier between the materials of the light emitting functional layer, and the effect of preventing color crosstalk can be improved.

[0142] FIG. IB is a partial enlarged view of M in FIG. 1A, and FIG. 1C is a partial view of the display panel obtained by Focused ion beam milling (FIB)-Transmission Electron Microscope (TEM), wherein EV in FIG. 1C represents the light-emitting functional layer.

[0143] Based on the above structure of the display substrate 100, in some embodiments, as shown in FIGS. 1A, 1B and 1C, the light-emitting device 210 includes at least two light-emitting layers 213 and a charge generation unit 214 located between the adjacent two light-emitting layers 213. The charge generation units 214 of the plurality of light-emitting devices 210 are of the same layer and material, and constitute a common unit 214G. The common unit 214G includes a fifth part 214A and a sixth part 214B. The fifth part 214A is located at a portion G where the first pattern 121a extends from the sidewall of the first groove 150, on one side of the second direction Y. The sixth part 214B is located in the first groove 150 and on one side of the first pattern 121a along the second direction Y. The second direction Y is the stacking direction of the multilayer flat layer 122. There is a spacing between the fifth part 214A and the sixth part 214B along the second direction Y.

[0144] Here, for the understanding of the charge generation unit 214, reference can be made to the exemplary description of the aforementioned partial charge generation unit 214, which will not be repeated here.

[0145] It can be understood that, through the above arrangement, the fifth part 214A and the sixth part 214B can be in a disconnected state (see FIG. 1A), so as to reduce the transmission of the lateral current between the adjacent light-emitting devices 210, avoid the color crosstalk phenomenon, so that the light-emitting device 210 included in the display panel 200 is a series light-emitting device, so that the light-emitting efficiency and the service life of the display panel 200 are improved, and the power consumption of the display panel 200 is reduced.

[0146] FIG. 10 is a flowchart of a method for manufacturing the display substrate 100 according to some embodiments of the present disclosure. FIGS. 11A-11H are schematic diagrams of manufacturing steps of the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 according to some embodiments of the present disclosure. FIGS. 11A-11C and FIGS. 12A-12D are schematic diagrams of manufacturing steps of the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 according to further embodiments of the present disclosure. FIGS. 13A-13G are schematic diagrams of manufacturing steps of the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 according to further embodiments of the present disclosure. FIGS. 13A and FIGS. 14A-14F are schematic diagrams of manufacturing steps of the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 according to further embodiments of the present disclosure. FIGS. 15A-15G are schematic diagrams of manufacturing steps of the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 according to further embodiments of the present disclosure. FIGS. 15A, 15B, FIGS. 16A-16E are schematic diagrams of manufacturing steps of the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 according to further embodiments of the present disclosure. FIGS. 17A-17G are schematic diagrams of manufacturing steps of the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 according to further embodiments of the present disclosure. FIGS. 10, 11A-11H, 12A-12D, 13A-13G, 14A-14F, 15A-15G, 16A-16E and 17A-17G will be described together below. It should be understood that the operations shown in the manufacturing method are not exhaustive, and other operations can also be performed before, after or between any of the operations shown. In the following manufacturing method, the process of patterning the film layer is, for example, an etching process.

[0147] As shown in FIG. 10, some embodiments of the present disclosure also provide a method for manufacturing the display substrate 100. The manufacturing method comprises S1-S5.

[0148] S1: forming the substrate 110.

[0149] S2: forming the insulating film group 120 on one side of the substrate 110; the insulating film group 120 comprises a first passivation layer 121 and a multilayer planar layer 122 arranged in a stack; the multilayer planar layer 122 comprises a first planar layer 122A; the first passivation layer 121 is located on the side of the first planar layer 122A away from the substrate 110 and in contact with the first planar layer 122A. The surface of the insulating film group 120 away from the substrate 110 comprises a plurality of first grooves 160 arranged along a first direction X; the first direction X intersects the stacking direction of the multilayer planar layer 122.

[0150] S3: forming the reflective layer 130 on the side of the insulating film group 120 away from the substrate 110, the reflective layer 130 covering the sidewalls and the bottom wall of the first grooves 160.

[0151] S4: forming a pixel defining layer 140 on a side of the reflective layer 130 distal to the substrate 110; the pixel defining layer 140 comprises a plurality of pixel openings Q1; each of the plurality of first recesses 160 surrounds one of the pixel openings Q1.

[0152] In some examples, the plurality of spacers PS are formed at the same time when the pixel defining layer 140 is formed.

[0153] S5: forming a plurality of first trenches 150, such that the first trenches 150 penetrate the pixel defining layer 140 and the first planar layer 122A; the first trenches 150 are located between two adjacent first recesses 160 of the plurality of first recesses 160. Wherein, the first passivation layer 121 comprises a first pattern 121a, the first pattern 121a comprises a portion extending from a sidewall of the first trench 150, and a gap E is present between the portion G of the first pattern 121a extending from the sidewall of the first trench 150 and a bottom of the first trench 150.

[0154] The display substrate 100 prepared by the above method has the same beneficial effects as the display substrate 100 described above, which will not be repeated here.

[0155] In the above preparation method, the process of forming the plurality of first recesses 160 and the plurality of first trenches 150 is, for example, an etching process.

[0156] On the one hand, as described above, in S3, the plurality of first recesses 160 can be formed by patterning a layer or a plurality of layers of the insulating film group 120 distal to the substrate 110; or the plurality of first recesses 160 can also be formed by patterning a layer or a plurality of layers of the insulating film group 120 located at an intermediate position, and making the insulating film group 120 located on a side distal to the substrate 110 of the plurality of recessed structures continue the topography of the plurality of recessed structures.

[0157] It should be understood that when the plurality of first recesses 160 are formed in the above manner, a layer or a plurality of layers of the insulating film group 120 need to be patterned.

[0158] On the other hand, in S5, when the first trench 150 is formed by penetrating the pixel defining layer 140 to the first planar layer 122A, at least the pixel defining layer 140, the first passivation layer 121 and the first planar layer 122A need to be patterned to form the plurality of first trenches 150; that is, as shown in FIGS. 3-9, the first trench 150 at least includes the fifth opening Q6 in the pixel defining layer 140, the sixth opening Q7 in the first passivation layer 121, and the seventh opening or the second recess K2 in the first planar layer 122A. Moreover, when the pixel defining layer 140 and the first planar layer 122A are present with other planar layers 122, these planar layers 122 also need to be patterned.

[0159] Therefore, when the plurality of first trenches 150 is formed, one or more film layers in the insulating film group 120 also need to be patterned. In this case, when the display panel 200 includes the plurality of first recesses 160 and the plurality of first trenches 150, the number of times of patterning of the insulating film group 120 can be increased, and the process difficulty of the manufacturing method of the display panel 200 can be increased.

[0160] In some embodiments, in order to reduce the number of times of patterning when the plurality of first recesses 160 and the plurality of first trenches 150 are formed, the method of forming the plurality of first recesses 160 and the plurality of first trenches 150 includes R1-R7.

[0161] R1: As shown in FIGS. 13B and 14A, a first initial planar layer 122Ai is formed.

[0162] R2: As shown in FIGS. 11C, 11H, 12B, 13G, 14B and 14F, the first initial planar layer 122Ai is patterned to form a first planar layer 122A, and the first planar layer 122A includes a plurality of seventh openings (not shown in the figures) or a plurality of second recesses K2.

[0163] R3: As shown in FIGS. 11D, 12A, 13C and 14B, an initial passivation layer is formed on a side of the first planar layer 122A away from the substrate 110.

[0164] R4: As shown in FIGS. 11D, 12A, 13C and 14B, the initial passivation layer is patterned to form a first passivation layer 121, and the first passivation layer 121 includes a plurality of sixth openings Q7.

[0165] R5: As shown in FIGS. 11E, 12B, 13D and 14C, a reflective layer 130 is formed on a side of the first passivation layer 121 away from the first planar layer 122A.

[0166] R6: As shown in FIG. 11F, FIG. 12C, FIG. 13E and FIG. 14D, the initial pixel defining layer 140i is formed on the side of the reflective layer 130 away from the first passivation layer 121.

[0167] R7: As shown in FIG. 11G, FIG. 12D, FIG. 13F and FIG. 14E, the initial pixel defining layer 140i (see FIG. 11F, FIG. 12C, FIG. 13E and FIG. 14D) is patterned to form the pixel defining layer 140, which includes a plurality of pixel openings Q1 and a plurality of fifth openings Q6.

[0168] In R2 and R4, as shown in FIG. 11C, FIG. 11D, FIG. 12A, FIG. 13C and FIG. 14B, the first initial planar layer 122Ai is patterned to form a plurality of seventh openings (not shown in the figures) or a plurality of second grooves K2, and the initial passivation layer is patterned to form a plurality of sixth openings Q7 and a plurality of first grooves 160.

[0169] It can be understood that, when the plurality of first grooves 160 and the plurality of first trenches 150 are formed by the above method, the plurality of first trenches 150 in the insulating film group 120 (i.e., the sixth openings Q7 and the seventh openings, or the sixth openings Q7 and the second grooves K2) are formed in the process of patterning the first passivation layer 121 and the first planar layer 122A, and the plurality of first grooves 160 are also formed, so that the number of times of patterning when forming the plurality of first grooves 160 and the plurality of first trenches 150 can be reduced, and the preparation process of the display panel 200 is simplified.

[0170] In some embodiments, as shown in FIG. 11D, FIG. 12A, FIG. 13C and FIG. 14B, when the plurality of first grooves 160 and the plurality of first trenches 150 are formed by the method including R1-R7, the first planar layer 122A includes a second pattern 122A-a. The sidewall of the first groove 160 includes the surface of the first pattern 121a; or the sidewall of the first groove 160 includes the surface of the first pattern 121a and the surface of the second pattern 122A-a.

[0171] It should be noted that the surface of the first pattern 121a includes the first type of surface and the second type of surface of the first pattern 121a. Similarly, the surface of the second pattern 122A-a includes the first type of surface and the second type of surface of the second pattern 122A-a.

[0172] The first type of surface of the first pattern 121a refers to the surface formed when the initial passivation layer is formed, and the first type of surface of the first pattern 121a can be a planar surface or a non-planar surface. The second type of surface of the first pattern 121a refers to the surface exposed after forming a plurality of openings or grooves in the initial passivation layer, and the second type of surface of the first pattern 121a can be the sidewall and bottom wall of the openings or grooves.

[0173] The first type of surface of the second pattern 122A-a and the second type of surface of the second pattern 122A-a can be understood with reference to the description of the first type of surface of the first pattern 121a and the second type of surface of the first pattern 121a, which will not be repeated here.

[0174] It should be understood that the beneficial effects that can be achieved by the above-mentioned arrangement are the same as those that can be achieved when the plurality of first grooves 160 and the plurality of first trenches 150 are formed by the method comprising R1-R7, which will not be repeated here.

[0175] When the sidewall of the first groove 160 comprises the surface of the first pattern 121a, or the sidewall of the first groove 160 comprises the surface of the first pattern 121a and the surface of the second pattern 122A-a, the following three cases can be included.

[0176] The first case: as shown in FIG. 13C, the sidewall of the first groove 160 comprises the second type of surface of the first pattern 121a and does not comprise the surface of the second pattern 122A-a, at this time, the first groove 160 can be formed by patterning the initial passivation layer.

[0177] The second case: as shown in FIG. 14F, the sidewall of the first groove 160 comprises the second type of surface of the first pattern 121a and comprises the second type of surface of the second pattern 122A-a, at this time, the first groove 160 can be formed by patterning the initial passivation layer and the first initial flat layer 122Ai.

[0178] The third case: as shown in FIGS. 11H and 12A, the sidewall of the first groove 160 comprises the first type of surface of the first pattern 121a and does not comprise the surface of the second pattern 122A-a, at this time, the first groove 160 can be formed by patterning the first initial flat layer to form openings or grooves, and making the first passivation layer 121 continue the topography of the openings or grooves.

[0179] The first case and the second case will be described exemplarily below.

[0180] In some embodiments, as shown in FIG. 13C and FIG. 14B, in the first case or the second case, a plurality of first openings Q2 are formed in the process of patterning the initial passivation layer in R4. The first openings Q2 constitute at least part of the first recesses 160.

[0181] In this case, the first passivation layer 121 includes a plurality of first openings Q2 arranged along the first direction X, and the first openings Q2 constitute at least part of the first recesses 160.

[0182] It can be understood that, by the above arrangement, the plurality of sixth openings Q7 and the plurality of first openings Q2 can be formed in the process of patterning the initial passivation layer, and the first openings Q2 can constitute part or all of the first recesses 160, so that the number of times of patterning in forming the plurality of first recesses 160 and the plurality of first grooves 150 can be reduced, and the preparation process of the display panel 200 can be simplified.

[0183] In some examples, as shown in FIG. 13C, in the first case, the first openings Q2 are the first recesses 160, that is, the first openings Q2 constitute all of the first recesses 160. In this case, the first recesses 160 can be formed by patterning the initial passivation layer, and the size L1 of the first passivation layer 121 along the second direction Y is consistent with the size H of the first recesses 160 along the second direction Y. Therefore, by controlling the size L1 of the first passivation layer 121 along the second direction Y, the size H of the first recesses 160 along the second direction Y can be within a reasonable range.

[0184] In some embodiments, as shown in FIG. 13C, in the case where the first openings Q2 constitute the first recesses 160, the size L1 of the first passivation layer 121 along the second direction Y is in the range of 0.5 μm to 1.5 μm, and the second direction Y is the stacking direction of the plurality of planar layers 122.

[0185] For example, the size L1 of the first passivation layer 121 along the second direction Y can be 0.5 μm, 0.7 μm, 0.9 μm, 1.0 μm, 1.2 μm, 1.4 μm, or 1.5 μm, etc.

[0186] It can be understood that, by such an arrangement, the size L1 of the first passivation layer 121 along the second direction Y can be relatively large, and the size H of the first recesses 160 along the second direction Y can be relatively large, which can improve the reflection effect of the reflective layer 130 on the light emitted by the light emitting device 210 to a certain extent.

[0187] In some examples, in the second case, the first opening Q2 constitutes a part of the first recess 160, and in this case, the rest of the first recess 160 except the first opening Q2 can be an opening formed in the first planar layer 122A or a groove formed in the first planar layer 122A.

[0188] For example, as shown in FIG. 18, the first opening Q2 constitutes a part of the first recess 160, and the first planar layer 122A includes a plurality of second openings Q3 connected corresponding to the plurality of first openings Q2, and the second openings Q3 constitute the rest of the first recess 160 except the first openings Q2. In this case, the bottom surface of the first groove 150 is closer to the base 110 than the bottom surface of the first recess 160.

[0189] It should be understood that when the bottom surface of the first groove 150 is closer to the base 110 than the bottom surface of the first recess 160, the second recess K2 is included in the first groove 150.

[0190] For example, when the first planar layer 122A is patterned, a half-tone mask can be used so that the second recess K2 can be formed in the process of forming the second opening Q3.

[0191] For another example, as shown in FIGS. 14B and 14F, the first opening Q2 constitutes a part of the first recess 160, and the first planar layer 122A includes a plurality of first sub-recesses K1 connected corresponding to the plurality of first openings Q2, and the first sub-recesses K1 constitute the rest of the first recess 160 except the first openings Q2.

[0192] It can be understood that through the above arrangement, when the first planar layer 122A is patterned, the plurality of seventh openings (not shown in the figure) or the plurality of second recesses K2 contained in the first groove 150, and the rest of the first recess 160 except the first openings Q2 (the second openings Q3 or the first sub-recesses K1) can be formed, so that the number of times of patterning when forming the plurality of first recesses 160 and the plurality of first grooves 150 can be reduced, and the preparation process of the display panel 200 is simplified.

[0193] In some embodiments, as shown in FIGS. 14B and 14F, in the case where the first planar layer 122A includes a plurality of first sub-recesses K1, the size L2 of the first planar layer 122A along the second direction Y ranges from 1.5 μm to 3.0 μm.

[0194] For example, the size L2 of the first planar layer 122A along the second direction Y can be 1.5 μm, 1.8 μm, 2.0 μm, 2.3 μm, 2.5 μm, 2.7 μm, or 3.0 μm, etc.

[0195] It can be understood that, by being thus configured, the first flat layer 122A can have a relatively large size L2 in the second direction Y, the first sub-groove K1 can have a relatively large size in the second direction Y, and the first groove 160 can also have a relatively large size in the second direction Y, so that the anti-crosstalk effect of the pixel boundary layer 140 can be increased, as described above.

[0196] For a clearer description, the method of forming the plurality of first grooves 160 and the plurality of first trenches 150 in the first case and the second case is described exemplarily as follows.

[0197] In some embodiments, in the first case, the method of forming the plurality of first grooves 160 and the plurality of first trenches 150 comprises V1-V6.

[0198] V1: As shown in FIG. 13B, a first initial flat layer 122Ai is formed.

[0199] V2: As shown in FIG. 13C, an initial passivation layer is formed on a side of the first initial flat layer 122Ai away from the substrate 110.

[0200] V3: As shown in FIG. 13C, an etching process is used to pattern the initial passivation layer to form a first passivation layer 121, the first passivation layer 121 comprising a plurality of sixth openings Q7 and a plurality of first openings Q2.

[0201] V4: As shown in FIG. 13D, a patterned reflective layer 130 is formed on a side of the first passivation layer 121 away from the first initial flat layer 122Ai.

[0202] V5: As shown in FIG. 13E and FIG. 13F, a patterned pixel boundary layer 140 is formed on a side of the reflective layer 130 away from the first passivation layer 121.

[0203] V6: As shown in FIG. 13G, the first initial flat layer 122Ai is patterned to form a plurality of second grooves K2 and a plurality of gaps E.

[0204] It should be understood that, in the case where the method of forming the plurality of first grooves 160 and the plurality of first trenches 150 comprises V1-V6, in the aforementioned preparation method, the step of patterning the first initial flat layer 122Ai in R2 is V6, in other words, R2 is performed after R7.

[0205] In some embodiments, in the second case, the method of forming the plurality of first grooves 160 and the plurality of first trenches 150 comprises W1-W6.

[0206] W1: As shown in FIG. 14A, a first initial flat layer 122Ai is formed.

[0207] W2: As shown in FIG. 14B, an initial passivation layer is formed on a side of the first initial planar layer 122Ai away from the substrate 110.

[0208] W3: As shown in FIG. 14B, the initial passivation layer and the first initial planar layer 122Ai are patterned by an etching process to form a first passivation layer 121 and a first initial pattern 122Aii, the first passivation layer 121 comprising a plurality of sixth openings Q7 and a plurality of first openings Q2, the first initial pattern 122Aii comprising a fourth recess K4 and a first sub-recess K1, the sixth openings Q7 being connected with the fourth recess K4 to form part of a first trench 150, and the first openings Q2 being connected with the first sub-recess K1 to form a first recess 160.

[0209] W4: As shown in FIG. 14C, a patterned reflective layer 130 is formed on a side of the first passivation layer 121 away from the first initial planar layer 122Ai.

[0210] W5: As shown in FIGS. 14D and 14E, a patterned pixel definition layer 140 is formed on a side of the reflective layer 130 away from the first passivation layer 121.

[0211] W6: As shown in FIG. 14F, the first initial pattern 122Aii is patterned to expand the fourth recess K4 into a second recess K2 and form a plurality of gaps E.

[0212] It should be understood that, in the case where the method of forming the plurality of first recesses 160 and the plurality of first trenches 150 comprises W1-W6, the aforementioned preparation method, the patterning of the first initial planar layer 122Ai in R2 can comprise R2.1A and R2.2B.

[0213] R2.1A: The first initial planar layer 122Ai is patterned to form a first initial pattern 122Aii, the first initial pattern 122Aii comprising a fourth recess K4 and a first sub-recess K1.

[0214] R2.2B: The first initial pattern 122Aii is patterned to expand the fourth recess K4 into a second recess K2 and form a plurality of gaps E.

[0215] That is, W3 comprises R2.1A, and W6 is R2.2B; in other words, R2 comprises the part performed in the process of R4 and the part performed after R7.

[0216] The above is an exemplary description of the first and second cases, and the third case is described exemplarily as follows.

[0217] In some embodiments, in the aforementioned fabrication method, S2 comprises forming an initial planar layer, and forming an initial passivation layer on a side of the initial planar layer distal to the substrate 110. S5 comprises patterning the initial passivation layer using an etching process.

[0218] In this case, during the patterning of the initial passivation layer, the etching parameters are controlled such that the portion of the initial planar layer proximal to the initial passivation layer is removed to form the portion of the first trench 150 located proximal to the substrate 110 of the first passivation layer 121, and to form the portion G of the first pattern 121a extending from the sidewall of the first trench 150, and the gap E from the bottom of the first trench 150.

[0219] It can be understood that, through the above arrangement, the gap E can be formed by over-etching the initial passivation layer, and thus the formation process of the gap E can be simplified.

[0220] In some embodiments, the aforementioned initial planar layer is the second initial pattern 122Aiii. The following will exemplarily illustrate this case.

[0221] In some embodiments, in the aforementioned fabrication method, the patterning of the first initial planar layer in R2 can comprise R2.1a.

[0222] R2.1a: As shown in FIG. 11C, the first initial planar layer is patterned to form the second initial pattern 122Aiii, the second initial pattern 122Aiii comprises a plurality of third openings Q4. The area where the plurality of third openings Q4 are located is directly opposite to the area where the plurality of first grooves 160 are located along the second direction Y.

[0223] In this case, when the initial passivation layer is formed in R3, the initial passivation layer follows the topography of the plurality of third openings Q4 of the second initial pattern 122Aiii. In some examples, when the initial passivation layer is patterned in R4, the portion of the initial passivation layer covering the plurality of third openings Q4 is retained.

[0224] In this case, in some embodiments, as shown in FIG. 11H and FIG. 12B, the first planar layer 122A further comprises a plurality of third openings Q4 arranged along the first direction X, and the first pattern 121a and the reflective layer 130 are sequentially arranged on the sidewall and bottom wall of the third openings Q4.

[0225] It can be understood that, through the above arrangement, the area of the first planar layer 122A opposite to the plurality of grooves 160 along the second direction Y can be covered by the first passivation layer 121, and thus, as shown in FIG. 12A, the gap E can be formed by over-etching the initial passivation layer in the process of forming the plurality of seventh openings (not shown in the figure) or the plurality of second grooves K2, and thus the formation process of the gap E can be simplified.

[0226] For a clearer illustration, the following takes the case that the first trench 150 includes the second groove K2 as an example to exemplarily introduce the above method of forming the plurality of second grooves K2 and the plurality of gaps E by over-etching the first passivation layer 121.

[0227] In some embodiments, the method of forming the plurality of first grooves 160 and the plurality of first trenches 150 includes T1-T7.

[0228] T1: Form a first initial flat layer.

[0229] T2: As shown in FIG. 11C, pattern the first initial flat layer to form a second initial pattern 122Aiii, the second initial pattern 122Aiii including a plurality of third openings Q4.

[0230] T3: As shown in FIG. 12A, form an initial passivation layer on a side of the second initial pattern 122Aiii away from the substrate 110.

[0231] T4: As shown in FIG. 12A, pattern the initial passivation layer and the second initial pattern 122Aiii by an etching process to form a first passivation layer 121 including a plurality of sixth openings Q7 and a first flat layer 122A including a plurality of second grooves K2 and a plurality of gaps E.

[0232] In some examples, the process of patterning the initial passivation layer to form the plurality of sixth openings Q7 also forms one or more eighth openings Q8 in the first passivation layer 121; the process of patterning the second initial pattern 122Aiii to form the plurality of second grooves K2 and the plurality of gaps E also forms one or more third grooves K3 in the first flat layer 122 and a plurality of first gaps J1, wherein the plurality of third grooves K3 are connected to the plurality of eighth openings Q8 in correspondence. The groove depth of the second grooves K2 is consistent with the groove depth of the third grooves K3. The first gaps J1 are cavities in the first pattern 121a on the side close to the substrate 110 and connected to the third grooves K3.

[0233] T5: As shown in FIG. 12B, form a patterned reflective layer 130 on a side of the first passivation layer 121 away from the first flat layer 122A.

[0234] T6: As shown in FIG. 12C, form an initial pixel defining layer 140i on a side of the reflective layer 130 away from the first passivation layer 121.

[0235] In some examples, as shown in FIG. 12C, the material of the initial pixel defining layer 140i also fills the plurality of sixth openings Q7, the plurality of second grooves K2, and the plurality of gaps E.

[0236] In some examples, as shown in Figure 12C, the material of the initial pixel defining layer 140i is also filled in one or more eighth openings Q8, one or more third grooves K3, and multiple first gaps J1.

[0237] T7: As shown in Figure 12D, the initial pixel definition layer 140i (see Figure 12C) is patterned to form a pixel definition layer 140, which includes a plurality of pixel openings Q1 and a plurality of fifth openings Q6.

[0238] In some examples, as shown in Figure 12D, during the patterning of the initial pixel defining layer 140i, the material of the initial pixel defining layer 140i located in the plurality of sixth openings Q7, the plurality of second grooves K2 and the plurality of gaps E is removed.

[0239] In some examples, as shown in Figure 12D, during the patterning of the initial pixel defining layer 140i, the material of the initial pixel defining layer 140i located in one or more third grooves K3 and multiple first gaps J1 is not removed and forms part of the pixel defining layer 140.

[0240] In this case, in some embodiments, as shown in FIG12D, the pixel defining layer 140 further includes a first portion 141 located on the side of the first passivation layer 121 near the substrate 110; the surface of the first portion 141 near the substrate 110 is flush with the bottom surface of the first trench 150; the edge portion of the first portion 141 overlaps with the edge portion of the first passivation layer 121.

[0241] It should be understood that the portion of the initial pixel defining layer 140i that fills one or more third grooves K3 and multiple first gaps J1 is the first portion 141; the edge portion of the first portion 141 is the portion of the initial pixel defining layer 140i that fills multiple first gaps J1.

[0242] Furthermore, when the first gap J1 is a cavity located on the side of the first pattern 121a near the substrate 110 and connected to the third groove K3, the edge portion of the first portion 141 overlaps with the edge portion of the first passivation layer 121. When the groove depth of the second groove K2 is the same as the groove depth of the third groove K3, the surface of the first portion 141 near the substrate 110 is flush with the bottom surface of the first groove 150.

[0243] It should be understood that the beneficial effects that the display substrate 100 can achieve through the above-described configuration are the same as those that can be achieved when a plurality of first grooves 160 and a plurality of first trenches 150 are formed using methods including T1 to T7, and will not be repeated here.

[0244] In some embodiments, the aforementioned method further includes R1A before R1.

[0245] R1A: As shown in FIG. 13A, a first source-drain metal layer SD2 is formed on one side of the substrate 110.

[0246] It should be understood that, in the case where R1A is included before R1, as shown in FIG. 13B and FIG. 14A, in R1, a first initial planar layer 122Ai is formed on the side of the first source-drain metal layer SD2 away from the substrate 110.

[0247] In some embodiments, in the case where R1A is included before R1, as shown in FIG. 13B and FIG. 14A, the first initial planar layer 122Ai formed in R1 includes a via connected to the pattern of the first source-drain metal layer SD2.

[0248] To this end, in some embodiments, as shown in FIG. 5 and FIG. 6, the side of the first planar layer 122A away from the first passivation layer 121 is provided with the first source-drain metal layer SD2. The reflective layer 130 is coupled to the pattern of the first source-drain metal layer SD2 through a via in the first planar layer 122A, and / or a via in the first passivation layer 121.

[0249] It should be understood that, in the case where the part of the reflective layer 130 covering the bottom wall of the first recess 160 is reused as the anode 211, the anode 211 can be coupled to the pixel driving circuit in turn through the pattern of the first source-drain metal layer SD2, the pattern of the second source-drain metal layer SD1, to realize the control of the light-emitting device by the pixel driving circuit.

[0250] Illustratively, the pixel driving circuit includes a light-emitting control transistor. The anode 211 can be coupled to the source or drain of the light-emitting control transistor of the pixel driving circuit in turn through the pattern of the first source-drain metal layer SD2, the pattern of the second source-drain metal layer SD1.

[0251] It can be understood that, when the first source-drain metal layer SD2 is provided on the side of the first planar layer 122A away from the first passivation layer 121, the distance between the first source-drain metal layer SD2 and the reflective layer 130 is relatively short, so that the reliability of the coupling between the first source-drain metal layer SD2 and the reflective layer 130 can be improved.

[0252] In some embodiments, the aforementioned method further includes R1B after R1A and before R1.

[0253] R1B: As shown in FIG. 11B, a second planar layer 122B is formed on the side of the first source-drain metal layer SD2 away from the substrate 110.

[0254] It should be understood that, in the case where R1A is followed by R1B and R1 is preceded by R1B, as shown in FIG. 11C, R1, the first initial planar layer is formed on the side of the second planar layer 122B away from the first source-drain metal layer SD2.

[0255] In some embodiments, in the case where R1A is followed by R1B and R1 is preceded by R1B, as shown in FIG. 11C, the first initial planar layer formed in R1 includes a via connected to the pattern of the first source-drain metal layer SD2.

[0256] To this end, in some embodiments, as shown in FIGS. 3 and 4, the insulating film group 120 further includes a second planar layer 122B on the side of the first planar layer 122A away from the first passivation layer 121; and the display substrate 100 further includes a first source-drain metal layer SD2 on the side of the second planar layer 122B away from the first planar layer 122A.

[0257] It can be understood that, by the above arrangement, the second planar layer 122B is located between the first planar layer 122A and the first source-drain metal layer SD2, so that when a plurality of seventh openings (not shown in the drawings) or a plurality of second grooves K2 are formed by over-etching the initial passivation layer, the etching process has relatively little effect on the first source-drain metal layer SD2.

[0258] The above is an exemplary description of patterning the first passivation layer 121 and the first planar layer 122A, forming part of the plurality of first grooves 150 and the plurality of first recesses 160 in the insulating film group 120, and in the following, another method of forming the plurality of first grooves 150 and the plurality of first recesses 160 will be exemplarily described.

[0259] As described above, when the gap E is formed by over-etching the initial passivation layer, in some examples, the initial planar layer can be the second initial pattern 122Aiii. In yet other embodiments, the initial planar layer is the first initial planar layer 122Ai, which will be described below.

[0260] In some embodiments, the method of forming the plurality of first recesses 160 and the plurality of first grooves 150 includes U1-U7.

[0261] U1: As shown in FIG. 15B, a first initial planar layer 122Ai is formed.

[0262] U2: An initial passivation layer is formed on the side of the first initial planar layer 122Ai away from the substrate 110.

[0263] U3: As shown in FIG. 15C, FIG. 16A and FIG. 17A, the initial passivation layer and the first initial planar layer 122Ai (see FIG. 15B) are patterned by an etching process to form the first passivation layer 121 and the first planar layer 122, the first passivation layer 121 includes a plurality of sixth openings Q7, and the first planar layer 122 includes a plurality of second grooves K2 and a plurality of gaps E.

[0264] In some examples, during the process of patterning the initial passivation layer to form the plurality of sixth openings Q7, one or more eighth openings Q8 are also formed in the first passivation layer 121; during the process of patterning the first initial planar layer 122Ai to form the plurality of second grooves K2 and the plurality of gaps E, one or more third grooves K3 and a plurality of first gaps J1 are also formed in the first planar layer 122, the one or more third grooves K3 are connected to the plurality of eighth openings Q8 in correspondence. The groove depth of the second grooves K2 is consistent with the groove depth of the third grooves K3. The first gaps J1 are cavities located on the side of the first pattern 121a close to the substrate 110 and connected to the third grooves K3.

[0265] U4: A third initial planar layer is formed on the side of the first passivation layer 121 away from the first planar layer 122A.

[0266] U5: As shown in FIG. 15D, FIG. 16B and FIG. 17D, the third initial planar layer is patterned to form a third planar layer 122C, the third planar layer 122C includes a plurality of fourth openings Q5 and a plurality of ninth openings Q9, the plurality of fourth openings Q5 are multiplexed as a plurality of first grooves 160, and the plurality of ninth openings Q9 are connected to the plurality of sixth openings Q7 in correspondence.

[0267] U6: As shown in FIG. 15E, FIG. 16C and FIG. 17E, a reflective layer 130 is formed on the side of the third planar layer 122C away from the first passivation layer 121.

[0268] U7: As shown in FIG. 15F, FIG. 15G, FIG. 16D, FIG. 16E, FIG. 17F and FIG. 17G, a patterned pixel defining layer 140 is formed on the side of the reflective layer 130 away from the first passivation layer 121, the pixel defining layer 140 includes a plurality of pixel openings Q1 and a plurality of fifth openings Q6.

[0269] Based on the above method, in some embodiments, as shown in FIG. 7-FIG. 9, the display substrate 100 further includes a third planar layer 122C. The third planar layer 122C is arranged on the side of the first passivation layer 121 away from the first planar layer 122A, and includes a plurality of fourth openings Q5 arranged along the first direction X; the plurality of fourth openings Q5 are multiplexed as a plurality of first grooves 160.

[0270] It can be understood that, in the first aspect, the method for forming the plurality of first grooves 160 and the plurality of first trenches 150 includes the arrangement of U1-U7, and the gap E can be formed in the process of forming the plurality of seventh openings (not shown in the figure) or the plurality of second grooves K2 by over-etching the initial passivation layer, so that the forming process of the gap E can be simplified. In the second aspect, by the above arrangement, the bottom surface of the first groove 160 is farther away from the substrate 110 than the bottom surface of the second groove K2, so that the depth of the first trench 150 can be deeper, and the blocking effect of the first trench 150 on the common film layer can be improved to some extent, and the transmission of the lateral current between the adjacent light emitting devices 210 can be reduced.

[0271] In some embodiments, as shown in FIGS. 15C, 15D, 16A and 16B, the third initial planar layer is in contact with the first passivation layer 121, and the material of the third initial planar layer also fills in the plurality of sixth openings Q7, the plurality of second grooves K2 and the plurality of gaps E.

[0272] In some examples, as shown in FIGS. 15C, 15D, 16A and 16B, the material of the third initial planar layer also fills in one or more third grooves K3 and the plurality of first gaps J1.

[0273] At this time, as shown in FIGS. 15C, 15D, 16A and 16B, in the process of patterning the third initial planar layer at U5, the material of the third initial planar layer located in the plurality of sixth openings Q7, the plurality of second grooves K2 and the plurality of gaps E is removed. In the process of patterning the third initial planar layer, the material of the third initial planar layer located in one or more third grooves K3 and the plurality of first gaps J1 is retained to form part of the third planar layer 122C.

[0274] To this end, in some embodiments, as shown in FIGS. 7 and 8, the third planar layer 122C further includes a third part 122C1 located on the side of the first passivation layer 121 close to the substrate 110; the edge part of the third part 122C1 overlaps the edge part of the first passivation layer 121.

[0275] Here, the part of the third initial planar layer that fills in one or more third grooves K3 and the plurality of first gaps J1 is the third part 122C1; the edge part of the third part 122C1 is the part of the third initial planar layer that fills in the plurality of first gaps J1. In the case where the first gap J1 is a cavity located on the side of the first pattern 121a close to the substrate 110 and in communication with the third groove K3, the edge part of the third part 122C1 overlaps the edge part of the first passivation layer 121.

[0276] It should be understood that in the above method, in U3, when the initial passivation layer and the first initial planar layer 122Ai are patterned by using the etching process, the portion of the initial passivation layer that is directly opposite the first groove 160 along the second direction Y can be etched away or can be retained. The above two cases will be described exemplarily below.

[0277] In some embodiments, as shown in FIG. 16A, in the above method, in U3, when the initial passivation layer and the first initial planar layer 122Ai are patterned by using the etching process, the portion of the initial passivation layer that is directly opposite the first groove 160 along the second direction Y is also etched away, so that the orthogonal projection of the first passivation layer 121 on the substrate 110 does not overlap with the orthogonal projection of the reflective layer 130 (see FIG. 16C) on the substrate 110.

[0278] At this time, as shown in FIG. 16B, in the process of forming the third initial planar layer in U4, the portion of the third initial planar layer that does not cover the first pattern 121a will be in contact with the first planar layer 122A.

[0279] As shown in FIG. 16B, in the process of patterning the third initial planar layer in U5, the bottom walls of the plurality of fourth openings Q5 formed are flush with the bottom walls of the third grooves K3, and both are located between the first pattern 121a and the substrate 110.

[0280] As shown in FIG. 16C, in the process of forming the reflective layer 130 in U6, the material of the reflective layer 130 will form on the bottom walls of the plurality of fourth openings Q5 (i.e., the first grooves 160), so that the surface of the portion of the reflective layer 130 that covers the bottom walls of the first grooves 160 closer to the substrate 110 is closer to the substrate 110 than the surface of the first passivation layer 121 closer to the substrate.

[0281] In this case, in some embodiments, as shown in FIG. 8, the orthogonal projection of the first passivation layer 121 on the substrate 110 does not overlap with the orthogonal projection of the reflective layer 130 on the substrate 110; the surface of the portion of the reflective layer 130 that covers the bottom walls of the first grooves 160 closer to the substrate 110 is closer to the substrate 110 than the surface of the first passivation layer 121 closer to the substrate.

[0282] It should be understood that through the above arrangement, the display substrate 100 can achieve the same beneficial effects as when the plurality of first grooves 160 and the plurality of first trenches 150 are formed by using the method comprising U1-U7, i.e., the formation process of the gap E can be simplified, and the transmission of the lateral current between adjacent light emitting devices 210 can be reduced.

[0283] In yet some embodiments, as shown in FIG. 15B and FIG. 15C, in the above method, in U3, when the initial passivation layer and the first initial planar layer 122Ai are patterned by using the etching process, the portion of the initial passivation layer which is directly opposite to the first recess 160 along the second direction Y is reserved, so that the orthographic projection of the first passivation layer 121 on the substrate 110 overlaps with the orthographic projection of the reflective layer 130 on the substrate 110 at least in the region where the first recess 160 (see FIG. 7) is located.

[0284] At this time, as shown in FIG. 15D, in the process of patterning the third initial planar layer in U5, the bottom wall of the plurality of fourth openings Q5 formed is flush with the surface of the first pattern 121a away from the substrate 110.

[0285] As shown in FIG. 15E, in the process of forming the reflective layer 130 in U6, the material of the reflective layer 130 is formed on the bottom wall of the plurality of fourth openings Q5 (i.e., the first recess 160), so that the reflective layer 130 is in contact with the first passivation layer 121 (or the first pattern 121a).

[0286] To this end, in some embodiments, as shown in FIG. 7, the reflective layer 130 is in contact with the first passivation layer 121. The third planar layer 122C further includes a third portion 122C1 located on the side of the first passivation layer 121 close to the substrate 110; the edge portion of the third portion 122C1 overlaps with the edge portion of the first passivation layer 121.

[0287] It can be understood that, on the one hand, through the above arrangement, the display substrate 100 can achieve the same beneficial effects as when the plurality of first recesses 160 and the plurality of first grooves 150 are formed by using the method comprising U1-U7, i.e., the formation process of the gap E can be simplified, and the transmission of the lateral current between the adjacent light emitting devices 210 can be reduced. On the other hand, through the above arrangement, the reflective layer 130 can be formed on the surface of the first passivation layer 121, which can make the surface of the reflective layer 130 close to the substrate 110 more flat, and the bottom surface of the anode 211 more flat, which is beneficial to improve the uniformity of light emission, as compared with the case where the reflective layer 130 is formed on the bottom wall of the third recess K3 (see FIG. 16C).

[0288] In some embodiments, before U1 in the above method, U1F is further included.

[0289] U1F: As shown in FIG. 15A, a patterned first source-drain metal layer SD2 is formed on the substrate 110.

[0290] In some examples, as shown in FIG. 15B, FIG. 15C and FIG. 16A, in the case that U1F is further included before U1, in U3, when the initial passivation layer and the first initial planar layer 122Ai are patterned by using the etching process, the parameters of the etching process can be controlled to make the etching depth shallow, for example, to make the surface of the first source-drain metal layer SD2 away from the substrate 110 located between the surface of the second recess K2 close to the substrate 110 and the substrate 110, so that the etching process can be avoided to the first source-drain metal layer SD2.

[0291] For this purpose, in some embodiments, as shown in FIG. 7 and FIG. 8, the display substrate 100 further includes a first source-drain metal layer SD2. The first source-drain metal layer SD2 is located on the side of the first planar layer 122A close to the substrate 110; the surface of the first source-drain metal layer SD2 away from the substrate 110 is closer to the substrate 110 than the surface of the first trench 150 close to the substrate 110.

[0292] It can be understood that through the above arrangement, the influence of the process of over-etching the initial passivation layer on the first source-drain metal layer SD2 can be reduced.

[0293] In some embodiments, after U3 and before U4, the above method further includes U3A-U3C.

[0294] U3A: As shown in FIG. 17B, the patterned first source-drain metal layer SD2 is formed on the side of the first passivation layer 121 away from the first planar layer 122A, and the orthographic projection of the plurality of gaps E on the substrate 110 does not overlap with the orthographic projection of the first source-drain metal layer SD2 on the substrate 110, and a spacing is left therebetween.

[0295] In the case that the first planar layer 122 includes a plurality of first gaps J1, the orthographic projection of the plurality of first gaps J1 on the substrate 110 does not overlap with the orthographic projection of the first source-drain metal layer SD2 on the substrate 110, and a spacing is left therebetween.

[0296] U3B: The second initial planar layer is formed on the side of the first source-drain metal layer SD2 away from the first passivation layer 121.

[0297] In some examples, as shown in FIG. 17B and FIG. 17C, the material of the second initial planar layer also fills in the plurality of sixth openings Q7, the plurality of second recesses K2 and the plurality of gaps E.

[0298] In some examples, as shown in FIG. 17B and FIG. 17C, the material of the second initial planar layer also fills in one or more third recesses K3 and the plurality of first gaps J1.

[0299] U3C: As shown in FIGS. 17B and 17C, the second initial planar layer is patterned to form a second planar layer 122B, the second planar layer 122B comprising a plurality of tenth openings Q10, the plurality of tenth openings Q10 corresponding to the plurality of sixth openings Q7.

[0300] In some examples, as shown in FIGS. 17B and 17C, in the process of patterning the second initial planar layer to form the second planar layer 122B, the material of the second initial planar layer located in the plurality of sixth openings Q7, the plurality of second grooves K2 and the plurality of gaps E is removed.

[0301] In some examples, as shown in FIGS. 17B and 17C, in the process of patterning the second initial planar layer, the material of the second initial planar layer 122Bi located in the one or more third grooves K3 and the plurality of first gaps Ji is retained to form part of the second planar layer 122B.

[0302] It should be understood that, as shown in FIG. 17D, in the case where U3A-U3C are further included after U3 and before U4, in U4, the third initial planar layer is formed on the side of the second planar layer 122B away from the first source-drain metal layer SD2.

[0303] Therefore, in some embodiments, as shown in FIG. 9, the insulating film group 120 further comprises a second planar layer 122B. The display substrate 100 further comprises a first source-drain metal layer SD2. The second planar layer 122B and the first source-drain metal layer SD2 are located between the first planar layer 122A and the third planar layer 122C; the second planar layer 122B is farther away from the substrate 110 than the first source-drain metal layer SD2. The surface SD2a of the first source-drain metal layer SD2 close to the substrate 110 is closer to the substrate 110 than the surface 121b of the first passivation layer 121 close to the substrate 110. The second planar layer 122B further comprises a second portion 122B1 located on the side of the first passivation layer 121 close to the substrate 110; the edge portion of the second portion 122B1 overlaps with the edge portion of the first passivation layer 121.

[0304] It should be understood that, as shown in FIGS. 17A and 17B, in the case where one or more third grooves K3 are formed in the first planar layer 122 in U3, the first source-drain metal layer SD2 can be formed on the bottom surface of the first groove K3, so that the surface SD2a of the source-drain metal layer SD1 close to the substrate 110 is closer to the substrate 110 than the surface 121b of the first passivation layer 121 close to the substrate 110.

[0305] Furthermore, as shown in FIGS. 17A, 17B and 17C, the second portion 122B1 is the portion of the second initial planar layer filled in the one or more third recesses K3 and the plurality of first gaps J1. The edge portion of the second portion 122B1 is the portion of the second initial planar layer filled in the plurality of first gaps J1. In the case that the first gap J1 is a cavity located on the side of the first pattern 121a close to the substrate 110 and in communication with the third recess K3, the edge portion of the second portion 122B1 overlaps with the edge portion of the first passivation layer 121.

[0306] It should be understood that, by the above arrangement, the display substrate 100 can achieve the same beneficial effects as when the plurality of first recesses 160 and the plurality of first trenches 150 are formed by the method comprising U1-U7, which will not be described herein again.

[0307] The above is an exemplary description of the case that the initial planar layer is the first initial planar layer 122Ai. The material of the pixel defining layer 140 and the relative position of the first trench 150 will be described exemplarily below.

[0308] In some embodiments, as shown in FIGS. 14E and 14F, in the process of forming the initial pixel defining layer 140i in R6, the material of the initial pixel defining layer 140i is filled in the plurality of fourth recesses K4, and in the process of patterning the initial pixel defining layer 140i in R7, the material of the initial pixel defining layer 140i filled in the plurality of fourth recesses K4 is partially removed.

[0309] In yet some embodiments, as shown in FIGS. 12C and 12D, in the process of forming the initial pixel defining layer 140i in T6, the material of the initial pixel defining layer 140i is filled in the plurality of second recesses K2 and the plurality of gaps E, and in the process of patterning the initial pixel defining layer 140i in T7, the material of the initial pixel defining layer 140i filled in the plurality of second recesses K2 and the plurality of gaps E is partially removed.

[0310] In yet some embodiments, in the process of forming the patterned pixel defining layer 140 in U7, the material of the initial pixel defining layer 140i is filled in the plurality of second recesses K2 and the plurality of gaps E, and the material of the initial pixel defining layer 140i filled in the plurality of second recesses K2 and the plurality of gaps E is partially removed in the patterning process.

[0311] Based on the above, the material of the initial pixel defining layer 140i will be retained in the plurality of second recesses K2. In some embodiments, as shown in FIGS. 4 and 6, the pixel defining layer 140 comprises a fourth portion 142 located on the side of the first passivation layer 121 close to the substrate 110, and the side surface of the fourth portion 142 constitutes part of the sidewall of the first trench 150.

[0312] It should be understood that, in the case where the pixel defining layer 140 includes the fourth portion 142, in the display substrate prepared, the size of the first trench 150 along the first direction X is smaller than the size of the second groove K2.

[0313] In some examples, the gap G is formed prior to the pixel defining layer 140 (for example, the case corresponding to FIGS. 15C-15G), and the ring side of the second groove K2 is provided with the gap G. At this time, when the initial pixel defining layer 140i is patterned, by controlling the position of the opening area of the mask plate, the part of the material filled in the gap G can be removed, and the remaining part of the material filled in the gap G can be retained to form the fourth portion 142.

[0314] In some examples, the pixel defining layer 140 is formed prior to the gap G (for example, the case corresponding to FIGS. 14A-14F), and at this time, when the initial pixel defining layer 140i is patterned, by controlling the position of the opening area of the mask plate, at least part of the edge of the first pattern 121a corresponding to the first trench 150 can be exposed after the initial pixel defining layer 140i is patterned (see FIG. 14E), so that the pixel defining layer 140 can be formed as shown in FIG. 14F, and the edge of the first pattern 121a exposed is etched to form the gap G.

[0315] It can be understood that, through the above arrangement, the size of the first trench 150 along the first direction X can be relatively small, and the design space of the pixel defining layer 140 can be improved, which is conducive to the improvement of the pixel density.

[0316] In some embodiments, as shown in FIGS. 3 and 6, the part G of the first pattern 121a extending from the side wall of the first trench 150 has a first distance L3 along the second direction Y from the surface of the substrate 110 to the bottom surface of the first trench 150. The insulating film group 120 has a second distance L4 along the second direction Y from the surface of the substrate 110 to the bottom surface of the first groove 160. The first distance L3 is less than or equal to the second distance L4; and the second direction Y is the stacking direction of the multi-layer flat layer 122.

[0317] It should be understood that, as described above, through the arrangement of the first distance L3, the common film layer formed on the part G of the first pattern 121a extending from the side wall of the first trench 150 can be in a disconnected state with the common film layer formed in the first trench 150, and the first distance L3 needs to be greater than a first threshold value. Through the arrangement of the second distance L4, the light emitted by the light-emitting layer 213 of the light-emitting device 210 can be reflected on the surface of the reflective layer 130, and the second distance L4 needs to be greater than a second threshold value. In some embodiments, the first threshold value is less than the second threshold value.

[0318] It can be understood that, through the above arrangement, the size of the gap E along the second direction Y can be relatively small, the size of the first groove 160 along the second direction Y can be relatively large, and the size of the gap E along the second direction Y and the size of the first groove 160 along the second direction Y can be matched with the corresponding functions, while the process difficulty in forming the gap E can be reduced.

[0319] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising: a substrate; an insulating film group on one side of the substrate, and comprising a first passivation layer and a multi-layer planarization layer stacked one on another; the multi-layer planarization layer comprising a first planarization layer; the first passivation layer on a side of the first planarization layer away from the substrate and in contact with the first planarization layer; a surface of the insulating film group away from the substrate comprising a plurality of first grooves arranged along a first direction; the first direction intersecting a stacking direction of the multi-layer planarization layer; a reflective layer on a side of the insulating film group away from the substrate and covering sidewalls and a bottom wall of the first grooves; a pixel defining layer on a side of the reflective layer away from the insulating film group and comprising a plurality of pixel openings; each of the plurality of first grooves surrounding one of the pixel openings; and a plurality of first trenches; the first trenches extending through the pixel defining layer to the first planarization layer and between two adjacent first grooves of the plurality of first grooves; wherein the first passivation layer comprises a first pattern comprising a portion extending from sidewalls of the first trenches, the portion of the first pattern extending from the sidewalls of the first trenches being proximate to a surface of the substrate and having a gap between the portion and a bottom of the first trenches. the first planarization layer comprises a second pattern; 2.The display substrate of claim 1, wherein, sidewalls of the first grooves comprise a face of the first pattern; or sidewalls of the first grooves comprise a face of the first pattern and a face of the second pattern. the first passivation layer comprises a plurality of first openings arranged along the first direction, the first openings constituting at least part of the first grooves. 3.The display substrate of claim 2, wherein, in a case where the first openings constitute the first grooves, a dimension of the first passivation layer along a second direction is in a range of 0.5 μm to 1.5 μm, the second direction being the stacking direction of the multi-layer planarization layer. 4.The display substrate of claim 3, wherein, in a case where the first openings constitute part of the first grooves, the first planarization layer comprises a plurality of first sub-grooves connected to the plurality of first openings, the first sub-grooves constituting remaining parts of the first grooves other than the first openings; or 5.The display substrate of claim 3, wherein, the first planarization layer comprises a plurality of second openings connected to the plurality of first openings, the second openings constituting the remaining parts of the first grooves other than the first openings; wherein a bottom surface of the first trench is closer to the substrate than a bottom surface of the first groove. in a case where the first planarization layer comprises the plurality of first sub-grooves, a dimension of the first planarization layer along a second direction is in a range of 1.5 μm to 3.0 μm, the second direction being the stacking direction of the multi-layer planarization layer. 6.The display substrate of claim 5, wherein, the first planarization layer further comprises a plurality of third openings arranged along the first direction, the first pattern and the reflective layer being sequentially stacked on sidewalls and a bottom wall of the third openings. 7.The display substrate of claim 2, wherein, the pixel defining layer further comprises a first portion on a side of the first passivation layer proximate to the substrate; a surface of the first portion proximate to the substrate is flush with the bottom surface of the first trench; an edge portion of the first portion overlaps with an edge portion of the first passivation layer. 8.The display substrate of claim 7, wherein, ​ 9. The display substrate according to one of claims 7 or 8, wherein, The insulating film group further comprises a second planar layer located on a side of the first planar layer distal to the first passivation layer; and the display substrate further comprises a first source-drain metal layer located on a side of the second planar layer distal to the first planar layer. 10.The display substrate of claim 1, wherein, The insulating film group further comprises: a third planar layer located on a side of the first passivation layer distal to the first planar layer, and comprising a plurality of fourth openings arranged along the first direction; the plurality of fourth openings are multiplexed as the plurality of first recesses. 11.The display substrate of claim 10, wherein, The insulating film group further comprises a second planar layer, and the display substrate further comprises a first source-drain metal layer; the second planar layer and the first source-drain metal layer are located between the first planar layer and the third planar layer; the second planar layer is farther away from the substrate than the first source-drain metal layer; a surface of the first source-drain metal layer proximal to the substrate is closer to the substrate than a surface of the first passivation layer proximal to the substrate; The second planar layer further comprises a second portion located on a side of the first passivation layer proximal to the substrate; an edge portion of the second portion overlaps an edge portion of the first passivation layer. 12.The display substrate of claim 10, wherein, Further comprising: a first source-drain metal layer located on a side of the first planar layer proximal to the substrate; a surface of the first source-drain metal layer distal to the substrate is closer to the substrate than a surface of the first trench proximal to the substrate. 13.The display substrate of claim 12, wherein, A normal projection of the first passivation layer on the substrate does not overlap a normal projection of the reflective layer on the substrate; a surface of a portion of the reflective layer covering a bottom wall of the first recess proximal to the substrate is closer to the substrate than a surface of the first passivation layer proximal to the substrate. 14.The display substrate of claim 12, wherein, The reflective layer is in contact with the first passivation layer; the third planar layer further comprises a third portion located on a side of the first passivation layer proximal to the substrate; an edge portion of the third portion overlaps an edge portion of the first passivation layer.

15. The display substrate according to any one of claims 1-14, wherein, The pixel definition layer comprises a fourth portion located on a side of the first passivation layer proximal to the substrate, and a side surface of the fourth portion constitutes part of a sidewall of the first trench.

16. The display substrate according to any one of claims 1, 2, and 7-15, wherein, A portion of the first pattern extending from a sidewall of the first trench has a first distance along a second direction between a surface distal to the substrate and a bottom surface of the first trench; a surface distal to the substrate of the insulating film group has a second distance along the second direction between the surface and a bottom surface of the first recess; wherein the first distance is less than or equal to the second distance; and the second direction is a stacking direction of the multilayer planar layer.

17. A method for manufacturing a display substrate, comprising: forming a substrate; forming an insulating film group on a side of the substrate; the insulating film group comprises a first passivation layer and a multilayer planar layer stacked; the multilayer planar layer comprises a first planar layer; the first passivation layer is located on a side of the first planar layer distal to the substrate and is in contact with the first planar layer; a surface distal to the substrate of the insulating film group comprises a plurality of first recesses arranged along a first direction; the first direction intersects a stacking direction of the multilayer planar layer. forming a reflective layer on a side of the insulating film group distal from the substrate; the reflective layer covers the sidewalls and the bottom wall of the first recesses; forming a pixel defining layer on a side of the reflective layer distal from the substrate; the pixel defining layer comprises a plurality of pixel openings; each of the first recesses surrounds one of the pixel openings; forming a plurality of first trenches, such that the first trenches penetrate the pixel defining layer to the first planar layer; the first trenches are located between two adjacent first recesses among the plurality of first recesses; wherein the first passivation layer comprises a first pattern, the first pattern comprises a portion extending from the sidewall of the first trench, and the portion of the first pattern extending from the sidewall of the first trench is proximate to the surface of the substrate with a gap between the portion of the first pattern extending from the sidewall of the first trench and the bottom of the first trench.

18. The method of manufacturing the display substrate according to claim 17, wherein, the forming of the insulating film group comprises forming an initial planar layer and forming an initial passivation layer on a side of the initial planar layer distal from the substrate; the forming of the plurality of first trenches comprises patterning the initial passivation layer using an etching process; wherein during the patterning of the initial passivation layer, the etching parameters are controlled such that a portion of the initial planar layer proximate to the initial passivation layer is removed to form the portion of the first trench located on the side of the first passivation layer proximate to the substrate, and to form the gap between the portion of the first pattern extending from the sidewall of the first trench and the bottom of the first trench.

19. A display panel comprising a plurality of light emitting devices and the display substrate of any one of claims 1-16, the light emitting devices being located in one of the pixel openings.

20. The display panel of claim 19, wherein, the light emitting device comprises: at least two light emitting layers; and a charge generation unit located between two adjacent light emitting layers; wherein the charge generation units of the plurality of light emitting devices are of the same layer and material, and constitute a common unit; the common unit comprises a fifth portion and a sixth portion, the fifth portion is located on one side of the portion of the first pattern extending from the sidewall of the first trench along a second direction; the sixth portion is located within the first trench and on one side of the first pattern along the second direction; the second direction is the stacking direction of the plurality of planar layers; wherein along the second direction, there is a spacing between the fifth portion and the sixth portion.

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