Interposer fortified OTP encryption method providing economical shannon perfect secrecy

Abstract

Embodiments of the disclosed technology generally include systems and methods for achieving Shannon Perfect Secrecy in a significantly more compact way, thereby making its unbreakable characteristic significantly more economical, hence accessible, to the global cryptography community.

Description

[0001] INTERPOSER FORTIFIED OTP ENCRYPTION METHOD PROVIDING ECONOMICAL SHANNON PERFECT SECRECY

[0002] Cross Reference to Related Applications

[0003] The present application claims priority to U. S. Provisional Application No. 63 / 667,322, entitled “INTERPOSER FORTIFIED OTP ENCRYPTION METHOD PROVIDING ECONOMICAL SHANNON PERFECT SECRECY”, and filed on July 3, 2024. The entire contents of the above-listed application are hereby incorporated by reference for all purposes.

[0004] Background and Summary

[0005] Practicing cryptographers skilled in the art have long appreciated Shannon Perfect Secrecy as an accepted method to realize unbreakable data encryption. First proven cryptographically unbreakable by Claude Shamion in the late 1940s, the encryption method is popularly referred to as the One Time Pad (OTP) encryption method.

[0006] With OTP. a first plaintext bit sequence needing encryption is XORed with a second bit sequence to produce a third encrypted, ciphertext bit sequence. Simplistically. this third ciphertext bit sequence is said to enjoy Shannon Perfect Secrecy if and only if (1) the first and second bit sequences are of equal length. (2) The second bit sequence is never reused in whole or in part to produce another ciphertext sequence, (3) the second bit sequence is kept secret, and (4) the second bit sequence is truly random.

[0007] In theory, OTP provides an excellent method to produce unbreakable cyphertext bit sequences. Unfortunately, while in theory, theory' and practice are the same, in practice, they are not.

[0008] Consider that decrypting such encrypted bit sequences requires using, hence keeping and hiding, the second encry pting bit sequence. Practicing cry ptographers skilled in the art usually consider this impractical as a consequence of the storage and administrative costs required to keep and hide the encrypting bit sequences that are as large as the encrypted bit sequences they help to produce.

[0009] The disclosed technology generally teaches a way to achieve Shamion Perfect Secrecy in a significantly more compact way, thereby making its unbreakable characteristic significantly more economical, hence accessible, to the global cryptography community .

[0010] Brief Description of the Drawings

[0011] Fig. 1 depicts an ordinary, conceptual processing system configuration comprising a standard processor-based host system with an optionally connected Graphics Processing Unit (GPU) system. The GPU may or may not reside in the same physical cabinet as the standard processor system. These commonplace systems are familiar to practitioners skilled in the art.

[0012] Fig. 2 depicts a standard bit-by-bit XOR operation involving two equal length random bit sequences that produces a third random bit sequence of the same length. This operation is familiar to practitioners skilled in the art. Each of the two equal length random bit sequences engaged in the bitwise XOR process may a be True Random bit sequence or an algorithmically generated Pseudo Random bit sequence. Any Pseudo Random Bit sequence referenced in this teaching is preferably, but not necessarily, computationally indistinguishable from a true Random Number bit sequence. Hereafter, both a True Random bit sequence and a Pseudo Random bit sequence will be referred to as a Random Bit Sequence (RBS).

[0013] Fig. 3 depicts an ordinary' OTP encryption process known to cryptographers skilled in the art.

[0014] Fig. 4 teaches that two unequal length RBSs can be XORed together by first repeatedly concatenating the shorter RBS to itself to create an extended-length, no-longer-random, bit sequence which is XORed to the original, second, longer RBS. The resulting composite bit sequence created is a RBS because the longer RBS in the XOR operation remains random, though what it is XORed with is not random as a consequence to repeated concatenation process.

[0015] Fig. 5 depicts an example method of the disclosed technology to achieve Interposer Fortified OTP Encryption Providing Practical Shannon Perfect Secrecy.

[0016] Detailed Description

[0017] Fig. 1 depicts an ordinary', conceptual processing system 100 configuration comprising a standard processor-based host system 110 with a multiplicity of optionally connected Graphics Processing Unit (GPUs) devices 150. These commonplace processing systems 100 are familiar to practitioners skilled in the art.

[0018] The multiplicity' of host system 110 host processor(s) 120 each contain a multiplicity' of processing cores. Any present GPU device(s) 150 may or may not reside in the same physical cabinet as the standard processor host system 110.

[0019] In Fig. 1, the host system 110 contains a multiplicity of host processors 120 and a host memory means 130 that intcrcomrcct using a memory' channel 140. If a GPU dcvicc(s) 150 is present, the host system 110 and the GPU device(s) 150 interconnect using a high -bandwidth memory' channel interconnect 190.

[0020] As is appreciated by practitioners skilled in the art, GPU device(s) 150 contains a multiplicity of processing cores 160 that access programming instructions and programming data host system 110 loads into GPU device memory 170 before the GPU cores 160 can begin processing. Processing cores 160 connect to GPU device memory' 170 via a high speed memory interconnect 180. All these concepts are familiar to practitioners skilled in the art.

[0021] Fig. 2 illustrates a standard bit sequence bit-wise XOR operation known to practitioners skilled in the art. RBS A 200 is XORed 220 to an equal length RBS B 210 on a bit-wise basis. This operation produces composite RBS C 230. Both RBS A 200 RBS B 210 can be true random bit sequences or algorithmically generated pseudo random number bit sequences. Any Pseudo Random Bit sequence referenced in this teaching is preferably computationally indistinguishable from a True Random Number bit sequence. Hereafter, both a True Pseudo Random Number bit sequence and a Pseudo Random Number bit sequence will be referred to as a Random Bit Sequence (RBS).

[0022] Fig. 3 depicts an ordinary OTP encryption process known to cryptographers skilled in the art. A plaintext bit sequence 300 needing encr ption is XORed bit-by-bit, byte, byte-byte, etc. with a second bit sequence 310. Simply speaking, the resulting ciphertext bit sequence 330 is said to enjoy Shannon Perfect Secrecy if and only if (1) plaintext sequence 300 and second bit sequence 310 are of equal length, (2) The second bit sequence 310 is never reused in whole or in part to produce another ciphertext sequence, (3) the second bit sequence 310 is kept secret, and (4) the second bit sequence 310 is a truly random bit sequence.

[0023] We now consider the advantages of creating a composite RBS 420 from two unequal length bit sequences 200 and 410 where one bit sequence 200 can be, and preferably is, is significantly shorter, but different, than the second bit sequence 410.

[0024] Fig. 4 teaches that two unequal length RBSs 200 and 410 can be XORed together to create a third composite RBS 420 by first repeatedly concatenating the shorter RBS 200 to itself to create an extended-length, no-longer-random, bit sequence 400 which is XORed to the original, longer RBS 410. The resulting composite bit sequence 420 created is an RBS because the longer RBS 410 remains random, though what it is XORed with is not random as a consequence of the repeated RBS 200 concatenation. This is a consequence of each RBS 200 instance in bit sequence 400 XORing with a portion of the authentic RBS 410. This makes composite bit sequence 420 a RBS. However, RBS 200 and RBS 410 should never be combined again as a pair because that would produce an identical composite RBS 420 which should never be reused to encrypt a subsequent plaintext sequence 500.

[0025] Fig. 5 illustrates one non-restricting example embodiment that reveals how to apply the previous teachings in a novel way to achieve a non-restricting compact Shannon Perfect Secrecy using GPU based OTP encry ption. Other processing hardware environments are similarly possible including multi -thread processing within single and multi-proccssor cores systems with and without using core affinity assignment methods. The scope of this convention is meant to include all such environments.

[0026] Fig. 5 depicts how GPU cores 160 perform a non-restricting, example OTP embodiment encryption. Using NVIDIA® CUDA® programming familiar to practitioners skilled in the art, host system 110 loads GPU Device(s) Memory 170 with plaintext data bit sequence 500; a small RBS 510 called an Interposer, a reusable, independent, and very large substrate RBS 520; and launches a kernel program 550 using a single dimension GPU device(s) 150 grid. Each kernel program 550 processing thread first individually determines which thread it is using Eq. 1: int i = threadldx.x + blockldx.x * blockDim.x; (Eq. 1)

[0027] The individual kernel thread then processes one 8-bit plaintext 500 byte using Eq. 2:

[0028] Threadldi Computation: c, = p, (i = 1 to n) (Eq. 2) where c, is an individual ciphertext byte placed in its corresponding offset position in Generated Ciphertext Bit Sequence buffer 530. Processing continues until all threads complete and host system 110 and GPU Device(s) 150 synchronize.

[0029] Practitioners skilled in the art appreciate that the p tenn XOR operation is not necessarily restricted to EQ. 2. For example, as a first non-restricting example, the encryption process could use the thread ID value to identify a sampling method to curate a multiplicity of bytes from both the Interposer and the substrate RBSs at some calculated offset(s) and use the curated values to XOR with the pi term.

[0030] As a second non-restricting example, consider the encryption algorithm encrypting four plaintext bytes at a time. The afore mentioned curation method could sample 8 bytes from each of the interposer and substrate RBSs at some calculated offset(s) to construct two independent 8-byte RBSs.

[0031] Next, the curation method could XOr the two 8-byte values together to construct an intermediate 8-byte value. Following that, the curation method could use any Permuted Congruential Generator (PCG) algorithm to produce a final curated 4-byte RBS which is XORed with the four -byte plaintext RBS it is encrypting.

[0032] Host system 110 then transfers the Generated Cipher bit sequence 530 to host system memory 130 for subsequent disposition.

[0033] There are many disposition means possible. One disposition means may comprise transmitting or passing the generated ciphertext to another processing entity intact, without change.

[0034] Another disposition means may comprise dividing the ciphertext into multiple, mutually exclusive, non-overlapping, collectively exhaustive fragments of any size, and assigning individual fragments to one of a multiplicity scatter gather lists in any order with each scatter-gather list associated with a recipient entity, transmission entity, or storage retention means.

[0035] These storage retention means can be logical or physical storage means, each storage retention means located at different coordinates within a 3D geophysical Cartesian space. Because each such storage retention means has its own scatter gather list performing assigned fragment Vectored IO, the collective multiplicity of scatter gather lists comprise a Vectored-Vectored IO (VVIO) disposition means. It is to be understood that Vectored-Vectored IO provides a measure of plaintext obfuscation and that it is within this invention’s scope.

[0036] In addition, it is to be understood that GPU encryption processing threads can process more than one byte. For example. GPU processing threads can each process four or eight bytes, allowing unlimited types of subsequent permutations of generated thread ciphertext.

[0037] A non-restricting example thread ciphertext permutation would be a pseudo random size. 32- bit circular bit shift operation. With such circular bit shifts occurring on 32-bit boundaries, the initially generated thread generated ciphertext is no longer byte aligned. Allowing VVIO fragmentation to occur on bye boundaries therefore likely causes consequent 32-bit thread ciphertext fractionation across storage retention means located at different coordinates within a 3D geophysical Cartesian space.

[0038] It is to be understood that including the I,mod M addend in the XOR process emulates the concatenation process illustrated in Fig. 4 without requiring construction of, or transfer of, bit sequence 400 for placement in buffer 510. This significantly reduces data transfer overhead, hence the name Interposer. Moreover, the large substrate bit sequence 520 in GPU Device Memory 170 remains available for further OTP encryption procedures with Interposers that are each different. After the first transfer operation, each subsequent encryption amortizes the initial cost of transferring the large RBS substrate from host system memory 130 to GPU device Memory 170. The only caution is that a subsequent OTB process should not reuse the Interposer value in order to ensure all four Shannon Perfect Secrecy criteria are fulfilled. Specifically, the Interposer and large substrate bit sequence 520 should never be paired and combined again.

[0039] There are many advantages to the disclosed technology. For example, memory transfer overhead between Host memory 130 and GPU Device(s) Memory 150 is significantly reduced. RBS storage retention and RBS administration costs are significantly reduced. Moreover, encryption does not have to be OTP. Rather, it can be a multi-bit carry-less add encryption where the carry-less add bit count can be uniform or variable. In addition, Interposer construction, Identification and substrate RBS identification, construction, and reuse considerations can be a consequence of a Multi Factor Authentication (MFA) directive.

[0040] The decryption means simply reverses the encryption steps.

[0041] It is to be understood this method involving Interposers can be performed on many other type systems with a multiplicity of processing cores and is not restricted to NVIDIA CUDA programmed GPUs. Thus, this example embodiment is not meant to constrain this invention’s scope.

[0042] Examples

[0043] An example may include an interposer fortified One Time Pad (OTP) encry ption method providing practical Shannon Perfect Secrecy, comprising: a host system loading a Graphics Processing Unit (GPU) device memory with a plaintext data bit sequence; the host system loading the GPU device memory with a Random Bit Sequence (RBS) called an Interposer, the host system loading the GPU device memory with a substrate RBS; and the host system launching a kernel program using a singledimension GPU device grid.

[0044] Certain examples may further include wherein each kernel program processing thread first individually determines which thread it is using based on the following equation: int i = threadldx.x + blockldx.x * blockDim.x.

[0045] Certain examples may further include the individual kernel thread processing one 8-bit plaintext byte using the following equation:

[0046] Thresdldj Computation: (i ~ 1 to n) wherein c, is an individual ciphertext byte placed in a corresponding offset position in a Generated Ciphertext Bit Sequence buffer.

[0047] Certain examples may further include processing continuing until all threads complete and the host system and GPU device synchronize.

[0048] Certain examples may further include using the thread ID value to identify a sampling method to curate a multiplicity of bytes from both the Interposer and the substrate RBS at some calculated offset and use the curated values to XOR with the pi term.

[0049] Certain examples may further include sampling 8 bytes from each of the Interposer and substrate RBS at some calculated offset to construct two independent 8-byte RBSs.

[0050] Certain examples may further include XOring the two 8-byte values together to construct an intermediate 8-byte value.

[0051] Certain examples may further include using any Permuted Congruential Generator (PCG) algorithm to produce a final curated 4-byte RBS which is XORed ith the four-byte plaintext RBS it is encrypting.

[0052] Certain examples may further include transferring the generated cipher bit sequence to the host system memory for subsequent disposition.

[0053] Certain examples may further include transmitting or passing the generated ciphertext to another processing entity intact, without change.

[0054] Certain examples may further include dividing the ciphertext into multiple, mutually exclusive, non-overlapping, collectively exhaustive fragments of any size.

[0055] Certain examples may further include assigning individual fragments to one of a multiplicity scatter gather lists in any order with each scatter-gather list associated with a recipient entity, transmission entity, or storage retention means.

[0056] Certain examples may further include the storage retention including logical or phy sical storage means, and each storage retention means is located at different coordinates within a 3D geophysical Cartesian space.

[0057] Certain examples may further include wherein the collective multiplicity of scatter gather lists comprises a Vectored-Vectored IO (VVIO) disposition means that provides a measure of plaintext obfuscation.

[0058] Certain examples may further include using Multi-Factor Authentication (MFA) to indicate how to construct the Interposer.

[0059] Certain examples may further include using Multi-Factor Authentication (MFA) to indicate how to construct the substrate RBS.

[0060] Certain examples may further include multi-core multi-bit encryption using carry-less add encryption performed by using a paired single-use Interposer and a reusable substrate bit sequence.

[0061] Certain examples may further include Interposer and substrate RBS sampling to construct a plaintext encrypting RBS value. Certain embodiments may include one or more non-transitory computer-readable storage media storing executable instructions drat, when executed by one or more processors, cause the one or more processors to perform the OTP encryption method.

[0062] Aspects of the disclosure may operate on particularly created hardware, firmware, digital signal processors, or on a specially programmed computer including a processor operating according to programmed instructions. The terms controller or processor as used herein are intended to include microprocessors, microcomputers, Application Specific Integrated Circuits (ASICs), and dedicated hardware controllers.

[0063] One or more aspects of the disclosure may be embodied in computer-usable data and computerexecutable instructions, such as in one or more program modules, executed by one or more computers (including monitoring modules), or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types when executed by a processor in a computer or other device.

[0064] The computer executable instructions may be stored on a computer readable storage medium such as a hard disk, optical disk, removable storage media, solid state memory. Random Access Memory (RAM), etc. As will be appreciated by one of skill in the art. the functionality of the program modules may be combined or distributed as desired in various aspects. In addition, the functionality may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, FPGA, and the like.

[0065] Particular data structures may be used to more effectively implement one or more aspects of the disclosure, and such data structures are contemplated within the scope of computer executable instructions and computer-usable data described herein.

[0066] The disclosed aspects may be implemented, in some cases, in hardware, firmware, software, or any combination thereof The disclosed aspects may also be implemented as instructions carried by or stored on one or more or computer-readable storage media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product.

[0067] Computer-readable media, as discussed herein, means any media that may be accessed by a computing device. By way of example, and not limitation, computer-readable media may comprise computer storage media and communication media.

[0068] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of any embodiment. As used herein, the singular forms “a.” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0069] It will be further understood that the terms “comprises” and / or “comprising.” when used in the present specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” may include any and all combinations of one or more of the associated listed items.

[0070] The previously described versions of the disclosed subject matter have many advantages that were either described or would be apparent to a person of ordinary skill. Even so, these advantages or features are not required in all versions of the disclosed apparatus, systems, or methods.

[0071] Additionally, this written description makes reference to particular features. It is to be understood that the disclosure in this specification includes all possible combinations of those particular features. Where a particular feature is disclosed in the context of a particular aspect or example, that feature can also be used, to the extent possible, in the context of other aspects and examples.

[0072] Also, when reference is made in this application to a method having two or more defined steps or operations, the defined steps or operations can be carried out in any order or simultaneously, unless the context excludes those possibilities.

[0073] Although specific examples of the invention have been illustrated and described for purposes of illustration, it will be understood that various modifications may be made without departing from the spirit and scope of the invention.

[0074] It will be appreciated to one of ordinary skill in the art that variants of the above-disclosed and other features and functions, or alternatives thereof, may be combined into many other different systems or applications.

[0075] Various presently rmforeseen or unanticipated alternatives, modifications, variations, or improvements therein may be subsequently made by those skilled in the art.

[0076] The following claims particularly point out certain combinations and sub-combinations regarded as novel and non-obvious. These claims may refer to “an” element or “a first” element or the equivalent thereof. Such claims should be understood to include incorporation of one or more such elements, neither requiring nor excluding two or more such elements. Other combinations and subcombinations of the disclosed features, functions, elements, and / or properties may be claimed through amendment of the present claims or through presentation of new claims in this or a related application. Such claims, whether broader, narrower, equal, or different in scope to the original claims, also are regarded as included within the subject matter of the present disclosure.

Claims

Claims1. An interposer fortified One Time Pad (OTP) encryption method providing practical Shannon Perfect Secrecy, comprising: a host system loading a Graphics Processing Unit (GPU) device memory with a plaintext data bit sequence; the host system loading the GPU device memory with a Random Bit Sequence (RBS) called an Interposer, the host system loading the GPU device memory with a substrate RBS; and the host system launching a kernel program using a single-dimension GPU device grid.

2. The OTP encryption method according to claim 1, wherein each kernel program processing thread first individually determines which thread it is using based on the following equation: int i = threadldx.x + blockldx.x * blockDim.x.

3. The OTP encryption method according to claim 2, further comprising the individual kernel thread processing one 8-bit plaintext byte using the following equation:Threadld; Computation: c;= p;@© r>- (1 = 1 to n) wherein c, is an individual ciphertext byte placed in a corresponding offset position in a Generated Ciphertext Bit Sequence buffer.

4. The OTP encryption method according to claim 3, further comprising processing continuing until all threads complete and the host system and GPU device synchronize.

5. The OTP encryption method according to claim 4, further comprising using the thread ID value to identify a sampling method to curate a multiplicity of bytes from both the Interposer and the substrate RBS at some calculated offset and use the curated values to XOR with the p, term.

6. The OTP encryption method according to claim 5, wherein the curation method includes sampling 8 bytes from each of the Interposer and substrate RBS at some calculated offset to construct two independent 8-byte RBSs.

7. The OTP encryption method according to claim 6, wherein the curation method further includes XOring the two 8-byte values together to construct an intermediate 8-byte value.

8. The OTP encry ption method according to claim 7, wherein the curation method further includes using any Permuted Congruential Generator (PCG) algorithm to produce a final curated 4- byte RBS which is XORed with the four-byte plaintext RBS it is encrypting.

9. The OTP encryption method according to claim 8, further comprising transferring the generated cipher bit sequence to the host system memory' for subsequent disposition.

10. The OTP encryption method according to claim 9, wherein the disposition includes transmitting or passing the generated ciphertext to another processing entity intact, without change.

11. The OTP encryption method according to claim 9. wherein the disposition includes dividing the ciphertext into multiple, mutually exclusive, non-overlapping, collectively exhaustive fragments of any size.

12. The OTP encryption method according to claim 11. wherein the disposition further includes assigning individual fragments to one of a multiplicity scatter gather lists in any order with each scatter-gather list associated with a recipient entity, transmission entity, or storage retention means.

13. The OTP encryption method according to claim 12, wherein the storage retention means includes logical or physical storage means, and each storage retention means is located at different coordinates within a 3D geophysical Cartesian space.

14. The OTP encry ption method according to claim 13, yvherein the collective multiplicity of scatter gather lists comprises a Vectored-Vectored IO (VVIO) disposition means that provides a measure of plaintext obfuscation.

15. The OTP encry ption method according to claim 1, further comprising using Multi-Factor Authentication (MFA) to indicate hoyv to construct the Interposer.

16. The OTP encry ption method according to claim 1, further comprising using Multi-Factor Authentication (MFA) to indicate hoyv to construct the substrate RBS.

17. The OTP encryption method according to claim 14, further comprising performing VVIO data disposition to a multiplicity of recipients.

18. The OTP encry ption method according to claim 1, further comprising multi-core multi-bit encryption using carry -less add encryption performed by using a paired single-use Interposer and a reusable substrate bit sequence.

19. The OTP encry ption method according to claim 1, further comprising Interposer and substrate RBS sampling to construct a plaintext encrypting RBS value.

20. One or more non-transitory computer-readable storage media storing executable instructions that, when executed by one or more processors, cause the one or more processors to perform the OTP encryption method according to claim 1.

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