Method for manufacturing mirror-twin-structured integrated capacitor incorporating low-noise and nonlinear-calibration process design

Abstract

Disclosed in the present invention is a method for manufacturing a mirror-twin-structured integrated capacitor incorporating a low-noise and nonlinear-calibration process design. The method comprises the steps of: 1) growing a field oxide layer above a P-type well of an analog integrated circuit; 2) depositing a polycrystalline capacitor lower electrode plate polycrystalline film layer on a field oxide layer above an N-type well, and performing matched implantation doping; 3) growing a capacitor dielectric layer; 4) depositing a polycrystalline capacitor upper electrode plate polycrystalline film layer, and manufacturing a protective film layer and a protective structure. The mirror-twin-structured integrated capacitor incorporating a low-noise and nonlinear-calibration process design comprises a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a low-dielectric-coefficient filling film layer, a metal interconnection film layer, and a passivation layer. The present invention reduces the impact of parasitic capacitance, substrate noise and crosstalk noise, and realizes the low noise characteristic of integrated capacitors.

Description

Low-noise nonlinear calibration process design and manufacturing method of mirror twin integrated capacitors Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, specifically to the design of low-noise nonlinear calibration processes and the manufacturing method of mirror twin integrated capacitors. Background Technology

[0002] The continuous development of "6G" communication technology has placed higher demands on the low noise, precise matching, nonlinear calibration, and dielectric hysteresis characteristics of radio frequency and mixed-mode (such as AD / DA data converters) integrated circuits. At the same time, the accuracy of passive devices integrated in the process technology is becoming increasingly important and has become a decisive factor affecting the final accuracy of circuits and systems.

[0003] With in-depth research into the electrical properties of polycrystalline silicon materials and continuous optimization of carrier transport models in polycrystalline silicon, integrated polycrystalline capacitors, due to their excellent matching characteristics, are widely used in the design of high-performance integrated circuits such as low-offset voltage operational amplifiers, voltage-controlled oscillators, voltage-controlled frequency modulators, and AD / DA data converters, as well as in RF and mixed-signal applications. However, the electrical stress, thermal stress, and hysteresis effects of polycrystalline capacitors exacerbate nonlinear errors and mismatch errors within integrated circuits, severely affecting the signal processing accuracy of integrated circuits.

[0004] On the other hand, Metal-Insulator-Metal and PolySicide-Insulator-Metal capacitor structures are widely used in RF and mixed-signal integrated circuit processes. While these integrated capacitors can improve capacitor nonlinearity by eliminating the polysilicon depletion effect, they are limited by process thermal budgets, resulting in numerous defects in the capacitor dielectric material. This leads to low dielectric strength, high leakage current, and high power consumption, making them particularly unsuitable for special environments such as deep space, deep sea, and polar regions. Furthermore, the second-order voltage coefficient (QVCC) of these integrated capacitor structures is uniform. Due to process errors such as metal sputtering and polysiliconization, the voltage coefficient varies significantly within and between batches. This results in poor precision matching of on-chip integrated capacitors, low uniformity and stability between chips and batches, ultimately severely affecting the precision matching performance of these integrated circuits.

[0005] Simply relying on circuit architecture optimization for calibration techniques is no longer sufficient to meet the linear design requirements of analog and digital signals in precision mixed-signal circuits. Therefore, employing effective integrated polysilicon capacitor nonlinear calibration process design to fundamentally improve key performance characteristics such as capacitor voltage coefficient and temperature coefficient has become a continuous research hotspot in industry and academia, and is also a key focus and challenge for RF and precision mixed-signal integrated circuit process innovation and device structure development.

[0006] Summary of the Invention

[0007] The purpose of this invention is to provide a low-noise nonlinear calibration process design and a method for manufacturing mirror-twin integrated capacitors, comprising the following steps:

[0008] 1) Create trench isolation on the substrate, and then form N-type well regions and P-type well regions;

[0009] 2) The N-type well region and the P-type well region are isolated by field oxygen-stop injection or by tank isolation;

[0010] 3) Deposit a polycrystalline film layer under a P0 Å capacitor in a uniformly flat region of a thick field oxide layer of n kilo Å;

[0011] 4) Adjust the doping concentration and impurity distribution of the polycrystalline film layer of the lower electrode of the capacitor by injecting N-type elements; according to the circuit design requirements, adjust the doping concentration and impurity distribution of the polycrystalline film layer in the twin capacitor cells C1 and C2 regions in the required areas of the polycrystalline film layer of the lower electrode of the capacitor by injecting N-type elements.

[0012] The lower electrode polycrystalline structure of twin capacitor cells C1 and C2 is formed;

[0013] 5) Etch the polycrystalline film layer to form centrosymmetric cells, grow the capacitor dielectric layer of the required thickness according to the process requirements, and fill the gaps between the twin capacitor cells formed in step 4); form the lower electrode protection structure of the capacitor.

[0014] 6) Deposit a P1 angstrom polycrystalline film layer on top of the capacitor dielectric layer and complete N-type element implantation doping;

[0015] 7) Photolithography is used to etch the polycrystalline film layer into centrosymmetric cells corresponding to the lower electrode of the capacitor formed in step 4). This polycrystalline film layer serves as the upper electrode of the polycrystalline capacitor.

[0016] 8) An n-µm thermal oxide layer is grown using a thermal oxidation method; a d1-µm silicon nitride dielectric layer is deposited to form the upper electrode protection structure of the capacitor;

[0017] 9) Complete the base and emitter injection of the bipolar transistor and / or the source and drain injection of the field-effect transistor, and then anneal and activate it;

[0018] 10) Metal silicide exposure etching, sputtering Ti metal thin film, polysilicon of capacitor cells C1 and C2, other exposed silicon, and after metal silicide of polysilicon regions, the unsilicided Ti metal is stripped off;

[0019] 11) Photolithography dielectric layer deposition, reflow filling and planarization, contact hole etching, tungsten plug filling and planarization;

[0020] 12) Interconnect the upper electrode of capacitor cell C1 with the upper electrode of capacitor cell C2; and simultaneously interconnect the lower electrode of capacitor cell C1 with the lower electrode of capacitor cell C2, thus forming a Twin-Combined-Bridge architecture unit.

[0021] Furthermore, when completing the base and emitter injection of bipolar transistors and / or the source and drain injection of field-effect transistors, the polycrystalline film layer of the gate of MOS transistors or the emitter of bipolar transistors does not undergo additional injection doping process adjustments and remains the same as the main process conditions;

[0022] The impurity concentration and interface distribution of the base polycrystalline film in the dedicated polycrystalline film layer of passive devices or the bipolar process are matched by the implantation doping process.

[0023] Capacitor cell C1 polycrystalline film layer implantation dose range 1e 15 cm -2 -1e 16 cm -2 Maintain the subdegenerate state of the polycrystalline film interface;

[0024] The injection dose range of the polycrystalline film layer of the electrode under capacitor cell C2 is >1e. 16 cm -2 Maintaining the degenerate state of the polycrystalline film interface, forming a shared carrier migration mode.

[0025] Furthermore, based on the process flow design, the polycrystalline capacitor electrode polycrystalline thin film is a necessary gate polycrystalline layer for MOS devices, or a polycrystalline layer deposited by a special passive device process.

[0026] Furthermore, the process for creating the trench isolation includes etching and backfilling processes.

[0027] Furthermore, the polycrystalline film layer under the capacitor in step 3) is deposited by low-pressure chemical vapor deposition.

[0028] The polycrystalline film layer in step 7) is deposited by low-pressure chemical vapor deposition.

[0029] Furthermore, methods for implanting doped N-type elements include photolithographic implantation.

[0030] Furthermore, the process of etching the polycrystalline film layer into centrally symmetrical cells to form the lower electrode protection structure of the capacitor includes photolithography.

[0031] Furthermore, when growing the n-angstrom thermal oxide layer, the main process temperature is ≤850℃ and the main process time is ≤30min.

[0032] Furthermore, the processes for completing the base and emitter injection of bipolar transistors and / or the source and drain injection of field-effect transistors include Bipolar, CMOS, or BiCMOS.

[0033] The integrated capacitor based on the low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method is characterized by mainly including a substrate, an isolation trench, an N-type buried layer, a P-type buried layer, an N-type epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a metal silicide film layer, a metal interconnect film layer, and a passivation layer.

[0034] The substrate is located at the bottom; the buried layer is located at the bottom of the epitaxial layer; the well region is located on the surface of the epitaxial layer;

[0035] The N-type trap and the P-type trap are isolated by an isolation trench medium;

[0036] The field oxide layer, sacrificial oxide layer, and gate oxide layer respectively cover different regions of the trap;

[0037] The polycrystalline film layer of the dual polycrystalline capacitor is located above the field oxide layer above the N-well;

[0038] The top and sidewalls of the polycrystalline film are covered with different silicon dioxide and silicon nitride composite dielectric layers and high dielectric coefficient capacitor dielectric layers.

[0039] The low dielectric constant filling film is filled in the region between silicon-metal 1, polycrystalline silicon-metal 1, field oxygen-metal 1 and the multilayer metal.

[0040] The technical advantages of this invention are undeniable. This invention provides a low-noise, low-mismatch nonlinear calibration process design and a method for manufacturing mirror-twin integrated capacitors. It employs a coupled bridge nonlinear calibration process design to achieve integrated polycrystalline capacitor connections. Within the RF and mixed-signal operating voltage range, the voltage coefficient of this integrated capacitor achieves a nonlinear accuracy of <2ppm / V.

[0041] The integrated capacitor nonlinear calibration process design and integration method proposed in this invention achieves high capacitance density of the capacitor while the capacitance density of capacitor cell C1 and capacitor cell C2 are equal, and achieves high dielectric strength, low leakage current and low power consumption of the integrated capacitor.

[0042] The capacitor twin cell doping proposed in this invention achieves mirror characteristics of the second-order voltage coefficient of the capacitor cell, that is, the second-order voltage coefficient QVCC of capacitor cell C1 is <0, while the second-order voltage coefficient QVCC of capacitor cell C2 is >0, ultimately achieving a voltage coefficient of <2ppm / V with precise linearity for the integrated capacitor.

[0043] The coupling-bridging architecture of twin capacitor cells proposed in this invention not only improves intra-chip precision matching but also enhances the uniformity and stability of integrated capacitors between chips and batches. Furthermore, by employing the coupling-bridging architecture proposed in this invention, a high potential is maintained at the upper electrode of the twin polycrystalline capacitor cell, reducing the impact of parasitic capacitance substrate noise and crosstalk noise, thus achieving low-noise characteristics for the integrated capacitor.

[0044] By using the low-noise, low-mismatch, nonlinear calibration process design and mirror twin integrated capacitor of this invention, the matching degree of integrated dual polycrystalline capacitors can be improved from ±0.1% mismatch to an ultra-precise matching level of ±0.0001%. This is applicable to high-precision A / D and D / A converters with resolutions of 20 bits or higher, improving process compatibility and device integration density, reducing the manufacturing cost of precision circuits, and enhancing product market competitiveness. Attached Figure Description

[0045] Figure 1 is a cross-sectional view of the shielding oxide layer grown after completing conventional simulated BiCMOS integrated circuit processes such as buried layer implantation, epitaxial growth, well implantation, annealing, and field oxidation.

[0046] Figure 2 is a cross-sectional view of the lower plate of a dual polycrystalline capacitor after polycrystalline film deposition and doping.

[0047] Figure 3 is a cross-sectional view of the edge protective film of the polycrystalline film layer on the lower electrode of a polycrystalline capacitor.

[0048] Figure 4 is a cross-sectional view of the completed polycrystalline capacitor dielectric layer deposition and exposure etching structure.

[0049] Figure 5 is a magnified cross-sectional view of the edge region of the dual polycrystalline capacitor structure after the subsequent wet etching and oxidation processes were completed using the edge optimization technology.

[0050] Figure 6 is a schematic diagram of the 3D structure after the polycrystalline film layer of the upper plate of the polycrystalline capacitor has been deposited and doped, and then exposed and etched.

[0051] Figure 7 is a schematic diagram of the main device structure of the simulated BiCMOS process before the metal interconnect process: including a polycrystalline emitter vertical bipolar transistor (VNPN), a MOS transistor (NMOS), a precision polycrystalline capacitor (PIP-Capacitor), and a low temperature coefficient polycrystalline resistor (Poly-Resistor).

[0052] Figure 8 shows the main device structure of the simulated BiCMOS process after the two-layer metal interconnect process is completed: including a polycrystalline emitter vertical bipolar transistor (VNPN), a MOS transistor (NMOS), a precision polycrystalline capacitor (PIP-Capacitor), and a low temperature coefficient polycrystalline resistor (Poly-Resistor).

[0053] Figure 9 is a schematic diagram of the simulated BiCMOS integrated precision polycrystalline capacitor structure of Example 12;

[0054] In the figure, 101 is an isolation trench (optional); 102 is an N-type well region (preferred); 103 is a LOCOS field oxide layer; 104 is a lower polycrystalline film layer; 105 is a capacitor dielectric layer; 106 is the upper electrode of the polycrystalline capacitor; 201 is an interlayer ILD dielectric planarization layer between polycrystalline silicon / field oxide and metal 1; 202 is a tungsten plug structure for contact holes between the polycrystalline capacitor electrode and metal 1; 203 is a metal layer 1 structure region; 204 is a multilayer metal interlayer IMD dielectric planarization layer; 205 is a multilayer metal interlayer via tungsten plug structure region; and 206 is the top metal layer region. Detailed Implementation

[0055] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.

[0056] Example 1:

[0057] Referring to Figures 1 to 9, the low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method include the following steps:

[0058] 1) Create trench isolation on the substrate, and then form N-type well regions and P-type well regions;

[0059] 2) The N-type well region and the P-type well region are isolated by field oxygen-stop injection or by tank isolation;

[0060] 3) Deposit a polycrystalline film layer 104 under a P0 angstrom capacitor in a uniformly flat region of a thick field oxide layer of n kilo-angstrom;

[0061] 4) Adjust the doping concentration and impurity distribution of the polycrystalline film layer of the lower electrode of the capacitor by injecting N-type elements; according to the circuit design requirements, adjust the doping concentration and impurity distribution of the polycrystalline film layer in the twin capacitor cells C1 and C2 regions in the required areas of the polycrystalline film layer of the lower electrode of the capacitor by injecting N-type elements.

[0062] The lower electrode polycrystalline structure of twin capacitor cells C1 and C2 is formed;

[0063] 5) Etch the polycrystalline film layer to form centrosymmetric cells, grow the capacitor dielectric layer 105 of the required thickness according to the process requirements, and fill the gaps between the twin capacitor cells formed in step 4); to form the protective structure of the lower electrode plate 106 of the capacitor.

[0064] 6) Deposit a P1 angstrom polycrystalline film layer on top of the capacitor dielectric layer and complete N-type element implantation doping;

[0065] 7) Photolithography is used to etch the polycrystalline film layer into centrosymmetric cells corresponding to the lower electrode of the capacitor formed in step 4). This polycrystalline film layer serves as the upper electrode 106 of the polycrystalline capacitor.

[0066] 8) An n-µm thermal oxide layer is grown using a thermal oxidation method; a d1-µm silicon nitride dielectric layer is deposited to form the upper electrode protection structure of the capacitor;

[0067] 9) Complete the base and emitter injection of the bipolar transistor and / or the source and drain injection of the field-effect transistor, and then anneal and activate it;

[0068] 10) Metal silicide exposure etching, sputtering Ti metal thin film, polysilicon of capacitor cells C1 and C2, other exposed silicon, and after metal silicide of polysilicon regions, the unsilicided Ti metal is stripped off;

[0069] 11) Photolithography dielectric layer deposition, reflow filling and planarization, contact hole etching, tungsten plug filling and planarization;

[0070] 12) Interconnect the upper electrode of capacitor cell C1 with the upper electrode of capacitor cell C2; and simultaneously interconnect the lower electrode of capacitor cell C1 with the lower electrode of capacitor cell C2, thus forming a Twin-Combined-Bridge architecture unit.

[0071] When completing the base and emitter implantation of bipolar transistors and / or the source and drain implantation of field-effect transistors, the polycrystalline film layer of the gate of MOS transistors or the emitter of bipolar transistors does not require additional implantation doping process adjustments and remains the same as the main process conditions.

[0072] The impurity concentration and interface distribution of the base polycrystalline film in the dedicated polycrystalline film layer of passive devices or the bipolar process are matched by the implantation doping process.

[0073] Capacitor cell C1 polycrystalline film layer implantation dose range 1e 15 cm -2 -1e 16 cm -2 Maintain the subdegenerate state of the polycrystalline film interface;

[0074] The injection dose range of the polycrystalline film layer of the electrode under capacitor cell C2 is >1e. 16 cm -2 Maintaining the degenerate state of the polycrystalline film interface, forming a shared carrier migration mode.

[0075] Based on the process flow, the polycrystalline capacitor electrode is designed and integrated. The polycrystalline thin film is a necessary gate polycrystalline material for MOS devices, or a polycrystalline layer deposited by special passive device processes.

[0076] The process of creating the trench isolation includes etching and backfilling.

[0077] The polycrystalline film layer under the capacitor in step 3) is deposited by low-pressure chemical vapor deposition.

[0078] The polycrystalline film layer in step 7) is deposited by low-pressure chemical vapor deposition.

[0079] Methods for implanting N-type doped elements include photolithographic implantation.

[0080] The process of etching polycrystalline films into centrally symmetrical cells to form the lower electrode protection structure of a capacitor includes photolithography.

[0081] When growing an n angstrom thermal oxide layer, the main process temperature is ≤850℃ and the main process time is ≤30min.

[0082] The processes for completing base and emitter injection in bipolar transistors and / or source and drain injection in field-effect transistors include Bipolar, CMOS, or BiCMOS.

[0083] Example 2:

[0084] A low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method includes the following steps:

[0085] 1) Create trench isolation on the substrate, and then form N-type well regions and P-type well regions;

[0086] 2) The N-type well region and the P-type well region are isolated by field oxygen-stop injection or by tank isolation;

[0087] 3) Deposit a polycrystalline film layer under a P0 Å capacitor in a uniformly flat region of a thick field oxide layer of n kilo Å;

[0088] 4) Adjust the doping concentration and impurity distribution of the polycrystalline film layer of the lower electrode of the capacitor by injecting N-type elements; according to the circuit design requirements, adjust the doping concentration and impurity distribution of the polycrystalline film layer in the twin capacitor cells C1 and C2 regions in the required areas of the polycrystalline film layer of the lower electrode of the capacitor by injecting N-type elements.

[0089] The lower electrode polycrystalline structure of twin capacitor cells C1 and C2 is formed;

[0090] 5) Etch the polycrystalline film layer to form centrosymmetric cells, grow the capacitor dielectric layer of the required thickness according to the process requirements, and fill the gaps between the twin capacitor cells formed in step 4); form the lower electrode protection structure of the capacitor.

[0091] 6) Deposit a P1 angstrom polycrystalline film layer on top of the capacitor dielectric layer and complete N-type element implantation doping;

[0092] 7) Photolithography is used to etch the polycrystalline film layer into centrosymmetric cells corresponding to the lower electrode of the capacitor formed in step 4). This polycrystalline film layer serves as the upper electrode of the polycrystalline capacitor.

[0093] 8) An n-µm thermal oxide layer is grown using a thermal oxidation method; a d1-µm silicon nitride dielectric layer is deposited to form the upper electrode protection structure of the capacitor;

[0094] 9) Complete the base and emitter injection of the bipolar transistor and / or the source and drain injection of the field-effect transistor, and then anneal and activate it;

[0095] 10) Metal silicide exposure etching, sputtering Ti metal thin film, polysilicon of capacitor cells C1 and C2, other exposed silicon, and after metal silicide of polysilicon regions, the unsilicided Ti metal is stripped off;

[0096] 11) Photolithography dielectric layer deposition, reflow filling and planarization, contact hole etching, tungsten plug filling and planarization;

[0097] 12) Interconnect the upper electrode of capacitor cell C1 with the upper electrode of capacitor cell C2; and simultaneously interconnect the lower electrode of capacitor cell C1 with the lower electrode of capacitor cell C2, thus forming a Twin-Combined-Bridge architecture unit.

[0098] Example 3:

[0099] The low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method are the same as in Example 2. Furthermore, when completing the injection of the base region and emitter region of the bipolar transistor and / or the source and drain of the field-effect transistor, the polycrystalline film layer of the gate of the MOS transistor or the emitter of the bipolar transistor is not adjusted by additional injection doping process and is kept the same as the main process conditions.

[0100] The impurity concentration and interface distribution of the base polycrystalline film in the dedicated polycrystalline film layer of passive devices or the bipolar process are matched by the implantation doping process.

[0101] Capacitor cell C1 polycrystalline film layer implantation dose range 1e 15 cm -2 -1e 16 cm -2 Maintain the subdegenerate state of the polycrystalline film interface;

[0102] The injection dose range of the polycrystalline film layer of the electrode under capacitor cell C2 is >1e. 16 cm -2 Maintaining the degenerate state of the polycrystalline film interface, forming a shared carrier migration mode.

[0103] Example 4:

[0104] The low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method are the same as any one of Examples 2-3. Furthermore, according to the process flow, the integrated polycrystalline capacitor electrode polycrystalline thin film is a gate polycrystalline material required for MOS devices, or a polycrystalline layer deposited by a special passive device process.

[0105] Example 5:

[0106] The low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method are the same as any one of Examples 2-4. Furthermore, the process for fabricating the trench isolation includes etching and backfilling processes.

[0107] Example 6:

[0108] The low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method are the same as any one of Examples 2-5. Further, in step 3), the lower electrode polycrystalline film layer of the capacitor is deposited by low-pressure chemical vapor deposition.

[0109] The polycrystalline film layer in step 7) is deposited by low-pressure chemical vapor deposition.

[0110] Example 7:

[0111] The low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method are the same as any one of Examples 2-6. Furthermore, the method of implanting doped N-type elements includes photolithographic implantation.

[0112] Example 8:

[0113] The low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method are the same as any one of Examples 2-7. Furthermore, the process of etching the polycrystalline film layer into centrally symmetrical cells to form the lower electrode protection structure of the capacitor includes photolithography.

[0114] Example 9:

[0115] The low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method are the same as any one of Examples 2-8. Further, when growing the n angstrom thermal oxide layer, the main process temperature is ≤850℃ and the main process time is ≤30min.

[0116] Example 10:

[0117] The low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method are the same as any one of Examples 2-9. Furthermore, the process for completing the injection of the base region and emitter region of the bipolar transistor and / or the source and drain injection of the field-effect transistor includes Bipolar, CMOS or BiCMOS.

[0118] Example 11:

[0119] An integrated capacitor based on the low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method described in any one of Examples 1-10 is characterized in that it mainly includes a substrate, an isolation trench 101, an N-type buried layer, a P-type buried layer, an N-type epitaxial layer, an N-type well 102, a P-type well, a LOCOS field oxide layer 103, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a metal silicide film layer, a metal interconnect film layer, and a passivation layer.

[0120] The substrate is located at the bottom; the buried layer is located at the bottom of the epitaxial layer; the well region is located on the surface of the epitaxial layer;

[0121] The N-type trap and the P-type trap are isolated by an isolation trench medium;

[0122] The field oxide layer, sacrificial oxide layer, and gate oxide layer respectively cover different regions of the trap;

[0123] The polycrystalline film layer of the dual polycrystalline capacitor is located above the field oxide layer above the N-well;

[0124] The top surface and sidewalls of the polycrystalline film are covered with different silicon dioxide and silicon nitride composite dielectric layers 106 and high dielectric coefficient capacitor dielectric layers.

[0125] The low dielectric constant filling film layer fills the region between the silicon-metal layer 1, the polysilicon-metal layer 1, the field oxide-metal layer 1, and the multilayer metal, including the polysilicon / field oxide-metal 1 interlayer ILD dielectric planarization layer 201 and the multilayer metal interlayer IMD dielectric planarization layer 204. The metal layer 1 structural region is marked as 203.

[0126] A polycrystalline capacitor electrode-metal 1 interlayer contact hole tungsten plug structure 202 is formed between the polycrystalline capacitor electrode-metal 1 interlayer, and a multilayer metal interlayer through hole tungsten plug structure region 205 is formed between the multilayer metals, and the top metal layer region of the integrated capacitor is marked as 206.

[0127] Example 12:

[0128] The method for implementing low-noise, low-mismatch, nonlinear calibration process design and mirror-twin integrated capacitor manufacturing in simulated BiCMOS integrated circuit technology mainly includes the following steps:

[0129] 1) Forming N-type buried layers and P-type buried layers on the substrate, followed by N-type epitaxial growth.

[0130] 2) Form N-type wells, P-type wells, and vertical NPN bipolar transistor collector N+ injection on the epitaxial layer and complete well push-in junction;

[0131] For SOI technology, after the epitaxial layer growth is completed, a trench isolation process is used to form a fully dielectric isolation region.

[0132] 3) Perform P-type injection of the base region of the vertical NPN Bipolar transistor in the N-type well;

[0133] 4) Deposit a silicon nitride thin film, expose and etch away the silicon nitride film layer outside the active device area, and grow a field oxide layer of m angstroms using a thermal oxidation process;

[0134] 5) A P1 angstrom polycrystalline film is deposited above the field oxide layer using low-pressure chemical vapor deposition, and N-type photolithography implantation doping is performed according to the capacitor performance requirements. This polycrystalline film can serve as the lower electrode of a polycrystalline capacitor;

[0135] Depositing a polycrystalline film layer on the lower electrode of a polycrystalline capacitor on the field oxide layer above a P-type well surrounded by a dielectric isolation trench can reduce the influence of parasitic capacitance and substrate noise, and improve the linearity of the polycrystalline capacitor.

[0136] 6) An n-angstrom thermal oxide layer was grown using a thermo-oxidative process.

[0137] The thermal oxidation process has a main process temperature of ≤850℃ and a main process time of ≤30min, which is beneficial for process compatibility and reduces the impact on analog BiCMOS integrated circuit main process devices.

[0138] 7) Based on the circuit design, the doping concentration and impurity distribution of the polycrystalline film layer of the lower electrode of capacitor cell C1 are adjusted by injecting N-type doping elements; based on the circuit design, the doping concentration and impurity distribution of the polycrystalline film layer of the lower electrode of capacitor cell C2 are adjusted by injecting N-type doping elements.

[0139] First, N-type doping was simultaneously injected into the polycrystalline film layers of capacitor cells C1 and C2 to adjust the doping concentration of the polycrystalline film layers. Then, N-type doping was injected again into the polycrystalline film layer of the lower electrode of capacitor cell C2 to adjust the doping concentration and impurity distribution of the polycrystalline film layers.

[0140] 8) Use photolithography to etch centrosymmetric cells into the polycrystalline film layer; grow a silicon dioxide-silicon nitride-silicon dioxide dielectric layer of the required thickness according to process requirements, and fill the cell gaps formed in 7); use photolithography to form the lower electrode protection structure of the capacitor.

[0141] High dielectric films can be selected for capacitor dielectric layers to increase the unit capacitance of double polycrystalline capacitors.

[0142] 9) Complete normal process steps such as sacrificial oxidation, trench implantation, exposure etching, and gate oxide oxidation before gate polysilicon deposition of simulated BiCMOS integrated circuits;

[0143] 10) A P2 Å MOS transistor gate polycrystalline film was deposited using low-pressure chemical vapor deposition, and polycrystalline doping of the MOS transistor gate was completed according to the performance requirements of the MOS device.

[0144] 11) Next, complete the source / drain injection of MOS transistors and emitter injection of Bipolar transistors in a normal analog BiCMOS integrated circuit, and then anneal and activate them;

[0145] The gate polycrystalline film layer of MOS transistors or the emitter polycrystalline film layer of bipolar transistors are kept the same as the main process conditions without any additional implantation doping process adjustments.

[0146] An implantation doping process is used to match the impurity concentration and interface distribution of the base polycrystalline film in specialized polycrystalline passive devices or dual polycrystalline bipolar processes.

[0147] The injection dose range for the polycrystalline film layer of the electrode under capacitor cell C1 is 3e. 15 cm -2 -1e 16 cm -2 Maintain the subdegenerate state of the polycrystalline film interface;

[0148] The injection dose range of the polycrystalline film layer of the electrode under capacitor cell C2 is >1e. 16 cm -2 Maintaining the degenerate state of the polycrystalline film interface and forming a shared carrier migration mode;

[0149] 12) Metal silicide exposure etching, sputtering Ti metal thin film. After metal silicideing of polysilicon in capacitor cells C1 and C2 and other exposed silicon and polysilicon regions, the unsilicided Ti metal is stripped off.

[0150] 13) Normal processes such as photolithography dielectric layer deposition, reflow filling and planarization, contact hole etching, tungsten plug filling and planarization;

[0151] 14) Interconnect the upper electrode of capacitor cell C1 with the upper electrode of capacitor cell C2; and simultaneously interconnect the lower electrode of capacitor cell C1 with the lower electrode of capacitor cell C2, thus forming a Twin-Combined-Bridge architecture unit.

[0152] Maintaining the same shape and area for capacitor cells Cn can reduce the impact of process errors on the nonlinear mismatch of the capacitor.

[0153] For processes where metallization is not suitable, the upper electrode of capacitor cell C11 can be metal-interconnected with the lower electrode of capacitor cell C12; simultaneously, the lower electrode of capacitor cell C11 can be metal-interconnected with the upper electrode of capacitor cell C12, ultimately forming a metal-silicon-free Combined-Bridge architecture unit. This improves the intra-chip matching and inter-chip and batch uniformity of the integrated capacitor in capacitor cell C1. Capacitor cell C2 can also adopt a similar coupling-bridging method.

[0154] Example 13:

[0155] For analog BiCMOS integrated circuit technology, after completing processes such as N-type buried layer, P-type buried layer, epitaxial growth, isolation trench technology, N-well injection and push-in, P-well injection and push-in, and field oxide layer growth, precision polycrystalline capacitors are integrated and fabricated.

[0156] 1) The gate polycrystalline film layer of the MOS transistor is used as the lower plate polycrystalline film layer of the polycrystalline capacitor without any additional adjustment to the implantation doping process, keeping it the same as the main process conditions.

[0157] 2) Deposit the polycrystalline film layer on the upper electrode of the dual polycrystalline capacitor, and complete doping, exposure, and etching to form the upper electrode structure of the polycrystalline capacitor.

[0158] For polycrystalline emitter bipolar transistors, an external emitter polycrystalline film layer can be used as the upper electrode of a polycrystalline capacitor, simplifying the process steps.

[0159] Subsequent steps will employ a standard analog BiCMOS integrated circuit process:

[0160] Example 14:

[0161] For analog BiCMOS / Bipolar integrated circuit technology integrating self-aligned dual polycrystalline Bipolar transistors, after completing processes such as N-type buried layer, P-type buried layer, epitaxial growth, isolation trench process, N-well injection and push-in, P-well injection and push-in, and field oxide layer growth, precision polycrystalline capacitors are integrated and fabricated.

[0162] 1) The outer base region polycrystalline layer is used as the lower electrode polycrystalline film layer of the polycrystalline capacitor, and the polycrystalline electrode matching implantation doping adjustment is adopted as described in Example 1.

[0163] The injection dose range for the polycrystalline film layer of the electrode under capacitor cell C1 is 1e15cm. -2 --1e16cm -2 Maintain the subdegenerate state of the polycrystalline film interface;

[0164] The injection dose range of the polycrystalline film layer of the electrode under capacitor cell C2 is >1e16cm. -2 1) Maintain the degenerate state of the polycrystalline film interface and form a common migration mode of charge carriers; 2) Use the external emitter polycrystalline film as the upper plate of the polycrystalline capacitor. The edge effect of the polycrystalline film on the upper plate of the polycrystalline capacitor can be optimized by the dielectric reflow filling after the emitter polycrystalline film is etched.

[0165] The subsequent steps are the same as the simulated BiCMOS integrated circuit process scheme in Example 12.

Claims

1. A method for designing low-noise nonlinear calibration processes and manufacturing mirror-twin integrated capacitors, characterized in that, Includes the following steps: 1) Create trench isolation on the substrate, and then form N-type well regions and P-type well regions. 2) The N-type well region and the P-type well region are isolated by field oxygen-stop injection or by tank isolation; 3) Deposit a polycrystalline film layer under a P0 Å capacitor in a uniformly flat region of a thick field oxide layer of n kilo Å; 4) Adjust the doping concentration and impurity distribution of the polycrystalline film layer of the lower electrode of the capacitor by injecting N-type elements; according to the circuit design requirements, adjust the doping concentration and impurity distribution of the polycrystalline film layer in the twin capacitor cells C1 and C2 regions in the required areas of the polycrystalline film layer of the lower electrode of the capacitor by injecting N-type elements. The lower electrode polycrystalline structure of twin capacitor cells C1 and C2 is formed; 5) Etch the polycrystalline film layer to form centrosymmetric cells, grow the capacitor dielectric layer of the required thickness according to the process requirements, and fill the gaps between the twin capacitor cells formed in step 4); form the lower electrode protection structure of the capacitor. 6) Deposit a P1 angstrom polycrystalline film layer on top of the capacitor dielectric layer and complete N-type element implantation doping; 7) Photolithography is used to etch the polycrystalline film layer into centrosymmetric cells corresponding to the lower electrode of the capacitor formed in step 4). This polycrystalline film layer serves as the upper electrode of the polycrystalline capacitor. 8) An n-µm thermal oxide layer is grown using a thermal oxidation method; a d1-µm silicon nitride dielectric layer is deposited to form the upper electrode protection structure of the capacitor; 9) Complete the base and emitter injection of the bipolar transistor and / or the source and drain injection of the field-effect transistor, and then anneal and activate it; 10) Metal silicide exposure etching, sputtering Ti metal thin film, polysilicon of capacitor cells C1 and C2, other exposed silicon, and after metal silicide of polysilicon regions, the unsilicided Ti metal is stripped off; 11) Photolithography dielectric layer deposition, reflow filling and planarization, contact hole etching, tungsten plug filling and planarization; 12) Interconnect the upper electrode of capacitor cell C1 with the upper electrode of capacitor cell C2; and simultaneously interconnect the lower electrode of capacitor cell C1 with the lower electrode of capacitor cell C2, thus forming a Twin-Combined-Bridge architecture unit.

2. The method for designing low-noise nonlinear calibration processes and manufacturing mirror-twin integrated capacitors according to claim 1, characterized in that, When completing the base and emitter implantation of bipolar transistors and / or the source and drain implantation of field-effect transistors, the polycrystalline film layer of the gate of MOS transistors or the emitter of bipolar transistors does not require additional implantation doping process adjustments and remains the same as the main process conditions. The impurity concentration and interface distribution of the base polycrystalline film in the dedicated polycrystalline film layer of passive devices or the bipolar process are matched by the implantation doping process. Capacitor cell C1 polycrystalline film layer implantation dose range 1e 15 cm -2 -1e 16 cm -2 Maintain the subdegenerate state of the polycrystalline film interface; The injection dose range of the polycrystalline film layer of the electrode under capacitor cell C2 is >1e. 16 cm -2 Maintaining the degenerate state of the polycrystalline film interface, forming a shared carrier migration mode.

3. The method for designing low-noise nonlinear calibration processes and manufacturing mirror-twin integrated capacitors according to claim 1, characterized in that: Based on the process flow, the polycrystalline capacitor electrode is designed and integrated. The polycrystalline thin film is a necessary gate polycrystalline material for MOS devices, or a polycrystalline layer deposited by special passive device processes.

4. The method for designing low-noise nonlinear calibration processes and manufacturing mirror-twin integrated capacitors according to claim 1, characterized in that: The process of creating the trench isolation includes etching and backfilling.

5. The method for designing low-noise nonlinear calibration processes and manufacturing mirror-twin integrated capacitors according to claim 1, characterized in that: The polycrystalline film layer under the capacitor in step 3) is deposited by low-pressure chemical vapor deposition. The polycrystalline film layer in step 7) is deposited by low-pressure chemical vapor deposition.

6. The method for designing low-noise nonlinear calibration processes and manufacturing mirror-twin integrated capacitors according to claim 1, characterized in that: Methods for implanting N-type doped elements include photolithographic implantation.

7. The method for designing low-noise nonlinear calibration processes and manufacturing mirror-twin integrated capacitors according to claim 1, characterized in that: The process of etching polycrystalline films into centrally symmetrical cells to form the lower electrode protection structure of a capacitor includes photolithography.

8. The method for designing low-noise nonlinear calibration processes and manufacturing mirror-twin integrated capacitors according to claim 1, characterized in that: When growing an n angstrom thermal oxide layer, the main process temperature is ≤850℃ and the main process time is ≤30min.

9. The method for designing low-noise nonlinear calibration processes and manufacturing mirror-twin integrated capacitors according to claim 1, characterized in that: The processes for completing base and emitter injection in bipolar transistors and / or source and drain injection in field-effect transistors include Bipolar, CMOS, or BiCMOS.

10. An integrated capacitor based on the low-noise nonlinear calibration process design and mirror twin integrated capacitor manufacturing method according to any one of claims 1 to 9, characterized in that: It mainly includes substrate, isolation trench, N-type buried layer, P-type buried layer, N-type epitaxial layer, N-type well, P-type well, field oxide layer, sacrificial oxide layer, gate oxide layer, polycrystalline thin film layer, silicon dioxide dielectric layer, silicon oxynitride dielectric layer, metal silicide film layer, metal interconnect film layer, and passivation layer. The substrate is located at the bottom; the buried layer is located at the bottom of the epitaxial layer; the well region is located on the surface of the epitaxial layer; The N-type trap and the P-type trap are isolated by an isolation trench medium; The field oxide layer, sacrificial oxide layer, and gate oxide layer respectively cover different regions of the trap; The polycrystalline film layer of the dual polycrystalline capacitor is located above the field oxide layer above the N-well; The top and sidewalls of the polycrystalline film are covered with different silicon dioxide and silicon nitride composite dielectric layers and high dielectric coefficient capacitor dielectric layers. The low dielectric constant filling film is filled in the region between silicon-metal 1, polycrystalline silicon-metal 1, field oxygen-metal 1 and the multilayer metal.

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