Host interconnection access method, system and apparatus, computer device and storage medium

Abstract

A host interconnection access method, system and apparatus, a computer device and a non-volatile readable storage medium. The method comprises: sending an access request to a memory node, and using a preset decoder in the memory node to decode the access request, so as to obtain request information (S801); sending the request information to a second host (S802); if the request information returned by the second host is received, sending the returned request information to a first host, so as to indicate that the first host cannot access the second host (S803); if a permission message is received from the second host, parsing the permission message to obtain permission information (S804); and sending the permission information to the first host, so as to instruct the first host to use a first memory in the first host to receive a memory resource mapped from a second memory in the second host, so as to access the second host (S805). The method solves the problems that the lack of a mechanism for fast access between hosts limits the performance of heterogeneous computing and affects the flexibility and cost of CXL usage.

Description

Host interconnection access method, system, device, computer equipment and storage medium

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411000729.9, filed on July 24, 2024, and entitled "Host interconnection access method, system, device, computer equipment and storage medium", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of servers, and specifically relates to a host interconnection access method, system, device, computer equipment and non-volatile readable storage medium. BACKGROUND

[0004] Currently, the CXL (Compute Express Link, cache consistency protocol) technology has been extended on heterogeneous computing to exceed the capacity of the full-configuration memory in the previous server architecture. However, in the current memory access and management, it is difficult to realize the interconnection access between hosts, which is not conducive to the management of the entire system data, to some extent, limits the performance of heterogeneous computing, and affects the use flexibility and cost of CXL. In addition, it is difficult for one host to quickly access the data in another host without affecting the operating system of the two hosts, which leads to the inability to free the memory bandwidth and CPU (Central Processing Unit, CPU) cycle of the host, and the inability to improve the performance of the application system on the host.

[0005] Therefore, the related technology lacks a mechanism for fast access between hosts, which limits the performance of heterogeneous computing and affects the use flexibility and cost of CXL. SUMMARY

[0006] Therefore, the present application provides a host interconnection access method, system, device, computer equipment and non-volatile readable storage medium to solve the problem of lacking a mechanism for fast access between hosts, which limits the performance of heterogeneous computing and affects the use flexibility and cost of CXL.

[0007] In a first aspect, the present application provides a host interconnection access system, which comprises: a computing node, a switching node and a memory node; the computing node comprises a first host and a second host;

[0008] The first host is connected to the switching node, and is configured to send an access request to the switching node;

[0009] The switching node is connected with the memory node, and is configured to transmit the access request to the memory node when the access request is obtained from the first host, decode the access request by using a preset decoder in the memory node to obtain request information and a first target port number;

[0010] The switching node is connected with the second host, and is configured to transmit the request information to the second host through an out port corresponding to the first target port number.

[0011] The second host is configured to return the request information to the switching node, or transmit an allowed message to the switching node.

[0012] The switching node is further configured to transmit the returned request information to the first host to indicate that the first host cannot access the second host, or transmit allowed information in the allowed message to the first host to instruct the first host to receive memory resources mapped from a second memory in the second host by using a first memory in the first host to access the second host, wherein the memory resources are obtained by the memory node from CXL resources of a plurality of hosts in the computing node.

[0013] The host interconnection access system provided in the embodiment decodes the access request of the first host to obtain access information, and transmits the access information to the second host. If the second host returns the access information, it indicates that the second host cannot be accessed. If the second host returns an allowed message, the allowed message is parsed to obtain allowed information, and the allowed information is transmitted to the first host to instruct the first memory in the first host to receive memory resources mapped from the second memory in the second host to access the second host. The hosts do not rely on the internal bus of the processor for mutual access, do not occupy other channels, and the performance of the host system will not be reduced due to the access process. The system memory cost and the access cost between the hosts are reduced without relying on the network card for interconnection access. The problem of lacking a fast access mechanism between the hosts, limiting the performance of the heterogeneous computing, and affecting the use flexibility and cost of CXL is solved.

[0014] In some embodiments, the switching node transmits the allowed information in the allowed message to the first host, including:

[0015] Removing the message source identifier and the message destination identifier in the allowed message to obtain a processed message;

[0016] Obtaining a second target port number from the processed message, and taking preset information in the processed message as the allowed information;

[0017] Transmitting the allowed information to the first host through an out port corresponding to the second target port number.

[0018] In the embodiment, the accept message is parsed to obtain the accept information and the second target port number, so as to facilitate determining the out port of the accept information by using the second target port number, and informing the first host that the second host can be accessed by accessing the memory.

[0019] In some embodiments, the second host returns the request information to the switching node, including:

[0020] Obtaining a first transmission path of the request information;

[0021] Returning the request information to the switching node through the first transmission path;

[0022] The second host sends an accept message to the switching node, including:

[0023] Determining a second transmission path different from the first transmission path;

[0024] Sending the accept message to the switching node through the second transmission path.

[0025] In some embodiments, the switching node is further used for:

[0026] Obtaining CXL resources of a plurality of hosts from a computing node;

[0027] Transmitting the CXL resources to a memory node, converting the CXL resources of the plurality of hosts by the memory node to obtain memory resources, and mapping the memory resources to a common extended memory of the plurality of hosts in the memory node.

[0028] In the embodiment, the switching node transmits the obtained CXL resources to the memory node, and the memory node converts the CXL resources of the plurality of hosts into memory resources, and maps the memory resources to the common extended memory of the plurality of hosts in the memory node, thereby providing a memory resource basis for host interconnection access.

[0029] In some embodiments, before sending the access request to the switching node, the first host is further used for:

[0030] In the case that the first host does not have an address decoder, mapping global integrated storage information in a physical address space to a preset address space, wherein the global integrated storage information is used to determine the first target port number, and the first target port number is used to determine the port of the request information sent to the second host;

[0031] Generating the access request according to the preset address space.

[0032] In the embodiment, the physical address space of the first host is mapped to a preset address space in the case that the first host does not have an address decoder, and an access request is generated according to the preset address space, so that the first target port number is obtained by decoding the access request by using the preset decoder.

[0033] In some embodiments, the second host is further configured to:

[0034] determine the direct-connection memory and the extended memory of the second host;

[0035] determine the second memory that can be mapped in the direct-connection memory and the extended memory, wherein the second memory is used to map the memory resource of the second memory to the first memory in the first host in the case that the second host is accessed by the first host.

[0036] In the embodiment, the second host determines the second memory that can be mapped in the direct-connection memory and the extended memory, so as to map the memory resource of the second memory to the first memory in the first host in the case that the second host is accessed by the first host, and the interconnection access of the hosts is realized.

[0037] In some embodiments, the switching node comprises a CXL switching board, a first preset number of first connectors, a first preset number of first cables, a second preset number of second connectors, and a second preset number of second cables.

[0038] The computing node is connected to the CXL switching board through the first connector and the first cable, and is configured to send the CXL resource of the plurality of hosts in the computing node to the CXL switching board.

[0039] The CXL switching board is connected to the memory node through the second connector and the second cable, and is configured to send the CXL resource to the memory node.

[0040] In some embodiments, the memory node comprises a memory extension controller, a second preset number of memory devices, and a second preset number of third connectors.

[0041] The memory extension controller is connected to the CXL switching board through the third connector and the second cable, and is configured to obtain the CXL resource from the CXL switching board.

[0042] The memory extension controller is connected to the memory device, and is configured to convert the CXL resource into the memory resource in the memory device.

[0043] In the embodiment, the CXL resource is converted into the memory resource in the memory device by the memory extension controller, so as to realize the memory extension for the host in the computing node, and the converted memory resource can be accessed by the host, thereby providing a basis for the interconnection access of the host by the memory.

[0044] In some embodiments, the CXL switch board card and the memory expansion controller are configured to be powered on before the host in the computing node issues a system reset instruction.

[0045] The host is configured to be powered on after the CXL switch board card and the memory expansion controller are powered on.

[0046] In the present embodiment, the power-on sequence of the CXL switch board card, the memory expansion controller and the host is set so that the host interconnection access system works normally, and the memory resources of the host can be expanded while the host interconnection access is implemented.

[0047] In a second aspect, the present application provides a host interconnection access method, the method is applied to a switching node, and the method comprises the following steps:

[0048] In the case that the access request is obtained from the first host, the access request is transmitted to the memory node, the access request is decoded by using a preset decoder in the memory node to obtain request information and a first target port number;

[0049] The request information is sent to the second host through the out port corresponding to the first target port number;

[0050] In the case that the request information returned by the second host is obtained, the request information returned by the second host is sent to the first host to indicate that the first host cannot access the second host;

[0051] In the case that the accept message is obtained from the second host, the accept message is parsed to obtain accept information and a second target port number;

[0052] The accept information is sent to the first host through the out port corresponding to the second target port number, and the first host is instructed to receive the memory resource mapped from the second memory in the second host by using the first memory in the first host to access the second host, wherein the memory resource is obtained by converting the CXL resources of a plurality of hosts by the memory node.

[0053] The host interconnection access method provided in the embodiment decodes the access request of the first host to obtain access information, and sends the access information to the second host. If the second host returns the access information, it indicates that the second host cannot be accessed. If the second host returns an allow message, the allow message is parsed to obtain allow information, which is sent to the first host to instruct the first memory in the first host to receive the memory resource mapped from the second memory in the second host to access the second host. The host-to-host access is realized without relying on the internal bus of the processor, and no other channel is occupied, so the performance of the host system will not be reduced due to the access process. The interconnection access does not rely on the network card, which reduces the cost of system memory and the access cost between hosts. The problem of lacking a fast access mechanism between hosts, limiting the performance of heterogeneous computing, and affecting the use flexibility and cost of CXL is solved.

[0054] In a third aspect, the present application provides a host interconnection access method, the method is applied to a first host, and the method comprises:

[0055] The access request is sent to the switch node through the ingress port of the switch node, and the request information in the access request is sent to the second host by the egress port corresponding to the first target port number through the switch node, wherein the first target port number is obtained by decoding the access request by using a preset decoder in the memory node;

[0056] In the case where the request information returned by the second host is obtained from the switch node, it is determined that the second host cannot be accessed;

[0057] In the case where the allow information is obtained from the switch node, the memory resource mapped from the second memory in the second host is received by the first memory in the first host to access the second host, wherein the memory resource is obtained by converting the CXL resource of the plurality of hosts by the memory node.

[0058] The host interconnection access method provided in the embodiment sends the access request containing the request information to the switch node by the first host, the switch node sends the request information to the second host, if the second host returns the access information, it indicates that the second host cannot be accessed. If the first host receives the allow information, the memory resource mapped from the second memory in the second host is received by the first memory to access the second host. The host-to-host access is realized without relying on the internal bus of the processor, and no other channel is occupied, so the performance of the host system will not be reduced due to the access process. The interconnection access does not rely on the network card, which reduces the cost of system memory and the access cost between hosts. The problem of lacking a fast access mechanism between hosts, limiting the performance of heterogeneous computing, and affecting the use flexibility and cost of CXL is solved.

[0059] In a fourth aspect, the present application provides a host interconnection access method, the method is applied to a second host, and the method comprises the following steps:

[0060] In the case that the request information is obtained from the switching node, it is checked whether the request information is legal;

[0061] In the case that the request information is not legal, the request information is returned to the switching node, and the returned request information is sent to the first host by the switching node to indicate that the first host cannot access the second host;

[0062] In the case that the request information is legal, the request information is converted into an accept message, the accept message is sent to the switching node, and the accept information in the accept message is sent to the first host by the switching node to indicate that the first memory in the first host receives the memory resource mapped from the second memory in the second host to access the second host, wherein the memory resource is obtained by converting the CXL resource of the plurality of hosts by the memory node.

[0063] The host interconnection access method provided in the embodiment can realize the interconnection and access between the hosts without relying on the internal bus of the processor, does not occupy other channels, and does not reduce the performance of the host system due to the access process. The interconnection and access between the hosts do not rely on the network card, thereby reducing the cost of the system memory and the access cost between the hosts. The problem that there is no fast access mechanism between the hosts, the performance of the heterogeneous computing is limited, and the flexibility and cost of the CXL are affected are solved.

[0064] In a fifth aspect, the present application provides a host interconnection access device, the device is deployed in a switching node, and comprises:

[0065] The decoding module is configured to, in the case that the access request is obtained from the first host, transmit the access request to the memory node, decode the access request by using a preset decoder in the memory node to obtain request information and a first target port number;

[0066] The first sending module is configured to send the request information to the second host through an outport corresponding to the first target port number;

[0067] The second sending module is configured to, in the case that the request information returned by the second host is obtained, send the returned request information to the first host to indicate that the first host cannot access the second host;

[0068] The parsing module is configured to, in a case where the accept message is obtained from the second host, parse the accept message to obtain accept information and a second target port number.

[0069] The third sending module is configured to send the accept information to the first host through an egress port corresponding to the second target port number, instruct the first host to receive memory resources mapped from a second memory in the second host by a first memory in the first host, and access the second host, wherein the memory resources are obtained by converting CXL resources of the plurality of hosts by the memory node.

[0070] In a sixth aspect, the present application provides a host interconnection access device, the device is deployed in a first host, and comprises:

[0071] The fourth sending module is configured to send an access request to the switching node through an ingress port of the switching node, and send, by the switching node, request information in the access request to the second host through an egress port corresponding to the first target port number, wherein the first target port number is obtained by decoding the access request by a preset decoder in the memory node.

[0072] The determining module is configured to, in a case where the request information returned by the second host is obtained from the switching node, determine that the second host cannot be accessed.

[0073] The access module is configured to, in a case where the accept information is obtained from the switching node, receive memory resources mapped from a second memory in the second host by a first memory in the first host, and access the second host, wherein the memory resources are obtained by converting CXL resources of the plurality of hosts by the memory node.

[0074] In a seventh aspect, the present application provides a host interconnection access device, the device is deployed in a second host, and comprises:

[0075] The checking module is configured to, in a case where the request information is obtained from the switching node, check whether the request information is legal.

[0076] The information returning module is configured to, in a case where the request information is illegal, return the request information to the switching node, and send, by the switching node, the returned request information to the first host, to instruct the first host that the second host cannot be accessed.

[0077] The fifth sending module is configured to, in a case where the request information is legal, convert the request information into an accept message, send the accept message to the switching node, and send, by the switching node, accept information in the accept message to the first host, to instruct the first host to receive memory resources mapped from a second memory in the second host by a first memory in the first host, and access the second host, wherein the memory resources are obtained by converting CXL resources of the plurality of hosts by the memory node.

[0078] In an eighth aspect, the present application provides a computer device, comprising: a memory and a processor, which are communicatively connected with each other, and the memory stores computer instructions; the processor executes the computer instructions to perform the host interconnection access method in the second aspect or any of the corresponding embodiments thereof, or to perform the host interconnection access method in the third aspect or any of the corresponding embodiments thereof, or to perform the host interconnection access method in the fourth aspect or any of the corresponding embodiments thereof.

[0079] In a ninth aspect, the present application provides a non-volatile readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer execute the host interconnection access method in the second aspect or any of the corresponding embodiments thereof, or to execute the host interconnection access method in the third aspect or any of the corresponding embodiments thereof, or to execute the host interconnection access method in the fourth aspect or any of the corresponding embodiments thereof.

[0080] In a tenth aspect, the present application provides a computer program product, which comprises computer instructions, and the computer instructions are used to make a computer execute the host interconnection access method in the second aspect or any of the corresponding embodiments thereof, or to execute the host interconnection access method in the third aspect or any of the corresponding embodiments thereof, or to execute the host interconnection access method in the fourth aspect or any of the corresponding embodiments thereof. BRIEF DESCRIPTION OF DRAWINGS

[0081] In order to more clearly illustrate the technical solutions in the specific embodiments or the related art of the present application, the drawings needed to be used in the specific embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0082] FIG. 1 is a schematic diagram of realizing host interconnection access by using UPI link according to an embodiment of the present application;

[0083] FIG. 2 is a schematic diagram of realizing host interconnection access by using network card according to an embodiment of the present application;

[0084] FIG. 3 is a schematic diagram of CXL application instance according to an embodiment of the present application;

[0085] FIG. 4 is a node topology diagram of CXL extended memory in a server in a cabinet according to an embodiment of the present application;

[0086] FIG. 5 is a multi-host connection topology diagram of CXL extended memory in a cabinet according to an embodiment of the present application;

[0087] FIG. 6 is a topology diagram for realizing host interconnection access based on CXL Fabric according to an embodiment of the present application;

[0088] FIG. 7 is a schematic diagram for mapping a physical address space to a preset address space according to an embodiment of the present application;

[0089] FIG. 8 is a flowchart of a host interconnection access method applied to a switching node according to an embodiment of the present application;

[0090] FIG. 9 is a flowchart of a host interconnection access method applied to a first host according to an embodiment of the present application;

[0091] FIG. 10 is a flowchart of a host interconnection access method applied to a second host according to an embodiment of the present application;

[0092] FIG. 11 is a structural block diagram of a host interconnection access apparatus deployed at a switching node according to an embodiment of the present application;

[0093] FIG. 12 is a structural block diagram of a host interconnection access apparatus deployed at a first host according to an embodiment of the present application;

[0094] FIG. 13 is a structural block diagram of a host interconnection access apparatus deployed at a second host according to an embodiment of the present application;

[0095] FIG. 14 is a hardware structure diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0096] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0097] Currently, there are two ways to enable mutual access between hosts (HOSTs). As shown in FIG. 1, the HOSTs in multiple computing nodes are connected to multiple DIMM (Dual In-line Memory Module) through a CXL switch processor and a memory expansion controller in the CPU of each HOST for memory expansion, and each HOST is connected to the CPU through a corresponding UPI (Ultra Path Interconnect) CON (Control) link. The connection between multiple HOSTs is generally achieved through a CABLE, and the mutual access between multiple HOSTs is achieved through a UPI link. However, the use of a UPI link for access between HOSTs requires a high-speed connector in the hardware design, and a relatively thick UPI cable is used for interconnection, which has a great limitation in structure and hardware layout and is relatively high in cost. The use of a UPI link for access between HOSTs is strictly dependent on the firmware design of the platform where the CPU is located. The access must be performed by the BMC (Board Management Controller) end to the CPU first, and then the CPU accesses the CPU of the other end HOST through a cable, so that the HOSTs can communicate. The link and protocol of such access are too complex, which limits the access rate and restricts the communication content. As shown in FIG. 2, the CPU in each HOST is connected to multiple DIMM (Dual In-line Memory Module) through a CXL switch processor and a memory expansion controller for memory expansion of the CPU, and the CPU is connected to a PCIE (Peripheral Component Interconnect Express) SLOT (slot). A network card, such as a NIC (Network Interface Card) network card, is inserted into the PCIE SLOT for interconnection and access between HOSTs. However, the use of a network card for access between HOSTs requires the use of an X8 or X16 PCIE external interface, and the access between them is limited by factors such as wiring length, network card performance, network cable type, and signal quality. The use of a network card for access between HOSTs has a great limitation in cost and structure. The server itself needs to be managed externally, so an additional network card needs to be designed, which increases the cost and occupies the space in the chassis. In addition, the memory expansion of the above two methods is limited in the chassis and cannot be truly pooled in the rack or data center.

[0098] Current memory expansion is based on CXL technology, CXL memory channel is the same as PCIE channel, but the protocol is different. Increase remote direct media access (RDMA) technology, use UIO (Unordered Input / Output) information and increase GIM (Global Integrated Memory) function, combined with the memory directly connected to the processor, it can be initially realized that the memory expansion is realized at the same time through the CXL memory channel to access between multiple HOSTs. Fabric is a highly interconnected network architecture that can connect a large number of nodes such as servers, storage devices, accelerators, etc., and provide high-bandwidth, low-latency communication. Fabric architecture is used to meet the communication needs of large-scale data centers and high-performance computing environments, usually including switches, routers and other network devices to form a flexible and scalable communication infrastructure. Figure 3 shows a CXL application example, as shown in Figure 3, different HOSTs are connected together through a CXL switch supporting Fabric, the CPU in each HOST connects multiple DIMMs (Dual In-line Memory Module) supporting GIM function through the memory expansion controller, realizing memory expansion for CPU, and the CPU is connected with local memory (NATIVE DIMM) supporting GIM function, each HOST can access the extended DIMM and directly connected DIMM of other HOSTs through GIM function, whether to map all or part of the memory of the HOST is free to choose.

[0099] Based on the above, all hosts are composed of computing nodes, a CXL switch processor supporting Fabric is used to form a switching node, and a memory expansion controller (MXC processor) is used to manage DIMMs supporting GIM functions to form a memory node. The computing node and the memory node are separately placed in a cabinet, the computing node connects the memory node in the form of BOARD-to-BOARD through MCIO (Multi-Channel I / O), the CXL resources are connected to the switching node, the CXL resources are expanded by the CXL SWITCH processor, and then the CXL resources are converted into standard memory resources by the MXC processor in the memory node or the CXL resources are directly connected to the MXC processor to convert into memory resources. When the devices in the computing node and the memory node have GIM functions, the CXL resources of multiple HOSTs can be interacted in the CXL SWITCH, the memory resources converted after the interaction can map the information in the memory resources in the system, so the information between the HOSTs is shared and can be accessed by other HOSTs when the system calls resources. The switching node uses the Fabric architecture for internal interconnection and management, so that the memory resources in a single CPU DOMAIN can be accessed by the remaining CPUs, the memory resources in the DOMAIN can map data into non-DOMAIN memory, and the non-DOMAIN memory can also access the DOMAIN memory according to the feedback process mechanism, realizing the mutual access mechanism between the CPUs in different HOSTs through the memory, and realizing the interconnection between the HOSTs under a certain access process according to the protocol. It can solve the problems of high cost and limited access of the high-speed channel IPB (inner processor bus) between HOSTs and HOSTs depending on the CPU itself, and solve the problems of unable direct access between HOSTs and HOSTs depending on the network card on multiple computing nodes, occupation of PCIE SLOT and cabinet space, low flexibility and high cost of CXL, so as to realize the interconnection and access of multiple HOSTs, improve the access efficiency and flexibility of the entire server and even data center, and realize the overall memory pooling, and the effect of the dynamic calling characteristics of the memory.

[0100] In the embodiment, a host interconnection and access system is provided, which comprises a computing node, a switching node and a memory node; the computing node comprises a first host and a second host;

[0101] The first host is connected with the switching node, and is configured to send an access request to the switching node;

[0102] The switching node is connected with the memory node, and is configured to, in the case that the access request is obtained from the first host, transmit the access request to the memory node, decode the access request by using a preset decoder in the memory node to obtain request information and a first target port number;

[0103] The switching node is connected with the second host, and is configured to transmit the request information to the second host through an egress port corresponding to the first target port number.

[0104] The second host is configured to return the request information to the switching node, or transmit an allow message to the switching node.

[0105] The switching node is further configured to transmit the returned request information to the first host to instruct the first host that the first host cannot access the second host, or transmit allow information in the allow message to the first host to instruct the first host to receive memory resources mapped from a second memory in the second host by using a first memory in the first host to access the second host, wherein the memory resources are obtained by the memory node from CXL resources of the plurality of hosts in the computing node.

[0106] Specifically, FIG. 4 is a node topology diagram of a server in a cabinet extending memory by CXL. As shown in FIG. 4, the computing node can be a dual-path node or a single-path node, that is, can include one central processor or two central processors. The computing node is connected with the switching node through a plurality of MCIOs. The computing node interfaces out CXL resources through the MCIOs, and transmits the CXL resources to the switching node by using cables (CABLEs). The CXL resources of the plurality of hosts are converged in the switching node. A CXL switch board card of the switching node takes a CXL switch processor (CXL SWITCH) as a core to exchange resources. The switching node exchanges and allocates data, and a physical link of a CXL fabric is generated in the switching node. The switching node is connected with the memory node through a plurality of MCIOs. The CXL switch processor transmits the CXL resources to the memory node through the MCIOs and the CABLEs. A core of the memory node is a memory extension controller (MXC processor). The memory extension controller converts the CXL resources into memory resources in a memory device (DEVICE) supporting a GIM function. The memory resources converted by the GIM function are remotely mapped to the extended memory shared by the hosts, thereby providing a basis for the hosts to access each other.

[0107] The host interconnection access system, for example, the system shown in FIG. 5, includes a computing node, a switching node and a memory node. The computing node includes a first host and a second host. The first host has two central processors, and the second host has two central processors. Each central processor is connected with a plurality of DIMMs as local memories. The computing node is connected with the switching node through a plurality of MCIOs.

[0108] As shown in Figure 6, this embodiment sets a preset decoder in the dynamic random-access memory (DRAM) of the memory node to decode access requests.

[0109] When the first host needs to access the second host, it generates an access request, such as a UIO request. UIOs allow unordered data transmission on the CXL link, allowing packets to be sent and received out of order, as long as they can be correctly reassembled. The first host sends the access request to the switching node via the MCIO of the compute node and the MCIO of the switching node. The physical interface and the ingress port of the switching node then transmit the access request to the CXL switching processor of the switching node. Correspondingly, at the firmware level, the UIO information is sent to the Fabric address range, pointing to the GIM space. When the switching node receives the access request from the first host—that is, when the UIO request information from the first host reaches the ingress port of the CXL SWITCH processor—as shown in Figure 6, the switching node transmits the access request to the memory expansion controller of the memory node. The memory node uses the preset decoder of the DRAM in the memory node to decode the access request. The decoded content includes the request information and the first destination port number, which is the Destination Port ID (DPID) of the specific path in the Fabric.

[0110] The switching node obtains the specified path through the egress port corresponding to the first target port number, and sends the request information to the second host from the specified path. As shown in Figure 6, the specified path includes the physical interface connected to the memory node, the egress port corresponding to the first target port number, the physical interface connected to the switching node and the compute node, the MCIO of the switching node, and the MCIO of the compute node. The request information (UIO REQUEST) is sent to the second host through the specified path.

[0111] After receiving the request information (UIO information), the second host will verify its validity. If the request information is invalid, the second host will not allow the first host to access it and will return the invalid request information. If the request information is valid, the second host will convert the UIO information into an acceptance message through the ingress port of the switching node. The acceptance message is, for example, a PBR (Port Based Routing) message.

[0112] When the switching node receives the request information returned by the second host, it can confirm that the request information is invalid and the first host cannot access the second host. The switching node then sends the returned request information back to the first host, indicating that the first host cannot access the second host. When the switching node receives the grant message, the CXL SWITCH processor in the switching node parses the grant message to obtain the grant information and the second target port number. As shown in Figure 6, the switching node determines the corresponding output port based on the second target port number, determines the path for transmitting the grant information, including the physical interface connecting the switching node to the memory node, the corresponding output port for the second target port number, the physical interface connecting the switching node to the compute node, the MCIO of the switching node, and the MCIO of the compute node. Through this path for transmitting the grant information, the switching node sends the grant information to the first host, indicating that the first host can access the second host by accessing the memory.

[0113] It should be noted that, taking a dual-host system as an example, this system includes a first host and a second host. Here, "HOST" refers to an Operating System (OS). Each domain contains more than one CPU processor. Therefore, a dual-CPU system is the minimum system that supports CXL Fabric for host interconnection and access. Switching nodes utilize the Fabric architecture for internal interconnection and management. All memory in this system supports GIM functionality, allowing the mapping of its own memory resources to the memory of other host domains under CXL Fabric management. Therefore, any CPU's CXL domain memory can receive memory resources mapped from the CXL domain memory of other CPUs, enabling multi-host access via memory interconnection. Here, "HOST DOMAIN" refers to the CXL memory extended from a single CPU, which becomes the HOST DOMAIN CXL memory for that CPU.

[0114] Based on the above, the steps for the first host to access the second host via memory access include: using the first memory in the first host to receive memory resources mapped from the second memory in the second host; the first memory, for example, is the DOMAIN CXL memory under any CPU in the first host; and the second memory, for example, is the DOMAIN CXL memory of the CPU in the second host. Access to the second host is achieved through memory resources.

[0115] The host interconnection access system provided in this embodiment decodes the access request from the first host to obtain access information, and then sends the access information to the second host. If the second host returns the access information, it indicates that access to the second host is unavailable. If the second host returns an acceptance message, the system parses the acceptance message to obtain acceptance information, and sends the acceptance information to the first host, instructing the first memory in the first host to receive the memory resources mapped from the second memory in the second host to access the second host. The hosts do not rely on the processor's internal bus for mutual access, do not occupy other channels, and the performance of the host system is not degraded during the access process. It eliminates the need for network interface cards (NICs) for interconnection access, reducing system memory costs and the cost of interconnection between hosts. It solves the problem of the lack of a fast access mechanism between hosts, which limits the performance of heterogeneous computing and affects the flexibility and cost of CXL usage.

[0116] In some implementations, the switching node sends the permission information in the permission message to the first host, including:

[0117] Remove the message source identifier and message destination identifier from the acceptance message to obtain the processed message;

[0118] Obtain the second destination port number from the processed message, and use the preset information in the processed message as the permission information;

[0119] The permission message is sent to the first host through the outgoing port corresponding to the second target port number.

[0120] Specifically, an acknowledgement message is, for example, a PBR message. After receiving the request information, if the request information is valid, the second host converts the request information into a PBR message through the ingress port and sends the PBR message to the switching node.

[0121] When a PBR message arrives at the SWITCH processor of a switching node, the SWITCH processor will retrieve the message source identifier (Source PBR ID) and message destination identifier (Destination PBR ID) from the message to obtain the processed message.

[0122] The switching node obtains the second destination port number from the processed message and uses the preset information in the processed message as the acceptance information. The preset information is, for example, the Transaction Layer Packet information in the processed message.

[0123] The switching node sends the permission information to the first host through the egress port corresponding to the second target port number.

[0124] In this embodiment, the permission message is parsed to obtain permission information and a second target port number. The second target port number is used to determine the output port for transmitting permission information, and the first host is notified that it can access the second host by accessing memory.

[0125] In some implementations, the second host returns the request information to the switching node, including:

[0126] The first transmission path for obtaining the requested information;

[0127] The request information is returned to the exchange node via the first transmission path;

[0128] The second host sends an acknowledgement message to the switching node, including:

[0129] Determine a second transmission path that is different from the first transmission path;

[0130] The acceptance message is sent to the switching node via the second transmission path.

[0131] Specifically, after receiving the request information, i.e., the UIO information, the second host will verify its validity. If the UIO information is invalid, the second host will return the invalid request information along the original transmission path from which it was sent. Therefore, if the request information is invalid, the first transmission path used by the second host when acquiring the request information will be used to return the request information to the switching node.

[0132] If the request is valid, the second host converts the UIO information into an acceptance message, such as a PBR (Port Based Routing) message, through the ingress port of the switching node. This process should use a second transmission path different from the first transmission path used when the request was transmitted to the second host. Therefore, if the request is valid, the second host determines a second transmission path different from the first transmission path and sends the acceptance message to the switching node through the second transmission path.

[0133] In some implementations, the switching node is also used for:

[0134] Obtain CXL resources from multiple hosts from compute nodes;

[0135] The CXL resources are transferred to the memory nodes, where the CXL resources from multiple hosts are converted into memory resources. These memory resources are then mapped onto the shared extended memory of the multiple hosts within the memory nodes.

[0136] Specifically, as shown in Figure 5, the compute node connects to CXL resources via MCIO, and connects these CXL resources to the switching node via external cable. The switching node obtains CXL resources from multiple hosts from the compute node. The switching node uses the CXL switching processor as its core for resource exchange, performing data exchange and allocation. The physical links of the CXL Fabric are generated at the switching node, and the CXL resources from multiple hosts converge within the switching node. After passing through the CXL switching processor, the CXL resources are transmitted to the memory node via MCIO and cable connections. The memory node is essentially memory in a broad sense, with memory capacity measured in terabytes (TB). The MXC processor in the memory node converts CXL resources into standard memory resources through the GIM function and can perform remote mapping of the extended memory resources to shared extended memory on multiple hosts within the memory node. When the system calls for resources, information is shared between hosts and can be accessed by other hosts, thus providing a foundation for multi-host communication.

[0137] In this embodiment, the switching node transmits the acquired CXL resources to the memory node, which then converts the CXL resources of multiple hosts into memory resources and maps the memory resources onto the shared extended memory of multiple hosts in the memory node, providing a memory resource foundation for host interconnection access.

[0138] In some implementations, the first host is further configured to:

[0139] In the absence of an address decoder on the first host, the globally integrated storage information in the physical address space is mapped to a preset address space. The globally integrated storage information is used to determine the first target port number, and the first target port number is used to determine the port to which the request information is sent to the second host.

[0140] An access request is generated based on the preset address space.

[0141] Specifically, in this embodiment, CXL allows the host or device to implement an address decoder through a private scheme, that is, to decode from the physical address space to obtain the DPID (Destination Port Identifier), so that it is not necessary to use the preset decoder in the memory node for decoding.

[0142] GIM functionality can only complete transactions via UIO; therefore, an access request is a UIO message. CXL allows hosts or other devices to implement an address decoder using a proprietary scheme, that is, to decode from the physical address space to obtain the first destination port number (DPID). If the host has an address decoder, i.e., implements it using a proprietary scheme, it can decode the first destination port number (DPID) from any field in the UIO message. Therefore, when subsequently decoding the access request using the default decoder in the DRAM of the memory node, the default decoder needs to use the host's proprietary algorithm for decoding.

[0143] If the first host does not have an address decoder, meaning it hasn't implemented one using a proprietary solution, when the default decoder in the DRAM of the memory node is used to decode the access request, the default decoder will only decode the first target port number (DPID) from the field corresponding to the default address space, which is the Fabric address space. To enable the default decoder to decode the DPID, the first host needs to map the GIM (Global Integrated Storage) information from the physical address space to the default address space. The GIM information records memory resource information. Therefore, the first host maps the GIM information in the physical address space to the Global Integrated Memory field in the Fabric address space, as shown in Figure 7. The left side of Figure 7 shows the UIO information after mapping, including: Local Other field, Local Memory Mapped Read / Write field, Global Integrated Memory field, Global Fabric-Attached Memory field, Unused field, Local CXL Memory Port X field, ..., Local CXL Memory Port 0 field, Local Memory(direct) field, where X is an integer greater than 0. The unused field, the local CXL memory port X field, ..., the local CXL memory port 0 field, and the local memory (directly connected) field belong to the local memory address space. The global integrated storage field and the global Fabric connection memory field belong to the Fabric address space. In this embodiment, the Fabric address space is divided into multiple segments. The global integrated storage space field contains segments N to M-1, and the global Fabric connection memory space field contains segments 0 to N-1. The specific values ​​of M and N are set according to requirements.

[0144] Additionally, the first host can configure the CXL to MMIO (Memory-Mapped I / O) type, meaning the cache type must be set to Uncacheable. In this case, the first host can generate a UIO message as an access request. When this UIO message arrives at the CXL Switch's Ingress Port, it can be decoded by the default decoder in the DRAM of the memory node to obtain the target-side DPID. The default decoder is the Fabric Address Segment Table (FAST).

[0145] In this embodiment, when the first host does not have an address decoder, the physical address space of the first host is mapped to a preset address space. Based on the preset address space, an access request is generated, which facilitates the subsequent decoding of the access request by the preset decoder to obtain the first target port number.

[0146] In some implementations, the second host is also used for:

[0147] Determine the direct-connect memory and extended memory of the second host;

[0148] In the context of direct-attached memory and extended memory, a mappable second memory is determined, wherein the second memory is used to map the memory resources of the second memory to the first memory in the first host when the second host is accessed by the first host.

[0149] Specifically, in the host interconnect access system, different hosts are connected using CXL switching processors in the switching nodes. The direct-attached memory of a host, as well as the extended memory directly expanded via CXL, can be accessed by other hosts via GIM. A host can freely choose whether to map all or part of its memory. The process for determining mappable memory for a second host is as follows: First, determine all memory of the second host, including direct-attached memory and extended memory. Then, set the mappable second memory among all memory of the second host. When the second host is accessed by the first host, the memory resources of the second memory are mapped to the first memory in the first host. The first memory, for example, is the DOMAIN CXL memory under any CPU in the first host.

[0150] In this embodiment, the second host determines a mappable second memory between direct memory and extended memory, so that when accessed by the first host, the memory resources of the second memory can be mapped to the first memory in the first host, thereby realizing host interconnection access.

[0151] In some implementations, the switching node includes: a CXL switching board, a first preset number of first connectors, a first preset number of first cables, a second preset number of second connectors, and a second preset number of second cables;

[0152] The compute node is connected to the CXL switch board via a first connector and a first cable, and is used to send the CXL resources of multiple hosts in the compute node to the CXL switch board.

[0153] The CXL switchboard connects to the memory node via a second connector and a second cable, and is used to send CXL resources to the memory node.

[0154] Specifically, this embodiment will be described with reference to Figure 5. The switching node includes: a CXL switching board, a first preset number of first connectors, and a first preset number of first cables. The first preset number indicates multiple connectors, and no specific quantity is limited here. The first connector is the MCIO connector connecting the CXL switching board in the switching node to the compute node, and the first cable is the physical cable connecting the CXL switching board in the switching node to the compute node. Additionally, the switching board includes multiple UP interfaces (uplink interfaces), such as UP0, UP1, ... . The UP interfaces are connected to the MCIOs of the compute node via the first connectors and first cables. Furthermore, the connection between the first connector and the UP interface is a physical link of the CXL Fabric, for example: the link between the first MCIO on the left and UP4, the link between the first MCIO on the right and UP3, ... See Figure 5 for details, which will not be repeated here.

[0155] The compute node is connected to the CXL switch board via a first connector and a first cable, and is used to send the CXL resources of multiple hosts in the compute node to the CXL switch board.

[0156] The switching node also includes: a second preset number of second connectors and a second preset number of second cables. The second preset number indicates multiple connectors, and no specific quantity is limited here. The second connectors are the MCIO connectors connecting the CXL switching board in the switching node to the memory node, and the second cables are the physical cables connecting the CXL switching board in the switching node to the memory node. Additionally, the switching board includes multiple DP interfaces (downlink interfaces), which are connected to the MCIO of the memory node via the second connectors and second cables.

[0157] The CXL switchboard connects to the memory node via a second connector and a second cable, and is used to send CXL resources to the memory node.

[0158] In some implementations, the memory node includes: a memory expansion controller, a second preset number of memory devices, and a second preset number of third connectors;

[0159] The memory expansion controller is connected to the CXL switchboard via a third connector and a second cable, and is used to obtain CXL resources from the CXL switchboard.

[0160] The memory expansion controller is connected to the memory device and is used to convert CXL resources into memory resources in the memory device.

[0161] Specifically, this embodiment will be described with reference to Figure 5. The memory node includes a memory expansion controller (MXC processor) and a second preset number of third connectors. The second preset number indicates multiple connectors, and no specific number is limited here. The third connectors are MCIO connectors that connect the memory expansion controller in the memory node to the CXL switching board of the memory node. Figure 5 shows multiple MXC processors, which together constitute the MXC memory expansion board.

[0162] The memory expansion controller connects to the CXL switch board via a third connector and a second cable to obtain CXL resources from the CXL switch board. The CXL switch board will be routed according to the CXL Fabric supported by the SWITCH processor, with consistent uplink and downlink counts. The downlink ports of the CXL switch board in the memory node connect to the MXC processor on the MXC memory expansion board via a second connector, a second cable, and a third connector, transferring CXL resources to the MXC processor.

[0163] As shown in Figure 5, the memory node also includes a second preset number of memory devices, such as 4 DIMMs supporting GIM functionality, where ×4 indicates that the DIMM's bit width is 4 times that of 64 bits. The memory expansion controller is connected to the memory devices, manages the memory devices, and converts CXL resources into standard memory resources within the memory devices.

[0164] In this embodiment, the CXL resources are converted into memory resources in the memory device through the memory expansion controller, enabling memory expansion for the host in the compute node. Furthermore, the converted memory resources can be accessed by the host, providing a foundation for subsequent interconnection access by the host through memory.

[0165] In some implementations, the CXL switchboard and memory expansion controller are configured to power on before the host in the compute node issues a system reset command;

[0166] The host is configured to power on after the CXL switchboard and memory expansion controller have been powered on.

[0167] Specifically, in the host interconnect access system, the system requires the CXL switch board and memory expansion controller (MXC memory expansion board) to be powered on first, followed by the host. The power-on of the CXL switch board and MXC memory expansion board must be completed before the host issues a system reset command. Therefore, the CXL switch board and memory expansion controller are configured to be powered on before the host issues a system reset command in the compute node; the host is configured to be powered on after the CXL switch board and memory expansion controller are powered on.

[0168] This will allow logical training to be performed on the CXL path, enabling the system to function normally, expanding memory resources, and allowing host-to-host access between hosts.

[0169] In this embodiment, the power-on sequence of the CXL switch board, memory expansion controller, and host is set to ensure that the host interconnection access system works normally, enabling host interconnection access while expanding the host's memory resources.

[0170] According to an embodiment of this application, a host interconnection access method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0171] In some embodiments, a host interconnection access method is provided. FIG8 is a flowchart of the host interconnection access method according to an embodiment of the present application. The method is applied to a switching node. As shown in FIG8, the process includes the following steps.

[0172] Step S801: If an access request is obtained from the first host, the access request is transmitted to the memory node, and the access request is decoded using the preset decoder in the memory node to obtain the request information and the first target port number.

[0173] Specifically, Figure 4 shows the node topology of a server within a rack using CXL memory expansion. As shown in Figure 4, compute nodes can be dual-socket or single-socket nodes, meaning they can contain one or two CPUs. Compute nodes connect to switching nodes via multiple MCIOs. Compute nodes expose CXL resources externally via MCIOs and transmit these resources to the switching nodes using cables. CXL resources from multiple hosts converge within the switching nodes. The switching nodes' CXL switching boards, centered around the CXL switch processor, perform resource switching, data exchange, and allocation within the switching nodes. The physical links of the CXL Fabric are generated at the switching nodes. Switching nodes connect to memory nodes via multiple MCIOs. The CXL switch processor transmits CXL resources to the memory nodes via MCIOs and cables. The core of the memory node is the memory expansion controller (MXC processor), which converts CXL resources into memory resources in memory devices supporting GIM functionality. The GIM function remotely maps the memory resources converted from CXL resources to the extended memory shared by this host, thus providing a basis for multiple hosts to access each other.

[0174] As shown in Figure 6, this embodiment sets a preset decoder in the dynamic random access memory (DRAM) of the memory node to decode access requests. When the first host needs to access the second host, it generates an access request, such as a UIO request. UIOs allow unordered data transmission on the CXL link, allowing data packets to be sent and received out of order, as long as they can be correctly reassembled. The first host sends the access request to the switching node via the MCIO of the compute node and the MCIO of the switching node. Then, the access request is transmitted to the CXL switching processor of the switching node via the physical interface and the ingress port of the switching node. Correspondingly, at the firmware level, the UIO information is sent to the Fabric address range, pointing to the GIM space. When a switching node receives an access request from the first host, i.e., when the UIO request information from the first host reaches the Ingress Port of the CXL SWITCH processor, as shown in Figure 6, the switching node transmits the access request to the memory expansion controller of the memory node. The access request is decoded using the preset decoder of the DRAM in the memory node. The decoded content includes the request information and the first destination port number. The first destination port number is the Destination Port ID (DPID) of the specific path in the Fabric.

[0175] In step S802, the request information is sent to the second host through the outgoing port corresponding to the first target port number.

[0176] Specifically, the specified path is obtained through the egress port corresponding to the first target port number, and the request information is sent to the second host from the specified path. As shown in Figure 6, the specified path includes the physical interface connected to the memory node, the egress port corresponding to the first target port number, the physical interface connected to the switching node and the compute node, the MCIO of the switching node, and the MCIO of the compute node. The request information (UIO REQUEST) is sent to the second host through the specified path.

[0177] Step S803: Upon receiving the request information returned by the second host, the returned request information is sent to the first host, indicating that the first host cannot access the second host.

[0178] Specifically, after receiving the request information, i.e., the UIO information, the second host will verify the validity of the request information. If the request information is invalid, the second host will not allow the first host to access it and will return the invalid request information.

[0179] Therefore, when the switching node receives the request information returned by the second host, it can confirm that the request information is invalid and the first host cannot access the second host. The switching node then sends the returned request information back to the first host, indicating that the first host cannot access the second host.

[0180] Step S804: If an acceptance message is obtained from the second host, the acceptance message is parsed to obtain the acceptance information and the second target port number.

[0181] Specifically, if the request information is valid, the second host converts the UIO information into an acceptance message through the ingress port of the switching node. The acceptance message is, for example, a PBR (Port Based Routing) message. When the PBR message arrives at the CXL SWITCH processor in the switching node, the CXL SWITCH processor parses the acceptance message to obtain the acceptance information and the second destination port number.

[0182] Step S805: Send the permission information to the first host through the outgoing port corresponding to the second target port number, instructing the first host to use the first memory in the first host to receive the memory resources mapped from the second memory in the second host in order to access the second host. The memory resources are obtained by the memory node after converting the CXL resources of multiple hosts.

[0183] Specifically, as shown in Figure 6, the switching node determines the corresponding output port based on the second target port number, determines the path for transmitting the permission information, and determines the physical interface connecting the switching node to the memory node, the corresponding output port for the second target port number, the physical interface connecting the switching node to the compute node, the MCIO of the switching node, and the MCIO of the compute node. Through this path for transmitting the permission information, the permission information is sent to the first host, indicating that the first host can access the second host by accessing the memory.

[0184] It should be noted that, taking a dual-host system as an example, this system includes a first host and a second host. Here, "HOST" refers to an OS domain, and each domain contains more than one CPU processor. Therefore, a dual-CPU system is the minimum system that supports CXL Fabric for host interconnection and access. Switching nodes utilize the Fabric architecture for internal interconnection and management. All memory in this system supports GIM functionality, allowing the mapping of its own memory resources to the memory of other host domains (domains) under CXL Fabric management. Therefore, any CPU's CXL domain memory can receive memory resources mapped from the CXL domain memory of other CPUs, enabling multi-host access via memory interconnection. Here, "HOST DOMAIN" refers to the CXL memory extended from a single CPU, which becomes the HOST DOMAIN CXL memory for that CPU.

[0185] Based on the above, the steps for the first host to access the second host via memory access include: using the first memory in the first host to receive memory resources mapped from the second memory in the second host; the first memory, for example, is the DOMAIN CXL memory under any CPU in the first host; and the second memory, for example, is the DOMAIN CXL memory of the CPU in the second host. Access to the second host is achieved through memory resources.

[0186] The host interconnection access method provided in this embodiment decodes the access request from the first host to obtain access information, which is then sent to the second host. If the second host returns the access information, it indicates that access to the second host is unavailable. If the second host returns an acceptance message, the acceptance message is parsed to obtain acceptance information, which is then sent to the first host. This instructs the first host's first memory to receive memory resources mapped from the second host's second memory to access the second host. This method enables hosts to access each other without relying on the processor's internal bus, without occupying other channels, and the host system's performance is not degraded during the access process. It eliminates the need for network interface cards (NICs) for interconnection, reducing system memory costs and the cost of interconnection between hosts. It solves the problem of the lack of a fast access mechanism between hosts, which limits the performance of heterogeneous computing and affects the flexibility and cost of CXL (Computer-Assisted Xenology).

[0187] In some embodiments, another host interconnection access method is provided. FIG9 is a flowchart of a host interconnection access method according to an embodiment of the present application. The method is applied to a switching node. As shown in FIG9, the process includes the following steps.

[0188] Step S901: Send an access request to the switching node through the ingress port of the switching node. The switching node then sends the request information in the access request to the second host through the egress port corresponding to the first target port number. The first target port number is obtained by the switching node after decoding the access request using a preset decoder in the memory node.

[0189] Specifically, when the first host needs to access the second host, it generates an access request, such as a UIO request. The first host sends the access request to the switching node through the MCIO of the compute node and the MCIO of the switching node. Then, the access request is transmitted to the CXL switching processor of the switching node through the physical interface and the ingress port of the switching node. Correspondingly, at the firmware level, the UIO information is sent to the Fabric address range, pointing to the GIM space.

[0190] The switching node transmits the access request to the memory node's memory expansion controller. The memory node uses the preset decoder in the DRAM to decode the access request. The decoded content includes the request information and the first target port number. The specified path is obtained through the egress port corresponding to the first target port number, and the request information is sent to the second host from the specified path.

[0191] Step S902: If the request information returned by the second host is obtained from the exchange node, it is determined that the second host cannot be accessed.

[0192] Specifically, after receiving the request information, i.e., the UIO information, the second host will perform a validity check on the request information. If the UIO information is invalid, the second host will return the invalid request information.

[0193] Therefore, if the switching node receives a rejection message from the second host, it indicates that the request is invalid and the first host cannot access the second host. The switching node will then send the rejection message back to the first host, instructing it that it cannot access the second host. Upon receiving the rejection message from the second host, the first host can confirm that it cannot access the second host.

[0194] Step S903: If permission information is obtained from the exchange node, the memory resources mapped from the second memory in the second host are received using the first memory in the first host to access the second host. The memory resources are obtained by the memory node after converting the CXL resources of multiple hosts.

[0195] Specifically, if the request information is valid, the second host converts the UIO information into an acceptance message, such as a PBR message, through the ingress port of the switching node. When the PBR message arrives at the CXL SWITCH processor in the switching node, the CXL SWITCH processor parses the corresponding acceptance message to obtain the acceptance information and the second destination port number.

[0196] The switching node determines the corresponding output port based on the second target port number, determines the path for transmitting the permission information, and sends the permission information to the first host through the path for transmitting the permission information, indicating that the first host can access the second host by accessing memory.

[0197] The mechanism for multiple hosts to interconnect and access each other via memory is described in the embodiment corresponding to step S405, and will not be repeated here. Based on the above mechanism, the step of the first host accessing the second host by accessing memory includes: using the first memory in the first host to receive memory resources mapped from the second memory in the second host. The first memory is, for example, the DOMAIN CXL memory under any CPU in the first host, and the second memory is, for example, the DOMAIN CXL memory of the CPU in the second host. Access to the second host is achieved through memory resources.

[0198] The host interconnection access method provided in this embodiment involves a first host sending an access request containing request information to a switching node. The switching node then forwards the request information to a second host. If the second host rejects the access request, it indicates that access to the second host is unavailable. If the first host receives an acceptance message, it receives memory resources mapped from the second host's second memory via its first memory to access the second host. This method enables hosts to access each other without relying on the processor's internal bus, without occupying other channels, and the performance of the host system is not degraded during the access process. It eliminates the need for network interface cards (NICs) for interconnection access, reducing system memory costs and the cost of interconnection between hosts. It solves the problem of the lack of a fast access mechanism between hosts, which limits the performance of heterogeneous computing and affects the flexibility and cost of CXL (Computer-Assisted Xenology).

[0199] In some embodiments, a host interconnection access method is provided. FIG10 is a flowchart of a host interconnection access method according to an embodiment of the present application. The method is applied to a second host. As shown in FIG10, the process includes the following steps.

[0200] Step S1001: If the request information is obtained from the exchange node, verify whether the request information is valid.

[0201] Specifically, after receiving the access request from the first host, the switching node transmits the access request to the memory expansion controller of the memory node. The memory node uses the preset decoder in the DRAM to decode the access request, which contains the request information and the first target port number. The specified path is obtained through the egress port corresponding to the first target port number, and the request information is sent to the second host from the specified path.

[0202] After receiving the request information, the second host will verify the validity of the request information.

[0203] In step S1002, if the request information is invalid, the request information is returned to the exchange node, which then sends the returned request information to the first host, indicating that the first host cannot access the second host.

[0204] Specifically, if the request information is invalid, the second host will not allow the first host to access it and will return the invalid request information.

[0205] If the switching node receives a request message returned by the second host indicating that the request message is invalid and the first host cannot access the second host, the switching node will send the returned request message back to the first host, indicating that the first host cannot access the second host.

[0206] Step S1003: If the request information is valid, the request information is converted into an acceptance message and sent to the exchange node. The exchange node then sends the acceptance information in the acceptance message to the first host, instructing the first host to use the first memory in the first host to receive the memory resources mapped from the second memory in the second host in order to access the second host. The memory resources are obtained by the memory node after converting the CXL resources of multiple hosts.

[0207] Specifically, if the request information is valid, the second host converts the UIO information into an acceptance message, such as a PBR message, through the ingress port of the switching node. When the PBR message arrives at the CXL SWITCH processor in the switching node, the CXL SWITCH processor parses the corresponding acceptance message to obtain the acceptance information and the second destination port number.

[0208] The switching node determines the corresponding output port based on the second target port number, determines the path for transmitting the permission information, and sends the permission information to the first host through the path for transmitting the permission information, indicating that the first host can access the second host by accessing memory.

[0209] The mechanism for multiple hosts to interconnect and access each other via memory is described in the embodiment corresponding to step S405, and will not be repeated here. Based on the above mechanism, the steps for the first host to access the second host via memory access include: using the first memory in the first host to receive memory resources mapped from the second memory in the second host. The first memory is, for example, the DOMAIN CXL memory under any CPU in the first host, and the second memory is, for example, the DOMAIN CXL memory of the CPU in the second host. Access to the second host is achieved through memory resources. The steps for the first host to access the second host via memory access include: using the first memory in the first host to receive memory resources mapped from the second memory in the second host. The first memory is, for example, the DOMAIN CXL memory under any CPU in the first host, and the second memory is, for example, the DOMAIN CXL memory of the CPU in the second host. In the above process, the second host needs to map the memory resources in the second memory to the first memory so that the first host can access the second host through memory resources. It should be noted that, as shown in Figure 6, the second host includes local memory. Memory resources in the local memory that do not support GIM and memory resources that only allow local access to memory cannot be mapped to the second memory in the second host.

[0210] The host interconnection access method provided in this embodiment allows the second host to verify access information. If the access information is invalid, the access information is returned, indicating that access to the second host is unavailable. If the access is valid, an acceptance message is returned, instructing the first memory in the first host to receive the memory resources mapped from the second memory in the second host to access the second host. This enables hosts to access each other without relying on the processor's internal bus, without occupying other channels, and the performance of the host system is not degraded during the access process. It eliminates the need for network cards for interconnection access, reducing system memory costs and the cost of interconnection between hosts. It solves the problem of the lack of a fast access mechanism between hosts, which limits the performance of heterogeneous computing and affects the flexibility and cost of CXL usage.

[0211] In some implementations, the memory expansion controller (CXL processor) monitors the operating parameters of the expanded memory in real time. Therefore, the CXL processor can obtain the health status of the expanded memory, assess its operational condition, and determine whether a power outage and memory replacement are necessary. Specifically, this includes:

[0212] Obtain parameter information of a set of operating parameters for each extended memory from the CXL processor to which each extended memory belongs. The operating status information of each extended memory includes parameter information of a set of operating parameters for each extended memory.

[0213] Retrieve mailbox event logs corresponding to each extended memory from the CXL processor to which each extended memory belongs. The running status information of each extended memory includes error records extracted from the mailbox event logs corresponding to each extended memory and associated with the running status of each extended memory.

[0214] The status reference information includes, but is not limited to: parameter information of a set of operating parameters for each extended memory, the operating status information of each extended memory including parameter information of a set of operating parameters for each extended memory, which may include, but is not limited to, status information such as voltage, temperature, and power consumption; and error records extracted from the mailbox event logs corresponding to each extended memory and associated with the operating status of each extended memory.

[0215] The baseboard management controller of the memory resource pool can obtain parameter information of a set of operating parameters for each extended memory from the CXL processor to which each extended memory belongs, and obtain mailbox event logs corresponding to each extended memory from the CXL processor to which each extended memory belongs. For the obtained mailbox event logs corresponding to each extended memory, error records associated with the operating status of each extended memory can be extracted. The status reference information corresponding to each extended memory includes: parameter information of a set of operating parameters for each extended memory, and error records associated with the operating status of each extended memory.

[0216] For example, the BMC of the memory resource pool can collect the memory data transfer status obtained from the MXC in the following ways: The BMC of the memory resource pool can interact with the MXC through I2C (Inter-Integrated Circuit, a communication protocol) commands to obtain the memory's voltage, temperature, power consumption and other status information, and determine its operating health status through thresholds; The BMC of the memory resource pool can also interact with the MXC through I2C commands to obtain the memory's Mailbox Event Records Log, identify Fatal Error, Failure Error and Warning Error in it, and use them to determine the operating health status of the memory.

[0217] The alarm information identified and reported by the host-side BIOS (Basic Input / Output System) can include: Memory errors such as Correctable Error (CE), Uncorrectable Error (UCE), ScrubFail, and Configuration Error, which the host-side BIOS can recognize and report. This information is then communicated to the host-side BMC via the IPMI command `AddSel`. The memory resource pool's BMC then retrieves memory status information (from the BIOS) from each host-side BMC via the network using Redfish commands.

[0218] The memory pool BMC integrates the above three memory health states to judge the memory operating status and determine whether the memory needs to be replaced by power-off.

[0219] This embodiment also provides a host interconnection access device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0220] This embodiment provides a host interconnection access device, which is deployed at a switching node, as shown in Figure 11, and includes:

[0221] The decoding module 1101 is used to transmit the access request to the memory node when the access request is obtained from the first host, and use the preset decoder in the memory node to decode the access request to obtain the request information and the first target port number.

[0222] The first sending module 1102 is used to send the request information to the second host through the output port corresponding to the first target port number;

[0223] The second sending module 1103 is used to send the returned request information to the first host when it receives the request information returned by the second host, indicating that the first host cannot access the second host.

[0224] The parsing module 1104 is used to parse the permission message when a permission message is obtained from the second host, and to obtain the permission information and the second target port number.

[0225] The third sending module 1105 is used to send an acceptance message to the first host through the output port corresponding to the second target port number, instructing the first host to use the first memory in the first host to receive the memory resources mapped from the second memory in the second host in order to access the second host. The memory resources are obtained by the memory node after converting the CXL resources of multiple hosts.

[0226] This embodiment provides a host interconnection access device, which is deployed on a first host, as shown in Figure 12, and includes:

[0227] The fourth sending module 1201 is used to send an access request to the switching node through the ingress port of the switching node, and the switching node sends the request information in the access request to the second host through the egress port corresponding to the first target port number. The first target port number is obtained by the switching node after decoding the access request using a preset decoder in the memory node.

[0228] The determination module 1202 is used to determine that the second host cannot be accessed when the request information returned by the second host is obtained from the switching node;

[0229] Access module 1203 is used to receive memory resources mapped from the second memory in the second host using the first memory in the first host, in order to access the second host, when permission information is obtained from the exchange node. The memory resources are obtained by the memory node after converting the CXL resources of multiple hosts.

[0230] This embodiment provides a host interconnection access device, which is deployed on a second host, as shown in Figure 13, and includes:

[0231] The verification module 1301 is used to verify whether the request information is valid when the request information is obtained from the exchange node;

[0232] The information return module 1302 is used to return the request information to the exchange node when the request information is invalid. The exchange node then sends the returned request information to the first host, indicating that the first host cannot access the second host.

[0233] The fifth sending module 1303 is used to convert the request information into an acceptance message when the request information is valid, and send the acceptance message to the switching node. The switching node then sends the acceptance information in the acceptance message to the first host, instructing the first host to use the first memory in the first host to receive the memory resources mapped from the second memory in the second host in order to access the second host. The memory resources are obtained by the memory node after converting the CXL resources of multiple hosts.

[0234] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0235] In this embodiment, the host interconnection access device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, including a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0236] This application also provides a computer device having the host interconnection access device shown in FIG11, FIG12 or FIG13.

[0237] Please refer to Figure 14, which is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application. As shown in Figure 14, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components communicate with each other using different buses and can be installed on a common motherboard or otherwise as needed. The processor can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, multiple processors and / or multiple buses can be used with multiple memories, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 14 shows an example of a single processor 10.

[0238] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware processor. The hardware processor may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0239] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0240] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0241] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0242] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0243] This application also provides a non-volatile readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the non-volatile readable storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0244] A portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in non-volatile readable storage media include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the non-volatile readable storage medium can be any available non-volatile readable storage medium or communication medium accessible to a computer.

[0245] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A host interconnect access system, characterized by, The system comprises a computing node, a switching node and a memory node; the computing node comprises a first host and a second host; The first host is connected with the switching node and is configured to send an access request to the switching node; The switching node is connected with the memory node and is configured to, in the case that the access request is obtained from the first host, transmit the access request to the memory node, decode the access request by using a preset decoder in the memory node to obtain request information and a first target port number; The switching node is connected with the second host and is configured to send the request information to the second host through an out port corresponding to the first target port number; The second host is configured to return the request information to the switching node or send an allow message to the switching node; The switching node is further configured to send the returned request information to the first host to indicate that the first host cannot access the second host, or send allow information in the allow message to the first host to indicate that the first host receives memory resources mapped from a second memory in the second host by using a first memory in the first host to access the second host, wherein the memory resources are obtained by the memory node converting CXL resources of a plurality of hosts in the computing node.

2. The system of claim 1, wherein, There are two central processing units in the first host and two central processing units in the second host, each of the central processing units is connected with at least two DIMMs as local memories, and the computing node is connected with the switching node through the at least two MCIOs.

3. The system of claim 1, wherein, The switching node sending the allow information in the allow message to the first host comprises: Removing message source identification and message destination identification in the allow message to obtain a processed message; Obtaining a second target port number from the processed message and taking preset information in the processed message as the allow information; Sending the allow information to the first host through an out port corresponding to the second target port number.

4. The system of claim 1, wherein, The second host returning the request information to the switching node comprises: Obtaining a first transmission path of the request information; Returning the request information to the switching node through the first transmission path. The second host sending the allow message to the switching node comprises: Determining a second transmission path different from the first transmission path; Sending the allow message to the switching node through the second transmission path.

5. The system of claim 4, wherein, The second host being configured to return the request information to the switching node or send the allow message to the switching node comprises: After the second host receives the request information, the second host performs legality verification on the request information; If the request information is not legal, the second host returns the illegal request information along the transmission path from which the request information is sent; If the request information is legal, the second host converts the request information into the allow message through an in port of the switching node.

6. The system of claim 1, wherein, The exchange node is further configured to: obtain CXL resources of a plurality of the hosts from the computing node; transmit the CXL resources to a memory node, convert the CXL resources of a plurality of the hosts by the memory node to obtain memory resources, and map the memory resources to a shared extended memory of a plurality of the hosts in the memory node.

7. The system of claim 1, wherein, Before sending the access request to the exchange node, the first host is further configured to: in a case that the first host does not have an address decoder, map global integrated storage information in a physical address space to a preset address space, wherein the global integrated storage information is configured to determine the first target port number, and the first target port number is configured to determine a port for sending the request information to the second host; generate the access request according to the preset address space.

8. The system of claim 1, wherein, The second host is further configured to: determine a direct memory and an extended memory of the second host; determine a second memory that can be mapped in the direct memory and the extended memory, wherein the second memory is configured to map memory resources of the second memory to the first memory in the first host in a case that the second host is accessed by the first host.

9. The system of claim 1, wherein, The exchange node comprises a CXL exchange board, a first preset number of first connectors, a first preset number of first cables, a second preset number of second connectors, and a second preset number of second cables. The computing node is connected to the CXL exchange board through the first connector and the first cable, and is configured to send CXL resources of a plurality of hosts in the computing node to the CXL exchange board. The CXL exchange board is connected to the memory node through the second connector and the second cable, and is configured to send the CXL resources to the memory node.

10. The system of claim 9, wherein, The memory node comprises a memory extension controller, a second preset number of memory devices, and a second preset number of third connectors. The memory extension controller is connected to the CXL exchange board through the third connector and the second cable, and is configured to obtain the CXL resources from the CXL exchange board. The memory extension controller is connected to the memory device, and is configured to convert the CXL resources into memory resources in the memory device.

11. The system of claim 10, wherein: the CXL exchange board and the memory extension controller are configured to be powered on before the host in the computing node issues a system reset instruction; the host is configured to be powered on again after the CXL exchange board and the memory extension controller are powered on.

12. A host interconnect access method, characterized by, The method is applied to an exchange node, and the method comprises: in a case that an access request is obtained from a first host, transmitting the access request to a memory node, decoding the access request by a preset decoder in the memory node to obtain request information and a first target port number; sending the request information to a second host through an out port corresponding to the first target port number. In the case that the request information returned by the second host is obtained, the returned request information is sent to the first host, indicating that the first host cannot access the second host; In the case that the accept message is obtained from the second host, the accept message is parsed to obtain accept information and a second target port number; The accept information is sent to the first host through the egress port corresponding to the second target port number, indicating that the first host receives the memory resource mapped from the second memory in the second host by using the first memory in the first host, to access the second host, wherein the memory resource is obtained by the memory node converting CXL resources of a plurality of hosts.

13. The method of claim 12, wherein, The request information is sent to the second host through the egress port corresponding to the first target port number, including: The request information is sent to the second host from the specified path through the egress port corresponding to the first target port number.

14. A host interconnect access method, characterized by, The method is applied to a first host, and the method includes: An access request is sent to the exchange node through the ingress port of the exchange node, and the request information in the access request is sent to a second host by the exchange node through an egress port corresponding to a first target port number, wherein the first target port number is obtained by the exchange node decoding the access request by using a preset decoder in a memory node; In the case that the request information returned by the second host is obtained from the exchange node, it is determined that the second host cannot be accessed; In the case that accept information is obtained from the exchange node, a memory resource mapped from a second memory in the second host is received by using a first memory in the first host, to access the second host, wherein the memory resource is obtained by the memory node converting CXL resources of a plurality of hosts.

15. A host interconnect access method, characterized by, The method is applied to a second host, and the method includes: In the case that the request information is obtained from the exchange node, it is checked whether the request information is legal; In the case that the request information is not legal, the request information is returned to the exchange node, and the returned request information is sent to the first host by the exchange node, indicating that the first host cannot access the second host; In the case that the request information is legal, the request information is converted into an accept message, and the accept message is sent to the exchange node, and accept information in the accept message is sent to the first host by the exchange node, indicating that the first host receives the memory resource mapped from the second memory in the second host by using the first memory in the first host, to access the second host, wherein the memory resource is obtained by the memory node converting CXL resources of a plurality of hosts.

16. A host interconnect access device, characterized by The device is deployed in an exchange node, and the device includes: A decoding module is configured to, in the case that an access request is obtained from a first host, transmit the access request to a memory node, and decode the access request by using a preset decoder in the memory node to obtain request information and a first target port number; The first sending module is configured to send the request information to the second host through an out port corresponding to the first target port number; The second sending module is configured to send the returned request information to the first host, indicating that the first host cannot access the second host, in the case that the returned request information of the second host is obtained; The parsing module is configured to parse the accept message to obtain accept information and a second target port number in the case that the accept message is obtained from the second host; The third sending module is configured to send the accept information to the first host through an in port corresponding to the second target port number, indicating that the first host receives memory resources mapped from a second memory in the second host by a first memory in the first host to access the second host, wherein the memory resources are obtained by converting CXL resources of a plurality of hosts by a memory node.

17. A host interconnect access device, characterized by The device is deployed on the first host and includes: The fourth sending module is configured to send an access request to the switch node through an in port of the switch node, and send request information in the access request to the second host through an out port corresponding to a first target port number by the switch node, wherein the first target port number is obtained by decoding the access request by a preset decoder in the memory node by the switch node; The determining module is configured to determine that the second host cannot be accessed in the case that the returned request information of the second host is obtained from the switch node; The access module is configured to receive memory resources mapped from a second memory in the second host by a first memory in the first host to access the second host, wherein the memory resources are obtained by converting CXL resources of a plurality of hosts by a memory node.

18. A host interconnect access device, characterized by The device is deployed on the second host and includes: The checking module is configured to check whether the request information is legal in the case that the request information is obtained from the switch node; The information returning module is configured to return the request information to the switch node in the case that the request information is illegal, and send the returned request information to the first host by the switch node, indicating that the first host cannot access the second host; The fifth sending module is configured to convert the request information into an accept message in the case that the request information is legal, and send the accept message to the switch node, and send accept information in the accept message to the first host by the switch node, indicating that the first host receives memory resources mapped from a second memory in the second host by a first memory in the first host to access the second host, wherein the memory resources are obtained by converting CXL resources of a plurality of hosts by a memory node.

19. A computer device, comprising: The device includes: a memory and a processor, which are connected in communication with each other, the memory has stored therein computer instructions, and the processor, by executing the computer instructions, performs the host interconnection access method according to any one of claims 12 to 15.

20. A non-transitory readable storage medium, characterized in that, The non-volatile readable storage medium has stored therein computer instructions, and the computer instructions are configured to cause a computer to perform the host interconnection access method according to any one of claims 12 to 15.

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