Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a substrate (BS) and a plurality of sub-pixels disposed on one side of the substrate (BS); each sub-pixel comprises a pixel driving circuit, and the pixel driving circuit comprises at least one first-type transistor (TL) and at least one second-type transistor (TO); the at least one first-type transistor (TL) includes a driving transistor (T3), and active layers (TOa) of at least some of the second-type transistors (TO) are located on the side of a gate (T3g) of the driving transistor (T3) distant from the substrate (BS); at least some of the second-type transistors (TO) each comprise at least one first-type electrode (Tds), the first-type electrode (Tds) is connected in an overlapping manner to the gate (T3g) of the driving transistor (T3), the at least one first-type electrode (Tds) includes a first electrode or a second electrode of at least one transistor among the at least some of the second-type transistors (TO), and the active layer (TOa) of each second-type transistor (TO) is arranged in the same layer as the first-type electrode (Tds) thereof.

Description

Display substrate and its preparation method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate, including: a substrate and a plurality of sub-pixels disposed on one side of the substrate, at least one sub-pixel including a pixel driving circuit, the at least one pixel driving circuit including at least one first type transistor and at least one second type transistor; the at least one first type transistor includes a driving transistor, and in a direction perpendicular to the plane of the substrate, at least a portion of the active layer of the second type transistor is located on the side of the gate of the driving transistor away from the substrate;

[0006] The at least some of the second type transistors include at least one first type electrode, which is connected to the gate of the driving transistor. The at least one first type electrode includes the first or second electrode of at least one transistor in the at least some of the second type transistors. The active layer of the second type transistor is disposed on the same layer as the first type electrode.

[0007] In an exemplary embodiment, the display substrate is provided with at least one first type of via, at least a portion of the first type of vias correspond one-to-one with at least a portion of the first type of electrodes, and the first type of electrodes are connected to the gate of the driving transistor through the corresponding first type of via.

[0008] In an exemplary embodiment, the display substrate is provided with at least one second type of via, and the pixel driving circuit further includes at least one connection structure. In a direction perpendicular to the plane where the substrate is located, the connection structure is located on the side of the active layer of the second type of transistor away from the substrate.

[0009] The at least one connection structure corresponds one-to-one with at least a portion of the second type of via and at least a portion of the first type of electrode, and the gate of the driving transistor and the corresponding first type of electrode are overlapped and connected to the corresponding connection structure at the corresponding second type of via position.

[0010] In an exemplary embodiment, in the first type of via and the second type of via corresponding to the same first type of electrode, the orthographic projection of the first type of via on the substrate and the orthographic projection of the second type of via on the substrate at least partially overlap.

[0011] In an exemplary embodiment, in the first type of via and the second type of via corresponding to the same first type of electrode, the orthographic projection of the first type of via on the substrate covers the orthographic projection of the corresponding second type of via on the substrate.

[0012] In an exemplary embodiment, the orthographic projection of the first type of electrode on the substrate overlaps the orthographic projection of the corresponding first type of via on the substrate.

[0013] In an exemplary embodiment, the orthographic projection of the first type of electrode on the substrate at least partially overlaps with the orthographic projection of the corresponding first type of via on the substrate, and at least partially does not overlap.

[0014] In an exemplary embodiment, the display substrate is provided with at least one second type of via, and the pixel driving circuit further includes at least one connection structure. In a direction perpendicular to the plane where the substrate is located, the connection structure is located on the side of the active layer of the second type of transistor away from the substrate.

[0015] The at least one connection structure corresponds one-to-one with at least a portion of the second type of vias and at least a portion of the first type of electrodes. The gate of the driving transistor and the corresponding first type of electrode are connected by the corresponding connection structure at the corresponding second type of via position.

[0016] In an exemplary embodiment, at least a portion of the surface of the gate of the driving transistor on the side away from the substrate and the sidewall of the corresponding first type electrode near the corresponding second type via are connected to the corresponding connection structure through the corresponding second type via.

[0017] In an exemplary embodiment, at least a portion of the surface of the gate of the driving transistor on the side away from the substrate, the sidewall of the corresponding first type electrode near the corresponding second type via, and at least a portion of the surface of the corresponding first type electrode on the side away from the substrate are connected to the corresponding connection structure through the corresponding second type via.

[0018] In an exemplary embodiment, the active layer of the first type of transistor is located on a first semiconductor layer, and the active layer of the second type of transistor is located on a second semiconductor layer. In a direction perpendicular to the plane of the substrate, the second semiconductor layer is located on the side of the first semiconductor layer away from the substrate. The at least one second type of transistor includes a first reset transistor and a compensation transistor. The second electrode of the first reset transistor and the first electrode of the compensation transistor are located in the conductor region in the second semiconductor layer.

[0019] The first type of electrode includes the second electrode of the first reset transistor and the first electrode of the compensation transistor. The second electrode of the first reset transistor and the first electrode of the compensation transistor are interconnected and connected to the gate of the driving transistor.

[0020] In an exemplary embodiment, the at least one first type of transistor further includes a first light-emitting control transistor, the active layer of the first light-emitting control transistor being connected to the second electrode of the compensation transistor and the first electrode of the first light-emitting control transistor, the first electrode of the first light-emitting control transistor being located in a conductive region in the second semiconductor layer and interconnected with the second electrode of the compensation transistor.

[0021] In an exemplary embodiment, the display substrate further includes a first initial signal line, which is located on the side of the second semiconductor layer near the substrate in a direction perpendicular to the plane of the substrate. The first electrode of the first reset transistor is connected to the first initial signal line, and the first electrode of the first reset transistor is located in a conductor region in the second semiconductor layer.

[0022] In an exemplary embodiment, the connection structure includes a first connection structure, a second connection structure, and a third connection structure, and the second type of via includes a fifth via, a sixth via, and a seventh via;

[0023] The first connection structure is connected to the first initial signal line and the first electrode of the first reset transistor through the seventh via;

[0024] The second connection structure is connected to the gate of the driving transistor, the second terminal of the first reset transistor, and the first terminal of the compensation transistor through the sixth via.

[0025] The third connection structure is connected to the active layer of the first light-emitting control transistor and the second electrode of the compensation transistor through the fifth via.

[0026] In an exemplary embodiment, the display substrate further includes a first initial signal line, the active layer of the first type of transistor is located on a first semiconductor layer, the active layer of the second type of transistor is located on a second semiconductor layer, and in a direction perpendicular to the plane of the substrate, the second semiconductor layer is located on the side of the first semiconductor layer away from the substrate, and the first initial signal line is located on the side of the second semiconductor layer close to the substrate; the at least one first type of transistor further includes a first light-emitting control transistor, and the at least one second type of transistor includes a first reset transistor and a compensation transistor;

[0027] The first type of electrode includes the second electrode of the first reset transistor and the first electrode of the compensation transistor. The second electrode of the first reset transistor, the first electrode of the compensation transistor, and the first electrode of the first light-emitting control transistor are located in the conductor region in the second semiconductor layer. The second electrode of the first reset transistor and the first electrode of the compensation transistor are interconnected, and the first electrode of the first light-emitting control transistor is interconnected with the second electrode of the compensation transistor.

[0028] The first type of via includes a first via, a second via, and a third via. The first terminal of the first reset transistor is connected to the first initial signal line through the first via. The second terminal of the first reset transistor and the first terminal of the compensation transistor are connected to the gate of the driving transistor through the second via. The second terminal of the compensation transistor and the first terminal of the first light-emitting control transistor are connected to the active layer of the first light-emitting control transistor through the third via.

[0029] Secondly, embodiments of this disclosure provide a display device including the display substrate described in any of the above embodiments.

[0030] Thirdly, embodiments of this disclosure provide a method for preparing a display substrate, comprising:

[0031] Multiple sub-pixels are formed on one side of the substrate. At least one sub-pixel includes a pixel driving circuit, which includes at least one first-type transistor and at least one second-type transistor. The at least one first-type transistor includes a driving transistor. In a direction perpendicular to the plane of the substrate, the active layer of at least a portion of the second-type transistor is located on the side of the driving transistor away from the substrate. The at least a portion of the second-type transistor includes at least one first-type electrode, which is connected to the gate of the driving transistor. The at least one first-type electrode includes a first electrode or a second electrode of at least one transistor in the at least a portion of the second-type transistor. The active layer of the second-type transistor is disposed on the same layer as the first-type electrode.

[0032] In an exemplary embodiment, forming a plurality of sub-pixels on one side of the substrate includes at least:

[0033] A first gate metal layer is formed on one side of the substrate, the first gate metal layer including the gate of the first type of transistor;

[0034] A first interlayer insulating layer is formed on the side of the first gate metal layer away from the substrate. At least one first type of via is provided on the first interlayer insulating layer. The first type of via corresponding to the gate of the driving transistor exposes at least a portion of the surface of the gate of the driving transistor.

[0035] A second semiconductor layer is formed on the side of the first interlayer insulating layer away from the substrate. The second semiconductor layer includes the at least one first type electrode and the active layer of the second type transistor. At least a portion of the first type vias correspond one-to-one with at least a portion of the first type electrodes. The first type electrodes are connected to the gate of the driving transistor through the corresponding first type vias.

[0036] In an exemplary embodiment, after forming the second semiconductor layer on the side of the first interlayer insulating layer away from the substrate, the method further includes:

[0037] A second interlayer insulating layer is formed on the side of the second semiconductor layer away from the substrate. At least one second type of via is provided on the second interlayer insulating layer. The second type of via corresponding to the gate of the driving transistor exposes at least a portion of the surface of the gate of the driving transistor.

[0038] A first source / drain metal layer is formed on the side of the second interlayer insulating layer away from the substrate. The first source / drain metal layer includes at least one connection structure. The at least one connection structure corresponds one-to-one with at least a portion of the second type vias, at least a portion of the first type electrodes, and at least a portion of the second type vias. The gate of the driving transistor and the corresponding first type electrode are connected to the corresponding connection structure at the corresponding second type via position.

[0039] In an exemplary embodiment, after forming the second semiconductor layer on the side of the first interlayer insulating layer away from the substrate and before forming the second interlayer insulating layer on the side of the second semiconductor layer away from the substrate, the method further includes:

[0040] A third gate insulating layer is formed on the side of the second semiconductor layer away from the substrate;

[0041] A third gate metal layer is formed on the side of the third gate insulating layer away from the substrate. The third gate metal layer includes a first gate of the second type of transistor. The orthographic projection of the first gate of the second type of transistor on the substrate at least partially overlaps with the orthographic projection of the active layer of the corresponding second type of transistor on the substrate.

[0042] In an exemplary embodiment, after forming a first gate metal layer on one side of the substrate and before forming a second semiconductor layer on the side of the first interlayer insulating layer away from the substrate, the method further includes:

[0043] A second gate insulating layer is formed on the side of the first gate metal layer away from the substrate;

[0044] A second gate metal layer is formed on the side of the second gate insulating layer away from the substrate, the second gate metal layer including the second gate of the second type of transistor.

[0045] In an exemplary embodiment, forming a plurality of sub-pixels on one side of the substrate includes at least:

[0046] A first gate metal layer is formed on one side of the substrate, the first gate metal layer including the gate of the driving transistor in the at least one pixel driving circuit;

[0047] A second interlayer insulating layer is formed on the side of the first gate metal layer away from the substrate. At least one second type of via is provided on the second interlayer insulating layer. The second type of via corresponding to the gate of the driving transistor exposes at least a portion of the surface of the gate of the driving transistor.

[0048] A first source / drain metal layer is formed on the side of the second interlayer insulating layer away from the substrate. The first source / drain metal layer includes at least one connection structure. The at least one connection structure corresponds one-to-one with at least a portion of the second type vias and at least a portion of the first type electrodes. The gate of the driving transistor and the corresponding first type electrode are connected to the corresponding connection structure at the corresponding second type via position.

[0049] In an exemplary embodiment, after forming a first gate metal layer on one side of the substrate and before forming a second interlayer insulating layer on the side of the first gate metal layer away from the substrate, the method further includes:

[0050] A second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, a second semiconductor layer, a third gate insulating layer, and a third gate metal layer are sequentially formed on the side of the first gate metal layer away from the substrate. The second semiconductor layer includes at least one first type electrode and an active layer of the second type transistor. The second gate metal layer includes a second gate of the second type transistor. The third gate metal layer includes a first gate of the second type transistor. The orthographic projection of the first gate of the second type transistor on the substrate at least partially overlaps the orthographic projection of the corresponding active layer of the second type transistor on the substrate.

[0051] In an exemplary embodiment, after forming the third gate metal layer and before forming the second interlayer insulating layer, the method further includes:

[0052] The region of the second semiconductor layer not blocked by the first gate of the second type of transistor is subjected to a conductor-enhancing process to form a conductor-enhanced region, wherein the conductor-enhanced region in the second semiconductor layer includes at least the at least one first type of electrode.

[0053] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0054] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0055] Figure 1 is a schematic diagram of a display device;

[0056] Figure 2 is a schematic diagram of the planar structure of the display area in a display substrate;

[0057] Figure 3a is an equivalent circuit diagram of a pixel driving circuit;

[0058] Figure 3b is an equivalent circuit diagram of a pixel driving circuit;

[0059] Figure 3c is an equivalent circuit diagram of a pixel driving circuit;

[0060] Figure 4a shows a cross-sectional view of the display substrate provided in an embodiment of this disclosure;

[0061] Figure 4b shows a cross-sectional view of a display substrate provided in an exemplary embodiment of this disclosure;

[0062] Figure 4c shows a cross-sectional view of a display substrate provided in an exemplary embodiment of this disclosure;

[0063] Figure 4d shows a cross-sectional view of a display substrate provided in an exemplary embodiment of this disclosure;

[0064] Figure 4e shows a cross-sectional view of a display substrate provided in an exemplary embodiment of this disclosure;

[0065] Figure 4f shows a cross-sectional view of a display substrate provided in an exemplary embodiment of this disclosure;

[0066] Figure 4g shows a cross-sectional view of a display substrate provided in an exemplary embodiment of this disclosure;

[0067] Figure 4h shows a cross-sectional view of a display substrate provided in an exemplary embodiment of this disclosure;

[0068] Figure 4i shows a cross-sectional structural diagram of a display substrate;

[0069] Figure 4j shows a schematic diagram of the conductor-encapsulation of the second semiconductor layer;

[0070] Figure 5a shows a cross-sectional structural diagram of a display substrate after forming a first type of via according to an exemplary embodiment of the present disclosure;

[0071] Figure 5b shows a cross-sectional structural diagram of a display substrate after the formation of a second semiconductor layer, provided in an exemplary embodiment of the present disclosure.

[0072] Figure 5c shows a cross-sectional structural diagram of a display substrate after the formation of the third gate metal layer, provided in an exemplary embodiment of the present disclosure.

[0073] Figure 5d shows a cross-sectional structural diagram of a display substrate after forming a second interlayer insulating layer, according to an exemplary embodiment of the present disclosure.

[0074] Figure 6a shows a cross-sectional structural diagram of a display substrate after forming a second type of via according to an exemplary embodiment of the present disclosure;

[0075] Figure 6b shows a cross-sectional view of a display substrate after removing the second semiconductor layer in a second type of via according to an exemplary embodiment of the present disclosure.

[0076] Figure 6c shows a schematic diagram of the planar structure in a display substrate provided by an exemplary embodiment of the present disclosure, in which the first connection structure is connected to the first initial signal line and the first pole of the first transistor.

[0077] Figure 6d shows a schematic diagram of the planar structure in a display substrate provided by an exemplary embodiment of the present disclosure, in which the second connection structure overlaps with the gate of the driving transistor and the second electrode of the first transistor.

[0078] Figure 6e shows a schematic diagram of the planar structure in a display substrate provided by an exemplary embodiment of the present disclosure, in which the third connection structure and the active layer of the sixth transistor and the first electrode of the sixth transistor overlap.

[0079] Figure 7 is a schematic cross-sectional view of a display substrate after the formation of the second semiconductor layer, provided in an exemplary embodiment of the present disclosure.

[0080] Figure 8a shows a cross-sectional structure of a display substrate after forming a second type of via according to an exemplary embodiment of the present disclosure;

[0081] Figure 8b shows a cross-sectional view of a display substrate provided in an exemplary embodiment of the present disclosure after the second semiconductor layer in the second type of via is removed.

[0082] Figure 8c shows a schematic diagram of the planar structure in a display substrate provided by an exemplary embodiment of the present disclosure, in which the first connection structure is connected to the first initial signal line and the first pole of the first transistor.

[0083] Figure 8d shows a schematic diagram of the planar structure in a display substrate provided by an exemplary embodiment of the present disclosure, in which the second connection structure overlaps with the gate of the third transistor and the second electrode of the first transistor.

[0084] Figure 8e shows a schematic diagram of the planar structure in a display substrate provided by an exemplary embodiment of the present disclosure, in which the third connection structure and the active layer of the sixth transistor and the first electrode of the sixth transistor overlap.

[0085] Figure 9 is a schematic cross-sectional view of a display substrate after forming a second type of via according to an exemplary embodiment of the present disclosure.

[0086] Figure 10a shows a schematic diagram of the planar structure of a display substrate after the formation of the second gate metal layer, according to an exemplary embodiment of the present disclosure.

[0087] Figure 10b shows a schematic diagram of the planar structure of a display substrate after the formation of the second semiconductor layer, provided in an exemplary embodiment of the present disclosure.

[0088] Figure 10c shows a schematic diagram of the planar structure of a display substrate after the formation of the third gate metal layer, according to an exemplary embodiment of the present disclosure.

[0089] Figure 10d is a schematic diagram of the planar structure of a display substrate after the formation of a second interlayer insulating layer, according to an exemplary embodiment of the present disclosure.

[0090] Figure 10e shows a schematic diagram of the planar structure of a display substrate after the fourth conductive layer is formed, according to an exemplary embodiment of the present disclosure.

[0091] Figure 11a shows a schematic diagram of the planar structure of a display substrate after the formation of a second interlayer insulating layer, according to an exemplary embodiment of the present disclosure.

[0092] Figure 11b shows a schematic diagram of the planar structure of a display substrate after the fourth conductive layer is formed, according to an exemplary embodiment of the present disclosure.

[0093] Figure 12 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0094] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0095] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0096] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0097] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0098] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0099] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0100] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0101] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0102] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0103] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0104] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0105] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0106] Figure 1 shows a schematic diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0107] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 5a, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0108] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0109] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 3a is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 3a, the pixel driving circuit can include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to nine signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, light emission signal line E, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, and second power supply line VSS).

[0110] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C. The third node N3 is connected to the second terminals of the second transistor T2, the second terminals of the third transistor T3, and the first terminal of the sixth transistor T6. The fourth node N4 is connected to the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7.

[0111] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0112] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first terminal of the first transistor T1 is connected to the initial signal line Vinit1, and the second terminal of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the first reset control line Reset1, the first transistor T1 transmits the initial voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0113] The control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the scan signal line Gate, the second transistor T2 causes the control electrode of the third transistor T3 to connect to its second electrode.

[0114] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0115] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scan transistor, etc. When a conduction-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0116] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device EL to emit light.

[0117] The control electrode of the seventh transistor T7 is connected to the second reset control line Reset2, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device EL. When the on-level scan signal is applied to the second reset control line Reset2, the seventh transistor T7 transmits the initial voltage to the first electrode of the light-emitting device EL, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device EL.

[0118] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0119] In an exemplary embodiment, the second electrode of the light-emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0120] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0121] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current, low-frequency drive capability, and low power consumption. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency drive, reducing power consumption, and improving display quality.

[0122] Figure 3b shows the circuit schematic of another LTPO pixel driving circuit. As shown in Figure 3b, the pixel driving circuit can include 9 transistors (first transistor T1 to ninth transistor T9) and 2 storage capacitors (first storage capacitor C1 and second storage capacitor C2). The pixel driving circuit is connected to 12 signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, third reset control line Reset3, light emission signal line E, first initial signal line Vinit1, second initial signal line Vinit2, bias signal line Vbias, reference voltage signal line Vref, first power supply line VDD and second power supply line VSS).

[0123] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. Specifically, the first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the eighth transistor T8, and the second terminal of the fifth transistor T5; the second node N2 is connected to the second terminal of the fourth transistor T4, the second terminal of the ninth transistor T9, the second terminal of the first storage capacitor C1, and the first terminal of the second storage capacitor C2; the third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6; the fourth node N4 is connected to the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7; and the fifth node N5 is connected to the second terminal of the second storage capacitor C2, the control terminal of the third transistor T3, the first terminal of the second transistor T2, and the second terminal of the first transistor T1.

[0124] In an exemplary embodiment, the first end of the first storage capacitor C1 is connected to the first power line VDD, and the second end of the first storage capacitor C1 is connected to the second node N2.

[0125] The first end of the second storage capacitor C2 is connected to the second node N2, and the second end of the second storage capacitor C2 is connected to the fifth node N5.

[0126] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first electrode of the first transistor T1 is connected to the initial signal line Vinit1, and the second electrode of the first transistor is connected to the fifth node N5.

[0127] The control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the fifth node N5, and the second electrode of the second transistor T2 is connected to the third node N3.

[0128] The control electrode of the third transistor T3 is connected to the fifth node N5, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0129] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 can be called a switching transistor, scan transistor, etc. When a conduction-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0130] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device EL to emit light.

[0131] The control electrode of the seventh transistor T7 is connected to the second reset control line Reset2, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode (i.e., the fourth node N4) of the light-emitting device EL. When the on-level scan signal is applied to the second reset control line Reset2, the seventh transistor T7 transmits the initial voltage to the first electrode of the light-emitting device EL to initialize or release the accumulated charge in the first electrode of the light-emitting device EL.

[0132] The control electrode of the eighth transistor T8 is connected to the second reset control line Reset2, the first electrode of the eighth transistor T8 is connected to the bias signal line Vbias, and the second electrode of the eighth transistor T8 is connected to the first node N1.

[0133] The control electrode of the ninth transistor T9 is connected to the third reset control line Reset3, the first electrode of the ninth transistor T9 is connected to the reference voltage signal line Vref, and the second electrode of the ninth transistor T9 is connected to the second node N2.

[0134] In an exemplary embodiment, the eighth transistor T8 and the ninth transistor T9 can be removed from the pixel driving circuit shown in FIG3b.

[0135] Figure 3c shows the circuit schematic of another LTPO pixel driving circuit. The difference between Figure 3c and Figure 3b is that the eighth transistor T8 and the ninth transistor T9 are removed, and the second terminal of the first transistor T1 is connected to the third node N3.

[0136] LTPO display substrates integrate LTPS transistors and Oxide transistors. The fabrication process of Oxide transistors is often affected by the high-temperature process of LTPS transistors, resulting in poor stability of Oxide transistors. In addition, the integration of LTPS transistors and Oxide transistors in LTPO display substrates makes the signal routing in the display area of ​​the substrate more complex, leading to a decrease in the resolution, aperture ratio and transmittance of the display substrate, and increasing the design difficulty.

[0137] An exemplary embodiment of this disclosure provides a display substrate, which may include: a substrate and a plurality of sub-pixels disposed on one side of the substrate, at least one sub-pixel including a pixel driving circuit, the at least one pixel driving circuit including at least one first type transistor and at least one second type transistor; the at least one first type transistor includes a driving transistor, and in a direction perpendicular to the plane of the substrate, at least a portion of the active layer of the second type transistor is located on the side of the driving transistor away from the substrate.

[0138] The at least some of the second type transistors include at least one first type electrode, which is connected to the gate of the driving transistor. The at least one first type electrode includes the first or second electrode of at least one transistor in the at least some of the second type transistors. The active layer of the second type transistor is disposed on the same layer as the first type electrode.

[0139] The display substrate provided in this disclosure includes at least one first-type transistor and at least one second-type transistor in at least one pixel driving circuit. The at least one first-type transistor includes a driving transistor, and at least some of the second-type transistors include at least one first-type electrode. The first-type electrode is connected to the gate of the driving transistor. The at least one first-type electrode includes the first or second electrode of at least some of the second-type transistors. The active layer of the second-type transistor is disposed on the same layer as the first-type electrode. This can simplify the signal routing of the display area of ​​the display substrate, reduce the number of vias, improve the resolution, aperture ratio and transmittance of the display substrate, and reduce the design difficulty.

[0140] Figures 4a to 4h show several cross-sectional structures of the display substrate provided in the embodiments of this disclosure. The display substrate provided in the embodiments of this disclosure may include: a substrate BS and a plurality of sub-pixels disposed on one side of the substrate BS. At least one sub-pixel may include a pixel driving circuit. At least one pixel driving circuit may include at least one first type transistor TL and at least one second type transistor TO. At least one first type transistor TL includes a driving transistor T3. In the direction Z perpendicular to the plane where the substrate BS is located, at least a portion of the active layer TOa of the second type transistor TO is located on the side of the gate T3g of the driving transistor T3 away from the substrate BS.

[0141] At least a portion of the second type transistor TO includes at least one first type electrode Tds, the first type electrode Tds being connected to the gate T3g of the driving transistor T3, the at least one first type electrode Tds including the first or second electrode of at least one transistor in the at least a portion of the second type transistor TO, and the active layer TOa of the second type transistor TO being disposed on the same layer as the first type electrode Tds.

[0142] In an exemplary embodiment, as shown in Figures 4a to 4e and 4h, at least one first type of via VL is provided on the display substrate. At least a portion of the first type of via VL corresponds one-to-one with at least a portion of the first type of electrode Tds. The first type of electrode Tds is connected to the gate T3g of the driving transistor T3 through the corresponding first type of via VL.

[0143] In an exemplary embodiment, as shown in Figures 4a to 4e and 4h, at least one second type of via VO is provided on the display substrate, and the pixel driving circuit may further include at least one connection structure CS. In the direction Z perpendicular to the plane where the substrate BS is located, the connection structure CS is located on the side of the active layer TOa of the second type of transistor TO away from the substrate BS.

[0144] At least one connection structure CS corresponds one-to-one with at least a portion of the second type via VO and at least a portion of the first type electrode Tds. The gate T3g of the driving transistor T3 and the corresponding first type electrode Tds are connected to the corresponding connection structure CS at the corresponding second type via VO position.

[0145] In an exemplary embodiment, as shown in Figures 4a to 4e and 4h, the connection structure CS may be located on the side of the active layer TOa of the second type of transistor TO that is away from the substrate BS. For example, as shown in Figures 4a to 4e, the connection structure CS may be located on the first source / drain metal layer SD1. As shown in Figure 4g, the connection structure CS may be located on the third gate metal layer Gate3. The embodiments disclosed herein are not limited to these. For example, the connection structure CS may be located on the second source / drain metal layer or on the third source / drain metal layer, with the second and third source / drain metal layers located on the side of the first source / drain metal layer SD1 that is away from the substrate BS.

[0146] In an exemplary embodiment, as shown in Figures 4a to 4e and 4h, in the first type via VL and the second type via VO corresponding to the same first type electrode Tds, the orthographic projection of the first type via VL on the substrate BS and the orthographic projection of the second type via VO on the substrate BS at least partially overlap.

[0147] In an exemplary embodiment, as shown in Figures 4a to 4e and 4h, in the first type via VL and the second type via VO corresponding to the same first type electrode Tds, the orthogonal projection of the first type via VL on the substrate BS covers the orthogonal projection of the corresponding second type via VO on the substrate BS.

[0148] In an exemplary embodiment, as shown in FIG4a, the orthogonal projection of the first type of electrode Tds on the substrate BS covers the orthogonal projection of the corresponding first type of via VL on the substrate BS.

[0149] In an exemplary embodiment, as shown in Figures 4c to 4e, the orthographic projection of the first type of electrode Tds on the substrate BS at least partially overlaps with the orthographic projection of the corresponding first type of via VL on the substrate BS, and at least partially does not overlap.

[0150] In an exemplary embodiment, as shown in Figures 4f to 4g, at least one second type of via VO is provided on the display substrate, and the pixel driving circuit may further include at least one connection structure CS. In the direction Z perpendicular to the plane where the substrate BS is located, the connection structure CS is located on the side of the active layer of the second type of transistor TO away from the substrate BS.

[0151] At least one connection structure CS corresponds one-to-one with at least a portion of the second type via VO and at least a portion of the first type electrode Tds. The gate T3g of the driving transistor T3 and the corresponding first type electrode Tds are connected by the corresponding connection structure CS at the position of the corresponding second type via VO.

[0152] In an exemplary embodiment, as shown in Figures 4b, 4d, 4g, and 4h, at least a portion of the surface of the gate T3g of the driving transistor T3 away from the substrate BS and the sidewall of the corresponding first type electrode Tds close to the corresponding second type via VO are connected to the corresponding connection structure CS through the corresponding second type via VO.

[0153] In an exemplary embodiment, as shown in Figures 4e and 4f, at least a portion of the surface of the gate T3g of the driving transistor T3 away from the substrate BS, the sidewall of the corresponding first type electrode Tds near the corresponding second type via VO, and at least a portion of the surface of the corresponding first type electrode Tds away from the substrate BS are connected to the corresponding connection structure CS through the corresponding second type via VO.

[0154] In an exemplary embodiment, as shown in Figures 4a to 4h, the active layer TLa of the first type transistor TL is located in the first semiconductor layer AT1, and the active layer TOa of the second type transistor TO is located in the second semiconductor layer AT2. In the direction Z perpendicular to the plane where the substrate BS is located, the second semiconductor layer AT2 is located on the side of the first semiconductor layer AT1 away from the substrate BS. At least one second type transistor TO may include a first reset transistor T1 and a compensation transistor T2. The second electrode T1d of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2 are located in the conductor region of the second semiconductor layer AT2.

[0155] The first type of electrode Tds may include the second electrode T1d of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2. The second electrode Tds of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2 are connected to each other and are connected to the gate T3g of the driving transistor T3.

[0156] In an exemplary embodiment, as shown in Figures 4a to 4h, at least one first type transistor TL may further include a first light-emitting control transistor T6. The active layer T6a of the first light-emitting control transistor T6 is connected to the second electrode T2d of the compensation transistor T2 and the first electrode T6s of the first light-emitting control transistor T6. The first electrode T6s of the first light-emitting control transistor T6 is located in the conductor region in the second semiconductor layer AT2 and is interconnected with the second electrode T2d of the compensation transistor T2.

[0157] In an exemplary embodiment, as shown in Figures 4a to 4h, the display substrate may further include a first initial signal line Vinit1. In the direction Z perpendicular to the plane where the substrate BS is located, the first initial signal line Vinit1 may be located on the side of the second semiconductor layer AT2 close to the substrate BS. The first electrode T1s of the first reset transistor T1 is connected to the first initial signal line Vinit1. The first electrode T1 of the first reset transistor T1 is located in the conductor region in the second semiconductor layer AT2.

[0158] In an exemplary embodiment, as shown in Figures 4b, 4d to 4h, the connection structure CS may include a first connection structure CS1, a second connection structure CS2 and a third connection structure CS3, and the second type of via VO may include a fifth via V5, a sixth via V6 and a seventh via V7.

[0159] The first connection structure CS1 can be connected to the first initial signal line Vinit1 and the first electrode T1s of the first reset transistor T1 via the seventh via V7; as shown in Figures 4b, 4d, 4g, and 4h, the first connection structure CS1 can be connected to at least a portion of the surface of the first initial signal line Vinit1 away from the substrate BS via the seventh via V7 and the sidewall of the first electrode T1s of the first reset transistor T1 near the seventh via V7; as shown in Figures 4e and 4f, the first connection structure CS1 can be connected to at least a portion of the surface of the first initial signal line Vinit1 away from the substrate BS via the seventh via V7, the sidewall of the first electrode T1s of the first reset transistor T1 near the seventh via V7 and the surface of the first electrode T1s of the first reset transistor T1 away from the substrate VS via the seventh via V7.

[0160] The second connection structure CS2 can be connected to the gate T3g of the driving transistor T3, the second electrode T1d of the first reset transistor T1, and the first electrode T2s of the compensation transistor T2 via the sixth via V6; as shown in Figures 4b, 4d, and 4g, the second connection structure CS2 can be connected to at least a portion of the surface of the gate T3g of the driving transistor T3 away from the substrate, the second electrode T1d of the first reset transistor T1, and the sidewall of the first electrode T2s of the compensation transistor T2 near the sixth via V6 via the sixth via V6; as shown in Figures 4e and 4f, the second connection structure CS2 can be connected to at least a portion of the surface of the gate T3g of the driving transistor T3 away from the substrate, the second electrode T1d of the first reset transistor T1, and the sidewall of the first electrode T2s of the compensation transistor T2 near the sixth via V6 via the sixth via V6, and at least a portion of the surface of the second electrode T1d of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2 away from the substrate via the sixth via V6.

[0161] The third connection structure CS3 can be connected to the active layer T6a of the first light-emitting control transistor T6 and the second electrode T2d of the compensation transistor T2 through the fifth via V5; as shown in Figures 4b, 4d and 4g, the third connection structure CS3 can be connected to at least a portion of the surface of the active layer T6a of the first light-emitting control transistor T6 away from the substrate and the sidewall of the second electrode T2d of the compensation transistor T2 near the fifth via V5 through the fifth via V5; as shown in Figures 4e and 4f, the third connection structure CS3 can be connected to at least a portion of the surface of the active layer T6a of the first light-emitting control transistor T6 away from the substrate through the fifth via V5, the sidewall of the second electrode T2d of the compensation transistor T2 near the fifth via V5 and at least a portion of the surface of the second electrode T2d of the compensation transistor T2 away from the substrate through the fifth via V5.

[0162] In an exemplary embodiment, as shown in Figures 4a to 4e and 4h, the display substrate may further include a first initial signal line Vinit1, the active layer TLa of the first type transistor TL may be located on the first semiconductor layer AT1, the active layer Toa of the second type transistor TO may be located on the second semiconductor layer AT2, and in the direction Z perpendicular to the plane of the substrate BS, the second semiconductor layer AT2 may be located on the side of the first semiconductor layer AT1 away from the substrate BS, and the first initial signal line Vinit1 may be located on the side of the second semiconductor layer AT2 close to the substrate BS; at least one first type transistor TL may further include a first light-emitting control transistor T6, and at least one second type transistor TO may include a first reset transistor T1 and a compensation transistor T2;

[0163] The first type of electrode Tds may include the second electrode T1d of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2. The second electrode T1d of the first reset transistor T1, the first electrode T2s of the compensation transistor T2, and the first electrode T6s of the first light-emitting control transistor T6 may be located in the conductor region in the second semiconductor layer AT2. The second electrode T1d of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2 are interconnected. The first electrode T6s of the first light-emitting control transistor T6 is interconnected with the second electrode T2d of the compensation transistor T2.

[0164] The first type of via VL may include a first via V1, a second via V2 and a third via V3. The first terminal T1s of the first reset transistor T1 can be connected to the first initial signal line Vinit1 through the first via V1. The second terminal T1d of the first reset transistor T1 and the first terminal T2s of the compensation transistor T2 can be connected to the gate T3g of the driving transistor T3 through the second via V2. The second terminal T2d of the compensation transistor T2 and the first terminal T6s of the first light-emitting control transistor T6 can be connected to the active layer T6a of the first light-emitting control transistor T6 through the third via V3.

[0165] Figure 4i shows a cross-sectional view of a display substrate. The first electrode T1s of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6 are all disposed on the first source / drain metal layer SD1. The first electrode T1s of the first transistor T1 needs to be electrically connected to the first initial signal line Vinit1 and the active layer T1a of the first transistor T1 through two vias on the second interlayer insulating layer ILD2, respectively. The second terminal T1d of transistor T1 and the first terminal T2s of transistor T2 are interconnected and need to be electrically connected to the active layer T1a of transistor T1, the gate T3g of driving transistor T3, and the active layer T2a of transistor T2 through three vias on the second interlayer insulating layer ILD2, respectively. The second terminal T2d of transistor T2 and the first terminal T6s of transistor T6 need to be electrically connected to the active layer T6a of transistor T6 and the active layer T2a of transistor T2 through two vias on the second interlayer insulating layer ILD2, respectively. Therefore, it can be seen that in the structure shown in Figure 4i, the second interlayer insulating layer ILD2 has significantly more vias than in the structures shown in Figures 4a to 4g. Firstly, the larger number of vias results in lower resolution and aperture ratio of the display substrate in the structure shown in Figure 4i. Secondly, in the structure shown in Figure 4i, the first source / drain metal layer SD1 has a larger number of structures (the first electrode T1s of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6 are all located in the first source / drain metal layer SD1), resulting in a larger metal size and area retained in the first source / drain metal layer SD1. This increases the wiring difficulty of the pixel driving circuit and reduces the aperture ratio. Thirdly, due to the increased wiring difficulty of the first source-drain metal layer SD1, in some cases, in order to avoid short circuits in the signal lines of the first source-drain metal layer SD1, it is necessary to bend the traces in the first source-drain metal layer SD1. The bent traces increase the trace length of the first source-drain metal layer SD1, which in turn affects the parasitic capacitance between the first source-drain metal layer SD1 and other metal film layers. In some cases, this will lead to an increase in the parasitic capacitance between the first source-drain metal layer SD1 and other metal film layers (for example, the parasitic capacitance between the first source-drain metal layer SD1 and the second source-drain metal layer increases, thereby affecting the signal of the data signal line D located in the second source-drain metal layer).

[0166] In the structures shown in Figures 4a to 4h of the embodiments of this disclosure, firstly, the number of vias in the second interlayer insulating layer ILD2 is greatly reduced, which can improve the resolution and aperture ratio of the display substrate; secondly, the metal size and area retained in the first source / drain metal layer SD1 are small, which reduces the wiring difficulty of the pixel driving circuit and improves the aperture ratio; thirdly, since the wiring difficulty of the pixel driving circuit is reduced, the traces in the first source / drain metal layer SD1 do not need to be bent in most cases, which reduces the parasitic capacitance between the first source / drain metal layer SD1 and other metal film layers.

[0167] In an exemplary embodiment, the transistors in the pixel driving circuit may include a first type of transistor (which may be a polysilicon transistor) and a second type of transistor (which may be a metal-oxide transistor). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal-oxide transistors on a single display substrate forms an LTPO (Low Temperature Poly-Silicon+Oxide) display substrate. This leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality. In the embodiments of this disclosure, the structures shown in Figures 4a to 4h involve the second semiconductor layer AT2 being overlapped downwards (i.e., the second semiconductor layer AT2 is overlapped and connected to the first type of transistor near the substrate BS). LTPO pixel driving circuits are applicable to all of these.

[0168] In an exemplary embodiment, the circuit schematic of the pixel driving circuit can be as shown in Figure 3a. The first type of transistor can be a polysilicon transistor (LTPS TFT), which may include a third transistor T3 (i.e., the aforementioned driving transistor T3), a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 (i.e., the aforementioned first light-emitting control transistor T6), and a seventh transistor T7. The second type of transistor can be a metal-oxide transistor (Oxide TFT), which may include a first transistor T1 (i.e., the aforementioned first reset transistor T1) and a second transistor T2 (i.e., the aforementioned compensation transistor T2). The active layers of the first transistor T1 and the second transistor T2 are located on the second semiconductor layer AT2, and the active layers of the third transistor T3 to the seventh transistor T7 are located on the first semiconductor layer AT1. The material of the first semiconductor layer AT1 can be polysilicon (P-Si); the material of the second semiconductor layer can be metal oxide, and the metal oxide layer can be transparent indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO).

[0169] The structure provided in this disclosure, in which the second semiconductor layer AT2 is connected downwards (i.e., the second semiconductor layer AT2 is connected to the first type of transistor near the substrate BS), is not limited to the pixel driving circuit shown in FIG3a. It can be applied to any LTPO pixel driving circuit. For example, as shown in FIG3a, the first type of transistor may only include the second transistor T2 or only the first transistor T1; or, as shown in FIG3b, the LTPO pixel driving circuit may include the first type of transistor T1, the third transistor T3 (i.e., the aforementioned driving transistor T3), the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 (i.e., the aforementioned first light-emitting control transistor T6), the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 (in the pixel driving circuit shown in FIG3b, the eighth transistor T8 and the ninth transistor T9 can be removed), and the second type of transistor may include the first transistor T1, the third transistor T3 (i.e., the aforementioned driving transistor T3), the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 (i.e., the aforementioned first light-emitting control transistor T6), the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 (in the pixel driving circuit shown in FIG3b, the eighth transistor T8 and the ninth transistor T9 can be removed). Two transistors T2 (i.e., the aforementioned compensation transistor T2) have their active layers located on the second semiconductor layer AT2. The active layers of the first transistor T1, the third transistor T3 to the ninth transistor T9 are located on the first semiconductor layer AT1. The first semiconductor layer AT1 can be made of polysilicon (P-Si), and the second semiconductor layer can be made of metal oxide. The metal oxide layer can be made of transparent indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO). Alternatively, as shown in Figure 3c, the LTPO pixel driving circuit can include the following transistors: the first type of transistors can include the first transistor T1, the third transistor T3 (i.e., the aforementioned driving transistor T3), the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 (i.e., the aforementioned first light-emitting control transistor T6), and the seventh transistor T7. The second type of transistors can include the second transistor T2 (i.e., the aforementioned compensation transistor T2).

[0170] Figure 4j shows a schematic diagram of the conductor formation of the second semiconductor layer AT2. Q1 represents particles in the second semiconductor layer AT2 before conductor formation, and Q2 represents particles (e.g., boron ions) added during the conductor formation process to make the second semiconductor layer AT2 conductive. It is easy to see from Figure 4j that during the conductor formation process of the second semiconductor layer AT2, the side of the second semiconductor layer AT2 furthest from the substrate BS is more sufficiently conductor-formed, while the side closer to the substrate BS may exhibit insufficient conductor formation. When the conductor of the second semiconductor layer AT2 near the substrate BS is insufficient, the structure shown in Figure 4a may have large contact resistances at the junction of the first electrode T1s of the first transistor T1 and the first initial signal line Vinit1, the junction of the second electrode T1d of the first transistor T1 and the first electrode T2s of the second transistor T2 with the gate T3g of the driving transistor T3, and the junction of the second electrode T2d of the second transistor T2 and the first electrode T6s of the sixth transistor T6 with the active layer T6a of the sixth transistor T6, thus affecting the quality of the display substrate. When the conductor of the second semiconductor layer AT2 near the substrate BS is sufficient, the problem of large contact resistance at the junctions can be avoided.

[0171] In the structure shown in Figure 4c, the second semiconductor layer AT2 is exposed in the first type of via VL, and the sidewall of the second semiconductor layer AT2 near the side of the corresponding first type of via VL is exposed. During the conductor-forming process, the sidewall of the second semiconductor layer AT2 near the side of the corresponding first type of via VL can be conductor-formed, which can avoid the problem of large contact resistance of the overlapping connection and improve the quality of the display substrate.

[0172] In the structures shown in Figures 4b, 4d to 4h, the connection structure CS is connected to the sidewall of the second semiconductor layer AT2 near the side corresponding to the second type of via VO, or the connection structure CS is connected to the sidewall of the second semiconductor layer AT2 near the side corresponding to the second type of via VO and the surface of the second semiconductor layer AT2 away from the substrate VS. This avoids the problem of large contact resistance in the lap connection and improves the quality of the display substrate.

[0173] In the structures shown in Figures 4a, 4c, and 4h, it is not necessary to set the connection structure on the first source / drain metal layer SD1 (or the second source / drain metal layer SD2, or the third source / drain metal layer SD3). This can further free up space on the first source / drain metal layer SD1 (or the second source / drain metal layer SD2, or the third source / drain metal layer SD3), which is beneficial for the first source / drain metal layer SD1 (or the second source / drain metal layer SD2, or the third source / drain metal layer SD3) to run a constant voltage line or to make the space more sufficient, thus reducing the design difficulty of the pixel driving circuit. In the structure shown in Figure 4h, the connection structure CS is set on the third gate metal layer Gate3. On the one hand, it can free up space on the first source / drain metal layer SD1 (or the second source / drain metal layer SD2, or the third source / drain metal layer SD3) and make the space more sufficient. On the other hand, it can avoid the problem of large contact resistance of the overlapping connection due to insufficient conductor formation of the second semiconductor layer AT2.

[0174] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate (or substrate plate) using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0175] In an exemplary embodiment, the fabrication process of the display substrate shown in FIG4a may include the following operations:

[0176] (101) Forming the first type of via.

[0177] In an exemplary embodiment, as shown in FIG5a, forming a first type of via may include: patterning a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, and a second buffer layer Buffer2 through a patterning process to form a first type of via. The first type of via may include a first via V1, a second via V2, and a third via V3.

[0178] In an exemplary embodiment, as shown in FIG5a, before forming the first type of via, the following may be included: sequentially forming on one side of the substrate BS a first flexible layer PI1, a first barrier layer Barrier1, a second flexible layer PI2, a second barrier layer Barrier2-1, a shielding layer BSM, a third barrier layer Barrier2-2, a first buffer layer Buffer1, a first semiconductor layer AT1, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, a first interlayer insulating layer ILD1, and a second buffer layer Buffer. 2; The orthographic projection of the shielding layer BSM on the substrate BS at least partially overlaps with the orthographic projection of the active layer T3a of the third transistor T3 on the substrate BS. The first semiconductor layer AT1 includes, but is not limited to, the active layer T3a of the third transistor T3 and the active layer T6a of the sixth transistor T6. The first gate metal layer Gate1 includes, but is not limited to, the gate T3g of the third transistor T3 and the gate T6g of the sixth transistor T6. The second gate metal layer Gate2 includes, but is not limited to, the first initial signal line Vinit1, the second gate T1g2 of the first transistor T1, and the second gate T1g2 of the second transistor T2. Specifically, the first interlayer insulating layer ILD1 and the second buffer layer Buffer2 within the first via V1 are etched away, exposing the surface of the first initial signal line Vinit1; the second gate insulating layer GI2, the first interlayer insulating layer ILD1, and the second buffer layer Buffer2 within the second via V2 are etched away, exposing the surface of the gate T3g of the third transistor T3; and the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, and the second buffer layer Buffer2 within the third via V3 are etched away, exposing the surface of the active layer T6a of the sixth transistor T6.

[0179] (102) Form the second semiconductor layer AT2.

[0180] In an exemplary embodiment, as shown in FIG5b, forming the second semiconductor layer AT2 may include: depositing a second semiconductor thin film on the substrate on which the above pattern is formed, and patterning the second semiconductor thin film by a patterning process to form a second semiconductor layer AT2 covering the second buffer layer Buffer2. The second semiconductor layer AT2 includes, but is not limited to, the first electrode T1s of the first transistor T1, the active layer T1a of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the active layer T2a of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6. The conductive region formed by subsequent conductive processing in the second semiconductor layer AT2 may include the first electrode T1s of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6. The portion of the conductive region in the second semiconductor layer AT2 located in the first type of via is connected to the structure exposed by the first type of via through the first type of via.

[0181] In the same pixel driving circuit, the second terminal T1d of the first transistor T1 is connected to the first terminal T2s of the second transistor T2. The second terminal T2d of the second transistor T2 is connected to the first terminal T6s of the sixth transistor T6. The first terminal T1s of the first transistor T1 is connected to the first initial signal line Vinit1 through the first via V1. The second terminal T1d of the first transistor T1 and the first terminal T2s of the second transistor T2 are connected to the gate T3g of the third transistor T3 through the second via V2. The second terminal T2d of the second transistor T2 and the first terminal T6s of the sixth transistor T6 are connected to the active layer T6a of the sixth transistor T6 through the third via V3.

[0182] (103) A third gate insulating layer GI3 and a third gate metal layer Gate3 are formed, and the second semiconductor layer is made conductive.

[0183] In an exemplary embodiment, as shown in FIG5c, step (103) may include: sequentially forming a third gate insulating layer GI3 and a third gate metal layer Gate3 on the side of the second semiconductor layer AT2 away from the substrate BS; performing a conductor treatment on the second semiconductor layer AT2; and conducting a conductor region in the area of ​​the second semiconductor layer AT2 not covered by the third gate metal layer Gate3. The third conductive layer Gate3 includes, but is not limited to, the first gate T1g1 of the first transistor T1 and the first gate T2g1 of the second transistor T2. The first gate T1g1 of the first transistor T1 and the first gate T2g1 of the second transistor T2 are connected. The orthographic projections of the active layer T1a of transistor T1 and the second gate T1g2 of the first transistor T1 onto the substrate BS at least partially overlap; the orthographic projections of the first gate T2g1 of the second transistor T2 onto the active layer T2a and the second gate T2g2 of the second transistor T2 onto the substrate BS at least partially overlap; the conductor region in the second semiconductor layer AT2 may include the first electrode T1s of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6.

[0184] (104) Form the second interlayer insulation layer ILD2.

[0185] In an exemplary embodiment, as shown in FIG5d, forming the second interlayer insulating layer ILD2 may include forming the second interlayer insulating layer ILD2 on the side of the third gate metal layer Gate3 away from the substrate BS.

[0186] (105) Form the fourth conductive layer SD1.

[0187] In an exemplary embodiment, forming the fourth conductive layer SD1 may include: forming a second type of via on the second interlayer insulating layer IDL2, the second type of via including at least a fourth via V4; depositing a fourth conductive film on the side of the second interlayer insulating layer IDL2 away from the substrate BS; and patterning the fourth conductive film by a patterning process to form a fourth conductive layer covering the second interlayer insulating layer IDL2. The fourth conductive layer includes, but is not limited to, the second electrode T6d of the sixth transistor T6. As shown in FIG4a, it is a cross-sectional structural diagram after the second type of via and the fourth conductive layer SD1 are sequentially formed based on the structure shown in FIG5d.

[0188] In an exemplary embodiment, the fabrication process of the display substrate shown in FIG4b may include the following operations:

[0189] (201) Form the first type of via. The same as step (101) above, and will not be repeated here.

[0190] (202) Form the second semiconductor layer AT2. This is the same as step (102) above, and will not be repeated here.

[0191] (203) A third gate insulating layer GI3 and a third gate metal layer Gate3 are formed, and the second semiconductor layer is conductiveized. This is the same as step (103) above, and will not be repeated here.

[0192] (204) Form the second interlayer insulating layer ILD2. This is the same as step (104) above, and will not be repeated here.

[0193] (205) Forming a second type of via.

[0194] In an exemplary embodiment, as shown in FIG6a, forming a second type of via may include: patterning a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a second buffer layer Buffer2, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2 to form a second type of via. The second type of via includes, but is not limited to, a fourth via V4, a fifth via V5, a sixth via V6, and a seventh via V7. In the fourth via V4, the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the second buffer layer Buffer2, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2 are etched away, exposing the surface of the active layer T6a of the sixth transistor T6; in the fifth via V5, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the second buffer layer Buffer2, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2 are etched away, exposing the first electrode T6d of the sixth transistor T6. The surface of the first transistor T1 is exposed; the third gate insulating layer GI3 and the second interlayer insulating layer ILD2 in the sixth via V6 are etched away, exposing the surface of the first electrode T2s of the second transistor T2; the third gate insulating layer GI3 and the second interlayer insulating layer ILD2 in the seventh via V7 are etched away, exposing the surface of the first electrode T1s of the first transistor T1; in the second type of via, the fourth via V4 exposes at least a portion of the surface of the first semiconductor layer AT1, and the fifth via V5, the sixth via V6 and the seventh via V7 expose at least a portion of the surface of the second semiconductor layer AT2.

[0195] (205) Remove the oxide layer of the second semiconductor layer AT2 in the second type of via and the first semiconductor layer AT1 in the second type of via.

[0196] In an exemplary embodiment, as shown in FIG6b, the oxide layers of the second semiconductor layer AT2 and the first semiconductor layer AT1 within the second type of via are removed. This may include: removing the second semiconductor layer AT2 exposed by the second type of via through etching, and removing the oxide layer on the surface of the active layer T6a of the sixth transistor T6 within the fifth via V5. For example, the second semiconductor layer AT2 and the oxide layer on the surface of the active layer T6a of the sixth transistor T6 within the fifth via V5 may be removed using a wet etching method. The wet etching liquid composition may include HF and NH4F. After the second semiconductor layer AT2 in the second type of via is etched away, the second semiconductor layer AT2 in the fifth via V5 is etched away, exposing at least a portion of the surface of the active layer T6a of the sixth transistor T6; the second semiconductor layer AT2 in the sixth via V6 is etched away, exposing at least a portion of the surface of the gate T3g of the third transistor T3; the second semiconductor layer AT2 in the seventh via V7 is etched away, exposing at least a portion of the surface of the first initial signal line Vinit1.

[0197] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate BS at least partially overlaps with the orthographic projection of the fifth via V5 on the substrate BS. For example, the orthographic projection of the third via V3 on the substrate BS may cover the orthographic projection of the fifth via V5 on the substrate BS, and the orthographic projections of the third via V3 and the fifth via V5 on the substrate BS may be concentric circles. The orthographic projection of the second via V2 on the substrate BS at least partially overlaps with the orthographic projection of the sixth via V6 on the substrate BS. For example, the orthographic projection of the second via V2 on the substrate BS may cover the orthographic projection of the fifth via V5 on the substrate BS. The projection can cover the orthographic projection of the sixth via V6 on the substrate BS. The orthographic projection of the second via V2 on the substrate BS and the orthographic projection of the sixth via V6 on the substrate BS can be concentric circles. The orthographic projection of the first via V1 on the substrate BS and the orthographic projection of the seventh via V7 on the substrate BS at least partially overlap. For example, the orthographic projection of the first via V1 on the substrate BS can be located within the range of the orthographic projection of the seventh via V7 on the substrate BS. The orthographic projection of the first via V1 on the substrate BS and the orthographic projection of the seventh via V7 on the substrate BS can be concentric circles.

[0198] In an exemplary embodiment, the second type of via can also expose the sidewalls of the second semiconductor layer AT2.

[0199] In an exemplary embodiment, after removing the second semiconductor layer AT2 inside the second type of via, the sidewalls of the second semiconductor layer AT2 exposed by the second type of via can be made conductive, so that the sidewalls of the second semiconductor layer AT2 exposed by the third type of via can be fully conductive.

[0200] (206) Form the fourth conductive layer SD1.

[0201] In an exemplary embodiment, as shown in FIG4b, it is a cross-sectional structural diagram after the fourth conductive layer SD1 is formed on the basis of the structure shown in FIG6b. Forming the fourth conductive layer SD1 may include: depositing a fourth conductive film on the side of the second interlayer insulating layer ILD2 away from the substrate BS, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer covering the second interlayer insulating layer ILD2, as shown in FIG4b. The fourth conductive layer includes, but is not limited to, the second electrode T6d of the sixth transistor T6, the first connection structure CS1, the second connection structure CS2, and the third connection structure CS3. The second electrode T6d of the sixth transistor T6 is electrically connected to the active layer T6a of the sixth transistor T6 through the fourth via V4; the first connection structure CS1 is connected to the first initial signal line Vinit1 and the sidewall of the first electrode T1s of the first transistor T1 through the first via V1; the second connection structure CS2 is connected to the gate T3g of the third transistor T3 and the first electrode T2s of the second transistor T2 through the second via V2; and the third connection structure CS3 is connected to the active layer T6a of the sixth transistor T6 and the sidewall of the first electrode T6s of the sixth transistor T6 through the third via V3.

[0202] In an exemplary embodiment, as shown in Figures 6c to 6e, a planar structure diagram is shown of the fourth conductive layer SD1 overlapping with the first semiconductor layer AT1, the first conductive layer Gate1, the second conductive layer Gate2, and the second semiconductor layer AT2 after the fourth conductive layer SD1 is formed.

[0203] In an exemplary embodiment, as shown in FIG6c, it is a schematic diagram of a planar structure in which the first connection structure CS1 is connected to the first initial signal line Vinit1 and the first electrode T1s of the first transistor T1. The orthographic projection of the first via V1 on the substrate BS and the orthographic projection of the seventh via V7 on the substrate BS can be concentric circles. The aperture size LV7 of the seventh via V7 is smaller than the aperture size LV1 of the first via V1. In an exemplary embodiment, the difference between the aperture size LV7 of the seventh via V7 and the aperture size LV1 of the first via V1 is approximately 0.5 micrometers to 2 micrometers.

[0204] In an exemplary embodiment, as shown in FIG6d, it is a schematic diagram of a planar structure in which the second connection structure CS2 is connected to the gate T3g of the third transistor T3 and the second terminal T1d of the first transistor T1 (which is also the first terminal T2s of the second transistor T2). The orthographic projection of the second via V2 on the substrate BS and the orthographic projection of the sixth via V6 on the substrate BS can be concentric circles. The aperture size LV6 of the sixth via V6 is smaller than the aperture size LV2 of the second via V2. In the exemplary embodiment, the difference between the aperture size LV6 of the sixth via V6 and the aperture size LV2 of the second via V2 is approximately 0.5 micrometers to 2 micrometers.

[0205] In an exemplary embodiment, as shown in FIG6e, it is a schematic diagram of the planar structure in which the third connection structure CS3 overlaps with the active layer T6a of the sixth transistor T6 and the first electrode T6s of the sixth transistor T6 (which is also the second electrode T2d of the second transistor T2). The orthographic projection of the third via V3 on the substrate BS and the orthographic projection of the fifth via V5 on the substrate BS can be concentric circles. The aperture size LV5 of the fifth via V5 is smaller than the aperture size LV3 of the third via V3. In the exemplary embodiment, the difference between the aperture size LV5 of the fifth via V5 and the aperture size LV3 of the third via V3 is approximately 0.5 micrometers to 2 micrometers.

[0206] In an exemplary embodiment, the fabrication process of the display substrate shown in FIG4c may include the following operations:

[0207] (301) Form the first type of via. This is the same as step (101) above, and will not be repeated here.

[0208] (302) Form the second semiconductor layer AT2.

[0209] In an exemplary embodiment, as shown in FIG7, forming the second semiconductor layer AT2 may include: depositing a second semiconductor thin film on the substrate on which the above pattern is formed, and patterning the second semiconductor thin film by a patterning process to form a second semiconductor layer AT2 covering the second buffer layer Buffer2. The second semiconductor layer AT2 includes, but is not limited to, the first electrode T1s of the first transistor T1, the active layer T1a of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the active layer T2a of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6. The conductive region formed by subsequent conductive processing in the second semiconductor layer AT2 may include the first electrode T1s of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6. The portion of the conductive region in the second semiconductor layer AT2 located in the first type of via is connected to the structure exposed by the second type of via through the first type of via.

[0210] In the same pixel driving circuit, the second terminal T2d of the second transistor T2 is connected to the first terminal T6s of the sixth transistor T6. The first terminal T1s of the first transistor T1 is connected to the first initial signal line Vinit1 through the first via V1. The second terminal T1d of the first transistor T1 is connected to the gate T3g of the third transistor T3 through the second via V2. The second terminal T2d of the second transistor T2 and the first terminal T6s of the sixth transistor T6 are connected to the active layer T6a of the sixth transistor T6 through the third via V3.

[0211] (303) A third gate insulating layer GI3 and a third gate metal layer Gate3 are formed, and the second semiconductor layer is conductiveized. This is the same as step (103) above, and will not be repeated here.

[0212] (304) Form the second interlayer insulating layer ILD2. This is the same as step (104) above, and will not be repeated here.

[0213] (305) Form the fourth conductive layer SD1. The same as step (105) above, and will not be repeated here. The cross-sectional structure after forming the fourth conductive layer SD1 can be shown in Figure 4c.

[0214] In an exemplary embodiment, the fabrication process of the display substrate shown in FIG4d may include the following operations:

[0215] (401) Form the first type of via. This is the same as step (301) above, and will not be repeated here.

[0216] (402) Form the second semiconductor layer AT2. This is the same as step (302) above, and will not be repeated here.

[0217] (403) A third gate insulating layer GI3 and a third gate metal layer Gate3 are formed, and the second semiconductor layer is conductiveized. This is the same as step (303) above, and will not be repeated here.

[0218] (404) Forming the second interlayer insulating layer ILD2. Same as step (304) above, and will not be repeated here. The cross-sectional structure after forming the second type of via is shown in Figure 8a. At least a portion of at least one of the second type of vias is covered by the second semiconductor layer AT2. For example, in the fifth via V5, the surface of the second electrode T2d of the second transistor T2 (which is also the first electrode T6a of the sixth transistor T6) and the surface of the active layer T6a of the sixth transistor T6 are exposed; in the sixth via V6, the surface of the first electrode T2s of the second transistor T2 (which is also the second electrode T1d of the first transistor T1) and the surface of the gate T3g of the third transistor T3 are exposed; in the seventh via V7, the surface of the first electrode T1s of the first transistor T2 and at least a portion of the surface exposing the first initial signal line Vinit1 are exposed.

[0219] (405) Remove the oxide layer of the semiconductor layer AT2 and the first semiconductor layer AT1 in the second type of via.

[0220] In an exemplary embodiment, as shown in FIG8b, the oxide layer of the first semiconductor layer AT1 in the fourth via V4 is removed, and simultaneously, the second semiconductor layer AT2 in the fifth via V5, the sixth via V6, and the seventh via V7 is removed. In an exemplary embodiment, the second semiconductor layer AT2 can be removed using a wet etching method, and the oxide layer on the surface of the active layer T6a of the sixth transistor T6 in the fifth via V5 can be removed. The wet etching liquid composition may include HF and NH4F.

[0221] (406) Form the fourth conductive layer SD1.

[0222] In an exemplary embodiment, forming the fourth conductive layer SD1 may include: depositing a fourth conductive film on the basis of FIG8b, and patterning the fourth conductive film by a patterning process to form a fourth conductive layer covering the second interlayer insulating layer ILD2. The fourth conductive layer includes, but is not limited to, the second electrode T6d of the sixth transistor T6. FIG4d is a cross-sectional structural diagram after forming the fourth conductive layer SD1 on the basis of the structure shown in FIG8b.

[0223] In an exemplary embodiment, as shown in Figures 8c to 8e, a planar structure diagram is shown of the fourth conductive layer SD1 overlapping with the first semiconductor layer AT1, the first conductive layer Gate1, the second conductive layer Gate2, and the second semiconductor layer AT2 after the fourth conductive layer SD1 is formed.

[0224] In an exemplary embodiment, as shown in FIG8c, it is a schematic diagram of a planar structure in which the first connection structure CS1 is connected to the first initial signal line Vinit1 and the first electrode T1s of the first transistor T1. The orthographic projection of the first via V1 on the substrate BS and the orthographic projection of the seventh via V7 on the substrate BS can be concentric circles. The aperture size LV7 of the seventh via V7 is smaller than the aperture size LV1 of the first via V1. In an exemplary embodiment, the difference between the aperture size LV7 of the seventh via V7 and the aperture size LV1 of the first via V1 is approximately 0.5 micrometers to 2 micrometers.

[0225] In an exemplary embodiment, as shown in FIG8d, it is a schematic diagram of a planar structure in which the second connection structure CS2 is connected to the gate T3g of the third transistor T3 and the second terminal T1d of the first transistor T1 (which is also the first terminal T2s of the second transistor T2). The orthographic projection of the second via V2 on the substrate BS and the orthographic projection of the sixth via V6 on the substrate BS can be concentric circles. The aperture size LV6 of the sixth via V6 is smaller than the aperture size LV2 of the second via V2. In the exemplary embodiment, the difference between the aperture size LV6 of the sixth via V6 and the aperture size LV2 of the second via V2 is approximately 0.5 micrometers to 2 micrometers.

[0226] In an exemplary embodiment, as shown in FIG8e, it is a schematic diagram of the planar structure in which the third connection structure CS3 overlaps with the active layer T6a of the sixth transistor T6 and the first electrode T6s of the sixth transistor T6 (which is also the second electrode T2d of the second transistor T2). The orthographic projection of the third via V3 on the substrate BS and the orthographic projection of the fifth via V5 on the substrate BS can be concentric circles. The aperture size LV5 of the fifth via V5 is smaller than the aperture size LV3 of the third via V3. In the exemplary embodiment, the difference between the aperture size LV5 of the fifth via V5 and the aperture size LV3 of the third via V3 is approximately 0.5 micrometers to 2 micrometers.

[0227] In an exemplary embodiment, the fabrication process of the display substrate shown in FIG4e may include the following operations:

[0228] (501) Form the first type of via. This is the same as step (401) above, and will not be repeated here.

[0229] (502) Form the second semiconductor layer AT2. This is the same as step (402) above, and will not be repeated here.

[0230] (503) A third gate insulating layer GI3 and a third gate metal layer Gate3 are formed, and the second semiconductor layer is conductiveized. This is the same as step (403) above, and will not be repeated here.

[0231] (504) Form the second interlayer insulating layer ILD2. This is the same as step (404) above, and will not be repeated here.

[0232] (505) Remove the oxide layer of the first semiconductor AT1 layer inside the second type of via.

[0233] In an exemplary embodiment, as shown in FIG9, the oxide layer of the first semiconductor layer AT1 in the fourth via V4 is removed by using gases such as CF4, SF6, and CHF3 (i.e., by dry etching), without removing the second semiconductor layer AT2 in the second type of via.

[0234] (506) Form the fourth conductive layer SD1.

[0235] In an exemplary embodiment, forming the fourth conductive layer SD1 may include: depositing a fourth conductive film on the basis of FIG9, and patterning the fourth conductive film by a patterning process to form a fourth conductive layer covering the second interlayer insulating layer ILD2. The fourth conductive layer includes, but is not limited to, the second electrode T6d of the sixth transistor T6. FIG4e is a schematic cross-sectional structure diagram after forming the fourth conductive layer SD1 on the basis of the structure shown in FIG9.

[0236] In an exemplary embodiment, after the fourth conductive layer SD1 is formed, a planar structure schematic diagram of the fourth conductive layer SD1 overlapping with the first semiconductor layer AT1, the first conductive layer Gate1, the second conductive layer Gate2, and the second semiconductor layer AT2 is shown in Figures 8c to 8e.

[0237] In an exemplary embodiment, the fabrication process of the display substrate shown in FIG4f may include the following operations:

[0238] (601) A first flexible layer PI1, a first barrier layer Barrier1, a second flexible layer PI2, a second barrier layer Barrier2-1, a third barrier layer Barrier2-2, a first buffer layer Buffer1, a first semiconductor layer AT1, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, and a second gate metal layer Gate2 are sequentially formed on one side of the substrate, as shown in Figure 10a, which is a schematic diagram of at least part of the planar structure after the formation of the second gate metal layer Gate2.

[0239] In an exemplary embodiment, the first semiconductor layer AT1 includes, but is not limited to, the active layer T3a of the third transistor T3 and the active layer T6a of the sixth transistor T6; the first gate metal layer Gate1 includes, but is not limited to, the gate T3g of the third transistor T3 and the gate T6g of the sixth transistor T6; and the second gate metal layer Gate2 includes, but is not limited to, the first initial signal line Vinit1, the second gate T1g2 of the first transistor T1, and the second gate T1g2 of the second transistor T2.

[0240] (602) Form the second semiconductor layer AT2.

[0241] In an exemplary embodiment, forming the second semiconductor layer AT2 may include: sequentially depositing a first interlayer insulating layer ILD1, a second buffer layer Buffer2, and a second semiconductor thin film on the substrate on which the above pattern is formed; patterning the second semiconductor thin film using a patterning process to form the second semiconductor layer AT2 covering the second buffer layer Buffer2, as shown in FIG10b. The second semiconductor layer AT2 includes, but is not limited to, the first electrode T1s of the first transistor T1, the active layer T1a of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the active layer T2a of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6; wherein, the conductive region (the conductive region becomes a conductive structure) formed by the subsequent conductive processing in the second semiconductor layer AT2 may include the first electrode T1s of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6.

[0242] In the same pixel driving circuit, the second terminal T1d of the first transistor T1 is connected to the first terminal T2s of the second transistor T2, and the second terminal T2d of the second transistor T2 is connected to the first terminal T6s of the sixth transistor T6. The first terminal T1s of the first transistor T1 at least partially overlaps with the orthographic projection of the first initial signal line Vinit1 on the substrate BS, and at least partially does not overlap. The second terminal T1d of the first transistor T1 and the first terminal T2s of the second transistor T2 at least partially overlap with the orthographic projection of the gate T3g of the third transistor T3 on the substrate BS, and at least partially does not overlap. The second terminal T2d of the second transistor T2 and the first terminal T6s of the sixth transistor T6 at least partially overlap with the orthographic projection of the active layer T6a of the sixth transistor T6 on the substrate BS, and at least partially does not overlap.

[0243] (603) A third gate insulating layer GI3 and a third gate metal layer Gate3 are formed, and the second semiconductor layer is conductiveized.

[0244] In an exemplary embodiment, as shown in FIG10c, (603) may include: sequentially forming a third gate insulating layer GI3 and a third conductive layer Gate3 on the side of the second semiconductor layer AT2 away from the substrate BS, performing a conductor treatment on the second semiconductor layer AT2, and conducting the area of ​​the second semiconductor layer AT2 not covered by the third gate metal layer Gate3 to form a conductor region, as shown in FIG10c. The third conductive layer Gate3 includes, but is not limited to, the first gate T1g1 of the first transistor T1 and the first gate T2g1 of the second transistor T2, and the first gate T1g1 of the first transistor T1 and... The orthographic projections of the active layer T1a and the second gate T1g2 of the first transistor T1 onto the substrate BS at least partially overlap; the orthographic projections of the first gate T2g1 of the second transistor T2 onto the active layer T2a and the second gate T2g2 of the second transistor T2 onto the substrate BS at least partially overlap; the conductor region in the second semiconductor layer AT2 may include the first electrode T1s of the first transistor T1, the second electrode T1d of the first transistor T1, the first electrode T2s of the second transistor T2, the second electrode T2d of the second transistor T2, and the first electrode T6s of the sixth transistor T6.

[0245] (604) Form the second interlayer insulation layer ILD2.

[0246] In an exemplary embodiment, forming the second interlayer insulating layer ILD2 may include: patterning the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the second buffer layer Buffer2, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2 to form a second type of via, as shown in FIG10d. The second type of via includes, but is not limited to, the fourth via V4, the fifth via V5, the sixth via V6, and the seventh via V7. The surface of the first semiconductor layer AT1 in the vias of the fourth via V4 and the fifth via V5 is dry-etched using gases such as CF4, SF6, and CHF3 to remove the oxide layer on the surface of the first semiconductor layer AT1. The first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the second buffer layer Buffer2, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2 within the fourth via V4 are etched away, exposing the surface of the active layer T6a of the sixth transistor T6; the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the second buffer layer Buffer2, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2 within the fifth via V5 are etched away, exposing the surface of the active layer T6a of the sixth transistor T6 and the surface of the second terminal T2d of the second transistor T2 (which is also the first terminal T6a of the sixth transistor T6); the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the second buffer layer Buffer2, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2 within the sixth via V6 are etched away, exposing the first terminal T2s of the second transistor T2. The surface of the first transistor T1 (also the second electrode T1d of the first transistor T1) and part of the surface of the gate T3g of the third transistor T3; the first interlayer insulating layer ILD1, the second buffer layer Buffer2, the third gate insulating layer GI3 and the second interlayer insulating layer ILD2 in the seventh via V7 are etched away, exposing the surface of the first electrode T1s of the first transistor T1 and part of the surface of the first initial signal line Vinit1. In the second type of via, the fourth via V4 exposes at least part of the surface of the first semiconductor layer AT1, and the fifth via V5, the sixth via V6 and the seventh via V7 expose at least part of the surface of the second semiconductor layer AT2.

[0247] (605) Remove the oxide layer of the first semiconductor AT1 layer within the second type of via. This is the same as step (505) above and will not be repeated here.

[0248] (606) Form the fourth conductive layer SD1.

[0249] In an exemplary embodiment, forming the fourth conductive layer SD1 may include: depositing a fourth conductive film on the side of the second interlayer insulating layer ILD2 away from the substrate BS, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer covering the second interlayer insulating layer ILD2, as shown in FIG10e. The fourth conductive layer includes, but is not limited to, the second electrode T6d of the sixth transistor T6, the first connection structure CS1, the second connection structure CS2, and the third connection structure CS3, as shown in FIG4f, which is a cross-sectional view of the structure along A1-A1 in FIG10e. The second electrode T6d of the sixth transistor T6 is electrically connected to the active layer T6a of the sixth transistor T6 through the fourth via V4, and the third connection structure CS3... The second connection structure CS2 is electrically connected to the surface of the active layer T6a of the sixth transistor T6 away from the substrate BS via the fifth via V5, and the surface of the second terminal T2d of the second transistor T2 (which is also the first terminal T6a of the sixth transistor T6) away from the substrate BS via the sixth via V6, and the surface of the gate T3g of the third transistor T3 away from the substrate BS via the sixth via V6, and the surface of the first terminal T1 of the first transistor T1 away from the substrate BS via the seventh via V7, and the surface of the first initial signal line Vinit1 away from the substrate BS.

[0250] In the exemplary embodiment, the fabrication process of the display substrate shown in FIG4g is basically the same as steps (601) to (606) described above, but differs from steps (605) and (606) in steps (601) to (606) described above, wherein:

[0251] The difference from step (605) is that after forming the second type of via, the surface of the first semiconductor layer AT1 in the fourth via V4 and the fifth via V5 is wet-etched to remove the oxide layer on the surface of the first semiconductor layer AT1 and remove the second semiconductor layer AT2 in the second type of via. The second semiconductor layer AT2 in the sixth via V6 and the seventh via V7 is etched away, so that the fourth conductive layer SD1 formed subsequently can be electrically connected to the sidewall of the second semiconductor layer AT2 in the sixth via V6 and the seventh via V7. That is, based on Figure 10d, the second semiconductor layer AT2 in the sixth via V6 and the seventh via V7 is etched away, as shown in Figure 11a.

[0252] The difference from step (606) is that the third connection structure CS3 is electrically connected to the sidewall of the second electrode T2d of the second transistor T2 (which is also the first electrode T6a of the sixth transistor T6) near the fifth via V5 through the fifth via V5. The second connection structure CS2 is electrically connected to the sidewall of the first electrode T2s of the second transistor T2 (which is also the second electrode T1d of the first transistor T1) near the sixth via V6 through the sixth via V6. The first connection structure CS1 is electrically connected to the sidewall of the first electrode T1 of the first transistor T1 near the seventh via V7 through the seventh via V7. As shown in Figure 11b, it is a schematic diagram of the planar structure after the fourth conductive layer SD1 is formed. The cross-sectional structure schematic diagram along the B1-B1 position in Figure 11b is shown in Figure 4g.

[0253] This disclosure also provides a display device, as shown in FIG12, which may include the display substrate of any of the foregoing embodiments. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0254] This disclosure also provides a method for preparing the above-described display substrate, which may include (for example, a method for preparing the display substrate shown in Figures 4a to 4g):

[0255] Multiple sub-pixels are formed on one side of the substrate BS. At least one sub-pixel includes a pixel driving circuit, which includes at least one first-type transistor TL and at least one second-type transistor TO. The at least one first-type transistor TL includes a driving transistor T3. In a direction perpendicular to the plane of the substrate BS, at least a portion of the active layer TOa of the second-type transistor TO is located on the side of the gate T3g of the driving transistor T3 away from the substrate BS. The at least a portion of the second-type transistor TO includes at least one first-type electrode Tds, which is connected to the gate T3g of the driving transistor T3. The at least one first-type electrode Tds includes the first or second electrode of at least one transistor in the at least a portion of the second-type transistor TO. The active layer TOa of the second-type transistor TO is disposed on the same layer as the first-type electrode Tds.

[0256] In an exemplary embodiment, forming a plurality of sub-pixels on one side of the substrate BS may at least include (e.g., a method for preparing the display substrate shown in Figures 4a to 4e):

[0257] A first gate metal layer Gate1 is formed on one side of the substrate BS, and the first gate metal layer Gate1 includes the gate of the first type of transistor TL;

[0258] A first interlayer insulating layer ILD1 is formed on the side of the first gate metal layer Gate1 away from the substrate BS. At least one first type via VL is provided on the first interlayer insulating layer ILD1. The first type via VL corresponding to the gate T3g of the driving transistor T3 exposes at least a portion of the surface of the gate T3g of the driving transistor T3.

[0259] A second semiconductor layer AT2 is formed on the side of the first interlayer insulating layer ILD1 away from the substrate BS. The second semiconductor layer AT2 includes at least one first type electrode Tds and an active layer TOa of the second type transistor TO. At least a portion of the first type vias VL correspond one-to-one with at least a portion of the first type electrodes Tds. The first type electrodes Tds are connected to the gate T3g of the driving transistor T3 through the corresponding first type vias VL.

[0260] In an exemplary embodiment, after forming the second semiconductor layer AT2 on the side of the first interlayer insulating layer ILD1 away from the substrate BS, the method may further include (for example, a method for preparing the display substrate shown in FIG4b, FIG4d to FIG4e):

[0261] A second interlayer insulating layer ILD2 is formed on the side of the second semiconductor layer AT2 away from the substrate BS. At least one second type via VO is provided on the second interlayer insulating layer ILD2. The second type via VO corresponding to the gate T3g of the driving transistor T3 exposes at least a portion of the surface of the gate T3g of the driving transistor T3.

[0262] A first source / drain metal layer SD1 is formed on the side of the second interlayer insulating layer ILD2 away from the substrate BS. The first source / drain metal layer SD1 may include at least one connection structure CS. The at least one connection structure CS corresponds one-to-one with at least a portion of the second type via VO, at least a portion of the first type electrode Tds, and at least a portion of the second type via VO. The gate T3g of the driving transistor T3 and the corresponding first type electrode Tds are connected to the corresponding connection structure CS at the corresponding second type via VO position.

[0263] In an exemplary embodiment, after forming the second semiconductor layer AT2 on the side of the first interlayer insulating layer ILD1 away from the substrate BS and before forming the second interlayer insulating layer ILD2 on the side of the second semiconductor layer AT2 away from the substrate BS, the method may further include (for example, a method for preparing the display substrate shown in FIG4a to FIG4e):

[0264] A third gate insulating layer GI3 is formed on the side of the second semiconductor layer AT2 away from the substrate BS;

[0265] A third gate metal layer Gate3 is formed on the side of the third gate insulating layer GI3 away from the substrate BS. The third gate metal layer Gate3 includes the first gate of the second type transistor TO. The orthographic projection of the first gate of the second type transistor TO on the substrate BS at least partially overlaps with the orthographic projection of the active layer TOa of the corresponding second type transistor TO on the substrate BS.

[0266] In an exemplary embodiment, after forming the first gate metal layer Gate1 on one side of the substrate BS and before forming the second semiconductor layer AT2 on the side of the first interlayer insulating layer ILD1 away from the substrate BS, the method may further include (for example, a method for preparing the display substrate shown in Figures 4a to 4e):

[0267] A second gate insulating layer GI2 is formed on the side of the first gate metal layer Gate1 away from the substrate BS;

[0268] A second gate metal layer Gate2 is formed on the side of the second gate insulating layer GI2 away from the substrate BS, and the second gate metal layer Gate2 includes the second gate of the second type of transistor TO.

[0269] In an exemplary embodiment, the formation of a plurality of sub-pixels on one side of the substrate BS may include at least (e.g., a method for preparing the display substrate shown in Figures 4f to 4g):

[0270] A first gate metal layer Gate1 is formed on one side of the substrate BS, and the first gate metal layer Gate1 includes the gate T3g of the driving transistor T3 in the at least one pixel driving circuit;

[0271] A second interlayer insulating layer ILD2 is formed on the side of the first gate metal layer Gate1 away from the substrate BS. At least one second type via VO is provided on the second interlayer insulating layer ILD2. The second type via VO corresponding to the gate T3g of the driving transistor T3 exposes at least a portion of the surface of the gate T3g of the driving transistor T3.

[0272] A first source / drain metal layer SD1 is formed on the side of the second interlayer insulating layer ILD2 away from the substrate BS. The first source / drain metal layer SD1 includes at least one connection structure CS. The at least one connection structure CS corresponds one-to-one with at least a portion of the second type via VO and at least a portion of the first type electrode Tds. The gate T3g of the driving transistor T3 and the corresponding first type electrode Tds are connected to the corresponding connection structure CS at the corresponding second type via VO position.

[0273] In an exemplary embodiment, after forming the first gate metal layer Gate1 on one side of the substrate BS and before forming the second interlayer insulating layer ILD2 on the side of the first gate metal layer Gate1 away from the substrate BS, the method may further include (for example, a method for preparing the display substrate shown in Figures 4f to 4g):

[0274] On the side of the first gate metal layer Gate1 away from the substrate BS, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a second semiconductor layer AT2, a third gate insulating layer GI3, and a third gate metal layer Gate3 are sequentially formed. The second semiconductor layer AT2 includes at least one first type electrode Tds and an active layer TOa of the second type transistor TO. The second gate metal layer Gate2 includes the second gate of the second type transistor TO. The third gate metal layer Gate3 includes the first gate of the second type transistor TO. The orthographic projection of the first gate of the second type transistor TO onto the substrate BS at least partially overlaps with the orthographic projection of the corresponding active layer TOa of the second type transistor TO onto the substrate BS.

[0275] In an exemplary embodiment, after forming the third gate metal layer Gate3 and before forming the second interlayer insulating layer ILD2, the method may further include (for example, a method for preparing the display substrate shown in Figures 4a to 4g):

[0276] The region of the second semiconductor layer AT2 that is not blocked by the first gate of the second type transistor TO is subjected to a conductor treatment to form a conductor region. The conductor region in the second semiconductor layer AT2 includes at least the at least one first type electrode Tds.

[0277] The display substrate and its fabrication method, as well as the display device provided in this disclosure, involve a gate of a driving transistor being connected to the first or second electrode of at least one second type transistor. The first or second electrode of the second type transistor connected to the gate of the driving transistor is disposed on the same layer as the active layer of the second type transistor. This simplifies the signal routing in the display area of ​​the display substrate, reduces the number of vias, improves the resolution, aperture ratio, and transmittance of the display substrate, and reduces design complexity. The accompanying drawings of this disclosure only illustrate the structures involved in the embodiments of this disclosure; other structures can be referenced from general designs.

[0278] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0279] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit the scope of these embodiments. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The substrate and a plurality of sub-pixels arranged on one side of the substrate, at least one sub-pixel comprising a pixel driving circuit, at least one pixel driving circuit comprising at least one first type transistor and at least one second type transistor; the at least one first type transistor comprises a driving transistor, and in a direction perpendicular to a plane where the substrate is located, an active layer of the at least part of the second type transistor is located on a side of a gate of the driving transistor away from the substrate; The at least part of the second type transistor comprises at least one first type electrode, the first type electrode is connected with the gate of the driving transistor in an overlap manner, and the at least one first type electrode comprises a first electrode or a second electrode of at least one transistor in the at least part of the second type transistor, and the active layer of the second type transistor is arranged in a same layer as the first type electrode. 2.The display substrate of claim 1, wherein, The display substrate is provided with at least one first type via hole, and at least part of the first type via hole corresponds to at least part of the first type electrode in a one-to-one manner, and the first type electrode is connected with the gate of the driving transistor in an overlap manner through the corresponding first type via hole. 3.The display substrate of claim 2, wherein, The display substrate is provided with at least one second type via hole, and the pixel driving circuit further comprises at least one connection structure, and in a direction perpendicular to a plane where the substrate is located, the connection structure is located on a side of an active layer of the second type transistor away from the substrate; The at least one connection structure corresponds to at least part of the second type via hole and at least part of the first type electrode in a one-to-one manner, and the gate of the driving transistor and the corresponding first type electrode are connected with the corresponding connection structure in an overlap manner at the position of the corresponding second type via hole. 4.The display substrate of claim 3, wherein, In the first type via hole and the second type via hole corresponding to the same first type electrode, a normal projection of the first type via hole on the substrate at least partially overlaps a normal projection of the second type via hole on the substrate. 5.The display substrate of claim 4, wherein, In the first type via hole and the second type via hole corresponding to the same first type electrode, a normal projection of the first type via hole on the substrate covers a normal projection of the corresponding second type via hole on the substrate. 6.The display substrate according to any one of claims 2 to 5, wherein A normal projection of the first type electrode on the substrate covers a normal projection of the corresponding first type via hole on the substrate. 7.The display substrate according to any one of claims 2 to 5, wherein The normal projection of the first type electrode on the substrate at least partially overlaps the normal projection of the corresponding first type via hole on the substrate, and at least part of the two does not overlap. 8.The display substrate of claim 1, wherein, The display substrate is provided with at least one second type via hole, and the pixel driving circuit further comprises at least one connection structure, and in a direction perpendicular to a plane where the substrate is located, the connection structure is located on a side of an active layer of the second type transistor away from the substrate; The at least one connection structure corresponds to at least part of the second type via hole and at least part of the first type electrode in a one-to-one manner, and the gate of the driving transistor and the corresponding first type electrode are connected with the corresponding connection structure in an overlap manner at the position of the corresponding second type via hole. 9.The display substrate according to any one of claims 3 to 5 and 8, wherein At least part of a surface of the gate of the driving transistor away from the substrate and a sidewall of the corresponding first type electrode close to the corresponding second type via hole are connected with the corresponding connection structure in an overlap manner through the corresponding second type via hole.

10. The display substrate according to any one of claims 3 to 5, 8, wherein, The gate of the driving transistor is connected to at least part of the surface of the substrate away from the substrate, the sidewall of the corresponding second type via hole close to the corresponding first type electrode, and at least part of the surface of the corresponding first type electrode away from the substrate through the corresponding second type via hole and the corresponding connecting structure.

11. The display substrate according to any one of claims 3 to 5, 8, wherein, The active layer of the first type transistor is located in the first semiconductor layer, and the active layer of the second type transistor is located in the second semiconductor layer, which is located away from the substrate on the side of the first semiconductor layer; the at least one second type transistor includes a first reset transistor and a compensation transistor, and the second electrode of the first reset transistor and the first electrode of the compensation transistor are located in the conductorized region in the second semiconductor layer. The first type electrode includes the second electrode of the first reset transistor and the first electrode of the compensation transistor, and the second electrode of the first reset transistor and the first electrode of the compensation transistor are connected to each other and connected to the gate of the driving transistor. 12.The display substrate of claim 11, wherein, The at least one first type transistor further includes a first light emitting control transistor, the active layer of the first light emitting control transistor is connected to the second electrode of the compensation transistor and the first electrode of the first light emitting control transistor, and the first electrode of the first light emitting control transistor is located in the conductorized region in the second semiconductor layer and connected to the second electrode of the compensation transistor.

13. The display substrate of claim 12, further comprising a first initial signal line, the first initial signal line is located on the side of the second semiconductor layer close to the substrate in the direction perpendicular to the plane where the substrate is located, the first electrode of the first reset transistor is connected to the first initial signal line, and the first electrode of the first reset transistor is located in the conductorized region in the second semiconductor layer. 14.The display substrate of claim 13, wherein, The connecting structure includes a first connecting structure, a second connecting structure and a third connecting structure, and the second type via hole includes a fifth via hole, a sixth via hole and a seventh via hole; The first connecting structure is connected to the first initial signal line and the first electrode of the first reset transistor through the seventh via hole; The second connecting structure is connected to the gate of the driving transistor, the second electrode of the first reset transistor and the first electrode of the compensation transistor through the sixth via hole; The third connecting structure is connected to the active layer of the first light emitting control transistor and the second electrode of the compensation transistor through the fifth via hole.

15. The display substrate according to any one of claims 2 to 5, further comprising a first initial signal line, the active layer of the first type of transistor is located in a first semiconductor layer, the active layer of the second type of transistor is located in a second semiconductor layer, in a direction perpendicular to the plane in which the substrate lies, the second semiconductor layer is located on a side of the first semiconductor layer away from the substrate, and the first initial signal line is located on a side of the second semiconductor layer close to the substrate; the at least one first type of transistor further comprises a first light-emitting control transistor, and the at least one second type of transistor comprises a first reset transistor and a compensation transistor; the first type of electrode comprises a second electrode of the first reset transistor and a first electrode of the compensation transistor, the second electrode of the first reset transistor, the first electrode of the compensation transistor, and a first electrode of the first light-emitting control transistor are located in a conductorized region in the second semiconductor layer, the second electrode of the first reset transistor and the first electrode of the compensation transistor are connected to each other, and the first electrode of the first light-emitting control transistor is connected to a second electrode of the compensation transistor; the first type of via comprises a first via, a second via, and a third via, the first electrode of the first reset transistor is connected to the first initial signal line through the first via, the second electrode of the first reset transistor and the first electrode of the compensation transistor are connected to the gate of the driving transistor through the second via, and the second electrode of the compensation transistor and the first electrode of the first light-emitting control transistor are connected to the active layer of the first light-emitting control transistor through the third via.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A method for manufacturing a display substrate, comprising: forming a plurality of sub-pixels on one side of a substrate, at least one sub-pixel comprising a pixel driving circuit, and at least one pixel driving circuit comprising at least one first type of transistor and at least one second type of transistor; the at least one first type of transistor comprising a driving transistor, and in a direction perpendicular to the plane in which the substrate lies, the active layer of at least part of the second type of transistor is located on a side of the gate of the driving transistor away from the substrate; the at least part of the second type of transistor comprising at least one first type of electrode, the first type of electrode being connected to the gate of the driving transistor through a via, and the active layer of the second type of transistor being disposed in the same layer as the first type of electrode. the forming a plurality of sub-pixels on one side of a substrate comprises:

18. The method of manufacturing the display substrate according to claim 17, wherein forming a first gate metal layer on one side of the substrate, the first gate metal layer comprising the gate of the first type of transistor; forming a first interlayer insulating layer on a side of the first gate metal layer away from the substrate, and the first interlayer insulating layer being provided with at least one first type of via, and the first type of via corresponding to the gate of the driving transistor exposing at least part of the surface of the gate of the driving transistor; ​ A second semiconductor layer is formed on the side of the first interlayer insulating layer away from the substrate, the second semiconductor layer comprising the at least one first type electrode and the active layer of the second type transistor, at least part of the first type via hole corresponding to at least part of the first type electrode, and the first type electrode being connected to the gate of the driving transistor through the corresponding first type via hole.

19. The method of manufacturing the display substrate according to claim 18, wherein, After the second semiconductor layer is formed on the side of the first interlayer insulating layer away from the substrate, the method further comprises: A second interlayer insulating layer is formed on the side of the second semiconductor layer away from the substrate, the second interlayer insulating layer being provided with at least one second type via hole, and at least part of the surface of the gate of the driving transistor being exposed through the second type via hole corresponding to the gate of the driving transistor; A first source / drain metal layer is formed on the side of the second interlayer insulating layer away from the substrate, the first source / drain metal layer comprising at least one connection structure, the at least one connection structure corresponding to at least part of the second type via hole, at least part of the first type electrode, and at least part of the second type via hole, and the gate of the driving transistor and the corresponding first type electrode being connected to the corresponding connection structure at the position of the corresponding second type via hole.

20. The method of manufacturing the display substrate according to claim 17, wherein, The method of forming a plurality of sub-pixels on the side of the substrate comprises at least: A first gate metal layer is formed on the side of the substrate, the first gate metal layer comprising the gate of the driving transistor in the at least one pixel driving circuit; A second interlayer insulating layer is formed on the side of the first gate metal layer away from the substrate, the second interlayer insulating layer being provided with at least one second type via hole, and at least part of the surface of the gate of the driving transistor being exposed through the second type via hole corresponding to the gate of the driving transistor; A first source / drain metal layer is formed on the side of the second interlayer insulating layer away from the substrate, the first source / drain metal layer comprising at least one connection structure, the at least one connection structure corresponding to at least part of the second type via hole, at least part of the first type electrode, and at least part of the second type via hole, and the gate of the driving transistor and the corresponding first type electrode being connected to the corresponding connection structure at the position of the corresponding second type via hole. ​

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