Gate drive circuit and display panel

Abstract

A gate drive circuit and a display panel. A first control module (10) transmits a forward scanning control signal (U2D) or a backward scanning control signal (U2D) to a first node (N1) on the basis of a first control signal (Ct1) and a second control signal (Ct2); a second control module (20) transmits a first clock signal (CK1) or a second clock signal (CK2) to a second node (N2) on the basis of the first control signal (Ct1) and the second control signal (Ct2); and on the basis of a signal from the second node (N2) and switch control signals (SC1, SC2), a switching control module (40) controls a switching frequency for two switch transistors (Ts1, Ts2), which operate alternately, in a potential holding module (30).

Description

Gate drive circuit and display panel

[0001] The present application claims priority to the Chinese patent application No. 202411103197.1, filed on August 12, 2024, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0002] The present application relates to, but is not limited to, the technical field of display, in particular to a gate drive circuit and a display panel. BACKGROUND

[0003] Threshold voltage shift of transistors caused by long time bias will lead to increase of transistor leakage current. In a gate drive circuit, threshold voltage shift of transistors connected to a key node caused by bias will cause potential change of the key node, thereby affecting working state of output transistors electrically connected to the key node, and further affecting working stability of the gate drive circuit. SUMMARY

[0004] The embodiments of the present application provide a gate drive circuit and a display panel, which can improve the working stability of the gate drive circuit.

[0005] The embodiments of the present application provide a gate drive circuit, a plurality of cascaded gate drive sub-circuits, the gate drive sub-circuit comprising a first control module, a second control module, a potential maintaining module, a switching control module and an output module. The first control module is electrically connected to a first node, and the first control module is configured to receive a first control signal and a second control signal, and transmit one of a forward scanning control signal and a reverse scanning control signal to the first node. The first control signal is a start signal or a gate control signal output by a previous stage gate drive sub-circuit of the gate drive sub-circuit, and the second control signal is a gate control signal output by a subsequent stage gate drive sub-circuit of the gate drive sub-circuit. The second control module is electrically connected to a second node, and the second control module is configured to receive the first control signal and the second control signal, and transmit one of a first clock signal and a second clock signal to the second node. The potential maintaining module is electrically connected to the first node and a first power supply terminal, and the potential maintaining module comprises two switching transistors. The switching control module is electrically connected between the second node and the potential maintaining module, and the switching control module is configured to control switching frequency of alternating work of the two switching transistors according to a signal of the second node and a received switching control signal. The output module is electrically connected to the first node, and the output module is configured to output a gate control signal to an output terminal of the gate drive circuit.

[0006] The display panel provided in the present application comprises any of the above-mentioned gate drive circuits. The pulse width of the active pulse of the switch control signal is less than or equal to the time length of one frame of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1 is a structural schematic diagram of a gate drive circuit provided in an embodiment of the present application;

[0008] FIG. 2 is a principle block diagram of a gate drive sub-circuit provided in an embodiment of the present application;

[0009] FIGS. 3A-3B are structural schematic diagrams of a gate drive sub-circuit provided in an embodiment of the present application;

[0010] FIGS. 4A-4B are timing diagrams corresponding to the gate drive sub-circuit shown in FIG. 3A;

[0011] FIGS. 4C-4D are timing diagrams corresponding to the gate drive sub-circuit shown in FIG. 3B;

[0012] FIG. 5 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0013] FIG. 6 is a comparison diagram for verifying the gate drive sub-circuit shown in FIGS. 3A-3B. Embodiments of the present application

[0014] To make the objectives, technical solutions and effects of the present application clearer and more explicit, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0015] The embodiments of the present application provide a gate drive circuit and a display panel. The first control module transmits one of the forward scan control signal and the reverse scan control signal to the first node according to the first control signal and the second control signal, so as to raise or lower the potential of the first node. The second control module transmits one of the first clock signal and the second clock signal to the second node according to the first control signal and the second control signal, and the switching control module controls the switching frequency of the two switching transistors in the potential maintaining module to alternate work according to the signal of the second node and the received switch control signal, so as to reduce the time length of each switching transistor subjected to the bias stress, and then improve the problem that the threshold voltage of the switching transistor deviates, the potential of the first node changes, the output module normally outputs, and the working stability of the gate drive circuit is affected.

[0016] FIG. 1 is a structural schematic diagram of a gate drive circuit provided in an embodiment of the present application. The present application provides a gate drive circuit GM comprising a plurality of cascaded gate drive sub-circuits GA. Each gate drive sub-circuit GA is configured to output a gate control signal.

[0017] Fig. 2 is a principle block diagram of a gate drive sub-circuit according to an embodiment of the present application. The gate drive sub-circuit GA comprises a first control module 10, a second control module 20, a potential maintaining module 30, a switching control module 40 and an output module 50.

[0018] The first control module 10 is electrically connected to the first node N1. The first control module 10 is configured to receive a first control signal Ct1 and a second control signal Ct2, and transmit one of a forward scan control signal U2D and a reverse scan control signal D2U to the first node N1 to raise or lower the potential of the first node N1.

[0019] The forward scan control signal U2D and the reverse scan control signal D2U are opposite to each other, so that one of the forward scan control signal U2D and the reverse scan control signal D2U is used to raise the potential of the first node N1, and the other of the forward scan control signal U2D and the reverse scan control signal D2U is used to lower the potential of the first node N1.

[0020] Optionally, the first control module 10 is configured to transmit the forward scan control signal U2D to the first node N1 according to the first control signal Ct1 to raise the potential of the first node N1; and the first control module 10 is configured to transmit the reverse scan control signal D2U to the first node N1 according to the second control signal Ct2 to lower the potential of the first node N1. The first control signal Ct1 can be referred to as a pull-up control signal, and the second control signal Ct2 can be referred to as a pull-down control signal.

[0021] Optionally, the first control module 10 is configured to transmit the forward scan control signal U2D to the first node N1 according to the first control signal Ct1 to lower the potential of the first node N1; and the first control module 10 is configured to transmit the reverse scan control signal D2U to the first node N1 according to the second control signal Ct2 to raise the potential of the first node N1. The first control signal Ct1 can be referred to as a pull-down control signal, and the second control signal Ct2 can be referred to as a pull-up control signal.

[0022] Optionally, the first control signal Ct1 is a start signal or a gate control signal output by a previous stage gate drive sub-circuit of the gate drive sub-circuit GA, and the second control signal Ct2 is a gate control signal output by a subsequent stage gate drive sub-circuit of the gate drive sub-circuit GA.

[0023] The first control signal Ct1 corresponding to the nth-stage gate driving sub-circuit GA(n) is the nth-A-stage gate control signal G(n-A) output by the nth-A-stage gate driving sub-circuit GA(n-A), and the second control signal Ct2 corresponding to the nth-stage gate driving sub-circuit GA(n) is the nth+A-stage gate control signal G(n+A) output by the nth+A-stage gate driving sub-circuit GA(n+A). Wherein, n>1, A≥1.

[0024] In the embodiment, for any one target gate driving sub-circuit other than the first-stage gate driving sub-circuit and the last-stage gate driving sub-circuit in the plurality of cascaded gate driving sub-circuits GA, the gate driving sub-circuit cascaded before the target gate driving sub-circuit is the preceding-stage gate driving sub-circuit of the target gate driving sub-circuit, and the gate driving sub-circuit cascaded after the target gate driving sub-circuit is the following-stage gate driving sub-circuit of the target gate driving sub-circuit.

[0025] Please continue to refer to FIG. 1. The first control signal Ct1 corresponding to the nth-stage gate driving sub-circuit GA(n) is the nth-2-stage gate control signal G(n-2) output by the nth-2-stage gate driving sub-circuit GA(n-2), and the second control signal Ct2 corresponding to the nth-stage gate driving sub-circuit GA(n) is the nth+2-stage gate control signal G(n+2) output by the nth+2-stage gate driving sub-circuit GA(n+2).

[0026] Optionally, the first control signal Ct1 corresponding to the first m-stage gate driving sub-circuit GA in the plurality of gate driving sub-circuits GA is a start signal. For example, the first control signal Ct1 corresponding to the first-stage gate driving sub-circuit GA(1) is a first start signal, the first control signal Ct1 corresponding to the second-stage gate driving sub-circuit GA(2) is a second start signal, the first control signal Ct1 corresponding to the third-stage gate driving sub-circuit GA(3) is the first-stage gate control signal G(1) output by the first-stage gate driving sub-circuit GA(1); the second control signal Ct2 corresponding to the first-stage gate driving sub-circuit GA(1) is the third-stage gate control signal G(3) output by the third-stage gate driving sub-circuit GA(3), the second control signal Ct2 corresponding to the second-stage gate driving sub-circuit GA(2) is the fourth-stage gate control signal G(4) output by the fourth-stage gate driving sub-circuit GA(4), and the second control signal Ct2 corresponding to the third-stage gate driving sub-circuit GA(3) is the fifth-stage gate control signal G(5) output by the fifth-stage gate driving sub-circuit GA(5).

[0027] Optionally, the second control signal Ct2 corresponding to the mth gate drive sub-circuit in the multi-stage gate drive sub-circuit GA is a start signal. For example, the gate drive circuit GM includes X gate drive sub-circuits GA, the first control signal Ct1 corresponding to the Xth gate drive sub-circuit GA(X) is the (X-2)th gate control signal G(X-2) output by the (X-2)th gate drive sub-circuit GA(X-2), the first control signal Ct1 corresponding to the (X-1)th gate drive sub-circuit GA(X-1) is the (X-3)th gate control signal G(X-3) output by the (X-3)th gate drive sub-circuit GA(X-3), and the first control signal Ct1 corresponding to the (X-2)th gate drive sub-circuit GA(X-2) is the (X-4)th gate control signal G(X-4) output by the (X-4)th gate drive sub-circuit GA(X-4). The second control signal Ct2 corresponding to the Xth gate drive sub-circuit GA(X) is a first start signal, the second control signal Ct2 corresponding to the (X-1)th gate drive sub-circuit GA(X-1) is a second start signal, and the second control signal Ct2 corresponding to the (X-2)th gate drive sub-circuit GA(X-2) is the Xth gate control signal G(X) output by the Xth gate drive sub-circuit GA(X).

[0028] Please continue to refer to FIG. 2. The second control module 20 is electrically connected to the second node N2. The second control module 20 is configured to receive the first control signal Ct1 and the second control signal Ct2, and transmit one of the first clock signal CK1 and the second clock signal CK2 to the second node N2.

[0029] The potential maintaining module 30 is electrically connected to the first node N1 and the first power terminal VGL. The potential maintaining module 30 includes two switching transistors.

[0030] The switching control module 40 is electrically connected between the second node N2 and the potential maintaining module 30. The switching control module 40 is configured to control the switching frequency of the two switching transistors according to the signal of the second node N2 and the received switching control signal SC.

[0031] The output module 50 is electrically connected to the first node N1. The output module 50 is configured to output the gate control signal. For example, G(n) in FIG. 1 represents the nth gate control signal output by the nth gate drive sub-circuit GA(n).

[0032] The first control module 10 transmits one of the positive scan control signal U2D and the negative scan control signal D2U to the first node N1 according to the first control signal Ct1 and the second control signal Ct2 to raise or lower the potential of the first node N1. The second control module 20 transmits one of the first clock signal CK1 and the second clock signal CK2 to the second node N2 according to the first control signal Ct1 and the second control signal Ct2, and the switching control module 40 controls the switching frequency of the alternately working two switch transistors in the potential maintaining module 30 according to the signal of the second node N2 and the received switch control signal SC, thereby reducing the time length of the bias stress on each switch transistor, and then improving the problem that the threshold voltage of the switch transistor deviates, the potential of the first node N1 changes, the normal output of the output module 50 is affected, and the stability of the gate drive circuit is affected.

[0033] FIGS. 3A-3B are structural schematic diagrams of a gate drive sub-circuit according to an embodiment of the present application. The two switch transistors include a first switch transistor Ts1 and a second switch transistor Ts2.

[0034] The first switch transistor Ts1 includes a control end electrically connected to the switching control module 40, a first source-drain end electrically connected to the first power supply end VGL, and a second source-drain end electrically connected to the first node N1.

[0035] The second switch transistor Ts2 includes a control end electrically connected to the switching control module 40, a first source-drain end electrically connected to the first power supply end VGL, and a second source-drain end electrically connected to the first node N1.

[0036] The switching control module 40 controls the switching frequency of the alternately working first switch transistor Ts1 and second switch transistor Ts2, so that the first power supply end VGL is electrically connected to the first node N1 through the first switch transistor Ts1 or the second switch transistor Ts2.

[0037] Optionally, the first switch transistor Ts1 and the second switch transistor Ts2 can be both P-type transistors or both N-type transistors. Optionally, the first switch transistor Ts1 is one of a P-type transistor and an N-type transistor, and the second switch transistor Ts2 is the other one of the P-type transistor and the N-type transistor.

[0038] Please continue to refer to FIG. 3A. The switch control signal SC includes a first switch control signal SC1 and a second switch control signal SC2, and the switching control module 40 includes a third switch transistor Ts3 and a fourth switch transistor Ts4.

[0039] The third switch transistor Ts3 includes a control terminal electrically connected to the second node N2, a first source-drain terminal configured to receive the first switch control signal SC1, and a second source-drain terminal electrically connected to the control terminal of the first switch transistor Ts1.

[0040] The fourth switch transistor Ts4 includes a control terminal electrically connected to the second node N2, a first source-drain terminal configured to receive the second switch control signal SC2, and a second source-drain terminal electrically connected to the control terminal of the second switch transistor Ts2.

[0041] To avoid the switching control module 40 affecting the working state of the gate drive sub-circuit GA, the third switch transistor Ts3 and the fourth switch transistor Ts4 are both N-type transistors or both P-type transistors.

[0042] When the third switch transistor Ts3 is turned on, the first switch control signal SC1 is transmitted to the control terminal of the first switch transistor Ts1 to realize the on-off control of the first switch transistor Ts1. When the fourth switch transistor Ts4 is turned on, the second switch control signal SC2 is transmitted to the control terminal of the second switch transistor Ts2 to realize the on-off control of the second switch transistor Ts2.

[0043] To enable the first switch transistor Ts1 and the second switch transistor Ts2 to work alternately, the first switch control signal SC1 and the second switch control signal SC2 are inverted.

[0044] Alternatively, the first switch transistor Ts1 and the second switch transistor Ts2 can also be controlled by the same switch control signal SC to realize alternate working, so as to reduce the number of switch control signals SC used by the gate drive sub-circuit GA. For example, the first switch transistor Ts1 is a P-type transistor, the second switch transistor Ts2 is an N-type transistor, and the switching control module 40 includes a third switch transistor Ts3. The third switch transistor Ts3 includes a control terminal electrically connected to the second node N2, a first source-drain terminal configured to receive the switch control signal SC, and a second source-drain terminal electrically connected to the control terminal of the first switch transistor Ts1 and the control terminal of the second switch transistor Ts2.

[0045] Referring to FIG. 3A, the first control module 10 includes a first transistor T1 and a second transistor T2.

[0046] The first transistor T1 includes a control terminal configured to receive a first control signal Ct1, a first source-drain terminal configured to receive a positive scan control signal U2D, and a second source-drain terminal electrically connected to the first node N1.

[0047] The second transistor T2 includes a control terminal configured to receive a second control signal Ct2, a first source-drain terminal configured to receive a reverse scan control signal D2U, and a second source-drain terminal electrically connected to the first node N1.

[0048] Referring to FIG. 3A, the second control module 20 includes a third transistor T3 and a fourth transistor T4.

[0049] The third transistor T3 includes a control terminal configured to receive a first control signal Ct1, a first source-drain terminal configured to receive a first clock signal CK1, and a second source-drain terminal electrically connected to the second node N2.

[0050] The fourth transistor T4 includes a control terminal configured to receive a second control signal Ct2, a first source-drain terminal configured to receive a second clock signal CK2, and a second source-drain terminal electrically connected to the second node N2.

[0051] Referring to FIG. 2, the gate driving sub-circuit GA includes a third control module 60 electrically connected to the first node N1, the second node N2, and the third node N3, and configured to control one of the first power supply end VGL and the second power supply end VGH to be electrically connected to the third node N3 according to signals of the first node N1 and the second node N2.

[0052] Referring to FIG. 3A, the third control module 60 includes a fifth transistor T5 and a sixth transistor T6.

[0053] The fifth transistor T5 includes a control terminal electrically connected to the first node N1, a first source-drain terminal electrically connected to the first power supply end VGL, and a second source-drain terminal electrically connected to the third node N3.

[0054] The sixth transistor T6 includes a control terminal electrically connected to the second node N2, a first source-drain terminal electrically connected to the second power supply end VGH, and a second source-drain terminal electrically connected to the third node N3.

[0055] The third switch transistor Ts3 and the fourth switch transistor Ts4 are synchronously turned on or turned off with the sixth transistor T6, so that the switching control module 40 electrically connects the first node N1 to the first power supply end VGL in a period corresponding to a time when the gate control signal does not need to output an effective level, thereby avoiding the switching control module 40 from affecting the normal operation of the gate driving sub-circuit GA.

[0056] Optionally, the voltage supplied by the first power supply end VGL is less than the voltage supplied by the second power supply end VGH.

[0057] Please continue to refer to FIG. 2 and FIG. 3A, the output module 50 is electrically connected with the third node N3 and the first power supply end VGL. The output module 50 comprises a first output transistor To1, a second output transistor To2, a first capacitor C1 and a second capacitor C2.

[0058] The first output transistor To1 comprises a control end electrically connected with the first node N1, a first source-drain end configured to receive the third clock signal CK3, and a second source-drain end electrically connected with the output end of the gate driving sub-circuit GA.

[0059] The second output transistor To2 comprises a control end electrically connected with the third node N3, a first source-drain end electrically connected with the first power supply end VGL, and a second source-drain end electrically connected with the output end of the gate driving sub-circuit GA.

[0060] The first capacitor C1 is connected in series between the first node N1 and the first power supply end VGL, and the second capacitor C2 is connected in series between the third node N3 and the first power supply end VGL.

[0061] Optionally, the multi-stage gate driving sub-circuit GA can share multiple clock signals. The phase difference between the first clock signal CK1 corresponding to each gate driving circuit GA and the third clock signal CK3 is equal to the phase difference between the third clock signal CK3 and the second clock signal CK2. For example, the first clock signal corresponding to the nth gate driving sub-circuit GA(n) is CK(N+2), the second clock signal is CK(N-2), and the third clock signal is CK(N). The phase difference between the clock signal CK(N+2) and the clock signal CK(N) is equal to the phase difference between the clock signal CK(N) and the clock signal CK(N-2). Wherein, N>2.

[0062] Optionally, the gate driving sub-circuit GA can further comprise an output control module 70, so that the level state of the gate control signal output by the gate driving sub-circuit GA directly changes to an effective level or an ineffective level.

[0063] Please continue to refer to FIG. 2, the output control module 70 is electrically connected with the third node N3, the first power supply end VGL and the output end of the gate driving sub-circuit GA. The output control module 70 is configured to control the signal transmission between the first power supply end VGL and the output end of the gate driving sub-circuit GA according to the first output control signal Gas1, or control the electrical connection between the first power supply end VGL and the third node N3 according to the second output control signal Gas2, and transmit the second output control signal Gas2 to the output end of the gate driving sub-circuit GA.

[0064] Please continue to refer to FIG. 3A, the output control module 70 includes a seventh transistor T7, the seventh transistor T7 includes a control end receiving a first output control signal Gas1, a first source-drain end electrically connected with a first power supply end VGL, and a second source-drain end electrically connected with an output end of the gate driving sub-circuit GA. In this way, the voltage of the gate control signal can be controlled to correspond to the voltage supplied by the first power supply end VGL according to the first output control signal Gas1.

[0065] Please refer to FIG. 3A, the output control module 70 includes an eighth transistor T8 and a ninth transistor T9.

[0066] The eighth transistor T8 includes a control end and a first source-drain end receiving a second output control signal Gas2, and a second source-drain end electrically connected with an output end of the gate driving sub-circuit GA. The ninth transistor T9 includes a control end receiving the second output control signal Gas2, a first source-drain end electrically connected with the first power supply end VGL, and a second source-drain end electrically connected with the third node N3. In this way, the second output transistor To2 can be turned off according to the second output control signal Gas2, so that the level of the gate control signal output by the gate driving sub-circuit GA corresponds to the level of the second output control signal Gas2.

[0067] Please continue to refer to FIG. 3A, in some embodiments, the gate driving sub-circuit GA further includes a tenth transistor T10, the tenth transistor T10 includes a first source-drain end electrically connected with the first node N1, and a second source-drain end electrically connected with a control end of the first output transistor To1. Optionally, the tenth transistor T10 is an N-type transistor, a control end of a second power supply end VGH is electrically connected with the second power supply end VGH; or, the tenth transistor T10 is a P-type transistor, a control end of the second power supply end VGH is electrically connected with the first power supply end VGL, so that the tenth transistor T10 is always in a conductive state.

[0068] It should be noted that the above-mentioned control end is a gate, the above-mentioned first source-drain end can be one of a source and a drain, and the above-mentioned second source-drain end is the other of the source and the drain.

[0069] Optionally, in some embodiments, the gate driving sub-circuit GA includes a first frequency division transistor, a second frequency division transistor, and a third capacitor. The first frequency division transistor includes a control end electrically connected with the third node N3, a first source-drain end configured to receive a frequency division control signal, and a second source-drain end. The second frequency division transistor includes a control end electrically connected with the second source-drain end of the first frequency division transistor, a first source-drain end electrically connected with the first node N1, and a second source-drain end electrically connected with the control end of the first output transistor To1 and the first capacitor C1. The third capacitor is connected in series between the control end of the second frequency division transistor and the second power supply end of the second frequency division transistor.

[0070] When the frequency division control signal has the active level and the potential of the first node N1 in the gate drive sub-circuit GA has been pulled up by the forward scan control signal U2D or the reverse scan control signal D2U, the first frequency division transistor in the gate drive sub-circuit GA is configured to be turned off according to the signal of the third node, while the second frequency division transistor remains turned on, so as to keep the first output transistor To1 in the gate drive sub-circuit GA turned on. After the potential of the first node N1 in the gate drive sub-circuit GA has been pulled up by the forward scan control signal U2D or the reverse scan control signal D2U, the frequency division control signal has the inactive level, the first frequency division transistor in the gate drive sub-circuit GA is configured to be turned off according to the signal of the third node, while the second frequency division transistor remains turned on, so as to keep the first output transistor To1 in the gate drive sub-circuit GA turned on, so that the gate control signal output by the gate drive sub-circuit GA does not appear abnormal due to the level jump (i.e. from the active level to the inactive level) of the frequency division control signal.

[0071] When the frequency division control signal has the active level and the potential of the first node N1 in the gate drive sub-circuit GA has not been pulled up by the forward scan control signal U2D or the reverse scan control signal D2U, the first frequency division transistor in the gate drive sub-circuit GA is configured to be turned on according to the signal of the third node, while the second frequency division transistor is turned on according to the frequency division control signal, so as to electrically connect the first output transistor To1 and the first node N1. When the frequency division control signal has the inactive level and the potential of the first node N1 in the gate drive sub-circuit GA has not been pulled up by the forward scan control signal U2D or the reverse scan control signal D2U, the first frequency division transistor in the gate drive sub-circuit GA is configured to be turned on according to the signal of the third node, while the second frequency division transistor is turned off according to the frequency division control signal, so as to disconnect the electrical connection between the first output transistor To1 and the first node N1.

[0072] Thus, by arranging the first frequency division transistor, the second frequency division transistor and the third capacitor, the gate control signal output by part of the gate drive sub-circuit GA can have the active pulse according to the frequency division control signal and the potential of the third node N3, while the gate control signal output by part of the gate drive sub-circuit does not have the active pulse. When the gate drive circuit is used in a display panel, the design of the display panel can support the realization of the frequency division in the partition.

[0073] FIGS. 4A-4B are timing diagrams of the gate driving sub-circuit shown in FIG. 3A. In the case where the transistors included in the gate driving sub-circuit GA are N-type transistors, the first control signal Ct1 corresponding to the nth gate driving sub-circuit GA(n) is the (n-2)th gate control signal G(n-2) output by the (n-2)th gate driving sub-circuit GA(n-2), and the second control signal Ct2 corresponding to the nth gate driving sub-circuit GA(n) is the (n+2)th gate control signal G(n+2) output by the (n+2)th gate driving sub-circuit GA(n+2). The working principle of the nth gate driving sub-circuit GA(n) is described below.

[0074] Please continue to refer to FIGS. 3A and 4A. The forward scanning control signal U2D is at a high level, the reverse scanning control signal D2U is at a low level, and the first output control signal Gas1 and the second output control signal Gas2 are at low levels.

[0075] The first stage t1: the first control signal Ct1 and the second clock signal CK2 are at high levels, and the second control signal Ct2, the first clock signal CK1, and the third clock signal CK3 are at low levels. The first transistor T1, the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the first output transistor To1 are turned on, and the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the first to fourth switching transistors Ts1-Ts4, and the second output transistor To2 are turned off. The forward scanning control signal U2D is transmitted to the first node N1, and the third node N3 is electrically connected to the first power supply end VGL.

[0076] The second stage t2: the third clock signal CK3 is at a high level, and the first control signal Ct1, the second control signal Ct2, the first clock signal CK1, and the second clock signal CK2 are at low levels. The first capacitor C1 has a holding effect on the charge, and the first output transistor To1 maintains the on state. The high level of the third clock signal CK3 is output to the output end of the nth gate driving sub-circuit GA(n) to make the nth gate control signal G(n) have a high level.

[0077] The third stage t3: the first control signal Ct1, the second control signal Ct2, the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are at low levels. The first capacitor C1 has a holding effect on the potential of the first node N1, and the low level of the third clock signal CK3 is output to the output end of the nth gate driving sub-circuit GA(n) to make the nth gate control signal G(n) have a low level.

[0078] The fourth stage t4: the first clock signal CK1, the second clock signal CK2 and the second control signal Ct2 are high level, the third clock signal CK3 and the first control signal Ct1 are low level. The second transistor T2, the third transistor T3, the sixth transistor T6, the tenth transistor T10 and the second output transistor To2 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the first output transistor To1 are turned off. The inverse scanning control signal D2U is transmitted to the first node N1 to pull down the potential of the first node N1.

[0079] In the fourth stage t4 and the fifth stage t5, after the first node N1 becomes low level, the first output transistor To1 is in the off state. The positive scanning control signal U2D is high level to turn on the third transistor T3. When the first clock signal CK1 jumps to high level, the sixth transistor T6 is turned on, the second power supply end VGH charges the third node N3, and the second output transistor To2 is turned on to make the first power supply end VGL electrically connected with the output end of the gate driving sub-circuit GA, so that the nth gate control signal G(n) remains stable low level. At the same time, the second capacitor C2 has a retaining effect on the high level of the third node N3.

[0080] In the fifth stage t5, the third switch transistor Ts3 and the fourth switch transistor Ts4 are turned on. When the first switch control signal SC1 is high level and the second switch control signal SC2 is low level, the first switch transistor Ts1 is turned on and the second switch transistor Ts2 is turned off. When the first switch control signal SC1 is low level and the second switch control signal SC2 is high level, the first switch transistor Ts1 is turned off and the second switch transistor is turned on. Therefore, the signal of the first node N1 can be guaranteed to have stable low level. In the fifth stage, the first switch transistor Ts1 and the second switch transistor Ts2 can be in the alternating working state all the time.

[0081] Please continue to refer to FIG. 3A and FIG. 4B. The inverse scanning control signal D2U is high level, the positive scanning control signal U2D is low level, the first output control signal Gas1 and the second output control signal Gas2 are low level.

[0082] The first stage t1: the second control signal Ct2 and the first clock signal CK1 are high level, the first control signal Ct1, the second clock signal CK2 and the third clock signal CK3 are low level. The second transistor T2, the fourth transistor T4, the fifth transistor T5, the tenth transistor T10 and the first output transistor To1 are turned on, the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the first switch transistor Ts1 to the fourth switch transistor Ts4 and the second output transistor To2 are cut off. The inverse scanning control signal D2U is transmitted to the first node N1, and the third node N3 is electrically connected with the first power supply end VGL.

[0083] The second stage t2: the third clock signal CK3 is high level, the first control signal Ct1, the second control signal Ct2, the first clock signal CK1 and the second clock signal CK2 are low level. The first capacitor C1 has a holding effect on the charge, and the first output transistor To1 maintains the on state, and the high level of the third clock signal CK3 is output to the output end of the nth gate driving sub-circuit GA(n) to make the nth gate control signal G(n) have high level.

[0084] The third stage t3: the first control signal Ct1, the second control signal Ct2, the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 are low level. The first capacitor C1 has a holding effect on the potential of the first node N1, and the low level of the third clock signal CK3 is output to the output end of the nth gate driving sub-circuit GA(n) to make the nth gate control signal G(n) have low level.

[0085] The fourth stage t4: the first clock signal CK1, the second clock signal CK2 and the first control signal Ct1 are high level, the third clock signal CK3 and the second control signal Ct2 are low level. The first transistor T1, the fourth transistor T4, the sixth transistor T6, the tenth transistor T10 and the second output transistor To2 are turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the first output transistor To1 are cut off. The positive scanning control signal U2D is transmitted to the first node N1 to pull down the potential of the first node N1.

[0086] In the fourth stage t4 and the fifth stage t5, the first node N1 becomes low level, and the first output transistor To1 is in the off state. The fourth transistor T4 is turned on by the high level of the inverse scan control signal D2U, and the sixth transistor T6 is turned on when the second clock signal CK2 jumps to high level. The second power supply end VGH charges the third node N3, and the second output transistor To2 is turned on to make the first power supply end VGL electrically connected to the output end of the gate drive sub-circuit GA, so that the nth gate control signal G(n) remains stable at low level. Meanwhile, the second capacitor C2 has a retaining effect on the high level of the third node N3.

[0087] In the fifth stage t5, the third switch transistor Ts3 and the fourth switch transistor Ts4 are turned on. When the first switch control signal SC1 is high level, the second switch control signal SC2 is low level, the first switch transistor Ts1 is turned on, and the second switch transistor Ts2 is turned off. When the first switch control signal SC1 is low level, the second switch control signal SC2 is high level, the first switch transistor Ts1 is turned off, and the second switch transistor is turned on. Therefore, the signal of the first node N1 can be guaranteed to have stable low level. In the fifth stage, the first switch transistor Ts1 and the second switch transistor Ts2 can be in an alternating working state.

[0088] In addition, corresponding to FIG. 3A and FIG. 4A-FIG. 4B, the plurality of gate drive sub-circuits GA share the first output control signal Gas1 and the second output control signal Gas2. When the first output control signal Gas1 is high level, the output end of each gate drive sub-circuit GA is electrically connected to the first power supply end VGL, so that the plurality of gate control signals output by the gate drive circuit GM all have low level. When the second output control signal Gas2 is high level, the output end of each gate drive sub-circuit GA corresponds to output the second output control signal Gas2, so that the plurality of gate control signals output by the gate drive circuit GM all have high level.

[0089] FIG. 3B is a comparative embodiment corresponding to FIG. 3A, and FIG. 4C-FIG. 4D are timing diagrams corresponding to the gate drive sub-circuit GA shown in FIG. 3B. It should be noted that the gate drive sub-circuit GA shown in FIG. 3B is only used to form a contrast with the gate drive sub-circuit GA shown in FIG. 3A, and should not be understood as prior art.

[0090] In the gate drive sub-circuit GA shown in FIG. 3B, the gate drive sub-circuit GA includes N-type first to thirteenth sub-transistors NT1-NT13, a first capacitor C1 and a second capacitor C2.

[0091] Please continue to refer to FIG. 3B and FIG. 4C, the forward scan control signal U2D is high, the backward scan control signal D2U is low, the first output control signal Gas1 and the second output control signal Gas2 are low.

[0092] The first stage t1: the first control signal Ct1 and the second clock signal CK2 are high, the first sub transistor NT1 is turned on, and the forward scan control signal U2D precharges the first node N1. When the first node N1 is high, the seventh sub transistor NT7 and the sixth sub transistor NT6 are turned on, and the fifth sub transistor NT5 is turned off, and the first power supply end VGL is electrically connected with the third node N3.

[0093] The second stage t2: the third clock signal CK3 is high, the first capacitor C1 has a holding effect on the charge so that the ninth sub transistor NT9 is turned on, and the high level of the third clock signal CK3 is output to the output end of the nth gate driving sub circuit GA(n) so that the nth gate control signal G(n) has a high level.

[0094] The third stage t3: the first capacitor C1 has a holding effect on the high level of the first node N1, and the low level of the third clock signal CK3 is output to the output end of the nth gate driving sub circuit GA(n).

[0095] The fourth stage t4: the second control signal Ct2 is high, the second sub transistor NT2 is turned on, and the backward scan control signal D2U is transmitted to the first node N1.

[0096] The fifth stage t5: the first node N1 maintains low, and the ninth sub transistor NT9 is turned off. The forward scan control signal U2D is high so that the third sub transistor NT3 is turned on, and when the first clock signal CK1 jumps to high, the eighth sub transistor NT8 is turned on, the second power supply end VGH charges the third node N3, the fifth sub transistor NT5 and the tenth sub transistor NT10 are turned on, and the first power supply end VGL is electrically connected with the output end of the nth gate driving sub circuit GA(n) and the first node N1. At the same time, the second capacitor C2 has a holding effect on the high level of the third node N3. In the fifth stage t5, the fifth sub transistor NT5 is always in the on state.

[0097] Please continue to refer to FIG. 3B and FIG. 4D, the forward scan control signal U2D is high, the backward scan control signal D2U is low, the first output control signal Gas1 and the second output control signal Gas2 are low.

[0098] The first stage t1: the second control signal Ct2 and the first clock signal CK1 are high, the second sub transistor NT2 is turned on, and the inverse scanning control signal D2U is transmitted to the first node N1. When the first node N1 is high, the seventh sub transistor NT7, the sixth sub transistor NT6 and the ninth sub transistor NT9 are turned on, the fifth sub transistor NT5 is cut off, and the first power supply end VGL is electrically connected with the third node N3.

[0099] The second stage t2: the third clock signal CK3 is high, the first capacitor C1 has a holding effect on the charge so that the ninth sub transistor NT9 is turned on, and the high level of the third clock signal CK3 is output to the output end of the nth gate driving sub circuit GA(n).

[0100] The third stage t3: the first capacitor C1 has a holding effect on the high level of the first node N1, and the low level of the third clock signal CK3 is output to the output end of the nth gate driving sub circuit GA(n).

[0101] The fourth stage t4: the first control signal Ct1 is high, the first sub transistor NT1 is turned on, and the forward scanning control signal U2D is transmitted to the first node N1.

[0102] The fifth stage t5: the first node N1 maintains low, and the ninth sub transistor NT9 is cut off. The inverse scanning control signal D2U is high so that the fourth sub transistor NT4 is turned on. When the second clock signal CK2 jumps to high, the eighth sub transistor NT8 is turned on, the second power supply end VGH charges the third node N3, the fifth sub transistor NT5 and the tenth sub transistor NT10 are turned on, the first power supply end VGL is electrically connected with the output end of the nth gate driving sub circuit GA(n) and the first node N1. At the same time, the second capacitor C2 has a holding effect on the high level of the third node N3. In the fifth stage t5, the fifth sub transistor NT5 is always in the turned-on state.

[0103] Wherein, when the first output control signal Gas1 is high, the thirteenth sub transistor NT13 is turned on, and the output end of each gate driving sub circuit GA is electrically connected with the first power supply end VGL. When the second output control signal Gas2 is high, the eleventh sub transistor NT11 and the twelfth sub transistor NT12 are turned on, and the output end of each gate driving sub circuit GA outputs the second output control signal Gas2 correspondingly.

[0104] According to the analysis of FIG. 3B, FIG. 4C and FIG. 4D, in the gate driving sub-circuit GA shown in FIG. 3B, the fifth sub-transistor NT5 for electrically connecting the first power terminal VGL and the first node N1 is controlled by the signal of the third node N3. Thus, after the output effective level of the gate control signal, the fifth sub-transistor NT5 is continuously turned on, and with the passage of time, the threshold voltage of the fifth sub-transistor NT5 negatively moves increases due to the bias stress, the off-state leakage current of the fifth sub-transistor NT5 is large, which causes the potential of the first node N1 to change, thereby affecting the working state of the first output transistor To1, and then affecting the level of the gate control signal. With the passage of time, the threshold voltage of the fifth sub-transistor NT5 negatively moves increases due to the bias stress, which will cause the leakage current of the fifth sub-transistor NT5 to increase after the reliability test of the gate driving circuit GM, and easily cause the problem of abnormal output of the gate driving sub-circuit GA. When the gate driving sub-circuit GA is applied to the display panel, the problem of display abnormality is easily caused.

[0105] However, in the gate driving sub-circuit GA shown in FIG. 3A, the switching control module 40 is provided, and the switching control module 40 controls the switching frequency of the first switch transistor Ts1 and the second switch transistor Ts2 to work alternately according to the signal of the second node N2 and the received switch control signal SC. Thus, the length of time that the first switch transistor Ts1 and the second switch transistor Ts2 are subjected to the bias stress is shortened, thereby reducing the leakage current of the first switch transistor Ts1 and the second switch transistor Ts2, which is beneficial to reduce the probability of abnormal output of the gate driving sub-circuit GA.

[0106] Please continue to refer to FIG. 4A and FIG. 4B, the duty cycle of the first switch control signal SC1 and the second switch control signal SC2 is adjustable. That is, the pulse width T of the effective pulse of the switch control signal SC (including the first switch control signal SC1 and the second switch control signal SC2) is adjustable, and the time corresponding to the first switch control signal SC1 for maintaining the first switch transistor Ts1 to be turned on and the time corresponding to the second switch control signal SC2 for maintaining the second switch transistor Ts2 to be turned on are adjustable, so as to realize the power consumption of the gate driving circuit GM to be adjustable.

[0107] It can be understood that the longer the time corresponding to the first switch control signal SC1 for maintaining the first switch transistor Ts1 to be turned on, the more beneficial to reduce the power consumption. Similarly, the longer the time corresponding to the second switch control signal SC2 for maintaining the second switch transistor Ts2 to be turned on, the more beneficial to reduce the power consumption.

[0108] The first switch transistor Ts1 and the second switch transistor Ts2 are alternately operated according to the first switch control signal SC1 and the second switch control signal SC2, respectively. Therefore, even if the first switch control signal SC1 and the second switch control signal SC2 have relatively long active level periods, the total time length during which any of the first switch transistor Ts1 and the second switch transistor Ts2 is maintained in conduction is less than the conduction time length of the fifth sub-transistor NT5 in FIG. 3B. Therefore, when the first switch control signal SC1 and the second switch control signal SC2 have relatively long active level periods, the problem of the leakage current increasing due to the threshold voltage drift of the transistor and the problem of the gate drive circuit GM being unstable can be improved.

[0109] FIG. 5 is a structural schematic diagram of a display panel provided by an embodiment of the present application. The present application also provides a display panel, which includes any of the above-mentioned gate drive circuits GM.

[0110] The display panel includes a plurality of sub-pixels Spi, which are electrically connected to the gate drive circuit GM and are configured to realize the display function of the display panel.

[0111] Optionally, the pulse width of the active pulse of the switch control signal SC is less than or equal to the time length during which the display panel displays one frame, so as to improve the working stability of the gate drive circuit GM.

[0112] Optionally, the pulse width of the active pulse of the switch control signal SC is equal to the time length during which the display panel displays one frame, so as to improve the working stability of the gate drive circuit GM while reducing the power consumption of the display panel.

[0113] FIG. 6 is a comparison diagram for verifying the gate drive sub-circuit shown in FIGS. 3A-3B. In FIG. 6, the vertical coordinate corresponds to the current value of the leakage current, and the horizontal coordinate corresponds to the test time. L1 is a leakage current change curve corresponding to the gate drive sub-circuit GA shown in FIG. 3A, and L2 is a leakage current change curve corresponding to the gate drive sub-circuit GA shown in FIG. 3B.

[0114] The inventor actually verified the gate drive sub-circuit GA shown in FIGS. 3A-3B. In the verification experiment, the ambient temperature was 85°C, the light brightness was 20,000 nits, and the test duration was 7200 seconds. The gate-source voltage difference of the first switch transistor Ts1 in FIG. 3A was 17V, and the drain-source voltage difference of the first switch transistor Ts1 was equal to 17V and 0V, respectively. The gate-source voltage difference of the second switch transistor Ts2 was equal to 17V, and the drain-source voltage difference of the second switch transistor Ts2 was equal to 17V and 0V, respectively. The duty cycles of the first switch control signal SC1 and the second switch control signal SC2 were both 50%, so that the on durations of the first switch transistor Ts1 and the second switch transistor Ts2 were equal. The gate-source voltage difference of the fifth sub-transistor NT5 in FIG. 3B was equal to 17V, and the drain-source voltage difference of the fifth sub-transistor NT5 was equal to 0V.

[0115] The verification results show that, with the gate drive sub-circuit GA shown in FIG. 3A, the drain current of the first switch transistor Ts1 and the second switch transistor Ts2 is at most 2.5E-6A. With the gate drive sub-circuit GA shown in FIG. 3B, the drain current of the switch transistor is at most 2.96E-5A. Therefore, the gate drive sub-circuit GA shown in FIG. 3A can significantly reduce the risk of threshold voltage negative drift of the switch transistor, thereby improving the problem of display abnormality caused by large transistor drain current after 240 hours of reliability test (double 85).

[0116] It should be understood by those skilled in the art that modifications or equivalent replacements can be made to the embodiments of the present application without departing from the spirit and scope of the present application, and such modifications or equivalent replacements should be covered in the scope of the present application. The embodiments can be combined with each other but are not described one by one.

[0117] The principles and implementation modes of the present application are described by applying specific examples herein, and the above description of the embodiments is only for helping to understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation modes and application ranges will have changes, and the above description of the present application should not be understood as a limitation.

Claims

1. A gate drive circuit, wherein, The gate drive sub-circuit comprises a plurality of cascaded gate drive sub-circuits, and the gate drive sub-circuit comprises: A first control module is electrically connected with the first node and is configured to receive a first control signal and a second control signal and transmit one of a forward scanning control signal and a reverse scanning control signal to the first node; wherein the first control signal is a start signal or a gate control signal output by a previous-stage gate drive sub-circuit of the gate drive sub-circuit, and the second control signal is a gate control signal output by a subsequent-stage gate drive sub-circuit of the gate drive sub-circuit; A second control module is electrically connected with the second node and is configured to receive the first control signal and the second control signal and transmit one of a first clock signal and a second clock signal to the second node; A potential maintaining module is electrically connected with the first node and a first power supply end and comprises two switching transistors; A switching control module is electrically connected between the second node and the potential maintaining module and is configured to control a switching frequency of the two switching transistors according to a signal of the second node and a received switching control signal; and An output module is electrically connected with the first node and is configured to output a gate control signal to an output end of the gate drive circuit.

2. The gate drive circuit according to claim 1, wherein The two switching transistors comprise: A first switching transistor comprises a control end electrically connected with the switching control module, a first source-drain end electrically connected with the first power supply end, and a second source-drain end electrically connected with the first node; and A second switching transistor comprises a control end electrically connected with the switching control module, a first source-drain end electrically connected with the first power supply end, and a second source-drain end electrically connected with the first node.

3. The gate drive circuit of claim 2, wherein, The switching control signal comprises a first switching control signal and a second switching control signal, and the switching control module comprises: A third switching transistor comprises a control end electrically connected with the second node, a first source-drain end configured to receive the first switching control signal, and a second source-drain end electrically connected with the control end of the first switching transistor; and A fourth switching transistor comprises a control end electrically connected with the second node, a first source-drain end configured to receive the second switching control signal, and a second source-drain end electrically connected with the control end of the second switching transistor.

4. The gate drive circuit of claim 1, wherein, The first control module comprises: A first transistor comprises a control end configured to receive the first control signal, a first source-drain end configured to receive the forward scanning control signal, and a second source-drain end electrically connected with the first node; and A second transistor comprises a control end configured to receive the second control signal, a first source-drain end configured to receive the reverse scanning control signal, and a second source-drain end electrically connected with the first node; The forward scanning control signal and the reverse scanning control signal are in opposite phases.

5. The gate drive circuit of claim 1, wherein, The second control module comprises: A third transistor comprises a control end configured to receive the first control signal, a first source-drain end configured to receive the first clock signal, and a second source-drain end electrically connected with the second node; and A fourth transistor comprises a control end configured to receive the second control signal, a first source-drain end configured to receive the second clock signal, and a second source-drain end electrically connected with the second node. A fourth transistor includes a control terminal configured to receive the second control signal, a first source-drain terminal configured to receive the second clock signal, and a second source-drain terminal electrically connected to the second node.

6. The gate drive circuit of claim 1, wherein, The gate drive sub-circuit includes: A third control module is electrically connected to the first node, the second node, and a third node, and is configured to control one of the first power supply terminal and the second power supply terminal to be electrically connected to the third node according to signals of the first node and the second node.

7. The gate drive circuit of claim 6, wherein, The third control module includes: A fifth transistor includes a control terminal electrically connected to the first node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the third node; and A sixth transistor includes a control terminal electrically connected to the second node, a first source-drain terminal electrically connected to the second power supply terminal, and a second source-drain terminal electrically connected to the third node.

8. The gate drive circuit of claim 6, wherein, The output module is electrically connected to the third node and the first power supply terminal, and includes: A first output transistor includes a control terminal electrically connected to the first node, a first source-drain terminal configured to receive a third clock signal, and a second source-drain terminal electrically connected to an output terminal of the gate drive circuit; A second output transistor includes a control terminal electrically connected to the third node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the output terminal of the gate drive circuit; A first capacitor is connected in series between the first node and the first power supply terminal; and A second capacitor is connected in series between the third node and the first power supply terminal.

9. The gate drive circuit of claim 6, wherein, The gate drive sub-circuit includes: An output control module is electrically connected to the third node, the first power supply terminal, and the output terminal of the gate drive circuit, and is configured to control signal transmission between the first power supply terminal and the output terminal of the gate drive circuit according to a first output control signal, or to control electrical connection between the first power supply terminal and the third node according to a second output control signal, and to transmit the second output control signal to the output terminal of the gate drive circuit.

10. The gate drive circuit of claim 9, wherein, The output control module includes: A seventh transistor includes a control terminal configured to receive the first output control signal, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the output terminal of the gate drive circuit; An eighth transistor includes a control terminal configured to receive the second output control signal and a first source-drain terminal, and a second source-drain terminal electrically connected to the output terminal of the gate drive circuit; and A ninth transistor includes a control terminal configured to receive the second output control signal, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the third node.

11. The gate drive circuit of claim 8, wherein, The gate drive sub-circuit includes: A tenth transistor includes a control terminal electrically connected to the second power supply terminal, a first source-drain terminal electrically connected to the first node, and a second source-drain terminal electrically connected to the control terminal of the first output transistor.

12. The gate drive circuit of claim 3, wherein, The first switch control signal and the second switch control signal are inversely related.

13. The gate drive circuit of claim 2, wherein, The switching control module comprises: The third switch transistor comprises a control end electrically connected with the second node, a first source-drain end configured to receive the switching control signal, and a second source-drain end electrically connected with the control end of the first switch transistor and the control end of the second switch transistor.

14. A display panel, wherein, The gate drive circuit comprises the gate drive circuit according to any one of claims 1-13. The pulse width of the active pulse of the switching control signal is less than or equal to the time length of one frame of the display panel.

15. The display panel of claim 14, wherein, The display panel comprises a plurality of sub-pixels, and the plurality of sub-pixels are electrically connected with the gate drive circuit.

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