Bandwidth allocation method, server, device, medium and program product

Abstract

The present application relates to the technical field of servers. Disclosed are a bandwidth allocation method, a server, a device, a medium and a program product. The method comprises: in an initialization phase for initializing a PCIe device, monitoring a PCIe interface of a central processing unit; in response to having acquired first device information on the basis of a first channel of the PCIe interface and having acquired second device information on the basis of a second channel of the PCIe interface, determining whether the first device information is the same as the second device information; when the first device information is the same as the second device information, determining that the first channel and the second channel correspond to the same PCIe device, and on the basis of the first channel and the second channel, respectively feeding back acknowledgment signals; and on the basis of the correspondence between the PCIe interface and the PCIe device, performing bandwidth allocation. In the present application, by acquiring, on the basis of channels of a PCIe interface, device information uploaded by a corresponding PCIe device, relevant information of the PCIe device can be determined and bandwidth allocation can be performed, thereby enabling a simple implementation.

Description

Bandwidth allocation method, server, device, medium and program product

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411104838.5, filed on August 13, 2024, and entitled "Bandwidth allocation method, server, device, medium and program product", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of servers, and in particular to a bandwidth allocation method, a server, a device, a medium and a program product. BACKGROUND

[0004] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, mainly used to connect CPUs (Central Process Unit) and various expansion cards such as graphics cards, sound cards, network adapters, etc. The bandwidth of PCIe is closely related to its version and Lane number. For example, the theoretical maximum bandwidth of PCIe x1 slot is 1GB / s, which is suitable for devices with low data transmission requirements; the theoretical maximum bandwidth of PCIe x4 slot is 4GB / s, which is suitable for devices with medium bandwidth requirements; the theoretical maximum bandwidth of PCIe x8 slot is 8GB / s, which is suitable for devices with higher data transmission speed requirements; PCIe x16 slot has the highest theoretical maximum bandwidth of 16GB / s, and is widely used to connect high-performance graphics cards.

[0005] The PCIe interface on the server motherboard generally uses PCIe x8 slot or PCIe x16 slot. When a PCIe device with a small number of Lanes is inserted, the PCIe device cannot be recognized, and PCIe resources are wasted, which requires automatic recognition and allocation of PCIe bandwidth. SUMMARY

[0006] Therefore, the present application provides a bandwidth allocation method, a server, a device, a medium and a program product to automatically recognize and allocate PCIe bandwidth.

[0007] In some embodiments, the present application provides a bandwidth allocation method applied to a central processor of a server, comprising:

[0008] In an initialization phase of initializing the PCIe device, the PCIe interface of the central processor is listened to;

[0009] In response to obtaining the first device information based on the first channel of the PCIe interface and obtaining the second device information based on the second channel of the PCIe interface, it is determined whether the first device information and the second device information are the same; the first device information and the second device information are device information of a PCIe device connected to the PCIe interface.

[0010] In response to determining that the first device information and the second device information are the same, it is determined that the first channel and the second channel correspond to the same PCIe device, and a confirmation signal is fed back based on the first channel and the second channel, respectively; and

[0011] According to the correspondence between the PCIe interface and the PCIe device, bandwidth allocation is performed.

[0012] In some embodiments, in response to determining that the first device information and the second device information are the same, it is determined that the first channel and the second channel correspond to the same PCIe device, including:

[0013] In response to determining that the first device information and the second device information are the same, and the first channel and the second channel are adjacent, it is determined that the first channel and the second channel correspond to the same PCIe device; and

[0014] In response to determining that the first channel and the second channel are not adjacent, it is determined that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device.

[0015] In some embodiments, in response to determining that the first channel and the second channel are not adjacent, it is determined that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device, including:

[0016] In response to determining that the first channel and the second channel are not adjacent, and the device information obtained by the other channels between the first channel and the second channel is the same as the first device information and / or the second device information, it is determined that the first channel, the second channel, and the other channels between the first channel and the second channel correspond to the same PCIe device.

[0017] In some embodiments, each channel of the PCIe device is configured to send device information to the central processor, and the method further includes:

[0018] In response to determining that the first device information and the second device information are the same, and the first channel and the second channel are not adjacent, and there is a fourth channel between the first channel and the second channel that does not receive device information, it is determined that the fourth channel link is abnormal.

[0019] In some embodiments, the method further includes:

[0020] In response to obtaining the third device information based on the third channel of the PCIe interface, and the third device information being different from the obtained other device information, determining that the third channel corresponds to one PCIe device with a channel number of 1, and feeding back a confirmation signal based on the third channel.

[0021] In some embodiments, the method further comprises:

[0022] In response to determining that the PCIe interface does not receive the device information in an initialization phase of initializing the PCIe device, performing bandwidth allocation based on a default bandwidth allocation strategy.

[0023] In some embodiments, after obtaining the fifth device information based on the fifth channel of the PCIe interface and feeding back a confirmation signal based on the fifth channel, in response to determining that abnormal information different from the fifth device information is obtained based on the fifth channel, it is determined that there is an unrecognized channel connected to the PCIe device.

[0024] In some embodiments, after obtaining the fifth device information based on the fifth channel of the PCIe interface and feeding back a confirmation signal based on the fifth channel, in response to determining that abnormal information different from the fifth device information is obtained based on the fifth channel, it is determined that there is an unrecognized channel connected to the PCIe device.

[0025] correcting the channel number of the PCIe device; and

[0026] In response to determining that the channel number cannot be corrected, taking the currently determined channel number as the minimum channel number of the PCIe device when performing bandwidth allocation.

[0027] In some embodiments, the PCIe device is configured to send the same device information to the central processor based on the first channel and the last channel in a cycle, wherein the first channel corresponds to the first channel and the second channel corresponds to the last channel.

[0028] In some embodiments, the bandwidth allocation is performed according to the correspondence between the PCIe interface and the PCIe device, comprising:

[0029] According to the correspondence between each channel of the PCIe interface and the PCIe device, the bandwidth allocation is performed according to the channel number of the PCIe device.

[0030] In some embodiments, the present application provides a bandwidth allocation method applied to a PCIe device, comprising:

[0031] obtaining a bandwidth configuration instruction issued by a baseboard management controller based on a system management bus;

[0032] The device information of the PCIe device is sent to the central processor of the server based on a first channel cycle, and the same device information is sent to the central processor based on a last channel cycle; the first channel is the first channel of the PCIe device, and the last channel is the last channel of the PCIe device; and

[0033] In response to obtaining the confirmation signal based on the first channel and the last channel, the sending of the device information based on the first channel and the last channel is stopped.

[0034] In some embodiments, the method further comprises:

[0035] In response to determining that the number of channels of the PCIe device is not less than 3, the same device information is sent to the central processor based on other channels except the first channel and the last channel; and

[0036] In response to obtaining the confirmation signal based on the other channels, the sending of the device information based on the other channels is stopped.

[0037] In some embodiments, the bandwidth configuration instruction issued by the baseboard management controller is obtained based on the system management bus, comprising:

[0038] The data frame in the system management bus is listened to; and

[0039] In response to listening to the data frame with the address identifier being all zeros, it is determined that the bandwidth configuration instruction is obtained.

[0040] In some embodiments, the method further comprises:

[0041] The vendor identification of the PCIe device is read from the vendor identification register, and the device identification of the PCIe device is read from the device identification register; and

[0042] The device information including the vendor identification and the device identification is generated.

[0043] In some embodiments, the bandwidth configuration instruction is broadcasted to the system management bus by the BCM; and

[0044] The PCIe device obtains the bandwidth configuration instruction by listening to the system management bus.

[0045] In some embodiments, the bandwidth configuration instruction issued by the baseboard management controller is obtained based on the system management bus, comprising:

[0046] It is judged whether the server has been powered off by alternating current power supply and whether the case cover has been opened; and

[0047] In response to determining that the server has been powered off by alternating current power supply and that the case cover has been opened, the bandwidth configuration instruction issued by the baseboard management controller is obtained based on the system management bus.

[0048] In some embodiments, after the first channel cycle and the last channel cycle send the device information of the PCIe device to the central processor of the server based on the first channel cycle and the last channel cycle send the same device information to the central processor, further comprising:

[0049] In response to the first channel receiving the acknowledgement signal and the last channel not receiving the acknowledgement signal, or in response to the first channel not receiving the acknowledgement signal and the last channel receiving the acknowledgement signal, converting the device information into exception information; and

[0050] Based on the first channel or the last channel having received the acknowledgement signal, sending the exception information to the central processor.

[0051] In some embodiments, the device information sent by the first channel and the last channel is used to instruct the central processor to determine that the first channel and the second channel receiving the same device information in the PCIe interface correspond to the first channel and the last channel of the PCIe device respectively, and based on the first channel and the second channel respectively feeding back the acknowledgement signal, the bandwidth is allocated according to the correspondence between each channel of the PCIe interface and the PCIe device according to the number of channels of the PCIe device.

[0052] In some embodiments, the present application provides a server, comprising: a baseboard management controller and a central processor;

[0053] The baseboard management controller is configured to issue a bandwidth configuration instruction to the PCIe device based on a system management bus;

[0054] The central processor is configured to execute the bandwidth allocation method described above.

[0055] In some embodiments, the present application provides a computer device, comprising:

[0056] One or more processors; and

[0057] A memory associated with the one or more processors, the memory being configured to store computer readable instructions, the computer readable instructions being configured to implement the bandwidth allocation method described above when read and executed by the one or more processors.

[0058] In some embodiments, the present application provides a non-volatile computer readable storage medium having stored thereon computer readable instructions, the computer readable instructions being configured to implement the bandwidth allocation method described above when executed by one or more processors.

[0059] In some embodiments, the present application provides a computer program product comprising computer readable instructions, the computer readable instructions being configured to implement the bandwidth allocation method described above when executed by one or more processors. BRIEF DESCRIPTION OF DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0061] Fig. 1 is a schematic diagram of a framework of bandwidth allocation by a CPU according to an embodiment of the present application;

[0062] Fig. 2 is a schematic diagram of a flow of a bandwidth allocation method according to an embodiment of the present application;

[0063] Fig. 3 is a schematic diagram of a flow of another bandwidth allocation method according to an embodiment of the present application;

[0064] Fig. 4 is a detailed flow chart of implementing bandwidth allocation according to an embodiment of the present application;

[0065] Fig. 5 is a structural block diagram of a bandwidth allocation apparatus according to an embodiment of the present application;

[0066] Fig. 6 is a structural block diagram of another bandwidth allocation apparatus according to an embodiment of the present application;

[0067] Fig. 7 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present application;

[0068] Fig. 8 is a schematic diagram of a hardware structure of a non-volatile computer readable storage medium according to an embodiment of the present application;

[0069] Fig. 9 is a schematic diagram of a hardware structure of a computer program product according to an embodiment of the present application. DETAILED DESCRIPTION

[0070] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0071] The baseboard management controller (BMC) is a hardware component specially used for monitoring and managing servers and other computer systems. It is located on the mainboard as an independent system, has its own processor and memory, can run independently of the host system, and can be accessed remotely through a network interface. The main functions and features of BMC include:

[0072] 1. Remote Monitoring and Management: BMC allows administrators to remotely monitor the health status of servers, including temperature, fan speed, power status, hard drive status, and chassis cover switch status, even when the operating system is not working.

[0073] 2. Fault Diagnosis and Alarm: When detecting system abnormalities such as overheating, voltage abnormalities or hardware failures, BMC can generate alarms and send them to the management system through the network, helping to quickly respond and troubleshoot.

[0074] 3. Hardware Control: BMC can control server operations such as power on, power off and restart, as well as adjust fan speed and other hardware configurations, thereby optimizing system performance and energy efficiency.

[0075] 4. Event Log Recording: Records important events during system operation, including hardware state changes and error information, providing historical data for system maintenance.

[0076] 5. Firmware Update: BMC itself also supports firmware updates to fix vulnerabilities, add new features or optimize performance, and can usually be updated remotely through the network.

[0077] 6. Compliance with Industry Standards: BMC complies with standards such as Intelligent Platform Management Interface (IPMI), ensuring interoperability between hardware and management software from different manufacturers.

[0078] 7. Security Features: Considering the remote access capabilities of BMC, modern BMC designs usually include security measures such as encrypted communication, Access Control Lists (ACL), authentication mechanisms, etc. to protect servers from unauthorized access and attacks.

[0079] In summary, the baseboard management controller is an indispensable part of modern data centers and enterprise IT (Internet Technology) infrastructure, providing powerful remote management capabilities that greatly improve server maintenance efficiency and system reliability.

[0080] PCIe takes a fundamental change in the bus structure, mainly in two aspects: one is from parallel bus to serial bus; two is to adopt point-to-point interconnection. The original parallel bus structure under the bridge hanging device is changed into a link, a link can contain one or more paths, each path is composed of two pairs of differential signal lines into a duplex serial transmission channel, without dedicated data, address, control and clock lines, various transactions on the bus are organized into information packets for transmission. Another feature of PCIe is to break through the traditional bus is to adopt point-to-point interconnection method, each device is connected by an independent link, and the bandwidth is shared, which is an effective solution to improve the transmission rate.

[0081] The PCIe interface on the server motherboard generally uses PCIe x8 slot or PCIe x16 slot, which is convenient for inserting different types of expansion cards later. Even if the gold finger on the expansion card is x2 or x4, it can also be inserted into the PCIe x8 slot or PCIe x16 slot. However, the bandwidth provided by the CPU to the PCIe x8 slot or PCIe x16 slot is the maximum bandwidth, which causes the expansion card with a small number of lanes to be unable to be effectively recognized. The CPU also allocates the maximum bandwidth, resulting in waste of PCIe resources and loss of CPU function. For example, two PCIE x8 devices are inserted into the PCIE x16 slot, and it is not possible to support two PCIE x8 devices in one PCIE x16 slot, that is, the automatic recognition and bandwidth allocation of PCIe cannot be realized.

[0082] Currently, the bandwidth can be dynamically configured using a GPIO (General Purpose Input Output) expansion device, or a physical detection circuit board resistance control current or voltage detection. Whether it is an expansion device detection or a physical resistance detection, a bandwidth allocation table needs to be added. After obtaining the change data, the value and the corresponding Lane number need to be matched with the bandwidth allocation table set in advance, and then the CPU analyzes the corresponding bandwidth for allocation. This requires early statistical data simulation table of different expansion cards, corresponding to the fixed type number of expansion cards. When the expansion card data that is not in the table is inserted, there is an identification error. When using, the table needs to be matched, and the overall identification and bandwidth allocation efficiency is low.

[0083] The embodiment of the present application provides a bandwidth allocation method, a BMC informs each PCIe device mounted by a server of bandwidth configuration by using a system management bus (SMBus), each PCIe device reports device information of the PCIe device based on a channel of the PCIe device, so that a CPU of the server can determine which pin in a PCIe interface is inserted into the PCIe device based on whether the obtained device information is same, and can determine the number of channels of the PCIe device, so that bandwidth allocation can be performed on the PCIe device.

[0084] Fig. 1 shows a schematic diagram of a framework of bandwidth allocation performed by a CPU of a server. As shown in Fig. 1, the server comprises a central processing unit (CPU) and a baseboard management controller (BMC). When bandwidth allocation is needed, the BMC sends a bandwidth configuration instruction to a PCIe device mounted by the server, so that the PCIe device can report device information of the PCIe device through each channel (Lane), so that the CPU can determine the number of channels of the PCIe device, and then perform bandwidth allocation based on the number of channels.

[0085] In the embodiment, a bandwidth allocation method is provided, which can be applied to a PCIe device, such as the PCIe device shown in Fig. 1. Fig. 2 is a flowchart of the bandwidth allocation method according to the embodiment of the present application. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a group of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0086] As shown in Fig. 2, the bandwidth allocation method comprises the following steps S201 to S203.

[0087] In step S201, a bandwidth configuration instruction issued by a baseboard management controller is obtained based on a system management bus.

[0088] In the embodiment, in response to determining that bandwidth needs to be reconfigured, the BMC can issue an instruction for reconfiguring bandwidth, i.e., a bandwidth configuration instruction, to a system management bus (SMBus), and the PCIe device can obtain the bandwidth configuration instruction based on the system management bus.

[0089] The bandwidth configuration instruction is a trigger instruction, and after the PCIe device receives the bandwidth configuration instruction, the PCIe device does not perform bandwidth configuration by itself, but cooperates with the CPU of the server to perform bandwidth configuration. For example, the bandwidth configuration instruction can be a mode switching instruction, and when the PCIe device receives the bandwidth configuration instruction, the PCIe device enters a bandwidth configuration mode.

[0090] Table 1 shows the interface definition of the front-end power interface part in the PCIe slot pin, and the A side and the B side are the two sides of the contact slot.

[0091] Table 1

[0092] As shown in Table 1, the PCIe slot reserves an SMBus interface, namely SMCLK (system management bus clock) and SMDAT (system management bus data). The BCM can broadcast a bandwidth configuration instruction to the system management bus, so that each PCIe device can obtain the bandwidth configuration instruction broadcasted by the BMC by listening to the system management bus.

[0093] In some embodiments, the BMC of the server can determine whether the bandwidth needs to be reconfigured after power-on; in some embodiments, the BMC can determine whether the server has experienced AC power outage and whether the case cover has been opened; in some embodiments, the BMC can determine whether the case cover has been opened by monitoring the opening and closing state of the case cover. If the server has experienced AC power outage and the case cover has been opened, it means that the server may have the situation of plugging and unplugging PCIe devices (such as replacing PCIe devices), so the CPU needs to reconfigure the bandwidth, that is, the BMC broadcasts a bandwidth configuration instruction to the system management bus.

[0094] In some embodiments, the step S201 of "obtaining the bandwidth configuration instruction issued by the baseboard management controller based on the system management bus" can include: listening to the data frame in the system management bus; and in response to listening to the data frame with an address identifier of all zeros, determining that the bandwidth configuration instruction is obtained.

[0095] In this embodiment, when the BMC broadcasts a bandwidth configuration instruction to the system management bus, in order to enable all PCIe devices to respond to the bandwidth configuration instruction, the address identifier of the bandwidth configuration instruction is set to all zeros, that is, the address identifier of the bandwidth configuration instruction is all zeros.

[0096] The address identifier is originally used to represent the address of the receiving device. In this embodiment, the address identifier of the bandwidth configuration instruction is set to all zeros, so that each PCIe device can respond to the bandwidth configuration instruction, and it is not necessary to send the bandwidth configuration instruction to each PCIe device in sequence. Moreover, the data frame with the address identifier of all zeros also has the highest processing priority, so that each PCIe device can process the bandwidth configuration instruction in priority.

[0097] Further, after the PCIe device is powered on, the system management bus can be monitored, and in response to determining that a certain data frame is monitored, it is determined whether the data frame is a bandwidth configuration instruction based on an address identifier of the data frame; and in response to determining that the address identifier of the data frame is all 0, the PCIe device can determine that the bandwidth configuration instruction is received.

[0098] Generally, after the PCIe device receives a certain data frame based on the system management bus, an ACK (Acknowledge character) needs to be fed back; for example, the PCIe device can pull down a data line corresponding to SMDAT for one bit of time. In the embodiment, since the all-0 address identifier is also different from the address of the PCIe device itself, the PCIe device does not need to feed back the ACK after receiving the bandwidth configuration instruction, which conforms to the provisions of the SMBus protocol, and multiple PCIe devices do not feed back the ACK, which is equivalent to that there is no slave device with an all-0 address, so that the normal operation of the system management bus can be ensured.

[0099] In step S202, the device information of the PCIe device is sent to the central processor of the server based on a first channel cycle, and the same device information is sent to the central processor based on a last channel cycle; the first channel is the first channel of the PCIe device, and the last channel is the last channel of the PCIe device.

[0100] Each PCIe device has unique device information, which can include a vendor ID (Vendor ID) and a device ID (Device ID) of the PCIe device.

[0101] In some embodiments, the process of obtaining the device information can include reading the vendor ID of the PCIe device from a vendor ID register and reading the device ID of the PCIe device from a device ID register; and generating the device information including the vendor ID and the device ID. The PCIe device maintains the vendor ID register and the device ID register, both of which are read-only memories; after the PCIe device is powered on (or after receiving the bandwidth configuration instruction), the vendor ID and the device ID of the PCIe device can be determined by reading the two registers, and then the device information to be reported can be generated.

[0102] In the embodiment, the PCIe device is connected to the PCIe interface of the CPU, as shown in FIG. 1, the PCIe device can be provided with a gold finger, through which the PCIe device can be connected to the PCIe interface of the CPU; and the data of each channel (Lane) of the PCIe device is transmitted to the CPU. For different PCIe devices, the number of channels can be different; for example, if the gold finger of the PCIe device is x4, the number of channels is 4, that is, four channels transmit data to the CPU.

[0103] On the basis of the above Table 1, in combination with the following Tables 2 to 5, the pin differences of PCIe x1 / x4 / x8 / x16 slots are described.

[0104] Table 2 shows the data interface definition of PCIe x1 slot. As shown in Table 2, the PCIe x1 slot includes one lane, i.e. lane 0. It can be understood that the pins of Table 1 and Table 2 jointly constitute the pins of PCIe x1 slot, in other words, the PCIe x1 slot contains 18 pins.

[0105] Table 2

[0106] Table 3 shows the subsequent data interface definition of PCIe x4 slot. As shown in Table 3, three pairs of differential signals and corresponding ground wires form three lanes, plus lane 0 shown in Table 2, all lanes of PCIe x4 slot are formed, i.e. the PCIe x4 slot includes four lanes, i.e. lanes 0-3. Similarly, the pins of Table 1, Table 2 and Table 3 jointly constitute the pins of PCIe x4 slot, in other words, the PCIe x4 slot contains 32 pins.

[0107] Table 3

[0108] Table 4 shows the subsequent data interface definition of PCIe x8 slot. In combination with Tables 1 to 4, it can be known that the PCIe x8 slot includes eight lanes, i.e. lanes 0-7.

[0109] Table 4

[0110] Table 5 shows the subsequent data interface definition of PCIe x8 slot. In combination with Tables 1 to 5, it can be known that the PCIe x16 slot includes sixteen lanes, i.e. lanes 0-15.

[0111] Table 5

[0112] In this embodiment, for the convenience of description, the first lane of the PCIe device is referred to as the "first lane", and the last lane of the PCIe device is referred to as the "last lane". For example, if the PCIe device is an x8 device, it has lanes 0-7, the first lane is lane 0, and the last lane is lane 7.

[0113] In the bandwidth configuration mode, after obtaining the device information, the PCIe device sends the device information to the CPU of the server at least on the first channel and the last channel, that is, the information sent by the first channel and the last channel is the same. In order to avoid the failure of receiving the device information due to the incomplete start of the server, the PCIe device reports the device information on the first channel and the last channel in a cycle, for example, once every interval (for example, 0.5s, 1s, etc.), that is, the device information is reported once to ensure that the server can receive the device information. The device information is used for the CPU to determine the number of channels of the PCIe device, which will be explained later.

[0114] It can be understood that if the PCIe device is an x1 device, it has one channel, so the first channel and the last channel are one channel, and at this time, the device information can be uploaded using only the unique channel.

[0115] Step S203, in response to obtaining the confirmation signal based on the first channel and the last channel, stop sending the device information based on the first channel and the last channel.

[0116] In this embodiment, after the CPU of the server receives the device information, it will feed back an acknowledgement signal (ACK signal) to the PCIe device through each channel. In response to determining that the PCIe device obtains the confirmation signal based on the first channel and the last channel, the PCIe device can determine that the CPU has successfully received the device information sent by each channel, and the PCIe device can stop sending the device information.

[0117] In this embodiment, the PCIe device can also set the total time length of sending the device information, for example, the PCIe device can set the time length of the bandwidth configuration mode, which is, for example, 10s. When the PCIe device receives the bandwidth configuration instruction, it enters the bandwidth configuration mode for 10s; in the bandwidth configuration mode, the device information is reported in a cycle, and in response to determining that the ACK signal fed back by the CPU is received, or because the time of 10s has been reached, the PCIe device exits the bandwidth configuration mode, and then the PCIe device stops sending the device information.

[0118] In some embodiments, each channel of the PCIe device is used to upload the device information. In some embodiments, the method further includes the following steps A1 to A2.

[0119] Step A1, in response to determining that the number of channels of the PCIe device is not less than 3, the same device information is sent to the central processor in a cycle based on the other channels except the first channel and the last channel.

[0120] Step A2, in response to obtaining the confirmation signal based on the other channels, stop sending the device information based on the other channels.

[0121] For example, if the PCIe device is an x4 device having channels 0-3, the PCIe device sends device information based on channel 0 (the first channel) and channel 3 (the last channel) in addition to sending device information based on the middle channels 1 and 2, so that the CPU can receive device information uploaded on all channels. Similarly, in response to determining that the middle channels 1 and 2 also respectively obtain the confirmation signal fed back by the CPU, the PCIe device stops sending device information to the CPU.

[0122] In addition, in response to determining that part of the channels of the PCIe device do not receive the confirmation signal, it can be determined that the link of the part of the channels is abnormal, and channel-granularity link detection can be implemented.

[0123] In some embodiments, the method further comprises: in response to the one of the first channel and the last channel receiving the confirmation signal and the other channel not receiving the confirmation signal, converting the device information into abnormal information; and sending the abnormal information to the central processor based on the first channel or the last channel that has received the confirmation signal.

[0124] In this embodiment, after sending the device information based on the first channel and the last channel, in response to determining that one of the channels A (for example, the first channel) receives the confirmation signal fed back by the CPU, but the other channel B (for example, the last channel) does not receive the confirmation signal fed back by the CPU, it can be determined that the link corresponding to the other channel B is abnormal. At this time, the CPU can not receive the device information of the other channel B, and the CPU can not know that there is a link abnormality problem; and because the CPU does not receive the device information of the other channel B, it will also lead to a misjudgment of the number of channels of the PCIe device.

[0125] In the above case, the PCIe device converts the original device information into abnormal information. For example, the device information includes a vendor identification and a device identification, and because the device identification is generally provided, when the device identification is all 1, it indicates that the device identification is invalid, so the device identification in the device information can be set to all 1, for example, the device identification is changed to 0xFFFF, thereby generating abnormal information of invalid device identification. And the PCIe device sends the abnormal information to the CPU based on the channel A that has received the confirmation signal, so that the CPU can determine the abnormal link after receiving the abnormal information, and then can try to determine the abnormal link or generate an alarm information to remind the operation and maintenance personnel to check the link.

[0126] If the first channel and the last channel both receive the confirmation signal, but the other channels in the middle do not receive the confirmation signal, because at this time the CPU can determine the abnormal link in the middle based on the first channel and the last channel, the PCIe device does not need to notify the CPU of the link abnormality by uploading abnormal information.

[0127] The bandwidth allocation method provided in the embodiment can enable the CPU of the server to determine the number of channels of the PCIe device based on the device information and determine which pins in the PCIe interface of the CPU are inserted with the PCIe device, so that the bandwidth allocation can be automatically performed. The method can be implemented based on the system management bus, without occupying GPIO resources or additional communication interfaces such as I2C (Inter-Integrated Circuit), and is simple to implement. Moreover, the bandwidth allocation table does not need to be set, and the bandwidth allocation efficiency can be improved.

[0128] In addition, the address identifier of the bandwidth configuration instruction is all zero, so that each PCIe device can obtain the bandwidth configuration instruction and can process the bandwidth configuration instruction in priority. Each channel of the PCIe device is used to upload the device information, which can further improve the accuracy of the CPU in identifying the PCIe device and enable the PCIe device link to be detected in the channel granularity.

[0129] In the embodiment, a bandwidth allocation method is provided, which can be applied to a central processing unit (CPU) of a server, such as the central processing unit shown in FIG. 1. FIG. 3 is a flowchart of the bandwidth allocation method according to the embodiment of the application. As shown in FIG. 3, the bandwidth allocation method includes the following steps S301 to S304.

[0130] In step S301, the PCIe interface of the CPU is listened to in an initialization phase of initializing the PCIe device.

[0131] In the embodiment, after the server is powered on, for example, after the server power-on button signal is triggered, the BIOS (Basic Input Output System) program of the server starts to run. When the PCIe device initialization is performed, the CPU can listen to the PCIe interface of the CPU to enter a state of receiving the device information uploaded by each channel. The CPU generally includes a plurality of PCIe interfaces, and the PCIe interface is a PCIe root port.

[0132] In step S302, in response to obtaining first device information based on a first channel of the PCIe interface and obtaining second device information based on a second channel of the PCIe interface, it is determined whether the first device information and the second device information are the same. The first device information and the second device information are both device information of the PCIe device connected to the PCIe interface.

[0133] In this embodiment, for a certain PCIe interface of the CPU, it includes multiple channels, for example, if the PCIe interface is an x16 interface, it includes 16 channels. For the first channel and the second channel, in response to determining that both channels obtain the device information sent by the PCIe device, the two device information can be compared. For ease of description, the device information obtained by the first channel is referred to as first device information, and the device information obtained by the second channel is referred to as second device information.

[0134] In some embodiments, by using the uniqueness of the device information, the CPU determines whether the first device information and the second device information are the same. If the first device information and the second device information are the same, it means that the first channel and the second channel are connected to the same PCIe device. If the first device information and the second device information are different, it can be considered that the first channel and the second channel are connected to different PCIe devices.

[0135] Among them, in response to determining that a certain channel of the PCIe interface does not receive the device information, it can be considered that the device information is empty or the device information is all 0.

[0136] In step S303, in response to determining that the first device information and the second device information are the same, it is determined that the first channel and the second channel correspond to the same PCIe device, and an acknowledgement signal is fed back based on the first channel and the second channel respectively.

[0137] As described above, in response to determining that the first device information and the second device information are the same, since the device information of different PCIe devices is different, that is, the device information has uniqueness, at this time it can be determined that the first channel and the second channel of the PCIe interface are connected to the same PCIe device. Moreover, the CPU also feeds back an acknowledgement signal (ACK signal) based on the first channel and the second channel respectively, to notify the PCIe device that the device information has been successfully received, and can instruct the PCIe device to stop uploading the device information.

[0138] It can be understood that if the first device information and the second device information are the same, the first device information can be the device information uploaded by the PCIe device based on its first channel, and the second device information can be the device information uploaded by the PCIe device based on its last channel.

[0139] Among them, if the PCIe device is an x1 device, the CPU has a channel to obtain the device information. In some embodiments, the method can further include: in response to obtaining third device information based on a third channel of the PCIe interface, and the third device information is different from other obtained device information, determining that the third channel corresponds to a PCIe device with a channel number of 1, and feeding back an acknowledgement signal based on the third channel.

[0140] In this embodiment, in response to determining that the PCIe interface has one channel obtaining the device information, i.e., the third channel obtains the third device information, but the device information obtained by the remaining channels are all different from the third device information, the CPU can determine that the PCIe device connected to the third channel is an x1 device, and the number of channels of the PCIe device is 1. Similarly, the CPU can also confirm the third channel to stop sending the device information based on the feedback confirmation signal of the third channel.

[0141] In some embodiments, the step S303 of determining that the first channel and the second channel correspond to the same PCIe device in response to determining that the first device information is the same as the second device information includes the following steps B1 to B2.

[0142] The step B1 includes determining that the first channel and the second channel correspond to the same PCIe device in response to determining that the first device information is the same as the second device information and the first channel is adjacent to the second channel.

[0143] The step B2 includes determining that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device in response to determining that the first channel is not adjacent to the second channel.

[0144] In this embodiment, for a PCIe interface of the CPU, in response to determining that the first device information received by the first channel is the same as the second device information received by the second channel, it can be determined that the first channel and the second channel are connected to the same PCIe device.

[0145] For example, in response to determining that the first channel is channel 0 of the PCIe interface, the second channel is channel 1 of the PCIe interface, and channel 2 of the PCIe interface does not receive the device information (or the device information received by the channel 2 is different from the first device information), it can be determined that the PCIe device has two channels, i.e., the number of channels of the PCIe device is 2.

[0146] If the first channel is not adjacent to the second channel, since the gold finger of the PCIe device is an integral whole, the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device. At this time, the number of channels of the PCIe device can be determined based on all channels corresponding to the PCIe device.

[0147] For example, if the first channel is channel 0 of the PCIe interface, and the second channel is channel 3 of the PCIe interface, the channels 1 and 2 between the two channels also correspond to the same PCIe device, i.e., the PCIe device corresponds to channels 0-3, and therefore the number of channels of the PCIe device is 4.

[0148] In this embodiment, the CPU receives the same device information through the first channel and the second channel, so that the number of channels of the PCIe device can be determined simply and quickly, and the identification result is not affected even if there are other channels between the first channel and the second channel, so that the reliability of identification can be ensured.

[0149] In some embodiments, the above step B2 “in response to determining that the first channel and the second channel are not adjacent, determining that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device”, can include the following step B21.

[0150] Step B21, in response to determining that the first channel and the second channel are not adjacent, and the device information obtained by the other channels between the first channel and the second channel is the same as the first device information and / or the second device information, determining that the first channel, the second channel, and the other channels between the first channel and the second channel correspond to the same PCIe device.

[0151] In this embodiment, each channel of the PCIe device is configured to send device information to the central processor, and at this time, in response to determining that the first channel and the second channel are not adjacent, it is also necessary to determine whether the device information obtained by the other channels between the first channel and the second channel is the same as the first device information and / or the second device information, in order to further improve the reliability of identification. Under normal circumstances, in response to determining that the same device identifier is uploaded on the two non-adjacent channels, the same device identifier will also be uploaded on the other channels between the two channels.

[0152] In some embodiments, each channel of the PCIe device is configured to send device information to the central processor, and the method further includes the following step C1.

[0153] Step C1, in response to determining that the first device information and the second device information are the same, and the first channel and the second channel are not adjacent, and there is a fourth channel between the first channel and the second channel that does not receive device information, determining that the fourth channel link is abnormal.

[0154] In this embodiment, if the first channel and the second channel that receive the same device information are not adjacent, i.e. there are other channels between them; and if each channel of the PCIe device is configured to send device information to the central processor, at this time, the same device information should also be able to be received by the other channels between them. For ease of description, the channels between the first channel and the second channel are referred to as the fourth channel; it can be understood that the number of fourth channels can be one or more; since there is no x3 device, the fourth channel is generally multiple.

[0155] In response to determining that the fourth channel between the first channel and the second channel does not receive any device information, the CPU can determine that the link between the fourth channel and the PCIe device is abnormal, thereby realizing link detection at the channel granularity.

[0156] In addition, in some embodiments, if the first channel and the second channel correspond to the first channel and the last channel of the PCIe device, the CPU can accurately determine the number of channels of the PCIe device even if the fourth channel in the middle does not receive the device information on the PCIe device. However, if the first channel or the second channel does not correspond to the first channel or the last channel of the PCIe device, or the third channel receives the device information, but the PCIe device is actually a multi-channel device, the CPU will determine the number of channels of the PCIe device inaccurately.

[0157] In the embodiment, if the CPU does not correctly receive the device information sent by the first channel and the last channel of the PCIe device, the PCIe device can determine whether the link is abnormal by whether the first channel and the last channel receive the ACK signal, and then feed back the corresponding information to the CPU, because the CPU will not feed back the corresponding ACK signal. As described above, in response to that one of the first channel and the last channel of the PCIe device receives the confirmation signal, and the other one does not receive the confirmation signal, the PCIe device converts the device information into abnormal information, and sends the abnormal information to the central processor based on the first channel or the last channel that has received the confirmation signal.

[0158] In addition, the CPU further performs the following steps: in response to determining that the fifth device information is obtained based on the fifth channel of the PCIe interface, and in response to determining that abnormal information different from the fifth device information is obtained based on the fifth channel after the confirmation signal is fed back based on the fifth channel, it is determined that there is an unrecognized channel connected to the PCIe device.

[0159] In the embodiment, the fifth channel can be the third channel described above, or the first channel or the second channel described above; in response to determining that the CPU obtains the corresponding device information (i.e., the fifth device information) based on the fifth channel, and then obtains abnormal information different from the fifth device information, it is determined that the first channel or the last channel of the PCIe device does not receive the ACK signal, that is, at least one channel of the link is abnormal, that is, there is a channel between the CPU and the PCIe device that is not recognized by the CPU, and the number of channels determined at this time is inaccurate.

[0160] The CPU can attempt to correct the determined number of lanes of the PCIe device; for example, if the number of lanes of the PCIe device is currently determined to be 14, and the exception information is received, since there is no x15 device, the PCIe device is an x16 device, and the number of lanes of the PCIe device can be corrected to 16. In response to determining that the number of lanes cannot be corrected, an alarm message is generated to remind the maintenance personnel to maintain; and in response to determining that the number of lanes cannot be corrected, the currently determined number of lanes is taken as the minimum number of lanes of the PCIe device when performing bandwidth allocation, and bandwidth allocation is performed based on this.

[0161] At step S304, bandwidth allocation is performed according to the correspondence between the PCIe interface and the PCIe device.

[0162] In this embodiment, after the correspondence between each lane of the PCIe interface and the PCIe device is determined, the PCIe bandwidth allocation can be performed based on this, and the allocation process is not limited here.

[0163] In some embodiments, in response to determining that the PCIe interface does not receive device information during the initialization phase of initializing the PCIe device, bandwidth allocation is performed based on a default bandwidth allocation strategy.

[0164] FIG. 4 shows a detailed flowchart of implementing bandwidth allocation. As shown in FIG. 4, the process of bandwidth allocation includes the following steps S401 to S405.

[0165] At step S401, after the BMC of the server is powered on, it is determined whether bandwidth needs to be allocated.

[0166] For example, the BMC determines whether the server has experienced an AC power outage, and whether the case cover has been opened; in response to determining that the server has experienced an AC power outage and the case cover has been opened, it is determined that bandwidth needs to be allocated.

[0167] At step S402, when bandwidth needs to be allocated, the BMC sends a bandwidth configuration instruction to the PCIe device using the system management bus.

[0168] In response to determining that bandwidth does not need to be allocated, the BMC can be normally started. Wherein, the BMC sends the bandwidth configuration instruction after the PCIe device is powered on.

[0169] At step S403, after the PCIe device receives the bandwidth configuration instruction based on the system management bus, it cyclically sends its own device information to the CPU of the server based on each lane.

[0170] At step S404, after the CPU receives the device information based on the lane of the PCIe interface, it feeds back a corresponding ACK signal based on the lane.

[0171] In step S405, the CPU determines the correspondence between the PCIe interface and the PCIe device according to the received device information, and performs bandwidth allocation.

[0172] The bandwidth allocation method provided in this embodiment can be used to automatically perform bandwidth allocation when the CPU needs to initialize the PCIe device, by obtaining the device information uploaded by the PCIe device based on the channel of the PCIe interface, simply determining the number of channels of the PCIe device based on the same device information, and determining which pins of the PCIe interface of the CPU are inserted into the PCIe device.

[0173] This embodiment also provides a server, as shown in FIG. 1, which includes a baseboard management controller and a central processing unit; the baseboard management controller is configured to issue a bandwidth configuration instruction to a PCIe device based on a system management bus; and the central processing unit is configured to execute the bandwidth allocation method provided in the above-described embodiments.

[0174] In some embodiments, the baseboard management controller is configured to determine whether the server has experienced an AC power outage and whether the case cover has been opened; in response to determining that the server has experienced an AC power outage and that the case cover has been opened, broadcast the bandwidth configuration instruction to the system management bus; and the address identifier of the bandwidth configuration instruction is all zero.

[0175] The server has the same functions as the corresponding embodiments described above, and thus will not be described again.

[0176] In this embodiment, a bandwidth allocation apparatus is also provided, which is configured to implement the above-described embodiments and implementation manners, and thus will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0177] This embodiment provides a bandwidth allocation apparatus applied to a central processing unit of a server, as shown in FIG. 5, which includes:

[0178] The listening module 501 is configured to listen to the PCIe interface of the central processing unit in an initialization phase of initializing the PCIe device.

[0179] The determination module 502 is configured to determine whether the first device information and the second device information are the same in response to that the first device information is acquired based on the first channel of the PCIe interface and the second device information is acquired based on the second channel of the PCIe interface; the first device information and the second device information are device information of a PCIe device connected to the PCIe interface.

[0180] The processing module 503 is configured to determine that the first channel and the second channel correspond to the same PCIe device in response to that the first device information and the second device information are determined to be the same, and feed back a confirmation signal based on the first channel and the second channel respectively.

[0181] The bandwidth allocation module 504 is configured to perform bandwidth allocation according to a correspondence between the PCIe interface and the PCIe device.

[0182] In some embodiments, the processing module 503, in response to that the first device information and the second device information are determined to be the same, determines that the first channel and the second channel correspond to the same PCIe device, and includes:

[0183] In response to that the first device information and the second device information are determined to be the same, and in response to that the first channel and the second channel are determined to be adjacent, it is determined that the first channel and the second channel correspond to the same PCIe device.

[0184] In response to that the first channel and the second channel are determined to be non-adjacent, it is determined that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device.

[0185] In some embodiments, the processing module 503, in response to that the first channel and the second channel are determined to be non-adjacent, determines that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device, and includes:

[0186] In response to that the first channel and the second channel are determined to be non-adjacent, and in response to that device information acquired by other channels between the first channel and the second channel is the same as the first device information and / or the second device information, it is determined that the first channel, the second channel, and the other channels between the first channel and the second channel correspond to the same PCIe device.

[0187] In some embodiments, each channel of the PCIe device is configured to send device information to the central processor, and the processing module 503 is further configured to:

[0188] In response to that the first device information and the second device information are determined to be the same, in response to that the first channel and the second channel are determined to be non-adjacent, and in response to that there is a fourth channel between the first channel and the second channel which does not receive device information, it is determined that the fourth channel link is abnormal.

[0189] In some embodiments, the processing module 503 is further configured to:

[0190] In response to obtaining the third device information based on the third channel of the PCIe interface, and the third device information being different from the obtained other device information, determining that the third channel corresponds to one PCIe device with a channel number of 1, and feeding back a confirmation signal based on the third channel.

[0191] In some embodiments, the bandwidth allocation module 504 is further configured to:

[0192] In response to determining that the PCIe device is in an initialization phase of initialization, and the PCIe interface does not receive device information, performing bandwidth allocation based on a default bandwidth allocation strategy.

[0193] The embodiment provides a bandwidth allocation apparatus applied to a PCIe device, as shown in FIG. 6, comprising:

[0194] An obtaining module 601 is configured to obtain a bandwidth configuration instruction issued by a baseboard management controller based on a system management bus;

[0195] An information sending module 602 is configured to send device information of the PCIe device to a central processing unit of a server based on a first channel cycle, and send the same device information to the central processing unit based on a last channel cycle; the first channel is the first channel of the PCIe device, and the last channel is the last channel of the PCIe device.

[0196] A responding module 603 is configured to, in response to obtaining a confirmation signal based on the first channel and the last channel, stop sending the device information based on the first channel and the last channel.

[0197] In some embodiments, the information sending module 602 is further configured to, in response to determining that the number of channels of the PCIe device is not less than 3, send the same device information to the central processing unit based on a cycle of other channels other than the first channel and the last channel.

[0198] The responding module 603 is further configured to, in response to obtaining a confirmation signal based on the other channels, stop sending the device information based on the other channels.

[0199] In some embodiments, the obtaining module 601 obtains the bandwidth configuration instruction issued by the baseboard management controller based on the system management bus, comprising:

[0200] Listening to a data frame in the system management bus;

[0201] In response to listening to the data frame with an address identifier of all zeros, determining that the bandwidth configuration instruction is obtained.

[0202] In some embodiments, the apparatus further comprises an information generating module configured to:

[0203] reading the vendor identification of the PCIe device from a vendor identification register and reading the device identification of the PCIe device from a device identification register;

[0204] generating device information including the vendor identification and the device identification.

[0205] Further function description of the above-mentioned modules and units is the same as the corresponding embodiments, and will not be repeated here.

[0206] The bandwidth allocation apparatus in the embodiment is in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, including a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0207] The embodiment of the present application also provides a computer device with the bandwidth allocation apparatus shown in FIG. 5 or FIG. 6.

[0208] Please refer to FIG. 7, which is a structural schematic diagram of a computer device provided by the embodiment of the present application. As shown in FIG. 7, the computer device includes one or more processors 10, a memory 20 associated with the one or more processors 10, and an interface for connecting various components, including a high-speed interface and a low-speed interface. Various components are communicatively connected with each other by different buses, and can be installed on a common motherboard or in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in the memory or graphics information stored on the memory to display a GUI on an external input / output device (such as a display device coupled to the interface). In some embodiments, multiple processors and / or multiple buses can be used with multiple memories, if necessary. Similarly, multiple computer devices can be connected, each providing part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). One processor 10 is taken as an example in FIG. 7.

[0209] The processor 10 can be a central processor, a network processor, or a combination thereof. The processor 10 can further include an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic gate array, a generic array logic, or any combination thereof.

[0210] The memory 20 stores computer readable instructions executable by the at least one processor 10, and the computer readable instructions are read and executed by the at least one processor 10 to implement the method shown in the above embodiments.

[0211] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs required for at least one function, and the like. The data storage area can store data created according to usage of the computer device, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory such as at least one of a magnetic disk storage device, a flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory 20 includes a memory disposed remotely with respect to the processor 10, which can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0212] The memory 20 can include a volatile memory such as a random access memory, and can further include a non-volatile memory such as a flash memory, a hard disk, or a solid state disk. The memory 20 can also include a combination of the above-mentioned types of memory.

[0213] The computer device further includes a communication interface 30 for communication of the computer device with other devices or communication networks.

[0214] As shown in FIG. 8, the embodiments of the present application further provide a non-transitory computer readable storage medium, and the above-mentioned method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and stored in a local storage medium through network downloading of computer code, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, and the like. Further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above-mentioned embodiments is implemented.

[0215] As shown in FIG. 9, part of the present application can be applied as a computer program product, for example, computer readable instructions, when executed by one or more processors, the operation of the processor can invoke or provide the method and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer readable instructions in computer readable medium includes but is not limited to source files, executable files, installation package files and the like, and accordingly, the way of executing the computer readable instructions by the processor includes but is not limited to: the processor directly executes the instructions, or the processor executes the corresponding compiled program after compiling the instructions, or the processor reads and executes the instructions, or the processor executes the corresponding installed program after reading and installing the instructions. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible by the computer.

[0216] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A bandwidth allocation method characterized by, A central processing unit applied to a server, the method comprising: In an initialization phase of initializing a PCIe (Peripheral Component Interconnect Express) device, listening to a PCIe interface of the central processing unit; In response to obtaining first device information based on a first channel of the PCIe interface and obtaining second device information based on a second channel of the PCIe interface, determining whether the first device information and the second device information are the same; the first device information and the second device information are both device information of a PCIe device connected to the PCIe interface; In response to determining that the first device information and the second device information are the same, determining that the first channel and the second channel correspond to the same PCIe device, and feeding back a confirmation signal based on the first channel and the second channel respectively; and According to the correspondence between the PCIe interface and the PCIe device, performing bandwidth allocation.

2. The method of claim 1, wherein, The response to determining that the first device information and the second device information are the same, and determining that the first channel and the second channel correspond to the same PCIe device, comprises: In response to determining that the first device information and the second device information are the same, and the first channel and the second channel are adjacent, it is determined that the first channel and the second channel correspond to the same PCIe device; and In response to determining that the first channel and the second channel are not adjacent, it is determined that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device.

3. The method of claim 2, wherein, The response to determining that the first channel and the second channel are not adjacent, and determining that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device, comprises: In response to determining that the first channel and the second channel are not adjacent, and the device information obtained by other channels between the first channel and the second channel is the same as the first device information and / or the second device information, it is determined that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device.

4. The method of claim 2, wherein, Each channel of the PCIe device is configured to send device information to the central processing unit, and the method further comprises: In response to determining that the first device information and the second device information are the same, and the first channel and the second channel are not adjacent, and there is a fourth channel between the first channel and the second channel that has not received device information, it is determined that the fourth channel link is abnormal.

5. The method of claim 1, wherein, Further comprising: In response to obtaining third device information based on a third channel of the PCIe interface, and the third device information being different from other obtained device information, it is determined that the third channel corresponds to one PCIe device with a channel number of 1, and a confirmation signal is fed back based on the third channel.

6. The method of claim 1, wherein, Further comprising: In response to determining that the PCIe interface does not receive device information in an initialization phase of initializing the PCIe device, performing bandwidth allocation based on a default bandwidth allocation strategy.

7. The method of claim 1, wherein, Further comprising: In response to determining that abnormal information different from the fifth device information is obtained based on the fifth channel after obtaining the fifth device information based on the fifth channel of the PCIe interface and feeding back a confirmation signal based on the fifth channel, it is determined that there is an unrecognized channel connected to the PCIe device.

8. The method of claim 7, wherein, Further comprising: Correcting the number of channels of the PCIe device; and In response to determining that the number of channels cannot be corrected, taking the currently determined number of channels as the minimum number of channels of the PCIe device when performing bandwidth allocation.

9. The method of claim 1, wherein, The PCIe device is configured to send the same device information to the central processor based on the first channel and the last channel, where the first channel corresponds to the first channel and the second channel corresponds to the last channel.

10. The method of claim 1, wherein, The bandwidth allocation according to the correspondence between the PCIe interface and the PCIe device includes: According to the correspondence between each channel of the PCIe interface and the PCIe device, the number of channels of the PCIe device is allocated bandwidth.

11. A bandwidth allocation method characterized by, Applied to a PCIe device, the method comprises: Obtaining bandwidth configuration instructions issued by a baseboard management controller based on a system management bus; Cyclically sending device information of the PCIe device to a central processor of a server based on a first channel, and cyclically sending the same device information to the central processor based on a last channel; the first channel is the first channel of the PCIe device, and the last channel is the last channel of the PCIe device; and In response to obtaining a confirmation signal based on the first channel and the last channel, stop sending the device information based on the first channel and the last channel.

12. The method of claim 11, wherein, Further comprising: In response to determining that the number of channels of the PCIe device is not less than 3, cyclically sending the same device information to the central processor based on other channels other than the first channel and the last channel; And In response to obtaining a confirmation signal based on the other channels, stop sending the device information based on the other channels.

13. The method of claim 11, wherein, The bandwidth configuration instructions issued by the baseboard management controller based on the system management bus include: Listening to data frames in the system management bus; and In response to listening to a data frame with an address identifier of all zeros, it is determined that bandwidth configuration instructions are obtained.

14. The method of claim 11, wherein, Further comprising: Reading the vendor identifier of the PCIe device from the vendor identifier register and reading the device identifier of the PCIe device from the device identifier register; And Generating device information including the vendor identifier and the device identifier.

15. The method of claim 11, wherein, The bandwidth configuration instructions issued by the baseboard management controller based on the system management bus include: broadcasting, by the BCM, a bandwidth configuration instruction to the system management bus; and The PCIe device acquires the bandwidth configuration instruction by listening to the system management bus.

16. The method of claim 11, wherein, The bandwidth configuration instruction issued by the baseboard management controller based on the system management bus comprises: determining whether the server has experienced an AC power outage and whether the case cover has been opened; and In response to determining that the server has experienced an AC power outage and that the case cover has been opened, the bandwidth configuration instruction issued by the baseboard management controller based on the system management bus is acquired.

17. The method of claim 11, wherein, After the first channel cycle and the last channel cycle send the device information of the PCIe device to the central processor of the server, and send the same device information to the central processor based on the last channel cycle, the method further comprises: In response to the first channel receiving an acknowledgement signal and the last channel not receiving an acknowledgement signal, or in response to the first channel not receiving an acknowledgement signal and the last channel receiving an acknowledgement signal, the device information is converted into exception information; and The first channel or the last channel that has received an acknowledgement signal sends the exception information to the central processor.

18. The method of claim 11, wherein, The device information sent by the first channel and the last channel is used to instruct the central processor to determine that the first channel and the second channel that receive the same device information in the PCIe interface correspond to the first channel and the last channel of the PCIe device respectively, and based on the first channel and the second channel respectively feeding back an acknowledgement signal, according to the correspondence between each channel of the PCIe interface and the PCIe device, bandwidth allocation is performed according to the number of channels of the PCIe device.

19. A server, comprising: comprise: a baseboard management controller and a central processor; the baseboard management controller is configured to issue a bandwidth configuration instruction to the PCIe device based on a system management bus; and the central processor is configured to perform the bandwidth allocation method of any one of claims 1 to 10.

20. The server of claim 19, wherein, The baseboard management controller is configured to: determine whether the server has experienced an AC power outage and whether the case cover has been opened; and In response to determining that the server has experienced an AC power outage and that the case cover has been opened, broadcast a bandwidth configuration instruction to the system management bus; the address identifier of the bandwidth configuration instruction is all zero.

21. A computer device, comprising: comprise: one or more processors; and a memory associated with the one or more processors, the memory being configured to store computer readable instructions that, when read and executed by the one or more processors, implement the bandwidth allocation method of any one of claims 1 to 18.

22. A non-transitory computer readable storage medium, comprising: The non-volatile computer readable storage medium has stored thereon computer readable instructions that, when executed by one or more processors, implement the bandwidth allocation method of any one of claims 1 to 18.

23. A computer program product, characterised in that, comprise computer readable instructions that, when executed by one or more processors, implement the bandwidth allocation method of any one of claims 1 to 18.

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