Array substrate, display panel, and display apparatus

Abstract

The present disclosure provides an array substrate, a display panel, and a display apparatus. The array substrate comprises a base substrate, wherein the base substrate comprises a display area, a first non-display area located on one side of the display area and configured to be bonded to a driving circuit, a second non-display area located on the side of the display area away from the first non-display area, and a third non-display area connecting the first non-display area and the second non-display area; a common electrode bus, which at least partially surrounds the display area; and a feedback line extending from the first non-display area through the third non-display area to the second non-display area, wherein the feedback line is electrically connected to the common electrode bus in the second non-display area.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:

[0005] On one hand, an array substrate provided in this disclosure includes:

[0006] A substrate, the substrate including a display area, a first non-display area located on one side of the display area and for bonding with a driving circuit, a second non-display area located in the display area away from the first non-display area, and a third non-display area connecting the first non-display area and the second non-display area;

[0007] A common electrode bus is configured to at least partially surround the display area;

[0008] The feedback line extends from the first non-display area through the third non-display area to the second non-display area, and the feedback line is electrically connected to the common electrode bus in the second non-display area.

[0009] In some embodiments, in the array substrate provided in the present disclosure, the feedback line is electrically connected to the common electrode bus in the middle region of the second non-display area.

[0010] In some embodiments, the array substrate provided in this disclosure further includes a short-circuit ring located in the second non-display area, and the feedback line is electrically connected to the common electrode bus across the short-circuit ring.

[0011] In some embodiments, the array substrate provided in this disclosure further includes a short-circuit ring located in the second non-display area, the short-circuit ring including a break; the feedback line passes through the break and is electrically connected to the common electrode bus.

[0012] In some embodiments, the array substrate provided in this disclosure further includes a plurality of electrostatic discharge structures electrically connected to the short-circuit ring, and the feedback line is electrically connected to the electrostatic discharge structures.

[0013] In some embodiments, in the array substrate provided in this disclosure, the feedback line is electrically connected to the common electrode bus at the end region near the second non-display area.

[0014] In some embodiments, the array substrate provided in this disclosure further includes a first common electrode line, which is electrically connected to the common electrode bus in the first non-display area.

[0015] In some embodiments, in the array substrate provided in the present disclosure, the first common electrode line includes a first sub-common electrode line, and the first sub-common electrode line is electrically connected to the common electrode bus in the middle region of the first non-display area.

[0016] In some embodiments, in the array substrate provided in the present disclosure, the first common electrode line includes a second sub-common electrode line, and the second sub-common electrode line is electrically connected to the common electrode bus in the end region near the first non-display area.

[0017] In some embodiments, in the array substrate provided in the present disclosure, the second sub-common electrode line is externally connected to a power management chip.

[0018] In some embodiments, in the array substrate provided in the present disclosure, the feedback line is electrically connected to the first common electrode line through an external operational amplifier.

[0019] In some embodiments, in the array substrate provided in the present disclosure, there are multiple first common electrode lines, and different first common electrode lines are electrically connected to different operational amplifiers.

[0020] In some embodiments, in the array substrate provided in the present disclosure, there are two feedback lines and an even number of first common electrode lines;

[0021] The two feedback lines are symmetrical about the central axis of the display area extending along the first direction, and an even number of the first common electrode lines are symmetrical about the central axis of the display area extending along the first direction. The first direction is the arrangement direction of the first non-display area and the second non-display area.

[0022] In some embodiments, in the array substrate provided in the present disclosure, there are multiple first common electrode lines, and at least a portion of the first common electrode lines share one operational amplifier.

[0023] In some embodiments, the array substrate provided in the present disclosure further includes dummy lines, at least a portion of which are symmetrical about the central axis of the display area extending along a first direction, wherein the first direction is the arrangement direction of the first non-display area and the second non-display area.

[0024] In some embodiments, in the array substrate provided in the present disclosure, the third non-display area includes a gate driving circuit area;

[0025] The array substrate also includes a shielding line and a clock signal line disposed in the gate driving circuit region. The shielding line extends from between the clock signal line and the feedback line to between the gate driving circuit region and the common electrode bus.

[0026] In some embodiments, in the array substrate provided in the present disclosure, the impedance of the feedback line is less than the impedance of the shielding line; and in the second non-display area, the linewidth of the feedback line is greater than the linewidth of the shielding line.

[0027] In some embodiments, the array substrate provided in this disclosure further includes multiple second common electrode lines and multiple data lines located in the display area, with each pair of adjacent data lines forming a group, and the second common electrode lines located between each group of data lines.

[0028] In some embodiments, the array substrate provided in the present disclosure further includes a plurality of pixel electrodes arranged in an array in the display area;

[0029] The data lines are located at part of the column gaps of the pixel electrodes, and the second common electrode lines are provided at the column gaps between each group of data lines.

[0030] The column gap width where the data line and the second common electrode line are located is greater than the column gap width between the pixel electrodes between two data lines in a group.

[0031] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.

[0032] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate includes a black matrix, the black matrix including a first black matrix strip and a second black matrix strip; wherein...

[0033] The first black matrix bar covers the data line and the second common electrode line, and the first black matrix bar is located within the column gap where the data line and the second common electrode line are located;

[0034] The second black matrix bar is located within the column gap of the pixel electrode between two data lines in a group, and the width of the first black matrix bar is greater than the width of the second black matrix bar.

[0035] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0036] Figure 1 is a schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0037] Figure 2 is a schematic diagram of the feedback line fb being coupled to the clock signal line CLK in Figure 1;

[0038] Figure 3 is another schematic diagram of the feedback line fb being coupled to the clock signal line CLK in Figure 1;

[0039] Figure 4 illustrates the coarse texture generation mechanism in the 8CLK architecture.

[0040] Figure 5 shows the CT1 crosstalk diagram;

[0041] Figure 6 is a schematic diagram of the pixel and polarity arrangement of the product corresponding to Figure 5;

[0042] Figure 7 is a schematic diagram of the coupling state of the common voltage signal in Figure 6;

[0043] Figure 8 shows the CT2 crosstalk diagram;

[0044] Figure 9 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0045] Figure 10 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0046] Figure 11 is a magnified structural diagram of region Z in Figure 10;

[0047] Figure 12 is a schematic diagram of another enlarged structure of region Z in Figure 10;

[0048] Figure 13 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0049] Figure 14 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0050] Figure 15 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0051] Figure 16 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0052] Figure 17a is a schematic diagram of the structure of 2*12 sub-pixels in the array substrate provided in the embodiment of this disclosure;

[0053] Figure 17b is a schematic diagram of the gate metal layer in Figure 17a;

[0054] Figure 17c is a schematic diagram of the source / drain metal layer in Figure 17a;

[0055] Figure 17d is a schematic diagram of the active layer in Figure 17a;

[0056] Figure 17e is a schematic diagram of the structure of the layer where the pixel electrode is located in Figure 17a;

[0057] Figure 17f is a schematic diagram of the structure of the layer where the common electrode is located in Figure 17a;

[0058] Figure 18 is a schematic diagram of the column gap structure of the pixel electrode where the second common electrode line is located;

[0059] Figure 19 is a schematic diagram of the enlarged column gap structure of the pixel electrode between two data lines in a group;

[0060] Figure 20 is a schematic diagram of a display panel provided in an embodiment of this disclosure;

[0061] Figure 21 is a schematic diagram of the structure of the first black matrix bar provided in an embodiment of this disclosure;

[0062] Figure 22 is a schematic diagram of the structure of the second black matrix bar provided in an embodiment of this disclosure;

[0063] Figure 23 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the following description will be made in conjunction with the accompanying drawings of the embodiments of this disclosure. For clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shapes in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shapes of the regions or reflect true proportions, but are only intended to illustrate the content of this disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0065] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0066] In the following description, when an element or layer is referred to as "on" another element or layer or "connected" to another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" another element or layer" or "directly connected" to another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items. The various embodiments of this disclosure may be combined and integrated with each other without conflict.

[0067] As display products continue to trend towards lower costs, the development of dual-gate products is constantly improving. However, current dual-gate products generally suffer from lateral crosstalk (H-CT), which severely impacts image quality. The inventors have studied the mechanism of lateral crosstalk, as detailed below:

[0068] Figure 1 is a schematic diagram of an array substrate provided in an embodiment of this disclosure. Figure 2 is a schematic diagram of the feedback line (fb) coupled to the clock signal line (CLK) in Figure 1. Figure 3 is another schematic diagram of the feedback line (fb) coupled to the clock signal line (CLK) in Figure 1. Figure 4 is the mechanism of coarse line generation in the 8CLK architecture. As can be seen from Figures 1 to 4, since the feedback line fb is close to the gate drive circuit area GOA (which may include the clock signal line), it is easily coupled to the clock signal line (CLK). The coupling of the feedback line (fb) causes the pixels connected by the gate lines G1, G2, G3, and G4 to be darker, while the pixels connected by the gate lines G5, G6, G7, and G8 are brighter. Therefore, in the four rows, the pixels in the first and second rows controlled by the gate lines G1, G2, G3, and G4 are displayed as dark lines, and the pixels in the third and fourth rows controlled by the gate lines G5, G6, G7, and G8 are displayed as bright lines, which macroscopically manifests as coarse line crosstalk.

[0069] Figure 5 shows another type of lateral crosstalk CT1 diagram, Figure 6 shows the pixel & polarity arrangement diagram corresponding to Figure 5, and Figure 7 shows the coupling state diagram of the common voltage signal in Figure 6. As shown in Figures 5 to 7, the mechanism of this lateral crosstalk is as follows: From the circuit perspective, the positive and negative polarities of pixels of the same color are unbalanced. The positive polarity of green pixels in the same row continuously accumulates, and there is no negative polarity - to cancel it out. The common electrode line (VCOM) is coupled by the data line connected to the green pixels, causing crosstalk. From the panel perspective, the panel has poor recovery capability. From the Dual Gate architecture perspective, the Dual Gate product is a vertical compensation architecture with a short 1H time. Within 1H, the coupled VCOM cannot be fully recovered.

[0070] Figure 8 shows another type of lateral crosstalk, CT2. Related products require that the Excel spreadsheet be free of crosstalk in all states: stationary, dragged, zoomed in, and zoomed out. In the stationary and zoomed-out states, the principle is the same as the mechanism of crosstalk in CT1 shown in Figure 5. When the Excel spreadsheet is zoomed out, only some compensation points can compensate for the common voltage, resulting in a high degree of crosstalk in the central area and a low degree of crosstalk in the edge area. Therefore, the crosstalk phenomenon is serious in small Excel windows and relatively mild in large windows.

[0071] To at least improve the aforementioned technical problems, this disclosure provides an array substrate. Figure 9 is a schematic diagram of one structure of the array substrate provided in this disclosure, and Figure 10 is a schematic diagram of another structure of the array substrate provided in this disclosure. Referring to Figures 9 and 10, it can be seen that the array substrate provided in this disclosure may include:

[0072] The substrate 101 includes a display area AA, a first non-display area DP located on one side of the display area AA and used for bonding with a driving circuit, a second non-display area DPO located in the display area AA away from the first non-display area DP, and a third non-display area GL&GR connecting the first non-display area DP and the second non-display area DPO. In some embodiments, a flexible circuit board (FPC) can be disposed in the first non-display area DP by means of a chip-on-film encapsulation (COF), or a data chip source IC and other driving circuits can be disposed in the first non-display area DP by means of a glass backplane encapsulation (COG). The flexible circuit board (FPC) or the data chip source IC and other driving circuits can provide data signals to the data line through fan-out lines (FL).

[0073] A common electrode bus 102 is configured to at least partially surround the display area AA. Optionally, the common electrode bus 102 is configured in a ring around the display area AA. The common electrode bus 102 provides a common voltage signal for the common electrode of the display area AA.

[0074] Feedback line 103 extends from the first non-display area DP through the third non-display area GL and / or GR to the second non-display area DPO, and is electrically connected to the common electrode bus 102 within the second non-display area DPO. Compared to the third non-display areas GL and GR, the second non-display area DPO has fewer wirings. Therefore, the path wiring of feedback line 103 can be wider, and the increased impedance is less than that of the feedback line (FB) shown in Figure 1, thus providing a more realistic feedback of the common voltage waveform within the screen.

[0075] In some embodiments, Table 1 shows the display effect when six points FB, V1 to V5 on the common electrode bus (BL) in Figure 1 are used as feedback points. FB is located at 1 / 12 to 1 / 4 (e.g., 1 / 6) of the common electrode bus 102 near the second non-display area DPO. V1 is located at the corner of the common electrode bus 102 on the second non-display area DPO side. V2 is located at 2 / 5 to 3 / 5 (e.g., 1 / 2) of the common electrode bus 102 from the second non-display area DPO. V3 is located at the corner of the common electrode bus 102 on the first non-display area DP side. V4 is located between adjacent COFs on the common electrode bus 102 near the third non-display area GL&GR side. V5 is located at 1 / 4 to 1 / 2 (e.g., 1 / 3) of the common electrode bus 102 near the third non-display area GL&GR side.

[0076] As shown in Table 1, when the connection point FB between the feedback line (fb) and the common electrode bus (BL) shown in Figure 1 is used as the feedback point, coarse lines and poor CT1 crosstalk occur. When V1, V2, and V5 are used as feedback points, not only are there no coarse lines, but the CT1 crosstalk is also reduced by about 3 levels, and the CT1 crosstalk is significantly reduced. Therefore, V1, V2, and V5 can be used as feedback points to replace the feedback line (fb) in this disclosure.

[0077] Table 1

[0078] Furthermore, since the wiring in the second non-display area DPO where V1 and V5 are located is less, the width of the peripheral traces connected to V1 and V5 (which can serve as the feedback line 103 of this disclosure) in the second non-display area DPO can be increased, ensuring that the impedance of the feedback line 103 of this disclosure is smaller, thereby enabling more accurate feedback of the common voltage waveform. Based on this, this disclosure sets the feedback line 103 to be electrically connected to the common electrode bus 102 within the second non-display area DPO. Specifically, Figure 9 illustrates the electrical connection of the feedback line 103 to the common electrode bus 102 in the end region of the second non-display area DPO (e.g., point V1 in the end region), and Figure 10 illustrates the electrical connection of the feedback line 103 to the common electrode bus 102 in the middle region of the second non-display area DPO (e.g., point V5 in the middle region).

[0079] In some embodiments, FIG11 is an enlarged structural schematic diagram of region Z in FIG10, and FIG12 is another enlarged structural schematic diagram of region Z in FIG10. As shown in FIG11 and FIG12, the array substrate provided in the embodiments of this disclosure may further include a short ring 104 located in the second non-display area DPO. Optionally, in FIG11, the feedback line 103 crosses the short ring 104 and is electrically connected to the common electrode bus 103; in FIG12, the short ring 104 includes a break F, and the feedback line 103 passes through the break F and is electrically connected to the common electrode bus 102. In some embodiments, the feedback line 103 is located in the gate metal layer, and the short-circuit ring 104 with a break F is located in the gate metal layer. The short-circuit ring 104 crossed by the feedback line 103 may include a connection portion ITO that is in the same layer and made of the same material as the common electrode or pixel electrode, and a trace portion GM located in the gate metal layer. The connection portion ITO can be connected to the trace portion GM by means of a hole. The feedback line 103 crosses the connection portion ITO to avoid short-circuiting between the feedback line 103 and the short-circuit ring 104.

[0080] Referring again to Figure 12, the array substrate provided in this embodiment may further include multiple electrostatic discharge structures 105 electrically connected to the short-circuit ring 104. Each electrostatic discharge structure 105 can be electrically connected to a data line via a fan-out line FL. The feedback line 103 can be electrically connected to the electrostatic discharge structure 105 closest to the break point F. Since the feedback line 103 is electrically connected to the common electrode bus 102, the electrostatic discharge structure 105 can be connected to the common electrode bus 102 via the feedback line 103 for electrostatic discharge, thereby increasing the electrostatic discharge path and improving the antistatic effect.

[0081] In some embodiments, the common electrode bus 102 may employ a double-layer wiring, where one layer of wiring is located on the gate metal layer and the other layer is located on the layer containing the common electrode or pixel electrode. Optionally, to reduce the coupling of the fan-out line FL to the common electrode bus 102, the common electrode bus 102 may include multiple first cutout structures OW1 that overlap with the fan-out line FL, as shown in Figures 11 and 12. Additionally, to enhance the curing effect of the sealant, the wider feedback line 103 may also be provided with multiple second cutout structures OW2, as shown in Figure 11.

[0082] In some embodiments, the array substrate provided in the present disclosure, as shown in Figures 9 and 10, may further include a first common electrode line 106, which is electrically connected to a common electrode bus 102 within the first non-display area DP. Optionally, the first common electrode line 106 includes a first sub-common electrode line 1061, which is electrically connected to the common electrode bus 102 in the middle region of the first non-display area DP (e.g., point V4 in the middle region). In some embodiments, the first common electrode line 106 may further include a second sub-common electrode line 1062, which is electrically connected to the common electrode bus 102 in the end region near the first non-display area DP (e.g., point V3 in the end region). The first sub-common electrode line 1061 and the second sub-common electrode line 1062 can serve as compensation lines to compensate for the common voltage signal, thereby improving the uniformity of the common voltage signal.

[0083] In some embodiments, the present disclosure may mark V4 as point A, V3 as point B, V2 as point C, FB as point D, V1 as point E, and V5 as point F, and set the center point of the panel as point O. The sum of the impedances between the two points can be obtained to obtain the values ​​shown in Table 2. As can be seen from Figure 1 and Table 2, due to the characteristics of the Dual Gate vertical architecture, the horizontal impedance from point C to point O is 3MΩ, while the vertical impedance from point F or A to point O is much smaller than the horizontal impedance, only 1KΩ. Therefore, in theoretical derivation, we can conclude that: (1) V1 effect: negative effect, the impedance from V1 to V5 is only 9Ω, V1 compensation will cancel the waveform feedback when V5 is doing feedback; (2) V2 effect: no effect, the Dual Gate product is a vertical VCOM architecture, the horizontal connection line is ITO (MΩ level), the horizontal compensation effect is weak; (3) V3 & V4 effect: positive effect, the vertical connection line of a single pixel is Cu (Ω level), so the vertical compensation point has the best compensation effect. Therefore, this disclosure can use the second sub-common electrode line 1062 and the first sub-common electrode line 1061 connected by V3 and V4 as compensation lines for compensation.

[0084] Table 2

[0085] Table 3

[0086] Table 4

[0087] This disclosure also uses the controlled variable method to verify the compensation effect using single and combined variables. The compensation effect of single variables is shown in Table 3, and the compensation effect of combined variables is shown in Table 4. Table 3 shows that the compensation combination of V2, V3, and V4 is optimal, while compensation with V1 actually exacerbates H-Crosstalk. Table 4 shows that the compensation combination of V3 and V4 is optimal, consistent with the conclusions of the single variable method and the theoretical derivation. Therefore, this disclosure can use the second sub-common electrode line 1062 connected by V3 and the first sub-common electrode line 1061 connected by V4 together as the compensation lines.

[0088] Table 5

[0089] Table 6

[0090] Table 7

[0091] In some embodiments, as shown in FIG10 and Table 5, when the feedback line 103 is set at point V5 for feedback, it is not necessary to set peripheral traces connecting V1 and V2; as shown in FIG9 and Table 6, when the feedback line 103 is set at point V1, it is not necessary to set peripheral traces connecting V2 and V5, thus reducing the number of traces. In some embodiments, Table 7 shows the parameters of the peripheral traces connecting points FB and V1 to V5 in this disclosure. As can be seen from Table 7, when the peripheral traces of V1 and V2 are omitted, at least 87μm of wiring space can be saved; when the peripheral traces of V2 and V5 are omitted, at least 75μm of wiring space can be saved. The saved wiring space can be effectively used for GOA area, AA area, Output compensation line, GND, VCOM, etc., to increase the overall performance of the Panel in terms of ESD protection, charge release, and compensation capabilities.

[0092] In some embodiments, Figures 13 to 16 are schematic diagrams of another structure of the array substrate provided in the embodiments of this disclosure. As shown in Figures 9, 10, and 13 to 16, in the array substrate provided in the embodiments of this disclosure, the feedback line 103 can also be electrically connected to the first common electrode line 106 through an operational amplifier (OP) 107 of an external circuit board (e.g., a printed circuit board PCB). Optionally, there are multiple first common electrode lines 106, and different first common electrode lines 106 are electrically connected to different operational amplifiers 107. For example, in Figures 9 and 10, there are two feedback lines 103 on the left and right, and an even number of first common electrode lines 106 (e.g., including two first sub-common electrode lines 1061 and two second sub-common electrode lines 1062). The number of operational amplifiers 107 is the same as the number of first common electrode lines 106, and each first common electrode line 106 is electrically connected to one operational amplifier 107. Optionally, the two feedback lines 103 may be symmetrical about the central axis MN extending along the first direction Y of the display area AA, and the even number of first common electrode lines 106 may be symmetrical about the central axis MN extending along the first direction Y of the display area AA. The first direction Y is the arrangement direction of the first non-display area DP and the second non-display area DPO. The operational amplifier 107 is placed randomly on the circuit board (e.g., a printed circuit board PCB) or according to other structural positions on the circuit board.

[0093] In some embodiments, as shown in Figures 15 and 16, to reduce the number of operational amplifiers 107 and save costs, at least a portion of the first common electrode lines 106 (e.g., two first sub-common electrode lines 1061) may share one operational amplifier 107. It should be noted that in Figures 15 and 16, when two first sub-common electrode lines 1061 share one operational amplifier 107, there may be only one feedback line 103. The array substrate may also include a dummy line 103', where at least a portion of the dummy line 103 is symmetrical about the central axis MN extending along the first direction Y of the display area AA. This is equivalent to using one of the feedback lines 103 in Figures 9, 10, 13, and 14 as a dummy line 103', thus allowing the use of the mask on the layer containing the feedback line 103. In some embodiments, to save wiring space, the dummy line 103' may not be provided; this disclosure does not impose specific limitations.

[0094] In some embodiments, as shown in Tables 2 and 7, the bus line impedance corresponding to V3 is 37Ω, and the output drive capability of the power management chip PMIC can effectively drive V3. Therefore, as shown in Figures 13 to 16, the second sub-common electrode line 1062 of this disclosure can be externally connected to the power management chip PMIC, so that the power management chip PMIC supplies power to the bus line (i.e., the common voltage bus 102) through the second sub-common electrode line 1062 and point V3 in sequence. This also avoids setting up an operational amplifier 107 electrically connected to the second sub-common electrode line 1062, which helps to reduce costs.

[0095] In some embodiments, Table 8 shows the improvement effect of the array substrate shown in Figure 13 on H-crosstalk, and Table 9 shows the improvement effect of the array substrate shown in Figure 14 on H-crosstalk. In Tables 8 and 9, Vcom represents the voltage provided by the power management chip (PMIC), which is 4V to 6V. From Tables 8 and 9, it can be concluded that the array substrates shown in Figures 13 and 14 effectively improve or even eliminate defects such as CT1 crosstalk, CT2 crosstalk, and roughness.

[0096] Table 8

[0097] Table 9

[0098] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 9, 10, and 13 to 16, may further include a shielding line 108. The shielding line 108 may extend from between the gate drive circuit region GOA and the feedback line 103 to between the gate drive circuit region GOA and the common electrode bus 102. Optionally, the impedance of the feedback line 103 is less than the impedance of the shielding line 108, and the linewidth of the feedback line 103 in the second non-display area DPO is greater than the linewidth of the shielding line 108 (for example, the linewidth of the feedback line 103 in the second non-display area DPO is more than 5 times the linewidth of the shielding line 108). The linewidth of the feedback line 103 in the third non-display area GL&GR may be greater than, less than, or equal to the linewidth of the shielding line 108. In some embodiments, a gate drive circuit and gate drive circuit signal lines electrically connected to the gate drive circuit may be provided in the gate drive circuit region GOA. The gate drive circuit signal lines include, but are not limited to, frame start signal lines, total reset signal lines, clock signal lines, and low-level signal lines. Optionally, the feedback line (fb) in Figure 1 can be used as the shield line 108. The shield line 108 can be set between the clock signal line CLK and the feedback line 103, and the shield line 108 is not electrically connected to the common electrode bus (BL) so as to prevent the clock signal line CLK and the like from coupling to the feedback line 103 through the shield line 103.

[0099] In some embodiments, FIG17a is a schematic diagram of the structure of 2*12 sub-pixels in the array substrate provided in the embodiments of the present disclosure, FIG17b to FIG17f are schematic diagrams of the structure of each single film layer in FIG17a, FIG18 is a schematic diagram of the column gap of the pixel electrode where the second common electrode line is located; FIG19 is a schematic diagram of the column gap of the pixel electrode between two data lines in a group. As shown in Figures 17a to 17f, 18, and 19, the array substrate provided in this embodiment may further include multiple second common electrode lines 109, multiple data lines 110, and multiple pixel electrodes 111 located in the display area AA. Each pair of adjacent data lines 110 forms a group, and the second common electrode lines 109 are located between each group of data lines 110. Optionally, the data lines 110 are located at part of the column gaps of the pixel electrodes 111, and the second common electrode lines 109 are provided at the column gaps between each group of data lines 110. The column gap width W1 where the data lines 110 and the second common electrode lines 109 are located is greater than the column gap width W2 between the pixel electrodes 111 in a group of two data lines 110. Compared to a scheme where data lines 110 and second common electrode lines 109 are alternately arranged in the column gaps of the pixel electrodes 111, this disclosure can reduce the number of second common electrode lines 109 by half, and the column gap width without second common electrode lines 109 is reduced, thereby increasing transmittance and improving the aperture ratio by 1.5%.

[0100] Referring to Figures 17a to 17f, two gate lines 112 can be disposed at the same row gap of the pixel electrode 111 in this disclosure, making the technical solution of this disclosure applicable to Dual Gate products. Optionally, the array substrate provided in this disclosure may further include a common electrode 113 electrically connected to the second common electrode line 109, and a transistor 114 electrically connected to the data line 110, the pixel electrode 111, and the gate line 112. In some embodiments, the pixel electrode 111 may be a block electrode, and the common electrode 113 may be a slit electrode; or, the pixel electrode 111 may be a slit electrode, and the common electrode 113 may be a block electrode, which is not specifically limited in this disclosure. In addition, the gate g of the transistor 114 in this disclosure may be integrally disposed with the gate line 112, the first electrode s of the transistor 114 may be integrally disposed with the data line 110, the second electrode d of the transistor 114 may be electrically connected to the pixel electrode 111 through the transition electrode 115 of the layer where the common electrode 113 is located, and the active layer a of the transistor 114 may be polycrystalline silicon, amorphous silicon, indium gallium zinc oxide, etc. Other essential components of the array substrate are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0101] Based on the same inventive concept, this disclosure provides a display panel. FIG20 is a schematic diagram of a structure of the display panel provided in this disclosure. As shown in FIG20, the display panel of this disclosure may include an array substrate 001 and a counter substrate 002 placed opposite each other, wherein the array substrate 001 is the array substrate 001 provided in the embodiment of this disclosure.

[0102] In some embodiments, the opposing substrate 002 may include a black matrix BM, which is a grid structure. The second common electrode line 109, data line 110, transistor 113, and gate line 112 are located within the black matrix BM region. Optionally, Figure 21 shows a schematic diagram of the structure of the first black matrix strip BM1 of the black matrix BM, and Figure 22 shows a schematic diagram of the structure of the second black matrix strip BM2 of the black matrix BM. The first black matrix strip BM covers the data line 110 and the second common electrode line 109, and is located within the column gap of width W1 where the data line 110 and the second common electrode line 109 are located. The second black matrix strip BM2 is located within the column gap of width W2 between two data lines 110 in a group. Since the first black matrix strip BM1 needs to cover the data line 110 and the second common electrode line 109, the width of the first black matrix strip BM1 is greater than the width of the second black matrix strip BM2. In addition, color resists CF may be disposed within the grid of the black matrix BM. The color resists include red color resists, blue color resists, green color resists, etc. In some embodiments, the color resist may also be disposed on the array substrate, which is not limited in this disclosure.

[0103] In some embodiments, as shown in FIG20, the display panel provided in this disclosure may further include a liquid crystal layer 003 between an array substrate 001 and a counter substrate 002, a first polarizer 004 located on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 located on the side of the counter substrate 002 away from the array substrate 001, wherein the polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting this disclosure.

[0104] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG23, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot LEDs.

[0105] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0106] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0107] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0108] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area, a first non-display area located on one side of the display area and for bonding with a driving circuit, a second non-display area located in the display area away from the first non-display area, and a third non-display area connecting the first non-display area and the second non-display area; A common electrode bus is configured to at least partially surround the display area; The feedback line extends from the first non-display area through the third non-display area to the second non-display area, and the feedback line is electrically connected to the common electrode bus in the second non-display area.

2. The array substrate as claimed in claim 1, wherein, The feedback line is electrically connected to the common electrode bus in the middle region of the second non-display area.

3. The array substrate as described in claim 2, wherein, It also includes a short-circuit ring located in the second non-display area, and the feedback line is electrically connected to the common electrode bus across the short-circuit ring.

4. The array substrate as claimed in claim 2, wherein, It also includes a short-circuit ring located in the second non-display area, the short-circuit ring including a break; the feedback line passes through the break and is electrically connected to the common electrode bus.

5. The array substrate as claimed in claim 4, wherein, It also includes multiple electrostatic discharge structures electrically connected to the short-circuit ring, and the feedback line is electrically connected to the electrostatic discharge structures.

6. The array substrate as claimed in claim 1, wherein, The feedback line is electrically connected to the common electrode bus at its end region near the second non-display area.

7. The array substrate according to any one of claims 1 to 6, wherein, It also includes a first common electrode line, which is electrically connected to the common electrode bus within the first non-display area.

8. The array substrate as claimed in claim 7, wherein, The first common electrode line includes a first sub-common electrode line, which is electrically connected to the common electrode bus in the middle region of the first non-display area.

9. The array substrate as claimed in claim 7 or 8, wherein, The first common electrode line includes a second sub-common electrode line, which is electrically connected to the common electrode bus at its end region near the first non-display area.

10. The array substrate as claimed in claim 9, wherein, The second sub-common electrode line is connected to an external power management chip.

11. The array substrate according to any one of claims 7 to 9, wherein, The feedback line is electrically connected to the first common electrode line via an external operational amplifier.

12. The array substrate as claimed in claim 11, wherein, There are multiple first common electrode lines, and different first common electrode lines are electrically connected to different operational amplifiers.

13. The array substrate as claimed in claim 12, wherein, There are two feedback lines, and the number of the first common electrode lines is even. The two feedback lines are symmetrical about the central axis of the display area extending along the first direction, and an even number of the first common electrode lines are symmetrical about the central axis of the display area extending along the first direction. The first direction is the arrangement direction of the first non-display area and the second non-display area.

14. The array substrate as claimed in claim 11, wherein, There are multiple first common electrode lines, and at least some of the first common electrode lines share one operational amplifier.

15. The array substrate as claimed in claim 14, wherein, It also includes a dummy line, at least a portion of which is symmetrical to the feedback line about the central axis of the display area extending along a first direction, the first direction being the arrangement direction of the first non-display area and the second non-display area.

16. The array substrate according to any one of claims 1 to 15, wherein, The third non-display area includes a gate drive circuit area; The array substrate also includes a shielding line and a clock signal line disposed in the gate driving circuit region. The shielding line extends from between the clock signal line and the feedback line to between the gate driving circuit region and the common electrode bus.

17. The array substrate as claimed in claim 16, wherein, The impedance of the feedback line is less than the impedance of the shielding line; and within the second non-display area, the linewidth of the feedback line is greater than the linewidth of the shielding line.

18. The array substrate according to any one of claims 1 to 17, wherein, It also includes multiple second common electrode lines and multiple data lines located in the display area, with each pair of adjacent data lines forming a group, and the second common electrode lines located between each group of data lines.

19. The array substrate as claimed in claim 18, wherein, It also includes a plurality of pixel electrodes arranged in an array in the display area; The data lines are located at part of the column gaps of the pixel electrodes, and the second common electrode lines are provided at the column gaps between each group of data lines. The column gap width where the data line and the second common electrode line are located is greater than the column gap width between the pixel electrodes between two data lines in a group.

20. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 19.

21. The display panel as claimed in claim 20, wherein, The opposing substrate includes a black matrix, which comprises a first black matrix stripe and a second black matrix stripe; wherein... The first black matrix bar covers the data line and the second common electrode line, and the first black matrix bar is located within the column gap where the data line and the second common electrode line are located; The second black matrix bar is located within the column gap of the pixel electrode between two data lines in a group, and the width of the first black matrix bar is greater than the width of the second black matrix bar.

22. A display device, wherein, It includes the display panel as described in claim 20 or 21, and a backlight module located on the light-incident side of the display panel.

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