Clock signal generation method and module, and display device

Abstract

A clock signal generation method and module, and a display device. The clock signal generation method comprises: within a frame period (F0), when an enable end (EN) provides a valid enable signal and clock indication terminals (CPV1, CPV2) provide valid clock indication signals, obtaining a timing sequence for generating clock signals; and when clock signal generation is stopped, a timer (J1) starting timing, and on the basis of the elapsed time measured by the timer (J1), obtaining a timing sequence for re-generating clock signals. Clock signal terminals (CLK1, CLK2, CLK3, CLK4, CLK5, CLK6) can be enabled for any row as needed, thereby achieving arbitrary row display on a display panel, reducing power consumption of the display panel and supporting multi-scenario applications thereof.

Description

Clock signal generation method, module and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a clock signal generation method, module, and display device. Background Technology

[0002] In related technologies, within a frame time, after a valid frame start signal is provided at the frame start end, each clock signal terminal is turned on sequentially according to the timing requirements of the Level Shifter (level converter) output of the display panel with fewer inputs and more outputs. This makes it impossible to turn on the clock signal terminal in any row, impossible to display in any row of the display panel, and impossible to reduce the power consumption of the display panel and enable multi-scenario applications.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a clock signal generation method, comprising: within a frame time,

[0005] When the enable terminal provides a valid enable signal and the clock indicator terminal provides a valid clock indicator signal, the timing sequence for generating the clock signal is obtained.

[0006] When the clock signal generation stops, the timer starts counting down. Based on the timer's countdown, the timing sequence for generating the clock signal again is determined.

[0007] The clock signal generation method described in at least one embodiment of this disclosure further includes:

[0008] Within one frame, the enabling terminal provides a valid enabling signal.

[0009] In at least one embodiment of this disclosure, a frame time includes an enable-enabled time period and an enable-disabled time period, and the clock signal generation method further includes:

[0010] During the effective enable period, the enable terminal provides a valid enable signal;

[0011] During the enabled invalid period, the enabling terminal provides an invalid enable signal.

[0012] In at least one embodiment of this disclosure, a frame time includes a sequentially set enable / disable time period and an enable / enabled time period; the clock signal generation method further includes:

[0013] During the enabled invalid period, the enabling terminal provides an invalid enable signal;

[0014] During the enabled effective time period, the enabling terminal provides a valid enabling signal.

[0015] In at least one embodiment of this disclosure, the timer timing step includes:

[0016] The timer starts counting after a valid frame start signal is provided at the frame start end.

[0017] In at least one embodiment of this disclosure, the timer timing step includes:

[0018] The timer starts counting when a valid frame start signal is provided at the frame start end and a valid clock indicator signal is stopped being provided at the clock indicator end.

[0019] The clock signal generation method described in at least one embodiment of this disclosure includes: within a frame time,

[0020] When the clock indicator terminal stops providing a valid clock indicator signal, the timer starts counting; when the clock indicator terminal provides a valid clock indicator signal again, the corresponding clock signal terminal is controlled to provide a corresponding clock signal based on the counting time obtained by the timer.

[0021] The clock signal generation method described in at least one embodiment of this disclosure includes: within a frame time,

[0022] The timer starts counting when the clock indicator stops providing a valid clock indicator signal;

[0023] During the enabled inactive period, the clock signal terminal stops providing the clock signal;

[0024] During the enabled effective time period, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal is controlled to provide a corresponding clock signal based on the timing time obtained by the timer.

[0025] The clock signal generation method described in at least one embodiment of this disclosure includes: within a frame time,

[0026] The timer starts counting from the beginning of the enabled invalidation period;

[0027] During the enabled inactive period, the clock signal terminal stops providing the clock signal;

[0028] During the enabled effective time period, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal is controlled to provide a corresponding clock signal based on the timing time obtained by the timer.

[0029] In a second aspect, embodiments of this disclosure provide a clock signal generation module, including a timing controller and a level converter, wherein the timing controller and the level converter are electrically connected, the timing controller being used to provide an enable signal to an enable terminal; the level converter is electrically connected to a gate driving circuit included in a display panel, and the level converter includes a timer and a clock signal generation circuit;

[0030] The clock signal generation circuit is used to obtain the timing sequence for generating a clock signal when the enable terminal provides a valid enable signal and the clock indicator terminal provides a valid clock indicator signal, and is used to control the timer to count down when the clock signal generation stops, and obtain the timing sequence for generating a clock signal again based on the countdown time obtained by the timer.

[0031] In at least one embodiment of this disclosure, the enabling terminal is configured to provide a valid enabling signal for a frame period.

[0032] In at least one embodiment of this disclosure, a frame time includes an enable valid time period and an enable invalid time period. The enable terminal is used to provide a valid enable signal during the enable valid time period and an invalid enable signal during the enable invalid time period. The enable signal is used to control the activation of the clock signal.

[0033] In at least one embodiment of this disclosure, a frame of time includes a sequentially set enable invalid period and an enable valid period; the enable terminal is configured to provide an invalid enable signal during the enable invalid period and to provide a valid enable signal during the enable valid period.

[0034] In a third aspect, embodiments of this disclosure provide a display device including the clock signal generation module described above. Attached Figure Description

[0035] Figure 1 is a timing diagram corresponding to the clock signal generation method according to at least one embodiment of the present disclosure;

[0036] Figure 2 is a timing diagram corresponding to the clock signal generation method according to at least one embodiment of the present disclosure;

[0037] Figure 3 is a timing diagram corresponding to the clock signal generation method according to at least one embodiment of the present disclosure;

[0038] Figure 4 is a structural diagram of a clock signal generation module according to at least one embodiment of the present disclosure;

[0039] Figure 5 is a structural diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0040] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0041] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0042] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0043] The clock signal generation method described in this embodiment includes: within one frame time,

[0044] When the enable terminal provides a valid enable signal and the clock indicator terminal provides a valid clock indicator signal, the timing sequence for generating the clock signal is obtained.

[0045] When the clock signal generation stops, the timer starts counting down. Based on the timer's countdown, the timing sequence for generating the clock signal again is determined.

[0046] In related technologies, within a frame time, after a valid frame start signal is provided at the frame start end, each clock signal terminal is turned on sequentially according to the timing requirements of the Level Shifter (level converter) output of the display panel with fewer inputs and more outputs. This makes it impossible to turn on the clock signal terminal in any row, impossible to display in any row of the display panel, and impossible to reduce the power consumption of the display panel and enable multi-scenario applications.

[0047] Based on this, this disclosure provides a clock signal generation method. When the enable terminal provides a valid enable signal and the clock indicator terminal provides a valid clock indicator signal, a timing sequence for generating the clock signal is obtained. According to the timing sequence, the corresponding clock signal terminal is controlled to provide the corresponding clock signal. When clock signal generation stops, a timer starts counting. When the enable terminal provides a valid enable signal and the clock indicator terminal again provides a valid clock indicator signal, a timing sequence for generating the clock signal again is obtained based on the timer's countdown. According to the timing sequence, the corresponding clock signal terminal is controlled to provide the corresponding clock signal. With the above settings, the clock signal terminal can be turned on in any row as needed, enabling display in any row of the display panel, reducing power consumption of the display panel, and facilitating multi-scenario applications.

[0048] The clock signal generation method described in at least one embodiment of this disclosure further includes:

[0049] Within one frame, the enabling terminal provides a valid enabling signal.

[0050] In a specific implementation, within one frame, all the enabling terminals can provide valid enabling signals. At this time, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal provides the corresponding clock signal; when the clock indicator terminal provides an invalid clock indicator signal, the clock signal terminal stops providing the clock signal.

[0051] In at least one embodiment of this disclosure, a frame time includes an enable-enabled time period and an enable-disabled time period, and the clock signal generation method further includes:

[0052] During the effective enable period, the enable terminal provides a valid enable signal;

[0053] During the enabled invalid period, the enabling terminal provides an invalid enable signal.

[0054] In practical implementation, within a single frame, there can be an enable effective time period and an enable invalid time period;

[0055] During the enable active period, the enable terminal provides a valid enable signal. At this time, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal provides the corresponding clock signal; when the clock indicator terminal provides an invalid clock indicator signal, the clock signal terminal stops providing the clock signal.

[0056] During the period when the enable signal is invalid, the enable terminal provides an invalid enable signal, and the clock signal terminal stops providing a clock signal.

[0057] In at least one embodiment of this disclosure, a frame time includes a sequentially set enable / disable time period and an enable / enabled time period; the clock signal generation method further includes:

[0058] During the enabled invalid period, the enabling terminal provides an invalid enable signal;

[0059] During the enabled effective time period, the enabling terminal provides a valid enabling signal.

[0060] In specific implementation, a frame time can include an enable invalid period and an enable valid period set successively. At the beginning of a frame time, when entering the enable invalid period, the enable terminal provides an invalid enable signal, the clock signal terminal stops providing a clock signal, and the timer starts counting. After entering the enable valid period, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal is controlled to provide a corresponding clock signal according to the counting time obtained by the timer.

[0061] In at least one embodiment of this disclosure, the timer timing step includes:

[0062] The timer starts counting after a valid frame start signal is provided at the frame start end.

[0063] In practice, the timer starts counting after a valid frame start signal is provided at the beginning of the frame within one frame time.

[0064] In at least one embodiment of this disclosure, the timer timing step includes:

[0065] The timer starts counting when a valid frame start signal is provided at the frame start end and a valid clock indicator signal is stopped being provided at the clock indicator end.

[0066] In practice, within one frame, after a valid frame start signal is provided at the frame start end, the timer starts counting when the clock indicator stops providing a valid clock indicator signal.

[0067] The clock signal generation method described in at least one embodiment of this disclosure includes: within a frame time,

[0068] The enabling terminal provides a valid enabling signal;

[0069] When the clock indicator terminal stops providing a valid clock indicator signal, the timer starts counting; when the clock indicator terminal provides a valid clock indicator signal again, the corresponding clock signal terminal is controlled to provide a corresponding clock signal based on the counting time obtained by the timer.

[0070] In practical implementation, the enabling terminal provides an effective enabling signal within one frame.

[0071] When the clock indicator stops providing a valid clock indicator signal, the timer starts counting; then, when the clock indicator provides a valid clock indicator signal again, the timing sequence for generating the clock signal again can be obtained based on the counting time, and the corresponding clock signal terminal can be controlled to provide the corresponding clock signal based on the timing sequence.

[0072] As shown in Figure 1, within one frame time F0, the enable terminal EN provides a high voltage signal;

[0073] A frame time F0 includes the first display time period SX1, the second display time period SX2, and the third display time period SX3, which are set sequentially.

[0074] During the first display time period SX1, the first clock indicator terminal CPV1 provides a square wave signal, the second clock indicator terminal CPV2 provides a square wave signal (that is, CPV1 provides a valid first clock indicator signal, and CPV2 provides a valid second clock indicator signal), the first row clock signal terminal CLK1 provides the first row clock signal, the second row clock signal terminal CLK2 provides the second row clock signal, the third row clock signal terminal CLK3 provides the third row clock signal, the fourth row clock signal terminal CLK4 provides the fourth row clock signal, the fifth row clock signal terminal CLK5 provides the fifth row clock signal, and the sixth row clock signal terminal CLK6 provides the sixth row clock signal.

[0075] During the second display period SX2, CPV1 provides a low voltage signal and CPV2 provides a low voltage signal (that is, CPV1 stops providing a valid first clock indication signal and CPV2 stops providing a valid second clock indication signal).

[0076] During the second display time period SX2, the timer records the time when CPV1 stops providing a valid first clock indication signal, and the timer records the time when CPV2 stops providing a valid second clock indication signal;

[0077] During the third display time period SX3, when CPV1 and CPV2 output square wave signals again, the clock signal count when CPV1 and CPV2 start outputting square waves again is calculated synchronously based on the timing time obtained by the timer, and the clock signal terminal of the corresponding row is controlled to be turned on, instead of following the clock signal terminal of the previous row.

[0078] For example, at the start of the third display time period SX3, CLK3 provides the third row of clock signals, and then CLK4, CLK5, CLK6, CLK1, and CLK2 provide their respective clock signals in sequence.

[0079] In Figure 1, STV0 refers to the signal that provides an overall reset to the gate drive circuit of the display panel before the start of a frame, such as resetting the pull-up node and / or output of the gate drive circuit. STV1 is the initial trigger signal of the gate drive circuit of the display panel, which is generally the initial trigger signal for the first row or the first few rows.

[0080] In at least one embodiment of this disclosure, the timer can be set inside the level shifter, and the timer can be designed according to the minimum unit time that the Tcon (timing controller) can output.

[0081] The clock signal generation method described in at least one embodiment of this disclosure includes: within a frame time,

[0082] The timer starts counting when the clock indicator stops providing a valid clock indicator signal;

[0083] During the enabled inactive period, the clock signal terminal stops providing the clock signal;

[0084] During the enabled effective time period, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal is controlled to provide a corresponding clock signal based on the timing time obtained by the timer.

[0085] Referring to Figure 1, optionally, the initial trigger signal STV1 and the enable terminal EN are activated synchronously. That is, if the valid signal is high, the rising edge of the high level will activate synchronously. The rising edge of CPV1 triggers CLK (e.g., CLK1) to turn on, i.e., the rising edge of CLK. The rising edge of CPV2 triggers CLK (e.g., CLK1) to turn off, i.e., the falling edge of CLK. Here, CLK refers to the gate signal used to turn on the gate lines of the display area of ​​the display panel.

[0086] In practical implementation, there is a situation where the enable signal terminal does not continuously output a high-voltage signal (the high-voltage signal can be a valid enable signal) within a frame. That is, within a frame, the enable signal terminal provides high-voltage and low-voltage signals in a time-division manner. When the enable signal terminal provides a low-voltage signal, regardless of whether CPV1 and CPV2 are normally outputting square wave signals or have stopped outputting square wave signals, the clock signal output is controlled by the enable signal. When the enable signal is a high-voltage signal, each clock signal terminal controls whether to output the corresponding clock signal according to the timing sequence of CPV1 and CPV2. When the enable signal terminal provides a low-voltage signal, the clock signal terminal stops outputting, but the level shifter internally sets a timer to record the time when CPV1 and CPV2 stop or normally output, and synchronously calculates the corresponding row clock signal to be started when the enable signal is restarted, rather than starting with the clock signal of the previous row.

[0087] As shown in Figure 2, a frame time F0 can include a first enabled effective time period SY1, an enabled invalid time period SW, and a second enabled effective time period SY2, which are set sequentially.

[0088] During the first enable active period SY1 and the second enable active period SY2, EN provides a high voltage signal;

[0089] During the enable inactive period SW, EN provides a low voltage signal;

[0090] The first enable effective time period SY1 includes the first output time period SC1 and the first stop output time period ST1;

[0091] During the first output time period SC1, CPV1 and CPV2 normally provide square wave signals, and the first row clock signal terminal CLK1, the second row clock signal terminal CLK2, the third row clock signal terminal CLK3, the fourth row clock signal terminal CLK4, the fifth row clock signal terminal CLK5, and the sixth row clock signal terminal CLK6 sequentially output the corresponding row clock signals.

[0092] During the first stop output period ST1, EN provides a high voltage signal, and CPV1 and CPV2 both provide low voltage signals. The clock signal terminals of each row stop outputting clock signals and output low voltage signals.

[0093] The timer starts counting from the beginning of the first stop output period ST1;

[0094] During the enable invalid period, SW and EN provide low voltage signals, CPV1 and CPV2 both provide square wave signals, each row clock signal terminal stops outputting clock signals, and each row clock signal terminal outputs low voltage signals.

[0095] During the second enable effective time period SY2, EN provides a high voltage signal, and the clock signal is output normally starting from the third row clock signal terminal CLK3, for example, based on the timing time obtained from the timer.

[0096] The clock signal generation method described in at least one embodiment of this disclosure includes: within a frame time,

[0097] The timer starts counting from the beginning of the enabled invalidation period;

[0098] During the enabled inactive period, the clock signal terminal stops providing the clock signal;

[0099] During the enabled effective time period, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal is controlled to provide a corresponding clock signal based on the timing time obtained by the timer.

[0100] In specific implementation, a frame of time may include an enabled invalid period and an enabled valid period set successively. At the beginning of the enabled invalid period, the timer starts counting. During the enabled valid period, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal can be controlled to provide the corresponding clock signal according to the counting time.

[0101] In at least one embodiment of this disclosure, the enable signal is high between adjacent frames, or is switched between high and low levels as required, and the enable signal is the output of a first priority control clock signal.

[0102] As shown in Figure 3, the first frame time F1 includes the first output time period SC1 and the first stop output time period ST1;

[0103] The second frame time F2 includes the enable / disable period SW and the enable / enable period SY;

[0104] During the first output time period SC1, EN outputs a high voltage signal, CPV1 and CPV2 output square wave signals normally, and the clock signals are output sequentially from the first row clock signal terminal CLK1, the second row clock signal terminal CLK2, the third row clock signal terminal CLK3, the fourth row clock signal terminal CLK4, the fifth row clock signal terminal CLK5, and the sixth row clock signal terminal CLK6.

[0105] During the first stop output period ST1, EN outputs a low voltage signal, CPV1 and CPV2 output low voltage signals, and all row clock signal terminals output low voltage signals.

[0106] During the enable invalid period, SW and EN output a low voltage signal, CPV1 and CPV2 output square wave signals normally, and all clock signal terminals output a low voltage signal.

[0107] When the enable invalid period SW begins, the timer starts counting, synchronously recording and calculating the time of the EN output low voltage signal;

[0108] During the enable effective period SY, EN outputs a high voltage signal, and CPV1 and CPV2 output square wave signals normally. According to the timing time obtained by the timer, for example, the clock signal is output normally starting from the third row clock signal terminal.

[0109] Referring to Figure 3, the start time of the enable invalidation period is after the initial trigger signal STV1, even if the rising edge of the start of the enable invalidation period overlaps with the valid period of SV1.

[0110] The clock signal generation module described in this embodiment includes a timing controller and a level converter. The timing controller and the level converter are electrically connected. The timing controller is used to provide an enable signal to an enable terminal. The level converter is electrically connected to a gate driving circuit included in the display panel and is used to provide a clock signal to the gate driving circuit. The level converter includes a timer and a clock signal generation circuit.

[0111] The clock signal generation circuit is used to obtain the timing sequence for generating a clock signal when the enable terminal provides a valid enable signal and the clock indicator terminal provides a valid clock indicator signal, and is used to control the timer to count down when the clock signal generation stops, and obtain the timing sequence for generating a clock signal again based on the countdown time obtained by the timer.

[0112] In practical implementation, the clock signal generation module may include a timing controller and a level converter. The level converter may include a timer and a clock signal generation circuit. The timing controller provides an enable signal to the enable terminal. The clock signal generation circuit obtains the timing sequence for generating the clock signal when the enable terminal provides a valid enable signal and the clock indicator terminal provides a valid clock indicator signal. It also controls the timer to count down when clock signal generation stops, and obtains the timing sequence for generating the clock signal again based on the timer's countdown. With the above settings, the clock signal terminal can be turned on in any row as needed, enabling display in any row of the display panel, reducing power consumption of the display panel, and facilitating multi-scenario applications.

[0113] As shown in Figure 4, the clock signal generation module of at least one embodiment of this disclosure may include a timing controller 41 and a level converter 42;

[0114] The timing controller 41 is electrically connected to the enable terminal EN, the first clock indicator terminal CPV1, and the second clock indicator terminal CPV2, and is used to provide an enable signal to the enable terminal EN, a first clock indicator signal to the first clock indicator terminal CPV1, and a second clock indicator signal to the second clock indicator terminal CPV2.

[0115] The level converter 42 includes a timer J1 and a clock signal generation circuit 420;

[0116] The clock signal generation circuit 420 is electrically connected to the enable terminal EN, the first clock indicator terminal CPV1, the second clock indicator terminal CPV2, the first row clock signal terminal CLK1, the second row clock signal terminal CLK2, the third row clock signal terminal CLK3, the fourth row clock signal terminal CLK4, the fifth row clock signal terminal CLK5, the sixth row clock signal terminal CLK6, and the timer J1. It is used to generate clock signals when the enable terminal EN provides a valid enable signal, the first clock indicator terminal CPV1 provides a valid first clock indicator signal, and the second clock signal terminal CPV2 provides a valid second clock indicator signal. The timing sequence for generating clock signals is obtained. Based on this timing sequence, the first row of clock signals is provided through CLK1, the second row of clock signals through CLK2, the third row of clock signals through CLK3, the fourth row of clock signals through CLK4, the fifth row of clock signals through CLK5, and the sixth row of clock signals through CLK6. These signals are used to control the timer J1 to keep time when clock signal generation stops. Based on the time obtained from the timer J1, the timing sequence for generating clock signals again is obtained. Based on the timing sequence for generating clock signals again, the corresponding clock signals are output starting from the corresponding row.

[0117] In at least one embodiment of this disclosure, the enable signal is a signal sent by a front-end Tcon (timing controller) IC (Integrated Circuit) or SOC (System On Chip). The level converter determines whether to output a clock signal based on the high or low level of the enable signal. Based on the existing level converter's Terminate signal, the first approach is to retain the Terminate signal and add an enable signal to achieve arbitrary row output of the clock signal, thereby enabling dynamic display on the display panel. The second approach is to modify the existing Terminate signal, changing its timing logic to that of the enable signal, to control arbitrary row output of the clock signal, thereby achieving dynamic display on the display panel.

[0118] In at least one embodiment of this disclosure, the enabling terminal is configured to provide a valid enabling signal for a frame period.

[0119] In at least one embodiment of this disclosure, a frame time includes an enable valid time period and an enable invalid time period. The enable terminal is used to provide a valid enable signal during the enable valid time period and an invalid enable signal during the enable invalid time period. The enable signal is used to control the activation of the clock signal.

[0120] In at least one embodiment of this disclosure, a frame of time includes a sequentially set enable invalid period and an enable valid period; the enable terminal is configured to provide an invalid enable signal during the enable invalid period and to provide a valid enable signal during the enable valid period.

[0121] The display device described in this disclosure includes the clock signal generation module described above.

[0122] As shown in Figure 5, the display device according to at least one embodiment of the present disclosure includes a display panel P0, a clock signal generation module 50, a first circuit board B1, a second circuit board B2, a third circuit board B3, and a fourth circuit board B4.

[0123] The clock signal generation module 50 is located in the display driver chip PD.

[0124] The clock signal generation module 50 is used to transmit clock signals to the display panel through the first circuit board B1, the second circuit board B2, the third circuit board B3 and the fourth circuit board B4.

[0125] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method for generating a clock signal, comprising: Within one frame, When the enable terminal provides a valid enable signal and the clock indicator terminal provides a valid clock indicator signal, the timing sequence for generating the clock signal is obtained. When the clock signal generation stops, the timer starts counting down. Based on the timer's countdown, the timing sequence for generating the clock signal again is determined.

2. The clock signal generation method as described in claim 1, wherein, Also includes: Within one frame, the enabling terminal provides a valid enabling signal.

3. The clock signal generation method as described in claim 1, wherein, A frame of time includes an enable-active time period and an enable-disable time period, and the clock signal generation method further includes: During the effective enable period, the enable terminal provides a valid enable signal; During the enabled invalid period, the enabling terminal provides an invalid enable signal.

4. The clock signal generation method as described in claim 1, wherein, A frame of time includes a sequentially set enable / disable time period and an enable / enabled time period; the clock signal generation method further includes: During the enabled invalid period, the enabling terminal provides an invalid enable signal; During the enabled effective time period, the enabling terminal provides a valid enabling signal.

5. The clock signal generation method according to any one of claims 2 to 4, wherein, The timing steps of the timer include: The timer starts counting after a valid frame start signal is provided at the frame start end.

6. The clock signal generation method according to any one of claims 2 to 4, characterized in that, The timing steps of the timer include: The timer starts counting when a valid frame start signal is provided at the frame start end and a valid clock indicator signal is stopped being provided at the clock indicator end.

7. The clock signal generation method as described in claim 2, wherein, include: Within one frame, The timer starts counting when the clock indicator stops providing a valid clock indicator signal; When the clock indicator terminal provides a valid clock indicator signal again, the corresponding clock signal terminal is controlled to provide a corresponding clock signal based on the timing time obtained by the timer.

8. The clock signal generation method as described in claim 3, wherein, include: Within one frame, The timer starts counting when the clock indicator stops providing a valid clock indicator signal; During the enabled inactive period, the clock signal terminal stops providing the clock signal; During the enabled effective time period, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal is controlled to provide a corresponding clock signal based on the timing time obtained by the timer.

9. The clock signal generation method as described in claim 4, wherein, include: Within one frame, The timer starts counting from the beginning of the enabled invalidation period; During the enabled inactive period, the clock signal terminal stops providing the clock signal; During the enabled effective time period, when the clock indicator terminal provides a valid clock indicator signal, the corresponding clock signal terminal is controlled to provide a corresponding clock signal based on the timing time obtained by the timer.

10. A clock signal generation module, comprising a timing controller and a level converter, wherein the timing controller and the level converter are electrically connected, and the timing controller is used to provide an enable signal to an enable terminal; The level converter is electrically connected to the gate driving circuit included in the display panel, and the level converter includes a timer and a clock signal generation circuit; The clock signal generation circuit is used to obtain the timing sequence for generating a clock signal when the enable terminal provides a valid enable signal and the clock indicator terminal provides a valid clock indicator signal, and is used to control the timer to count down when the clock signal generation stops, and obtain the timing sequence for generating a clock signal again based on the countdown time obtained by the timer.

11. The clock signal generation module as described in claim 10, wherein, The enable terminal is used to provide a valid enable signal throughout a frame.

12. The clock signal generation module as described in claim 10, wherein, A frame time includes an enable valid time period and an enable invalid time period. The enable terminal is used to provide a valid enable signal during the enable valid time period and an invalid enable signal during the enable invalid time period. The enable signal is used to control the activation of the clock signal.

13. The clock signal generation module as described in claim 10, wherein, A frame time includes a sequentially set enable invalid period and enable valid period; the enable terminal is used to provide an invalid enable signal during the enable invalid period and to provide a valid enable signal during the enable valid period.

14. A display device comprising a clock signal generation module as described in any one of claims 10 to 13.

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