Display panel and display device

Abstract

The present application discloses a display panel and a display device. A first insulating layer is disposed between a first transparent electrode layer and a second transparent electrode layer. A second insulating layer is disposed between a first light-shielding metal layer and a second light-shielding metal layer and is in contact with the first insulating layer. The orthographic projection of the second insulating layer in a display area on a substrate covers the orthographic projection of the first transparent electrode layer on the substrate.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of 5G communication technology and the improvement of virtual reality (VR) content and hardware, virtual reality technology is in a period of rapid development. Virtual reality technology has very high requirements for screen resolution (>1000).

[0003] For virtual reality devices manufactured using liquid crystal display panels, the in-plane aperture ratio is lower than that of conventional products due to the limitations of their high-resolution structural design. To improve the aperture ratio of the liquid crystal display panel, light-shielding structures are set for signal lines such as data lines. These light-shielding structures include two light-shielding lines and an insulating layer between them, in order to reduce the size of the organic light-shielding matrix while lowering the reflectivity of the light-shielding structure. However, the introduction of the light-shielding structure increases the manufacturing difficulty. Invention Overview

[0004] This application provides a display panel and a display device to reduce the manufacturing difficulty of the light-shielding layer of the display panel, thereby simplifying the manufacturing process of the display panel and the display device.

[0005] In a first aspect, this application provides a display panel having a display area and including an array substrate, the array substrate comprising:

[0006] substrate;

[0007] A driving circuit layer is disposed on one side of the substrate and includes signal lines located in the display area;

[0008] A first transparent electrode layer is disposed on the side of the driving circuit layer opposite to the substrate;

[0009] The second transparent electrode layer is disposed on the side of the first transparent electrode layer away from the driving circuit layer, and the orthographic projection of the second transparent electrode layer on the substrate overlaps with the orthographic projection of the first transparent electrode layer on the substrate.

[0010] A first insulating layer is disposed between the first transparent electrode layer and the second transparent electrode layer; and

[0011] A light-shielding layer is disposed on the side of the first insulating layer opposite to the driving circuit layer, and includes:

[0012] A first light-shielding metal layer is disposed on the side of the first insulating layer away from the first transparent electrode layer, and includes a first light-shielding metal line located in the display area, wherein the orthographic projection of the first light-shielding metal line on the substrate overlaps with the orthographic projection of the signal line on the substrate.

[0013] A second light-shielding metal layer is located on the side of the first light-shielding metal layer opposite to the driving circuit layer, and includes a second light-shielding metal line located in the display area. The orthographic projection of the second light-shielding metal line on the substrate overlaps with the orthographic projections of the first light-shielding metal line and the signal line on the substrate.

[0014] The second insulating layer is located between the first light-shielding metal layer and the second light-shielding metal layer, and is in contact with the first insulating layer. In the display area, the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the first transparent electrode layer on the substrate.

[0015] Secondly, this application also provides a display device, which includes the aforementioned display panel. Beneficial effects

[0016] In some embodiments of the display panel and display device of this application, a first insulating layer is disposed between a first transparent electrode layer and a second transparent electrode layer. A second insulating layer is disposed between a first light-shielding metal layer and a second light-shielding metal layer and is in contact with the first insulating layer. In the display area, the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the first transparent electrode layer on the substrate. This increases the coverage area of ​​the second insulating layer, thereby reducing the etching area of ​​the second insulating layer and simplifying the manufacturing difficulty of the light-shielding stack. Simultaneously, it improves the problem of over-etching of the first insulating layer between the first and second transparent electrode layers during the etching of the second insulating layer, and improves the problem of reduced performance of the storage capacitor formed by the first and second transparent electrode layers due to the reduction of the first insulating layer. Attached Figure Description

[0017] Figure 1 is a cross-sectional structural diagram of a display panel according to some embodiments of this application.

[0018] Figure 2 is a cross-sectional structural diagram of the display panel of some other embodiments of this application.

[0019] Figure 3 is a cross-sectional structural diagram of a display panel according to some other embodiments of this application.

[0020] Figure 4 is a cross-sectional structural diagram of a display panel according to some other embodiments of this application.

[0021] Figure 5 is a cross-sectional structural diagram of a display panel according to some other embodiments of this application.

[0022] Figure 6 is a partial plan view of the display panel of some embodiments of this application.

[0023] Figure 7 is a schematic diagram of the structure of a display device according to some embodiments of this application.

[0024] The attached figures are labeled as follows:

[0025] 100, display panel; 100a, display area; 100b, bezel area; 200, display device;

[0026] 10. Array substrate;

[0027] 11. Substrate;

[0028] 12, driving circuit layer; 121, low temperature polycrystalline silicon semiconductor layer; 1211, low temperature polycrystalline silicon active layer; 122, metal oxide semiconductor layer; 1221, metal oxide active layer;

[0029] 1231, First conductive layer; 1231A, Gate; 1231B, First gate; 1232, Second conductive layer; 1232A, Second gate; 1233, Third conductive layer; 1233A, Metal interconnect;

[0030] 1241, First gate insulating layer; 1242, Second gate insulating layer; 1243, Third gate insulating layer;

[0031] 1244, First interlayer dielectric layer; 1245, Second interlayer dielectric layer; 1246, Third interlayer dielectric layer;

[0032] 1247, Organic planarization layer; 1248, Passivation layer;

[0033] 125, color filter layer;

[0034] 126, Conductive structure; 127, Transparent conductive portion; 1271, First transparent conductive portion; 1272, Second transparent conductive portion;

[0035] H1, first connecting hole; H2, second connecting hole;

[0036] 1281, Organic filler material; 1282, Elevation structure; 1291, First transparent connecting layer; 1292, Second transparent connecting layer;

[0037] 13, First transparent electrode layer; 131, Transparent connection structure; 14, Second transparent electrode layer; 14a, Opening;

[0038] 15. First insulating layer;

[0039] 16, light-shielding layer; 161, first light-shielding metal layer; 1611, first light-shielding metal wire; 162, second insulating layer; 162A, opening in insulating layer; 163, second light-shielding metal layer; 1631, second light-shielding metal wire;

[0040] 17. Support column; 18. Organic light-shielding structure; 19. Buffer layer; 20. Opposing substrate;

[0041] 21, Connection structure; 211, First connection structure; 212,

[0042] 31. Metal-oxide transistor; 32. Low-temperature polysilicon transistor;

[0043] 41, signal line; 411, data line; 412, scan line. Embodiments of the present invention

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0045] As shown in Figures 1 to 5, this application provides a display panel 100. The display panel 100 has a display area 100a. The display panel 100 includes an array substrate 10. The array substrate 10 includes a substrate 11, a driving circuit layer 12, a first transparent electrode layer 13, a second transparent electrode layer 14, a first insulating layer 15, and a light-shielding stack 16.

[0046] As shown in Figures 1 to 5, the driving circuit layer 12 is disposed on one side of the substrate 11. The driving circuit layer 12 includes signal lines 41 located in the display area 100a.

[0047] A first transparent electrode layer 13 is disposed on the side of the driving circuit layer 12 facing away from the substrate 11. A second transparent electrode layer 14 is disposed on the side of the first transparent electrode layer 13 facing away from the driving circuit layer 12. The first transparent electrode layer 13 is one of a pixel electrode layer and a common electrode layer, and the second transparent electrode layer 14 is the other of a pixel electrode layer and a common electrode layer. The pixel electrode layer includes a plurality of pixel electrodes arranged in an array and spaced apart from each other. During the display process of the display panel, voltages are applied to the pixel electrodes and the common electrode layer respectively. The voltage difference between the pixel electrodes and the common electrode layer forms an electric field, which drives the liquid crystal of the display panel to rotate, controlling the light transmittance of the display panel.

[0048] As shown in Figures 1 to 5, in one exemplary embodiment, the first transparent electrode layer 13 can be a pixel electrode layer, and the second transparent electrode layer 14 is a common electrode layer. The pixel electrode layer includes a plurality of pixel electrodes spaced apart. In another exemplary embodiment, the first transparent electrode layer 13 can be a common electrode layer, and the second transparent electrode layer 14 is a pixel electrode layer.

[0049] The first transparent electrode layer 13 and the second transparent electrode layer 14 include a transparent conductive material, which includes at least one of indium tin oxide and indium zinc oxide.

[0050] A first insulating layer 15 is disposed between the first transparent electrode layer 13 and the second transparent electrode layer 14 to insulate the first transparent electrode layer 13 from the second transparent electrode layer 14. The orthographic projection of the second transparent electrode layer 14 onto the substrate 11 overlaps with the orthographic projection of the first transparent electrode layer 13 onto the substrate 11. Thus, the second transparent electrode layer 14, the first transparent electrode layer 13, and the first insulating layer 15 form a storage capacitor.

[0051] In some embodiments, the first insulating layer 15 may be disposed throughout the entire display area 100a to reduce the risk of short circuit between the first transparent electrode layer 13 and the second transparent electrode layer 14. When the first insulating layer 15 is disposed throughout the entire display area 100a, vias for electrical connection may be provided on the first insulating layer 15, or no vias may be provided.

[0052] In some embodiments, the first insulating layer 15 may also be disposed in the border area 100b outside the display area 100a. Thus, a portion of the first insulating layer 15 serves an insulating function in the border area 100b, and the manufacturing process of the second insulating layer 162 can be simplified. In other embodiments, the first insulating layer 15 may also include an opening located in the border area 100b.

[0053] In some embodiments, the first insulating layer 15 is located throughout the display area 100a and the border area 100b, thereby omitting the etching process of the first insulating layer 15 and simplifying the manufacturing process of the display panel 100. Wherein, when the first insulating layer 15 is located throughout the display area 100a and the border area 100b, vias for electrical connection may be provided on the first insulating layer 15, or no vias may be provided.

[0054] The light-shielding stack 16 is disposed on the side of the first insulating layer 15 away from the driving circuit layer 12 and on the side of the second transparent electrode layer 14. The light-shielding stack 16 provides light shielding for structures such as the signal line 41 and has low reflectivity. By adopting the design of the light-shielding stack 16, the size of the light-shielding matrix located above the signal line in the prior art can be smaller, thereby increasing the aperture ratio of the high-resolution display panel 100 and improving the display effect of the display panel 100.

[0055] As shown in Figures 1 to 5, the light-shielding stack 16 includes a first light-shielding metal layer 161, a second insulating layer 162, and a second light-shielding metal layer 163 stacked sequentially. Compared with a single light-shielding metal layer, the design of two light-shielding metal layers combined with the second insulating layer 162 in the light-shielding stack 16 can better reduce the reflectivity of the light-shielding stack 16 and improve the display effect of the display panel 100.

[0056] As shown in Figures 1 to 6, a first light-shielding metal layer 161 is disposed on the side of the first insulating layer 15 opposite to the first transparent electrode layer 13, and includes a first light-shielding metal line 1611 located in the display area 100a. The orthographic projection of the first light-shielding metal line 1611 on the substrate 11 overlaps with the orthographic projection of the signal line 41 on the substrate 11. A second light-shielding metal layer 163 is located on the side of the first light-shielding metal layer 161 opposite to the driving circuit layer 12, and includes a second light-shielding metal line 1631 located in the display area 100a. The orthographic projection of the second light-shielding metal line 1631 on the substrate 11 overlaps with the orthographic projections of the first light-shielding metal line 1611 and the signal line 41 on the substrate 11. A second insulating layer 162 is located between the first light-shielding metal layer 161 and the second light-shielding metal layer 163, and is in contact with the first insulating layer 15. As shown in Figures 1 to 5, in the display area 100a, the orthographic projection of the second insulating layer 162 on the substrate 11 covers the orthographic projection of the first transparent electrode layer 13 on the substrate 11.

[0057] It should be noted that the orthographic projection of the second insulating layer 162 on the substrate 11 in the display area 100a covers the orthographic projection of the first transparent electrode layer 13 on the substrate 11, including: the orthographic projection of the first transparent electrode layer 13 on the substrate 11 in the display area 100a is located within the orthographic projection of the second insulating layer 162 on the substrate 11, or the orthographic projection of the first transparent electrode layer 13 on the substrate 11 in the display area 100a completely overlaps with the orthographic projection of the second insulating layer 162 on the substrate 11.

[0058] By employing the aforementioned light-shielding stack 16 design, the light-shielding stack composed of the first light-shielding metal line 1611, the second light-shielding metal line 1631, and the second insulating layer 162 can effectively shield the signal line 41 and has low reflectivity, thereby improving the display effect of the display panel 100. Simultaneously, in the display area 100a, the orthogonal projection of the second insulating layer 162 onto the substrate 11 covers the orthogonal projection of the first transparent electrode layer 13 onto the substrate 11. This allows the second insulating layer 162 to cover the first insulating layer 15 located on the first transparent electrode layer 13, thus preserving at least the second insulating layer 162 located above the first transparent electrode layer 13. This reduces the problem of loss of the first insulating layer 15 on the first transparent electrode layer 13 due to etching the second insulating layer 162 above the first transparent electrode layer 13, and improves the problem of reduced performance of the storage capacitor formed by the first transparent electrode layer 13 and the second transparent electrode layer 14 due to the reduction of the first insulating layer 15.

[0059] For example, as shown in FIG1, a second insulating layer 162 is disposed in a portion of the display area 100a, and the orthographic projection of the second insulating layer 162 on the substrate 11 in the display area 100a covers the orthographic projection of the first transparent electrode layer 13 on the substrate 11. The second insulating layer 162 includes an insulating layer opening 162A that penetrates the second insulating layer 162. The orthographic projection of the insulating layer opening 162A on the substrate 11 is offset from the orthographic projection of the first transparent electrode layer 13 on the substrate 11.

[0060] In some embodiments, as shown in FIGS. 2 to 5, the orthographic projection of the second insulating layer 162 onto the substrate 11 at least covers the display area 100a. Thus, the second insulating layer 162 located in the display area 100a is retained, thereby eliminating the need to etch the second insulating layer 162 in the display area 100a. This further mitigates the problem of the first insulating layer 15 on the first transparent electrode layer 13 being lost due to etching the second insulating layer 162, and also improves the problem of reduced performance of the storage capacitor formed by the first transparent electrode layer 13 and the second transparent electrode layer 14 due to the reduction of the first insulating layer 15.

[0061] For example, as shown in FIG2, the orthographic projection of the second insulating layer 162 on the substrate 11 covers the entire display area 100a. The second insulating layer 162 includes an insulating layer opening 162A, which is located in the border area 100b outside the display area 100a.

[0062] In some embodiments, as shown in Figures 1, 3 to 5, a portion of the second insulating layer 162 may also be located in the border area 100b outside the display area 100a. Thus, the portion of the second insulating layer 162 serves an insulating function in the border area 100b, and also simplifies the manufacturing process of the second insulating layer 162. In other embodiments, the second insulating layer 162 may further include an opening located in the border area 100b.

[0063] For example, as shown in Figures 3 to 5, the second insulating layer 162 is located throughout the display area 100a and the border area 100b, thus omitting the etching process of the second insulating layer 162, simplifying the manufacturing difficulty of the light-shielding stack 16, and reducing the risk of over-etching the first insulating layer 15 during the etching of the second insulating layer 162. This also improves the problem of reduced performance of the storage capacitor formed by the first transparent electrode layer 13 and the second transparent electrode layer 14 due to the reduction of the first insulating layer 15. When the second insulating layer 162 is located throughout the display area 100a and the border area 100b, vias for electrical connection may or may not be provided in the second insulating layer 162.

[0064] In some embodiments, the light-shielding stack 16 is located on the side of the second transparent electrode layer 14 facing away from the substrate 11. In this way, the light-shielding stack 16 better shields the structure below it and reduces the impact of its manufacturing process on other structures.

[0065] As shown in Figures 1 to 3, in some embodiments, when the light-shielding stack 16 is located on the side of the second transparent electrode layer 14 facing away from the substrate 11, the first light-shielding metal layer 161 is located on the surface of the second transparent electrode layer 14 facing away from the substrate 11, the second insulating layer 162 covers the second transparent electrode layer 14, the first light-shielding metal layer 161, and the first insulating layer 15 and is in contact with the first insulating layer 15, and the second light-shielding metal layer 163 is located on the surface of the second insulating layer 162 facing away from the substrate 11. Thus, the first light-shielding metal layer 161 is located on the second transparent electrode layer 14, and when the second transparent electrode layer 14 is energized, the first light-shielding metal layer 161 is also energized, improving the problem of electrostatic discharge damage caused by the floating first light-shielding metal wire 1611.

[0066] As shown in Figures 1, 3 and 4, in some embodiments, the second transparent electrode layer 14 is provided with an opening 14a, the opening 14a exposes the first insulating layer 15, and the second insulating layer 162 contacts the first insulating layer 15 through the opening 14a.

[0067] As shown in Figure 5, in some embodiments, the light-shielding stack 16 is located between the second transparent electrode layer 14 and the first insulating layer 15. Thus, the light-shielding stack 16 is closer to the signal line 41, providing better shielding for the signal line 41.

[0068] In some embodiments, when the light-shielding stack 16 is located between the second transparent electrode layer 14 and the first insulating layer 15, the first light-shielding metal layer 161 is located on the surface of the first insulating layer 15 facing away from the first transparent electrode layer 13, the second insulating layer 162 covers the first light-shielding metal layer 161 and the first insulating layer 15 and is in contact with the first insulating layer 15, the second light-shielding metal layer 163 is located on the second insulating layer 162, and the second transparent electrode layer 14 is located on the second light-shielding metal layer 163 and the second insulating layer 162. Thus, the second transparent electrode layer 14 is located on the second light-shielding metal layer 163. When the second transparent electrode layer 14 is energized, the second light-shielding metal wire 1631 is also energized, improving the problem of electrostatic discharge damage caused by the floating of the second light-shielding metal wire 1631.

[0069] As shown in Figures 1 to 5, in some embodiments, the display panel 100 further includes a bezel area 100b located around the display area 100a. The array substrate 10 also includes a connection structure 21 located in the bezel area 100b and connected to at least one of the second light-shielding metal line 1631 and the first light-shielding metal line 1611. The connection structure 21 is used to transmit voltage. Thus, the connection structure 21 provides voltage to at least one of the second light-shielding metal line 1631 and the first light-shielding metal line 1611, mitigating the problem of electrostatic discharge damage caused by the floating of the second light-shielding metal line 1631 and the first light-shielding metal line 1611.

[0070] When the first light-shielding metal layer 161 is located on the second transparent electrode layer 14, the second light-shielding metal line 1631 is connected to the connection structure 21. When the second transparent electrode layer 14 is located on the second light-shielding metal layer 163, the first light-shielding metal line 1611 is connected to the connection structure 21.

[0071] As shown in Figures 1 to 5, in some embodiments, the first light-shielding metal layer 161 may include a first connection structure 211 located in the border region 100b. The second light-shielding metal layer 163 includes a second connection structure 212 located in the border region 100b. The first connection structure 211 and the second connection structure 212 can be connected via a connection on the second insulating layer 162 located in the border region 100b. The connection structure 21 includes the first connection structure 211 and the second connection structure 212.

[0072] In some embodiments, the orthographic projection of at least one first light-shielding metal line 1611 on the substrate 11 lies within the orthographic projection of at least one second light-shielding metal line 1631 on the substrate 11; and / or, the orthographic projection of at least one second light-shielding metal line 1631 on the substrate 11 lies within the orthographic projection of at least one first light-shielding metal line 1611 on the substrate 11; and / or, the orthographic projection of at least one second light-shielding metal line 1631 on the substrate 11 completely overlaps with the orthographic projection of at least one first light-shielding metal line 1611 on the substrate 11. Thus, the first light-shielding metal line 1611 and the second light-shielding metal line 1631 overlap to better achieve the light-shielding effect.

[0073] In this configuration, the orthographic projection of at least one first light-shielding metal line 1611 on the substrate 11 lies within the orthographic projection of at least one second light-shielding metal line 1631 on the substrate 11 (as shown in Figures 2 and 5), and / or, the orthographic projection of at least one second light-shielding metal line 1631 on the substrate 11 lies within the orthographic projection of at least one first light-shielding metal line 1611 on the substrate 11 (as shown in Figure 1). This not only provides better light-shielding but also reduces the etching difficulty of either the first light-shielding metal line 1611 or the second light-shielding metal line 1631, thereby reducing the manufacturing difficulty of the display panel 100.

[0074] In the design shown in Figures 3 and 4, the orthographic projection of at least one second light-shielding metal line 1631 on the substrate 11 completely overlaps with the orthographic projection of at least one first light-shielding metal line 1611 on the substrate 11, which not only provides better light-shielding but also reduces the reflectivity of the second light-shielding metal line 1631 and the first light-shielding metal line 1611 to light, thereby further improving the display effect of the display panel 100.

[0075] It should be noted that the orthographic projection of at least one second light-shielding metal line 1631 on the substrate 11 completely overlaps with the orthographic projection of at least one first light-shielding metal line 1611 on the substrate 11. Complete overlap includes complete overlap within the process deviation range. Furthermore, the overlap design of the first light-shielding metal line 1611 and the second light-shielding metal line 1631 can adopt any one, two, or three of the designs in Figures 1, 2, and 3.

[0076] In some embodiments, the driving circuit layer 12 further includes a metal-oxide transistor 31 and a conductive structure 126. The metal-oxide transistor 31 is located in the display area 100a and connected to the signal line 41. The conductive structure 126 connects the metal-oxide active layer 1221 of the metal-oxide transistor 31 to one of the first transparent electrode layer 13 and the second transparent electrode layer 14. The conductive structure 126 includes a transparent conductive portion 127 located in the display area 100a. Thus, the metal-oxide active layer 1221 of the metal-oxide transistor 31 is transparent, and the transparent conductive portion 127 is also transparent. The combination of the two further improves the aperture ratio of the high-resolution display panel 100 and improves the display effect of the display panel 100.

[0077] In some embodiments, the transparent conductive portion 127 includes a first transparent conductive portion 1271 and a second transparent conductive portion 1272. The first transparent conductive portion 1271 is in contact with the metal oxide active layer 1221 of the metal oxide transistor 31. The second transparent conductive portion 1272 is located on the side of the first transparent conductive portion 1271 facing away from the substrate 11 and is connected between the first transparent conductive portion 1271 and one of the first transparent electrode layer 13 and the second transparent electrode layer 14. Thus, the entire conductive structure 126 is transparent, thereby further improving the aperture ratio of the high-resolution display panel 100 and improving the display effect of the display panel 100.

[0078] In some embodiments, the metal-oxide transistor 31 includes a metal-oxide active layer 1221 and a gate, with the gate facing the metal-oxide active layer 1221. The gate may be located on one side of the metal-oxide active layer 1221 or on both sides of the metal-oxide active layer 1221.

[0079] When the gate can be located on one side of the metal oxide active layer 1221, the metal oxide transistor 31 is a single-gate metal oxide transistor 31. This simplifies the structure and manufacturing process of the metal oxide transistor 31.

[0080] The gate may include a first gate 1231B and a second gate 1232A connected to each other. The first gate 1231B and the second gate 1232A are located on opposite sides of the metal oxide active layer 1221, respectively. The first gate 1231B is located between the substrate 11 and the metal oxide active layer 1221, and the second gate 1232A is located on the side of the metal oxide active layer 1221 facing away from the substrate 11. In this case, the metal oxide transistor 31 is a dual-gate metal oxide transistor, which increases the on-state current of the metal oxide transistor 31 and reduces its off-state leakage current.

[0081] In some embodiments, the areas of the first gate 1231B and the second gate 1232A may be different to simplify the gate manufacturing process. Exemplarily, the orthographic projection of the second gate 1232A on the substrate 11 lies within the orthographic projection of the first gate 1231B on the substrate 11.

[0082] In some embodiments, the driving circuit layer 12 further includes a first connection hole H1. The first connection hole H1 exposes the metal oxide active layer 1221 of the metal oxide transistor 31. At least a portion of a first transparent conductive portion 1271 is located within the first connection hole H1 and contacts the metal oxide active layer 1221. Thus, the first transparent conductive portion 1271 located in the first connection hole H1 connects the metal oxide active layer 1221 and the second transparent conductive portion 1272.

[0083] In some embodiments, the first connection hole H1 penetrates at least one inorganic insulating layer.

[0084] In some embodiments, the drive circuit layer 12 further includes a second connection hole H2. The second connection hole H2 exposes the first transparent conductive portion 1271. At least a portion of the second transparent conductive portion 1272 is located within the second connection hole H2 and contacts the first transparent conductive portion 1271. Thus, the second transparent conductive portion 1272 located in the second connection hole H2 connects the first transparent conductive portion 1271 to one of the first transparent electrode layer 13 and the second transparent electrode layer 14. Furthermore, the design of the first connection hole H1 in conjunction with the second connection hole H2 can reduce the risk of connection failure between the metal oxide transistor 31 and one of the first transparent electrode layer 13 and the second transparent electrode layer 14.

[0085] In some embodiments, the second connection hole H2 penetrates at least one organic insulating layer.

[0086] In some embodiments, the second connecting hole H2 is offset from the first connecting hole H1 to ensure that the second transparent conductive portion 1272 and the first transparent conductive portion 1271 can be better connected.

[0087] In some embodiments, the display panel 100 further includes a support pillar 17 and an organic filler material 1281. The support pillar 17 serves to maintain the cell thickness of the display panel 100. The support pillar 17 is located in the display area 100a and on the side of the second transparent electrode layer 14 facing away from the substrate 11. The orthographic projection of the support pillar 17 on the substrate 11 overlaps with the orthographic projection of the second connection hole H2 on the substrate 11. The organic filler material 1281 fills the second connection hole H2. The support pillar 17 is generally located in the non-light-emitting area. The overlap between the support pillar 17 and the second connection hole H2 can further improve the aperture ratio of the high-resolution display panel 100 and improve the display effect of the display panel 100. Furthermore, the organic filler material 1281 is located within the second connection hole H2, ensuring that the support pillar 17 is at a higher height, providing better support and reducing the risk of the support pillar 17 sliding under external force and losing the alignment layer.

[0088] In some embodiments, the support column 17 comprises an organic material. This is to improve the impact resistance of the support column 17.

[0089] In some embodiments, the display panel 100 further includes a padding structure 1282. The padding structure 1282 is located in the display area 100a and is disposed on the side of the second connection hole H2 opposite to the substrate 11. The orthographic projection of the padding structure 1282 on the substrate 11 overlaps with the orthographic projections of the organic filler material 1281 and the support pillar 17 on the substrate 11. Thus, the padding structure 1282 further raises the position of the support pillar 17 to better fix the support pillar 17 and improve the problem of the support pillar 17 slipping onto the alignment layer (not shown) of the light-emitting area, causing damage to the organic alignment layer and resulting in display defects.

[0090] In some embodiments, the raised structure 1282 includes an organic support block. This allows the raised structure 1282 to be thicker, better securing the support pillar 17, and increasing the distance between the bottom of the support pillar 17 in contact with the array substrate 10 and the alignment layer of the light-emitting area, making it less likely for the support pillar 17 to scratch the alignment layer of the light-emitting area. The organic support block may include an organic insulating material. The organic support block may also include a black organic material so that the raised structure 1282 also serves a light-shielding function. In other embodiments, the raised structure 1282 may also include an inorganic support block.

[0091] As shown in Figures 1 to 3, in some embodiments, at least one raised structure 1282 is located between the organic filler material 1281 and the first transparent electrode layer 13, and is in contact with both the first transparent electrode layer 13 and the organic filler material 1281. This improves the bonding strength between the raised structure 1282 and the organic filler material 1281.

[0092] As shown in Figures 4 and 5, in some embodiments, at least one raised structure 1282 is located on the side of the first transparent electrode layer 13 facing away from the substrate 11. This reduces the impact of the height of the raised structure 1282 on the first transparent electrode layer 13 and other film layers.

[0093] In other embodiments, at least one raised structure 1282 is located between the organic filler material 1281 and the first transparent electrode layer 13, and at least one raised structure 1282 is located on the side of the first transparent electrode layer 13 facing away from the substrate 11.

[0094] In some embodiments, the light-shielding stack 16 is located on the side of the second transparent electrode layer 14 facing away from the substrate 11, and at least one padding structure 1282 is located on the side of the light-shielding stack 16 facing away from the substrate 11. In this way, the influence of the height of the padding structure 1282 on the film layers such as the first transparent electrode layer 13 and the second transparent electrode layer 14 is reduced.

[0095] In some embodiments, the display panel 100 further includes an organic light-shielding structure 18. The organic light-shielding structure 18 is located on the side of the light-shielding stack 16 facing away from the substrate 11. The orthographic projection of the organic light-shielding structure 18 onto the substrate 11 overlaps with the orthographic projections of the first light-shielding metal line 1611 and the second light-shielding metal line 1631 onto the substrate 11. This provides better light-shielding. Due to the design of the first light-shielding metal line 1611 and the second light-shielding metal line 1631, the size of the organic light-shielding structure 18 can be smaller, thereby increasing the aperture ratio of the high-resolution display panel 100.

[0096] In some embodiments, the orthographic projection of the organic light-shielding structure 18 onto the substrate 11 also overlaps with the orthographic projection of the support pillar 17 onto the substrate 11. Thus, the organic light-shielding structure 18 also serves to shield the support pillar 17.

[0097] In some embodiments, the organic light-shielding structure 18 includes a black matrix.

[0098] In some embodiments, the display panel 100 further includes a counter substrate 20 disposed opposite to the array substrate 10. The support pillar 17 may be located on the array substrate 10 or on the counter substrate 20. The organic light-shielding structure 18 may be located on the array substrate 10 or on the counter substrate 20.

[0099] In some embodiments, the array substrate 10 further includes a color filter layer 125 disposed on the substrate 11. Thus, the color filter layer 125 is located on the array substrate 10 to improve the large viewing angle color shift problem of the display panel 100.

[0100] In some embodiments, the color filter layer 125 includes multiple photoresists of different colors, such as red photoresist, green photoresist, and blue photoresist.

[0101] In some embodiments, the color filter layer 125 is located inside the driving circuit layer 12 and between adjacent insulating layers.

[0102] In some embodiments, the driving circuit layer 12 includes a low-temperature polysilicon transistor 32 located in the frame region 100b. Thus, the design of the low-temperature polysilicon transistor 32 can improve the stability of the gate driving circuit and other circuits located in the frame region 100b under high temperature and high humidity conditions. The low-temperature polysilicon transistor 32 includes a low-temperature polysilicon active layer 1211.

[0103] As shown in Figure 6, in some embodiments, the signal line 41 includes at least one of a data line 411 and a scan line 412 that are insulated from each other. The extension direction of the data line 411 intersects the extension direction of the scan line 412, and the data line 411 and the scan line 412 are insulated from each other. Exemplarily, a plurality of first light-shielding metal lines 1611 extend along the extension directions of the data line 411 and the scan line 412, respectively, and a plurality of second light-shielding metal lines 1631 extend along the extension directions of the data line 411 and the scan line 412, respectively. Each data line 411 overlaps with one first light-shielding metal line 1611 and one second light-shielding metal line 1631. Each scan line 412 overlaps with another first light-shielding metal line 1611 and another second light-shielding metal line 1631.

[0104] It is understandable that a first light-shielding metal line 1611 and a second light-shielding metal line 1631, as a whole, can also overlap with only one of the data line 411 and the scan line 412 to block either the data line 411 or the scan line 412.

[0105] In some embodiments, the driving circuit layer 12 may include a cryogenic polysilicon semiconductor layer 121 and a metal-oxide-semiconductor layer 122. The metal-oxide-semiconductor layer 122 is located on the side of the cryogenic polysilicon semiconductor layer 121 facing away from the substrate 11. The metal-oxide-semiconductor layer 122 includes the metal-oxide active layer 1221 of the metal-oxide transistor 31. The cryogenic polysilicon semiconductor layer 121 includes the cryogenic polysilicon active layer 1211 of the cryogenic polysilicon transistor 32. In this way, the impact of the manufacturing process of the cryogenic polysilicon active layer 1211 on the metal-oxide active layer 1221 is reduced.

[0106] In some embodiments, the driving circuit layer 12 further includes a first conductive layer 1231, which is located between the low-temperature polysilicon semiconductor layer 121 and the metal-oxide-semiconductor layer 122. The first conductive layer 1231 includes the gate of at least one of the metal-oxide transistor 31 and the low-temperature polysilicon transistor 32. The first conductive layer 1231 may also include a scan line 412 connected to the gate. Exemplarily, the first conductive layer 1231 includes a first gate 1231B of the metal-oxide transistor 31 and a gate 1231A of the low-temperature polysilicon transistor. A first gate insulating layer 1241 is disposed between the first conductive layer 1231 and the low-temperature polysilicon semiconductor layer 121. A second gate insulating layer 1242 is disposed between the metal-oxide-semiconductor layer 122 and the first conductive layer 1231.

[0107] In some embodiments, the driving circuit layer 12 further includes a second conductive layer 1232, which is located on the side of the metal-oxide-semiconductor layer 122 facing away from the substrate 11. The second conductive layer 1232 may include a second gate 1232A of the metal-oxide-semiconductor transistor 31. The second conductive layer 1232 may also include a scan line 412 and the source and drain of the low-temperature polysilicon transistor 32. A third gate insulating layer 1243 is disposed between the second conductive layer 1232 and the metal-oxide-semiconductor layer 122.

[0108] In some embodiments, the driving circuit layer 12 further includes a third conductive layer 1233, which is located on the side of the second conductive layer 1232 facing away from the substrate 11. The third conductive layer 1233 includes a data line 411. The third conductive layer 1233 may also include a metal connection line 1233A spaced apart from the data line 411, which is located in the frame area 100b. The metal connection line is connected to voltage and is connected to the connection structure 21. A first interlayer insulating layer 1244 is disposed between the third conductive layer 1233 and the second conductive layer 1232.

[0109] In some embodiments, the driving circuit layer 12 further includes a first transparent interconnect layer 1291, which is located on the side of the third conductive layer 1233 facing away from the substrate 11. The first transparent interconnect layer 1291 includes a first transparent conductive portion 1271. A second interlayer insulating layer 1245 is disposed between the first transparent interconnect layer 1291 and the third conductive layer 1233, and the first transparent conductive portion 1271 is also located on the second interlayer insulating layer 1245. A first connection hole H1 penetrates the second interlayer insulating layer 1245, the first interlayer insulating layer 1244, and the third gate insulating layer 1243.

[0110] In some embodiments, the color filter layer 125 is located on the side of the first transparent interconnect layer 1291 facing away from the substrate 11. A third interlayer insulating layer 1246 is disposed between the color filter layer 125 and the first transparent interconnect layer 1291.

[0111] In some embodiments, the driving circuit layer 12 further includes an organic planarization layer 1247. The organic planarization layer 1247 covers the color filter layer 125. In this way, the surface of the array substrate 10 is planarized.

[0112] In some embodiments, the driving circuit layer 12 further includes a passivation layer 1248, which is located on the side of the organic planarization layer 1247 away from the substrate 11.

[0113] In some embodiments, the driving circuit layer 12 further includes a second transparent interconnect layer 1292, which is located on the side of the passivation layer 1248 facing away from the substrate 11. The second transparent interconnect layer 1292 includes a second transparent conductive portion 1272.

[0114] As shown in Figure 1, in some embodiments, the organic filler material 1281 is located between the second transparent connecting layer 1292 and the first transparent electrode layer 13. This ensures better connection between the second transparent connecting layer 1292 and the first transparent connecting layer 1291, and also ensures better connection between the second transparent connecting layer 1292 and the first transparent electrode layer 13.

[0115] In some embodiments, the first transparent electrode layer 13 is located on the surface of the second transparent connection layer 1292 away from the substrate 11 to reduce the impedance of the first transparent electrode layer 13. The first transparent electrode layer 13 also includes a transparent connection structure 131 located in the frame region 100b, the transparent connection structure 131 connecting the metal connection line 1233A and the connection structure 21.

[0116] In some embodiments, the materials of the first gate insulating layer 1241 to the third gate insulating layer 1243, the first interlayer insulating layer 1244 to the third interlayer insulating layer 1246, and the passivation layer 1248 may be inorganic insulating materials. Inorganic insulating materials include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0117] In some embodiments, the material of the organic planarization layer 1247 may be the same as, but is not limited to, the material of the organic filler material 1281 and at least one padding structure 1282.

[0118] In some embodiments, the materials of the first light-shielding metal layer 161 to the second light-shielding metal layer 163 and the first conductive layer 1231 to the third conductive layer 1233 include at least one of molybdenum, aluminum, titanium, copper and silver.

[0119] In some embodiments, the first insulating layer 15 and the second insulating layer 162 may be made of the same material to increase their bonding strength. The first insulating layer 15 and the second insulating layer 162 may be made of different materials.

[0120] In some embodiments, the array substrate 10 further includes a buffer layer 19 located between the substrate 11 and the driving circuit layer 12. The buffer layer 19 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0121] As shown in FIG7, this application also provides a display device 200, which includes the display panel 100 of any of the above embodiments.

[0122] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, wherein, The display panel has a display area and includes an array substrate, the array substrate comprising: substrate; A driving circuit layer is disposed on one side of the substrate and includes signal lines located in the display area; A first transparent electrode layer is disposed on the side of the driving circuit layer opposite to the substrate; The second transparent electrode layer is disposed on the side of the first transparent electrode layer away from the driving circuit layer, and the orthographic projection of the second transparent electrode layer on the substrate overlaps with the orthographic projection of the first transparent electrode layer on the substrate. A first insulating layer is disposed between the first transparent electrode layer and the second transparent electrode layer; and A light-shielding layer is disposed on the side of the first insulating layer opposite to the driving circuit layer, and includes: A first light-shielding metal layer is disposed on the side of the first insulating layer away from the first transparent electrode layer, and includes a first light-shielding metal line located in the display area, wherein the orthographic projection of the first light-shielding metal line on the substrate overlaps with the orthographic projection of the signal line on the substrate. A second light-shielding metal layer is located on the side of the first light-shielding metal layer opposite to the driving circuit layer, and includes a second light-shielding metal line located in the display area. The orthographic projection of the second light-shielding metal line on the substrate overlaps with the orthographic projections of the first light-shielding metal line and the signal line on the substrate. The second insulating layer is located between the first light-shielding metal layer and the second light-shielding metal layer, and is in contact with the first insulating layer. In the display area, the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the first transparent electrode layer on the substrate.

2. The display panel according to claim 1, wherein, The orthographic projection of the second insulating layer on the substrate at least covers the display area.

3. The display panel according to claim 1, wherein, The light-shielding stack is located on the side of the second transparent electrode layer that is away from the substrate.

4. The display panel according to claim 3, wherein, The first light-shielding metal layer is located on the surface of the second transparent electrode layer facing away from the substrate. The second insulating layer covers the second transparent electrode layer, the first light-shielding metal layer, and the first insulating layer. The second light-shielding metal layer is located on the surface of the second insulating layer facing away from the substrate.

5. The display panel according to claim 1, wherein, The light-shielding layer is located between the second transparent electrode layer and the first insulating layer.

6. The display panel according to claim 5, wherein, The first light-shielding metal layer is located on the surface of the first insulating layer opposite to the first transparent electrode layer. The second insulating layer covers the first light-shielding metal layer and the first insulating layer. The second light-shielding metal layer is located on the second insulating layer. The second transparent electrode layer is located on the second light-shielding metal layer and the second insulating layer.

7. The display panel according to claim 1, wherein, The orthographic projection of at least one of the first light-shielding metal lines on the substrate lies within the orthographic projection of the at least one of the second light-shielding metal lines on the substrate; And / or, The orthographic projection of at least one of the second light-shielding metal lines on the substrate lies within the orthographic projection of at least one of the first light-shielding metal lines on the substrate; And / or, The orthographic projection of at least one of the second light-shielding metal lines on the substrate completely overlaps with the orthographic projection of the at least one of the first light-shielding metal lines on the substrate.

8. The display panel according to claim 1, wherein, The driving circuit layer further includes: Metal-oxide transistors, located in the display area; and A conductive structure connects the metal oxide active layer of the metal oxide transistor to one of the first transparent electrode layer and the second transparent electrode layer, the conductive structure including a transparent conductive portion located in the display area.

9. The display panel according to claim 8, wherein, The transparent conductive portion includes: The first transparent conductive portion is in contact with the metal oxide active layer of the metal oxide transistor; and The second transparent conductive portion is located on the side of the first transparent conductive portion away from the substrate, and is connected between the first transparent conductive portion and one of the first transparent electrode layer and the second transparent electrode layer.

10. The display panel according to claim 9, wherein, The driving circuit layer further includes: A first connection hole exposes the metal oxide active layer of the metal oxide transistor, and at least a portion of the first transparent conductive portion is located within the first connection hole and in contact with the metal oxide active layer.

11. The display panel according to claim 9, wherein, The driving circuit layer further includes: A second connection hole exposes the first transparent conductive portion, and at least a portion of the second transparent conductive portion is located within the second connection hole and in contact with the first transparent conductive portion.

12. The display panel according to claim 11, wherein, The display panel also includes: A support pillar, located in the display area and on the side of the second transparent electrode layer opposite to the substrate, wherein the orthographic projection of the support pillar on the substrate overlaps with the orthographic projection of the second connecting hole on the substrate; and Organic filler material is filled into the second connection hole.

13. The display panel according to claim 12, wherein, The display panel also includes: A raised structure is located in the display area, disposed on the side of the second connection hole away from the substrate, and the orthographic projection of the raised structure on the substrate overlaps with the orthographic projection of the organic filler material and the support column on the substrate.

14. The display panel according to claim 13, wherein, The raised structure includes organic support blocks.

15. The display panel according to claim 13, wherein, At least one of the raised structures is located between the organic filler material and the first transparent electrode layer, and is in contact with both the first transparent electrode layer and the organic filler material.

16. The display panel according to claim 13, wherein, At least one of the raised structures is located on the side of the first transparent electrode layer opposite to the substrate.

17. The display panel according to claim 13, wherein, The light-shielding stack is located on the side of the second transparent electrode layer away from the substrate, and at least one of the padding structures is located on the side of the light-shielding stack away from the substrate.

18. A display device, wherein, The display device includes a display panel, the display panel having a display area and including an array substrate, the array substrate including: substrate; A driving circuit layer is disposed on one side of the substrate and includes signal lines located in the display area; A first transparent electrode layer is disposed on the side of the driving circuit layer opposite to the substrate; The second transparent electrode layer is disposed on the side of the first transparent electrode layer away from the driving circuit layer, and the orthographic projection of the second transparent electrode layer on the substrate overlaps with the orthographic projection of the first transparent electrode layer on the substrate. A first insulating layer is disposed between the first transparent electrode layer and the second transparent electrode layer; and A light-shielding layer is disposed on the side of the first insulating layer opposite to the driving circuit layer, and includes: A first light-shielding metal layer is disposed on the side of the first insulating layer away from the first transparent electrode layer, and includes a first light-shielding metal line located in the display area, wherein the orthographic projection of the first light-shielding metal line on the substrate overlaps with the orthographic projection of the signal line on the substrate. A second light-shielding metal layer is located on the side of the first light-shielding metal layer opposite to the driving circuit layer, and includes a second light-shielding metal line located in the display area. The orthographic projection of the second light-shielding metal line on the substrate overlaps with the orthographic projections of the first light-shielding metal line and the signal line on the substrate. The second insulating layer is located between the first light-shielding metal layer and the second light-shielding metal layer, and is in contact with the first insulating layer. In the display area, the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the first transparent electrode layer on the substrate.

19. The display device according to claim 18, wherein, The light-shielding stack is located on the side of the second transparent electrode layer that is away from the substrate.

20. The display device according to claim 18, wherein, The driving circuit layer further includes: Metal-oxide transistors, located in the display area; and A conductive structure connects the metal oxide active layer of the metal oxide transistor to one of the first transparent electrode layer and the second transparent electrode layer, the conductive structure including a transparent conductive portion located in the display area.

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