Video recording system

Abstract

A video recording system (100) comprises: a storage (3) having a flash memory (33); a plurality of information processing devices (1); and a configuration unit (5). The configuration unit (5) determines an access size that is an integer multiple of an erase block. The configuration unit (5) allocates, on the basis of the access size, a first slot for each of a plurality of video channels respectively possessed by the plurality of information processing devices (1) such that the first slots are organized into a group of time slots for each of the information processing devices (1). A CPU (11) of each of the plurality of information processing devices (1) buffers a plurality of pieces of video data by the access size in a buffer region allocated to each video channel, and records the buffered data in the flash memory (33) in the first slot.

Description

Video Recording System

[0001] The present disclosure relates to a video recording system that stores multiple pieces of video data in a storage device configured with NAND elements.

[0002] A system is known that inputs video data output by a video output device such as a camera and records the video data in a recording device configured with a NAND element. Recording devices configured with a NAND element are known as solid state drives (SSDs), for example. The video data recorded in the recording device is used, for example, for future playback or video editing.

[0003] When recording data such as video data in storage, it is known to reduce the amount of data collected if the total rate of collected data exceeds the throughput parameters of the network infrastructure (see, for example, Patent Document 1).

[0004] Special Publication No. 2020-530159

[0005] Currently, studies are being conducted on recording devices that include NAND elements and that output multiple video data sets from multiple video output devices. Recording multiple video data sets on a recording device without any control can result in multiple video data sets being recorded simultaneously on the recording device. When attempting to simultaneously record multiple video data sets on a recording device, a large amount of video data sets is transmitted over the data line connected to the recording device, which can result in a decrease in the recording rate of the video data sets.

[0006] Furthermore, there is a possibility that video data may be recorded without taking into consideration the characteristics of a recording device configured with NAND elements. Specifically, video devices configured with NAND elements need to erase data in units called "erase blocks," but video data may not be recorded in erase block units in the recording device. In other words, video data may only be recorded up to the middle of an erase block.

[0007] When video data that has only been recorded partway through an erase block is erased, other data recorded in that erase block must be moved to another block and then re-recorded (garbage collection processing). If this processing occurs frequently, problems such as slow operation of the recording device may occur.

[0008] The present disclosure aims to prevent a decrease in the recording rate of video data and a slowdown in the operation of the recording device when a plurality of video data are stored in a storage device configured with NAND elements.

[0009] The video recording system of the present disclosure includes a storage, multiple information processing devices, and a configuration unit. The storage has a nonvolatile memory unit that writes data in page units and erases data in erase block units consisting of multiple pages. Each of the multiple information processing devices records multiple pieces of video data acquired via multiple video channels in the nonvolatile memory unit. The configuration unit sets time slots. Each of the multiple information processing devices includes a temporary storage unit and a control unit. The temporary storage unit has multiple buffer areas assigned to the multiple video channels, respectively. The control unit controls the recording of the multiple pieces of video data in the nonvolatile memory unit.

[0010] In the above video recording system, the configuration unit determines an access size. The access size is an integer multiple of the size of an erase block. The configuration unit collectively assigns time slots for each of multiple video channels owned by each of multiple information processing devices based on the access size. The control units of the multiple information processing devices each buffer multiple pieces of video data acquired via the multiple video channels in a buffer area assigned to each video channel by the access size. Furthermore, the control units of the multiple information processing devices each record the buffered data buffered in each buffer area in the nonvolatile memory unit in the time slot assigned to the video channel corresponding to each buffer area.

[0011] In the video recording system disclosed herein, video data from multiple information processing devices is not recorded simultaneously in storage. In the video recording system, time slots for each video channel are collectively assigned to each information processing device. This makes it possible to prevent a decrease in the video data recording rate due to locking between multiple information processing devices.

[0012] In the video recording system disclosed herein, video data from a corresponding video channel is buffered in each of multiple buffer areas of each information processing device by an amount equal to an integer multiple of an erase block, which is the storage's erase unit. In the video recording system, the buffered data buffered in each buffer area is recorded in the storage in a time slot assigned to the video channel corresponding to that buffer area. In other words, multiple pieces of video data (buffered data) are recorded in the storage in individually assigned time slots. This allows the data transmission bandwidth of the data line connecting the information processing device and the storage to be monopolized by the transmission of a single piece of video data (buffered data), thereby preventing a decrease in the video data recording rate.

[0013] Furthermore, in the video recording system disclosed herein, the size of buffered data recorded in one time slot is set to an integer multiple of the erase block size, which is the unit of data erasure in the storage. This reduces the occurrence of erase blocks in which video data is only partially recorded, thereby suppressing fragmentation. As a result, the occurrence of garbage collection processes is suppressed, and a decrease in the operating speed of the storage is suppressed.

[0014] FIG. 1 is a block diagram showing the configuration of a video recording system. FIG. 2 is a block diagram showing the configuration of an information processing device. FIG. 3 is a block diagram showing the configuration of a storage. FIG. 4 is a diagram showing the configuration of a recording area. FIG. 5 is a sequence diagram showing signal transmission and reception in the video recording system. FIG. 6 is a flowchart showing the operation of the information processing device in the video recording system. FIG. 7 is a diagram schematically showing the recording of video data.

[0015] Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed description of already well-known matters or redundant description of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art. Note that the inventors provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present disclosure, and do not intend for them to limit the subject matter described in the claims.

[0016] In this disclosure, "video data" refers to data including video data, audio data, and metadata, data including only video data, and data including still image data.

[0017] [1. First Embodiment] [1-1. Video Recording System] A video recording system 100 according to the present disclosure will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the video recording system 100. FIG. 2 is a block diagram showing the configuration of an information processing device 1 included in the video recording system 1. The video recording system 100 is a system that records video data acquired via multiple video channels CH1, CH2, ... CHn in a storage 3 configured with NAND elements. The video data recorded in the storage 3 is used, for example, for future playback and editing. Editing video data includes, for example, generating new video data by inserting a specific portion of other video data into video data.

[0018] The video recording system 100 includes a plurality of information processing devices 1a, 1b, ..., 1n and a storage 3. The number of information processing devices 1 provided in the video recording system 100 can be any number. The plurality of information processing devices 1a, 1b, ..., 1n have common configurations and functions. In this embodiment, when the information processing devices 1a, 1b, ..., 1n are not individually distinguished, they are simply referred to as information processing devices 1.

[0019] The information processing device 1 has a plurality of video channels CH1, CH2, ... CHn. In this embodiment, when the video channels CH1, CH2, ... CHn are not individually distinguished, they are simply referred to as video channels CH. Each video channel CH is an interface for connecting video processing devices 2. That is, the information processing device 1 is connected to a plurality of video processing devices 2 via the plurality of video channels CH. In this embodiment, video processing devices 2a, 2b, ... 2n are connected to the video channel CHs of the information processing devices 1a, 1b, ... 1n, respectively. In this embodiment, when the video processing devices 2a, 2b, ... 2n are not individually distinguished, they are simply referred to as video processing devices 2.

[0020] The video processing device 2 is a device that acquires video and audio data, converts it into electrical signals, and outputs it externally as video data. The video processing device 2 is, for example, a video capture device equipped with a camera that captures a predetermined video, a microphone that captures the audio of the predetermined video, etc. Alternatively, the video processing device 2 may be a media server that records a large number of videos. The video output from the video processing device 2 is, for example, high-quality video such as uncompressed 4K video. As shown in FIG. 2 , the video processing device 2 has an output interface 21 that connects the information processing device 1 and the video processing device 2. The output interface 21 can be connected to a video channel CH of the information processing device 1.

[0021] The video channel CH may be connected to a video playback device that acquires video data from the information processing device 1 and displays it on a display device (e.g., a display), or a device that performs operations to edit the video data.

[0022] The information processing device 1 executes various information processes related to the video data input from the video processing device 2. Specifically, for example, the information processing device 1 can execute a process of converting the video data into compressed data. The information processing device 1 can also output the video data to an external device in uncompressed format. The information processing device 1 can edit the video data in accordance with user operations. Furthermore, if the external device connected to the information processing device 1 is a video display device, the information processing device 1 can also function as a video playback device.

[0023] The information processing device 1 is connected to a storage 3. The information processing device 1 records video data input from the video processing device 2, video data converted into a compressed format, edited video data, etc. in the storage 3. The information processing device 1 also outputs video data acquired from the storage 3 to a video playback device or the like.

[0024] The information processing device 1 buffers multiple pieces of video data from multiple video processing devices 2 in buffer areas BF1, BF2, ..., BFn assigned to video channels CH1, CH2, ..., CHn, respectively, by an integer multiple of the size of the erase block BL of the storage 3. In this embodiment, when the buffer areas BF1, BF2, ..., BFn are not individually distinguished, they are simply referred to as buffer areas BF. The video data buffered in the buffer areas BF are referred to as "buffered data." The information processing device 1 records the buffered data buffered in the buffer areas BF assigned to each video channel CH in the storage 3 in the time slot assigned to that video channel CH.

[0025] The storage 3 records video data received from the information processing device 1 in accordance with a command from the information processing device 1. The storage 3 also reads designated video data in accordance with a command from the information processing device 1. As will be described later, the storage 3 is a recording device configured with a NAND element. The storage 3 is, for example, a solid state drive (SSD). In the video recording system 100 of this embodiment, one storage 3 is provided, but two or more storages 3 may be provided. The number of storages 3 provided in the video recording system 100 can be any number.

[0026] The video recording system 100 includes a configuration unit 5. The configuration unit 5 is connected to multiple information processing devices 1 and an arbitration unit 6 (described later). The configuration unit 5 performs settings related to time slots. Specifically, the configuration unit 5 determines the size of video data that can be recorded or transmitted in one time slot (hereinafter referred to as access size) based on the size of the erase block BL of the storage 3, and notifies the information processing devices 1 and the arbitration unit 6 of this size. The configuration unit 5 individually assigns time slots to each of multiple video channels CH of the multiple information processing devices 1. At this time, the configuration unit 5 assigns time slots so that the time slots for multiple video channels CH of one information processing device 1 are grouped together, as shown in FIG. 7. FIG. 7 is a diagram schematically illustrating the recording of video data. A time slot consisting of multiple time slots assigned to one information processing device 1 is called a first slot. In other words, the first slot refers to the time during which the information processing device 1 to which it is assigned is permitted to access the storage 3. Furthermore, a time slot means a time during which video data acquired from a video channel CH to which the time slot is assigned is permitted to be recorded, or a time during which video data is permitted to be transmitted to a video channel CH to which the time slot is assigned. The configuration unit 5 notifies the information processing device 1 and the arbitration unit 6 of the settings related to the time slot.

[0027] The component 5 is, for example, hardware configured by circuits that realize the above functions. The component 5 may be a computer system that includes a CPU (Central Processing Unit), a storage device, various interfaces, etc., and realizes the above functions. The component 5 may realize some or all of the above functions by software. The functions of the component 5 may be realized by any of the information processing devices 1.

[0028] The video recording system 100 includes an arbitration unit 6. The arbitration unit 6 is connected to the multiple information processing devices 1 and the configuration unit 5. When an access request to the storage 3 is made from one information processing device 1, that is, information processing device 1a, the arbitration unit 6 determines whether or not to permit access to the storage 3 from the information processing device 1a and notifies the information processing device 1a of the decision result. The same applies when an access request is made from other information processing devices 1b, ..., 1n.

[0029] The arbitration unit 6 is, for example, hardware configured by circuits that realize the above functions. The arbitration unit 6 may be a computer system that includes a CPU, a storage device, various interfaces, etc. and realizes the above functions. The arbitration unit 6 may realize some or all of the above functions by software. The functions of the arbitration unit 6 may be realized by any of the information processing devices 1.

[0030] 2, the configuration of the information processing device 1 will be described. The information processing device 1 has a CPU (controller) 11, a RAM (Random Access Memory) (temporary storage unit) 12, a storage device 13, a video interface 14, a storage interface 15, and an interface 16.

[0031] The CPU 11 executes various processes in the information processing device 1. Specifically, the CPU 11 executes information processes such as video data compression, information processing related to video data editing, and video data analysis. The CPU 11 executes the above processes by executing instructions indicated in a program stored in the storage device 13. Note that some of the processes in the information processing device 1 may be realized by hardware implemented separately from the CPU 11 or by an external device. The CPU 11 generates commands for executing various processes.

[0032] The RAM 12 is a storage area that temporarily stores commands, video data, etc. generated by the CPU 11. In the RAM 12, buffer areas BF1, BF2, ..., BFn are allocated to the video channels CH1, CH2, ..., CHn, respectively. The buffer areas BF1, BF2, ..., BFn are temporary storage areas that buffer the video data acquired via the corresponding video channels CH1, CH2, ..., CHn. The size of one buffer area BF is set to a size that provides a certain margin for the access size.

[0033] The storage device 13 is configured with at least one of a ROM (Read Only Memory), a hard disk (HDD), a solid state drive (SSD), etc. The storage device 13 stores programs executed by the CPU 11, settings related to the processing of the information processing device 1, parameters used for the processing, etc.

[0034] The video interface 14 connects the information processing device 1 and the video processing device 2. As shown in FIG. 2 , the video interface 14 is provided with a plurality of connection terminals. One of the plurality of connection terminals of the video interface 14 corresponds to one video channel CH. The connection terminals can be connected to the video processing device 2. One video processing device 2 may be connected to only one connection terminal (i.e., one video channel CH), or may be connected to multiple connection terminals of one information processing device 1 (i.e., multiple video channel CHs of one information processing device 1), or may be connected to multiple connection terminals of multiple information processing devices 1 (i.e., multiple video channel CHs of multiple information processing devices 1). The video interface 14 is an interface for connecting video-related devices, such as an interface conforming to the Serial Digital Interface (SDI) standard.

[0035] Alternatively, the video interface 14 may be a network interface, in which case transmission according to the ST2110 standard of the SMPTE standardization organization, for example, may be used.

[0036] The storage interface 15 connects the information processing device 1 and the storage 3. The storage interface 15 connects the information processing device 1 and the storage 3 via a direct transfer path. The storage interface 15 is, for example, a PCIe interface that complies with the PCI express standard of the PCI-SIG standard. This allows the information processing device 1 and the storage 3 to send and receive data at high speed using a protocol dedicated to non-volatile memory (NVMe (Non-Volatile Memory Express)) using a PCI-Express bus.

[0037] In NVMe, the controller acquires data from the NAND memory using the NAND protocol, converts it to the PCIe protocol, and transfers it to the host. In contrast, with conventional SATA (Serial-ATA), the DMA controller that transfers data directly to the host converts data from the NAND memory to the SATA protocol, acquires it, and then converts the data to the PCIe protocol before transferring it to the host. In other words, because NVMe processing directly converts from the NAND protocol to the PCIe protocol, the data transfer processing speed is faster than conventional SATA.

[0038] The interface 16 is an interface for connecting the information processing device 1 to an external device. The interface 16 is a network interface such as a Gigabit Ethernet (registered trademark) interface that connects the information processing device 1 to an external device via a network such as a WAN (Wide Area Network) or a LAN (Local Area Network). When the configuration unit 5 and the arbitration unit 6 are configured outside the information processing device 1, the configuration unit 5 and the arbitration unit 6 are connected to the interface 16.

[0039] At least one of the storage interface 15 and the interface 16 may be capable of directly transmitting and receiving data between the RAM 12 of the information processing device 1 and a storage device of an external device by remote direct memory access (RDMA), thereby enabling high-speed data transmission and reception between the information processing device 1 and the external device.

[0040] The multiple information processing devices 1, the component unit 5, and the arbitration unit 6 synchronize their time using a protocol such as NTP (Network Time Protocol) or PTP (Precision Time Protocol). Note that the time synchronization method is not limited to the above and is arbitrary. This allows the multiple information processing devices 1, the component unit 5, and the arbitration unit 6 to acquire correct time information and synchronize their time.

[0041] [1-3. Storage] The configuration of the storage 3 will be described using Fig. 3. Fig. 3 is a diagram showing the configuration of the storage 3. The storage 3 has an access port 31, a flash memory (non-volatile memory unit) 33, a controller 35, and a storage unit 37. The access port 31 is an interface that connects the storage 3 to other devices. A plurality of information processing devices 1 are connected to the access port 31.

[0042] The flash memory 33 is composed of multiple NAND elements. A table is recorded in the flash memory 33, which associates, for example, addresses (logical addresses) designated by an external device with addresses (physical addresses) of erase blocks BL corresponding to the logical addresses. Figure 4 is a diagram showing the configuration of the recording area RA of the flash memory 33. As shown in Figure 4, the flash memory 33 has a recording area RA for recording video. The recording area RA is also divided into multiple erase blocks BL.

[0043] An erase block BL is a unit of data erasure in the flash memory 33. An erase block BL is further divided into a plurality of pages PA. A page PA is a unit of data recording. When data in an erase block BL is erased in the flash memory 33, a process (garbage collection) is executed in which the data contained in this erase block BL is moved to another erase block BL and then erased. As a result, the erase block BL from which data has been erased becomes a "free block" into which data can be written.

[0044] The controller 35 executes control related to the storage 3. In particular, the controller 35 controls the recording of data to the flash memory 33 and the reading of data from the flash memory 33. The controller 35 also executes other processes required for the solid state drive, such as garbage collection and wear leveling. The controller 35 executes the above processes by executing programs stored in the storage unit 37. The controller 35 may also realize the above processes by its own hardware.

[0045] The storage unit 37 is provided as a memory separate from the flash memory 33, or is part of the recording area RA. The storage unit 37 stores various parameters related to the control of the storage 3. The storage unit 37 stores, for example, information related to the life of the flash memory 33, the size of the page PA, the size of the erase block BL, the number of times data is recorded in each erase block BL, parameters for executing various processes, and the like.

[0046] 1-4. Operation of the Video Recording System The operation of the video recording system 100 will be described below with reference to Fig. 5 and Fig. 6. Fig. 5 is a sequence diagram showing signal transmission and reception in the video recording system 100. Fig. 6 is a flowchart showing the operation of the information processing device 1 in the video recording system 100. In Fig. 5, the explanation will be given using information processing devices 1a and 1b as an example, but the number of information processing devices 1 is not limited to this and can be any number.

[0047] First, the users of the information processing devices 1a and 1b instruct the configuration unit 5 on the mode (recording mode, playback mode) to be used when recording / playing back video data in the video recording system 100. The recording mode includes the recording rate of the video data (the amount of video data recorded per unit time), and the playback mode includes the playback rate of the video data (the amount of video data read per unit time). The recording mode may also include the video characteristics of the video data (compressed, uncompressed, etc.). These modes may be set individually for each video channel CH, or the same mode may be set for all video channels CH. In this embodiment, for convenience of explanation, it is assumed that the recording mode is set for all video channels CH1, CH2, ..., CHn. In FIG. 5, the video processing devices 2a and 2b are used as the video processing devices 2 connected to the information processing devices 1a and 1b.

[0048] Next, the configuration unit 5 requests information about the size of pages PA and erase blocks BL stored in the flash memory 33 of the storage 3 from the storage 3 (step S101 in FIG. 5). Upon receiving this request, the controller 35 of the storage 3 reads information about the size of pages PA and erase blocks BL from the memory unit 37 and transmits this information to the configuration unit 5 (step S102 in FIG. 5).

[0049] Thereafter, the configuration unit 5 determines the access size based on the size of the page PA, the size of the erase block BL, etc. received from the storage 3. The access size can be determined to be an integer multiple of the size of the erase block BL and a size that suppresses fragmentation of the video data. The configuration unit 5 may determine the access size for each video channel CH based on the recording rate of the video data, or may determine one access size that is applied to all video channel CHs.

[0050] The configuration unit 5 also sets time slots for each of the multiple video channel CHs possessed by the information processing device 1a and the information processing device 1b. The configuration unit 5 sets the duration of the time slots and the cycle for allocating time slots to each video channel CH based on the determined access size, the recording mode designated by the user, and the like. At this time, the configuration unit 5 collectively allocates time slots for each video channel CH for each information processing device 1. In other words, the configuration unit 5 allocates time slots so that the time slots for the multiple video channel CHs of one information processing device 1 are grouped together in a time period. The time period grouped together for each information processing device 1 in this way is the above-mentioned first slot. As shown in FIG. 7 , one first slot is composed of one or more time slots.

[0051] Specifically, the configuration unit 5 calculates the processing time for processing video data acquired from a specific video channel CHk based on the data transfer rate between the information processing device 1 and the storage 3 and the access size of the specific video channel CHk, and sets this as the length of the time slot to be allocated to the specific video channel CHk. The configuration unit 5 may calculate the processing time by subtracting a predetermined margin from the data transfer rate between the information processing device 1 and the storage 3. Furthermore, the configuration unit 5 calculates the processing cycle required for the video data based on the recording rate of the video data acquired from the specific video channel CHk and the access size of the specific video channel CHk, and sets this as the cycle to which the time slot is allocated.

[0052] For example, if the data transfer rate between the information processing device 1 and the storage 3 is a Mbps and the access size of a particular video channel CHk is determined to be b MB (8*b Mbit), the duration of the time slot to be allocated to that video channel CHk can be determined to be 8*b / a seconds. Also, if the recording rate of video data acquired from a particular video channel CHk is c Mbps, it can be determined that c / (8*b) time slots are allocated to that video channel CHk per second.

[0053] After completing the time slot setting, the configuration unit 5 transmits the time slot setting information to the arbitration unit 6 (step S103 in FIG. 5). The arbitration unit 6, which has received the time slot setting information, determines, based on the time slot setting, when to permit each of the video channels CH1, CH2, ... CHn of the information processing device 1a and the information processing device 1b to access the storage 3 (record video data in the storage 3).

[0054] Furthermore, the configuration unit 5 transmits the time slot setting information to the information processing device 1a and the information processing device 1b (step S104 in FIG. 5). The CPUs 11 of the information processing device 1a and the information processing device 1b each execute a process of receiving the time slot setting information transmitted from the configuration unit 5 (step S1 in FIG. 6).

[0055] Thereafter, the CPU 11 configures the information processing device 1 based on the received time slot configuration. Specifically, the CPU 11 determines the sizes of buffer areas BF1, BF2, ..., BFn to be allocated to each of the video channels CH1, CH2, ..., CHn based on the time slot configuration, and allocates the buffer areas BF1, BF2, ..., BFn in the RAM 12 (step S2 in FIG. 6). The size of each buffer area BF to be allocated can be determined as the access size determined for the video channel CH to which the buffer area BF is allocated, plus a predetermined margin.

[0056] After the buffer area BF is secured, when a user issues a command to output video data from the plurality of video processing devices 2a and the plurality of video processing devices 2b, the plurality of video data are output from the plurality of video processing devices 2a and the plurality of video processing devices 2b (step S105 in FIG. 5). The plurality of video data output from the plurality of video processing devices 2a and the plurality of video processing devices 2b are recorded in the storage 3. The operation of recording the plurality of video data in the storage 3 will be described in detail below.

[0057] The following describes the operation when recording multiple pieces of video data from the information processing device 1a and the information processing device 1b within a predetermined time into the storage 3. The video recording system 100 repeatedly executes the operation described below as long as there is video data output to be recorded into the storage 3.

[0058] The CPU 11 acquires a plurality of pieces of video data output from a plurality of video processing devices 2 via a plurality of video channels CH (step S3 in FIG. 6 ). The CPU 11 buffers the video data acquired via each video channel CH in a buffer area BF allocated to the video channel CH (step S4 in FIG. 6 ).

[0059] While buffering each of the multiple video data in the corresponding buffer area BF, the CPU 11 determines whether a sufficient amount of video data has been buffered in each buffer area BF (step S5 in FIG. 6). For example, when recording video data acquired via video channel CHk, the CPU 11 determines whether a sufficient amount of video data has been buffered in the buffer area BFk assigned to that video channel CHk. Note that k starts from 1 and increases by 1 up to n by repeating the following steps S5 to S10.

[0060] "The amount of video data buffered in the buffer area BF is sufficient" means that the buffered video data (buffered data) has an access size determined for the video channel CH assigned to the buffer area BF.

[0061] If a sufficient amount of video data is not buffered in the buffer area BFk allocated to the video channel CHk ("No" in step S5 of Figure 6), the video data recording operation returns to step S4 above, and buffering of the video data in the buffer area BFk continues.

[0062] On the other hand, if a sufficient amount of video data has been buffered in the buffer area BFk allocated to the video channel CHk ("Yes" in step S5 of Figure 6), the CPU 11 requests the arbitration unit 6 to access the storage 3 for the video channel CHk in order to record the buffered data buffered in the buffer area BFk in the storage 3 (step S106 of Figure 5, step S6 of Figure 6).

[0063] When an access request is received from the information processing device 1a (step S106a in FIG. 5 ), the arbitration unit 6 determines, based on the time slot setting information, whether to allocate a time slot for accessing the storage 3 to the video channel CHk of the information processing device 1a. Based on the time slot setting information, the arbitration unit 6 determines whether the current time (the timing at which the access request is received) is a time at which a time slot can be allocated to the video channel CHk of the information processing device 1a. Specifically, based on the time slot setting information, the arbitration unit 6 determines whether the current time (the timing at which the access request is received) is the start time of the time slot allocated to the video channel CHk of the information processing device 1a. If the arbitration unit 6 determines that a time at which a time slot can be allocated to the video channel CHk of the information processing device 1a is a start time, the arbitration unit 6 transmits an access permission to the information processing device 1a in response to the access request of step S6 (step S107a in FIG. 5 ).

[0064] If no access permission is received from the arbitration unit 6 ("No" in step S7 in FIG. 6), the CPU 11 of the information processing device 1a waits until access permission is received.

[0065] On the other hand, if an access permission is received from the arbitration unit 6 ("Yes" in step S7 of FIG. 6), the CPU 11 of the information processing device 1a determines that a time slot for accessing the storage 3 and recording video data has been allocated to the video channel CHk. In this case, the CPU 11 of the information processing device 1a transmits the buffered data buffered in the buffer area BFk to the storage 3 in the time slot allocated to the video channel CHk (step S108a in FIG. 5, step S8 in FIG. 6).

[0066] Similarly, when an access request is received from information processing device 1b (step S106b in FIG. 5), arbitration unit 6 determines, based on the time slot setting information, whether to allocate a time slot for accessing storage 3 to video channel CHk of information processing device 1b. Based on the time slot setting information, arbitration unit 6 determines whether the current time (the timing at which the access request is received) is a time at which a time slot can be allocated to video channel CHk of information processing device 1b. If arbitration unit 6 determines that a time at which a time slot can be allocated to video channel CHk of information processing device 1b is a time at which a time slot can be allocated to video channel CHk of information processing device 1b, arbitration unit 6 transmits an access permission to information processing device 1b in response to the access request of step S6 (step S107b in FIG. 5).

[0067] If no access permission is received from the arbitration unit 6 ("No" in step S7 in FIG. 6), the CPU 11 of the information processing device 1b waits until access permission is received.

[0068] On the other hand, if an access permission is received from the arbitration unit 6 ("Yes" in step S7 of FIG. 6), the CPU 11 of the information processing device 1b determines that a time slot for accessing the storage 3 and recording video data has been allocated to the video channel CHk. In this case, the CPU 11 of the information processing device 1b transmits the buffered data buffered in the buffer area BFk to the storage 3 in the time slot allocated to the video channel CHk (step S108b of FIG. 5, step S8 of FIG. 6).

[0069] The controller 35 of the storage 3 receives the buffered data and records it in consecutive pages PA of the flash memory 33. At this time, the controller 35 determines the erase blocks BL in which to record the buffered data based on the number of times data has been recorded in each erase block of the flash memory 33. For example, the controller 35 determines multiple erase blocks BL with similar numbers of times data has been recorded as the erase blocks BL in which to record the buffered data. As described above, the buffered data has a size that is an integer multiple of the size of the erase blocks BL. Therefore, the buffered data is recorded across a predetermined number of consecutive erase blocks BL of the flash memory 33. In other words, the number of erase blocks BL in which data is only partially recorded can be reduced. As a result, the occurrence of garbage collection processing in the storage 3 can be suppressed. Furthermore, by recording relatively large buffered data (video data) in consecutive pages PA (consecutive erase blocks BL), fragmentation of the video data can be suppressed.

[0070] After recording the video data (buffering data) of one video channel CHk in storage 3 in the time slot assigned to that video channel CHk, CPU 11 determines whether there is a video channel CH for which video data has not been recorded, i.e., whether the video data of all video channels CH has been recorded (whether k has increased from 1 to n) (step S9 in Figure 6).

[0071] If there is a video channel CH that does not have video data recorded on it, i.e., if k is a value smaller than n ("No" in step S9 of FIG. 6), k is incremented by 1 (step S10 of FIG. 6), and steps S106 to S108 of FIG. 5 and steps S5 to S10 of FIG. 6 are executed for the next video channel CHk+1.

[0072] On the other hand, if there is no video channel CH on which video data has not been recorded, that is, if k becomes n (k=n) ("Yes" in step S9 of FIG. 6), it is determined that the video data acquired via all video channels CH of the information processing device 1 has been recorded in the storage 3. Thereafter, as long as video data is being output from the plurality of video processing devices 2 of the information processing device 1a and the information processing device 1b, steps S105 to S108 of FIG. 5 and steps S3 to S10 of FIG. 6 are repeatedly executed.

[0073] As a result, in the video recording system 100, as shown in Fig. 7, video data (buffered data) of the video channel CH of the information processing device 1a is recorded in the storage 3 in sequence in the time slots assigned to each video channel CH. As a result, within the time of a first slot consisting of a plurality of time slots, video data of all video channel CHs of the information processing device 1a to which the first slot is assigned is recorded in the storage 3. Furthermore, within a predetermined time consisting of a plurality of first slots, video data of all video channel CHs of all information processing devices 1 is recorded in the storage 3. In the video recording system 100, this operation is repeated at a predetermined cycle as long as video data is output from the video processing device 2. This cycle is determined based on, for example, the total time length of the plurality of time slots and the time at which each information processing device 1 is permitted to access the storage 3.

[0074] [2. Other Embodiments] While one embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment, and various modifications are possible without departing from the spirit and scope of the present disclosure. In particular, multiple embodiments and modifications described in this specification can be combined as needed.

[0075] (A) The order and content of each process in the sequence diagrams and flowcharts illustrating signal transmission and reception described above may be changed as appropriate without departing from the scope of the present disclosure. Furthermore, the entities that execute each process (information processing device 1, video processing device 2, configuration unit 5, arbitration unit 6, storage 3) may also be changed as appropriate without departing from the scope of the present disclosure.

[0076] (B) At least one of the configuration and function of at least one of the component unit 5 and arbitration unit 6 described above may be included in any one of the information processing devices 1 .

[0077] (C) The configuration unit 5 calculates the processing time for processing video data acquired from a specific video channel CHk based on the data transfer rate between the information processing device 1 and the storage 3 and the access size of the specific video channel CHk, and determines the time length of the time slot. However, the configuration unit 5 may calculate the length obtained by adding a predetermined time to the above-mentioned processing time, and determine the time length of the time slot. In other words, the time length of the time slot may include a margin.

[0078] (D) The arbitration unit 6 determines whether a time slot can be allocated by determining, based on the time slot setting information, whether the current time (the timing at which the access request is received) is the start time of the time slot allocated to the video channel CHk of the information processing device 1a. However, the arbitration unit 6 may also determine whether a time slot can be allocated by determining whether the current time (the timing at which the access request is received) is within the time of the first slot allocated to the information processing device 1a and whether buffered data corresponding to the previous video channel CHk-1 has already been transmitted to the storage 3. This allows free time slots to be aggregated in the latter half of the first slot, which is made up of multiple time slots. As a result, free time can be used efficiently.

[0079] (E) The video recording system 100 may have multiple flash memories 33. In this case, the controller 35 may determine the flash memory 33 in which to record the buffered data based on the lifespan of the flash memories 33. For example, the controller 35 may determine that the flash memories 33 that are close to reaching the end of their lifespan are the flash memories 33 in which to record the buffered data. This allows the flash memories 33 to be used efficiently.

[0080] (F) An external device may be connected to the information processing device 1 via the interface 16. When an external device of the information processing device 1 requests access to the storage 3, the configuration unit 5 may determine whether there is available time in the time slot. In the example shown in FIG. 6 , if there is no video channel CH on which video data is not recorded ("Yes" in step S9 of FIG. 6 ), the configuration unit 5 may compare the current time with the end time of the second slot assigned to the information processing device 1 to which the external device is connected to determine whether there is available time in the time slot. If the configuration unit 5 determines that there is available time, it may allocate the available time to access from the external device.

[0081] (G) The configuration unit 5 may determine the access size for each video channel CH based on the size of the erase block BL of the storage 3, the recording rate of the video data, and the video characteristics of the video data. For example, if the video data to be recorded is in a compressed format, the access size may be calculated based on the size of the video data after compression.

[0082] (H) The configuration unit 5 may calculate the processing cycle required for the video data based on the recording rate, video characteristics, and access size of the video data, and determine the cycle for allocating time slots. For example, if the video data to be recorded is in a compressed format, the cycle for allocating time slots may be calculated based on the size of the compressed video data.

[0083] (I) In the above embodiment, for convenience of explanation, an example in which one storage 3 is provided is shown. However, this is not limited to this, and two or more storages 3 may be provided. In this case, the configuration unit 5 determines a storage 3 for recording video data acquired from each of multiple video channel CHs of multiple information processing devices 1. For each storage 3, the configuration unit 5 sets a time slot for each of the multiple video channel CHs assigned to that storage 3. The configuration unit 5 sets the time length of the time slot and the cycle for allocating the time slots to each video channel CH based on the access size determined for each storage 3, the recording mode specified by the user, and the like. At this time, the configuration unit 5 allocates time slots so that the time slots for multiple video channel CHs of one information processing device 1 are grouped together in a time period. FIG. 7 is a diagram schematically illustrating the recording of video data to one storage 3 of two or more storages 3. The same applies to the recording of video data to the other storages 3.

[0084] [3. Features of the Present Disclosure] (1) A video recording system 100 of the present disclosure includes a storage 3, a plurality of information processing devices 1, and a configuration unit 5. The storage 3 has a flash memory 33 that writes in units of pages and erases in units of erase blocks consisting of a plurality of pages. Each of the plurality of information processing devices 1 records a plurality of pieces of video data acquired via a plurality of video channels CH in the flash memory 33. The configuration unit 5 sets time slots. Each of the plurality of information processing devices 1 has a RAM 12 and a CPU 11. The RAM 12 has a plurality of buffer areas BF1, BF2, ..., BFn that are assigned to the plurality of video channels CH1, CH2, ..., CHn, respectively. The CPU 11 controls the recording of the plurality of pieces of video data in the flash memory 33.

[0085] In the above-described video recording system 100, the configuration unit 5 determines an access size. The access size is an integer multiple of the size of the erase block BL. Based on the access size, the configuration unit 5 collectively assigns time slots for each of the multiple video channels CH possessed by each of the multiple information processing devices 1 to each of the multiple information processing devices 1. The CPUs 11 of the multiple information processing devices 1 each buffer multiple pieces of video data acquired via the multiple video channels CH in buffer areas BF1, BF2, ..., BFn assigned to the video channels CH1, CH2, ..., CHn, respectively, for the access size. Furthermore, the CPUs 11 of the multiple information processing devices 1 each record the buffered data buffered in the buffer areas BF1, BF2, ..., BFn in the flash memory 33 in the time slots assigned to the video channels CH1, CH2, ..., CHn, respectively, corresponding to the buffer areas BF1, BF2, ..., BFn.

[0086] In the above-described video recording system 100, video data from multiple information processing devices 1 is not simultaneously recorded in the storage 3. In the video recording system 100, time slots for each video channel CH are collectively assigned to each information processing device 1. This makes it possible to prevent a decrease in the video data recording rate due to locking between multiple information processing devices 1.

[0087] Furthermore, in the above-described video recording system 100, video data from the corresponding video channel CH is buffered in each of the multiple buffer areas BF of each information processing device 1 by an amount equal to an integer multiple of the erase block BL, which is the erase unit of the storage 3. In the video recording system 100, the buffered data buffered in each buffer area BF is recorded in the storage 3 in a time slot assigned to the video channel CH corresponding to that buffer area BF. In other words, multiple pieces of video data (buffered data) are recorded in the storage 3 in individually assigned time slots. This allows the data transmission bandwidth of the data line connecting the information processing device 1 and the storage 3 to be monopolized by the transmission of one piece of video data (buffered data), thereby preventing a decrease in the recording rate of the video data.

[0088] Furthermore, in the video recording system 100, the size of the buffering data recorded in one time slot is set to an integer multiple of the erase block size, which is the unit of data erasure in the storage 3. This makes it possible to prevent the occurrence of erase blocks BL in which video data is only partially recorded. As a result, the occurrence of garbage collection processes is suppressed, and a decrease in the operating speed of the storage 3 is suppressed. Furthermore, by recording buffering data that is an integer multiple of the erase block BL and is large in size in the storage 3 in one time slot, it is possible to prevent fragmentation of the video data recorded in the storage 3.

[0089] (2) In the video recording system 100 described above in (1), the configuration unit 5 may further allocate time slots to video channels CH corresponding to video data based on the recording rate of the video data. This allows for efficient use of the data transmission bandwidth of the data line connecting the information processing device 1 and the storage 3.

[0090] (3) In the video recording system 100 described in (2) above, the configuration unit 5 may further allocate time slots to video channels CH corresponding to video data based on the video characteristics of the video data. This allows for efficient use of the data transmission bandwidth of the data line connecting the information processing device 1 and the storage 3.

[0091] (4) In the video recording system 100 of any one of (1) to (3) above, the configuration unit 5 may set the time length of a time slot to a predetermined time added to the processing time based on the data transfer rate and the access size between the information processing device 1 and the storage 3. By adding a margin to the time of the time slot, it is possible to absorb fluctuations in the transmission of video data due to garbage collection processing, changes in the transmission environment, etc.

[0092] (5) The video recording system 100 according to any one of (1) to (4) above may further include an arbitration unit 6 that arbitrates access from the CPU 11 to the flash memory 33. The arbitration unit 6 may determine whether to permit access from the CPU 11 to the flash memory 33 based on the time slot setting set by the configuration unit 5. This allows arbitration of the transmission of video data (buffered data).

[0093] (6) In the video recording system 100 described above in (5), the information processing devices 1, the configuration unit 5, and the arbitration unit 6 may be time-synchronized. This improves the accuracy of switching between the time slots and the first slots.

[0094] (7) In the video recording system 100 of any one of (1) to (6) above, when an external device requests access to the storage 3, the configuration unit 5 may determine whether there is available time in a time slot. If the configuration unit 5 determines that there is available time, it may allocate the available time to access from the external device. This makes it possible to respond to access requests from external devices.

[0095] (8) In the video recording system 100 of any one of (1) to (7) above, the storage 3 may have a plurality of flash memories 33 and a controller 35 that executes control related to the storage 3. The controller 35 may determine the flash memory 33 in which to record the buffering data based on the number of times data is recorded for each erase block BL of the flash memory 33. By selecting a flash memory 33 that is close to reaching the end of its life and recording the buffering data therein, the storage 3 can be used efficiently.

[0096] The present disclosure can be widely applied to a recording method for recording video data in a predetermined recording area and a video recording system.

[0097] 100: Video recording system 11: CPU, control unit 12: RAM, temporary storage unit 13: Storage device 14: Video interface 15: Storage interface 16: Interface 1: Information processing device 2: Video processing device 21: Output interface 3: Storage 31: Access port 33: Flash memory, non-volatile memory unit 35: Controller 37: Storage unit 5: Configuration unit 6: Arbitration unit BF1 to BFn: Buffer area CH1 to CHn: Video channel RA: Recording area BL: Erase block PA: Page

Claims

1. A video recording system comprising: a storage having a non-volatile memory unit that writes in page units and erases in erase block units consisting of multiple pages; a plurality of information processing devices that record a plurality of video data acquired via a plurality of video channels in the non-volatile memory unit; and a configuration unit that sets time slots, wherein the plurality of information processing devices each have a temporary storage unit with a plurality of buffer areas allocated to each of the plurality of video channels, and a control unit that controls the recording of the plurality of video data in the non-volatile memory unit, the configuration unit determines an access size that is an integer multiple of the erase block size, and allocates time slots for each of the plurality of video channels owned by each of the plurality of information processing devices collectively for each information processing device based on the access size, and the control units of the plurality of information processing devices each buffer the plurality of video data acquired via the plurality of video channels by the access size in buffer areas allocated to each video channel, and record the buffered data buffered in each buffer area in the non-volatile memory unit in the time slots allocated to the video channel corresponding to each buffer area.

2. The video recording system according to claim 1, wherein the configuration unit further allocates the time slots to the video channels corresponding to the video data based on the recording rate of the video data.

3. The video recording system according to claim 2, wherein the configuration unit further allocates the time slot to the video channel corresponding to the video data based on video characteristics of the video data.

4. A video recording system as described in claim 1 or 2, wherein the component unit sets the time length of the time slot to a time obtained by adding a predetermined time to the processing time based on the data transfer rate between the information processing device and the storage and the access size.

5. The video recording system of claim 1 or 2, further comprising an arbitration unit that arbitrates access from the control unit to the non-volatile memory unit, and the arbitration unit determines whether or not to allow access from the control unit to the non-volatile memory unit based on the setting of the time slot set by the configuration unit.

6. The video recording system according to claim 5, wherein the plurality of information processing devices, the configuration unit, and the arbitration unit perform time synchronization.

7. A video recording system as described in claim 1 or 2, wherein the component determines whether there is available time in the time slot when an external device requests access to the storage, and if it determines that there is available time, allocates the available time to the access from the external device.

8. A video recording system as described in claim 1 or 2, wherein the storage has a plurality of non-volatile memory units and a controller that executes control related to the storage, and the controller determines the non-volatile memory unit in which to record the buffered data based on information regarding the lifespan of the non-volatile memory units.

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