Multi-channel memory module with variable-speed dram devices and data-buffer gearbox

Abstract

A memory component supports relatively wide, low-bitrate bursts in a first operational mode. A data buffer combines the wide, low-bitrate bursts from multiple memory components into relatively higher-bitrate bursts for host communication. The memory component also supports relatively narrow, higher-bitrate bursts in a second operational mode. The data buffer combines the narrower, relatively high bitrate bursts from the multiple memory components into one burst for host communication. The bursts for host communication can be the same in both modes.

Description

MULTI-CHANNEL MEMORY MODULE WITH VARIABLE-SPEED DRAM DEVICES AND DATA-BUFFER GEARBOXDongyun LeeTECHNICAL FIELD

[0001] The subject matter presented herein relates generally to memory systems, modules, and components.BACKGROUND

[0002] A “server” is a computer that processes requests and delivers data to client computers over a network. For example, web servers allow Internet browsers on client computers to access web pages and other data via the Internet. Servers include processing units that write and read data to and from memory coupled to the processing units via memory channels. A single memory channel includes a data pathway for transmitting and receiving data and a command pathway for transmitting and receiving commands and addresses. For example, a processing unit might write data to an address in memory by transmitting a write command with a target address over the command pathway and the write data over the data pathway. The data can later be read from memory by transmitting a read command with the target address over the command pathway and awaiting receipt of the data over the data pathway.

[0003] Modern servers could significantly benefit from more power-efficient memory modules due to the increasing demand for data processing and storage in today's digital landscape. As data centers grow to accommodate the explosion of data from cloud computing, artificial intelligence, and big-data analytics, the energy consumption of these facilities has become a major concern. Memory modules, being a crucial component of servers, consume a substantial portion of the total energy in data centers. By adopting more power-efficient memory, data centers can reduce their overall energy consumption, leading to lower operational costs and a smaller carbon footprint.

[0004] Power-efficient memory modules can also enhance the performance and reliability of servers. Power consumption generates heat, which can lead to thermal management challenges and potential overheating. This not only increases the cooling requirements but also risks reducing the lifespan and performance of the memory and other server components. Moreefficient memory modules can operate at lower temperatures, improving overall system stability and reducing the likelihood of hardware failures.BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0006] Figure 1 depicts a memory system 100 in which a memory module 105 stores and provides data responsive to instructions from a host 110 (e.g. a memory controller).

[0007] Figure 2 is a waveform diagram 200 illustrating data flow for a read transaction with module 105 of Figure 1 in a first mode in which devices 115 each communicate four-bit-wide data to and from data-buffer component 120.

[0008] Figure 3 is a waveform diagram 300 illustrating data flow for a read transaction with module 105 of Figure 1 in a second mode in which devices 115 each communicate two-bit-wide data to and from data-buffer component 120.

[0009] Figure 4 depicts a memory system 400 in which a load-reduce, dual-in-line memory module (LRD1MM) 405 incorporates components of module 105 of Figure 1 to communicate with a host controller 410.

[0010] Figure 5 depicts a memory system 500 in accordance with another embodiment.

[0011] Figure 6 depicts a memory system 600 with a memory module 605 incorporating DRAMs 505 of Figure 5 on a PCB 610 routed to receive them.DETAILED DESCRIPTION

[0012] Figure 1 depicts a memory system 100 in which a memory module 105 stores and provides data responsive to instructions from a host 110 (e.g. a memory controller). Module 105 stores data in two integrated-circuit (IC) memory components 115, dynamic, random-access memory (DRAM) devices in this example. A data-buffer component 120 manages communication between host 110 and memory components 115. Each memory component 115 includes a data (DQ) port with four input / output pads 125 to communicate data to and from data- buffer component 120. All four pads 125 communicate data in a wide, relatively low-power mode; only two of pads 125 communicate data in a narrower mode. Data-buffer component 120manages communication between host 1 10 and both memory components 1 15 simultaneously in each mode.

[0013] Memory components 115 are identical. The left and right devices 115 are respectively labeled DR AMO and DRAM1 so they can be referred to separately. Each DRAM 115 includes a memory core 130 for storing data DQ. Core 130 has a data interface (not shown) that communicates 64-bit data from a memory-core port 132 on parallel traces to a multi-level 1:32 serdes (pronounced 'SIR-deez') 135. A serdes is both a serializer and a deserializer, a bidirectional circuit that can both combine (serialize) and split (deserialize) digital signals to increase and reduce symbol (e.g. bit) rates. A 1:16 serdes 140 converts 64-bit data communicated with core 130 to four-bit data with a 1:2 serdes 145, and vice versa. Two of the four nodes between serdes 140 and 145 extend to two more 1:2 multiplexer 150, while the remaining two extend to respective ones of pads 125.

[0014] A mode register 155 stores a first mode value on node M that causes multiplexer 150 to bypass serdes 145 so that serdes 140, and thus memory component 115, communicates fourwide (x4) data in sixteen-bit bursts (64 bits per transaction) on pads 125. In this first mode, memory component 115 responds to each access request — read or write — by communicating a data burst of width Wl=4, length Ll=16, and a burst duration of eight cycles of clock signal CK. The access granularity, the product of width W1 and length LI, is 64 bits. A second mode value on line M causes multiplexer 150 to communicate between serdes 145 and the leftmost pair of pads 125 so that memory component 115 communicates two- wide (x2) data in 32-bit bursts. The access granularity, now the product of W2 and L2, and the burst duration are the same in the second mode as in the first. Clock circuitry 160 sends and receives a strobe signal DQS0, via a pad 165, timed to and in the direction of data signals DQ0[3:0] in either mode.

[0015] Data-buffer component 120 communicates simultaneously with both memory components 115 over respective module data channels DQ0[3:0] / DQS0[l:0] and DQl[3:0] / DQSl[l:0] in service of memory transactions with host 110 over host data and strobe paths DQ_H[3:0] / DQS_H[l:0] that can be components of a wider, host- level data channel. In this context, a "channel" refers to a set of electrical paths and related circuitry that allow chunks of data to be transferred to and from memory responsive to requests. A single memory component can have one or more channels, and memory-device channels can be combined to form larger host-level channels.

[0016] The signal paths between data-buffer component 120 and memory components 115 tend to be relatively short and direct in comparison to those between module 105 and host 110. Short, direct, and connector-free paths tend to exhibit less resistance, capacitance, and inductance, meaning improved signaling and less power wasted as heat.

[0017] Host 110 issues read and write commands DCA to module 105. A registered clock driver (Figure 4) interprets commands from host 110 and manages transactions by issuing command-and-address (CA) signals CA[13:0], chip-select signals CS, and clock signal CK to memory components 115 and control signals BCOM to data-buffer component 120. Signals BCOM can indicate the mode for each memory transaction or can be used to load a local mode register 167. Data buffers in some embodiments omit support for the second data mode, only operating in the wider, more efficient mode.

[0018] When reading from memory components 115, clock circuitry 170 senses the phases of strobe signals DQS0[l:0] and DQSl[l:0]. A delay-locked loop (DLL) can be used to detect and control phase misalignment. Data-alignment circuitry 175 uses phase information from clock circuitry 170 to align data from devices 115 in the read direction. A gearbox circuit 180 communicates data from both memory components 115 to host 110 via host channel DQ_H, adjusting the memory-side bitrate between operational modes, to maintain the same access granularity in either mode. A registered clock driver (RCD) illustrated in Figure 4 derives memory-device control and clocking signals CA0 / CS0 / CK0 and CA1 / CS1 / CK1 and data-buffer control signal BCOM from host commands DCA.

[0019] Memory components 115 can be used without data-buffer component 120 on an "unbuffered" DIMM, or UDIMM. A strobe (DQS) is shared between a pair of memory components 115 operating in the x2 mode. Host 110 thus communicates four DQ signals for each DQS signal without any intermediary buffer or register. UDIMMs tend to be simpler and less expensive than buffered DIMMS and can offer performance benefits in some scenarios. However, UDIMMs are less suited for environments requiring very high memory capacity or where signal integrity over long distances is crucial, such as in large server racks.

[0020] Figure 2 is a waveform diagram 200 illustrating data flow for a read transaction with module 105 of Figure 1 in a first mode in which devices 115 each communicate four-bit- wide data to and from data-buffer component 120. There arc three sets of four waveforms. The uppermost four are sixteen-bit bursts from the leftmost memory component 115, DRAM0; themiddle four are similar bursts from the rightmost memory component 1 15, DRAM1 ; and the bottom four arc the combined and interleaved bursts from both memory components 115 as conveyed from data-buffer component 120 to host 110. The bits on each bitstream from memory components 115 are shaded to illustrate how data-buffer component 120 interleaves bitstreams on adjacent DQ lines and transmits the result in 32-bit bursts (e.g. DQ0[3] and DQ0[2] are interleaved for transmit on host node DQ_H[3]).

[0021] Timing signals (strobes) DQS0 and DQS1 are misaligned due to e.g. different path lengths between data-buffer component 120 and each memory component 115. Clock circuits 170 provide measures of this misalignment to data- alignment circuit 175, which responsively provides eight internal time-aligned data bursts DQ_I[7:0] (Figure 1) and a corresponding internal strobe DQS_I[l:0] (Figure 1) to gearbox 180. In this context, a "gearbox" is a frequency multiplier and divider that "shifts gears" in terms of bitrates. The data communicated to host 110 in one read transaction is thus four 32-bit bursts, or 128 bits. Write transactions reverse the flow of the same data format to write 64 bits into each memory component 115.

[0022] Thermal design power (TDP) refers to the maximum amount of heat that a device, in this case a DRAM device, is expected to dissipate when running at a full load. TDP can be reduced by reducing the bitrate and lowering DRAM voltages, but at the cost of reduced system performance. When DRAM devices 115 communicate with host 110 in the x2 mode, the higher data frequency dissipates more power in driving pads 125 and increases the temperature of the DRAM device 115. This causes DRAM devices 115 to refresh more frequently to maintain data in core 130. Data-buffer component 120 provides a “gearbox” function in the x4 mode to lower the data frequency and thus reduce the power in driving pads 125.

[0023] Figure 3 is a waveform diagram 300 illustrating data flow for a read transaction with module 105 of Figure 1 in a second mode in which devices 115 each communicate two-bit-wide data to and from data-buffer component 120. There are two sets of two waveforms and one set of four. The uppermost two waveforms are thirty-two-bit bursts from the leftmost memory component 115, DRAM0; the middle two are similar bursts from the rightmost memory component 115, DRAM1; and the bottom four are the combined bursts from both memory components 115 as conveyed from data-buffer component 120 to host 110. The bits on each bitstream from memory components 115 are shaded to illustrate how data-buffer component 120 retimes and directs each of the four 32-bit bursts from memory components 115 to a respectivehost data line (e.g., the data burst on device line DQ0[3] is conveyed to host 110 via external connection DQ_H[3]). The DQ nodes used in the x2 mode can be physically separated rather than neighboring nodes for reduced cross talk.

[0024] Clock circuits 170 and data- alignment circuit 175 function in the manner of the first mode to align the data bursts from memory components 115 responsive to timing signals DQSO and DQS1 to provide four internal, time-aligned data bursts DQ_I[7:0] of sixteen bits and a corresponding internal strobe DQS_I[l:0] to gearbox 180. In this second mode, gearbox 180 does not retime the signals from memory but rather directs them to corresponding host data ports DQ_H[3:0] as indicated in Figure 3. The data communicated to host 110 in one read transaction is thus four 32-bit bursts, or 128 bits, the same as in the first mode. Write transactions reverse the flow of the same data format to write 64 bits into each memory component 115.

[0025] Figure 4 depicts a memory system 400 in which a load-reduce, dual-in-line memory module (LRDIMM) 405 incorporates components of module 105 of Figure 1 to communicate with a host controller 410. Like-identified elements between figures are the same or similar. Module 405 illustrates a practical implementation in which a single module supports four independent channels, each of which can be separately controlled to support transactions that communicate 640 bits, 64 eight-bit bytes for data and 16 eight-bit bytes for error detection and correction, over twenty out of a total of eighty DQ paths to controller 410. LRDIMM 405 supports Single Device Data Correction (SDDC), also known as Chipkill or package kill, for advanced error correction.

[0026] Memory module 405 is a printed-circuit board (PCB) 415 with two horizontal rows of memory components 115 on either side. “Dual inline” refers to electrical connections 425 that run along both size of the bottom edge of PCB 415 to form a module connector 430 with two host-side module command ports DCA_A[6:0] and DCA_B[6:0] and four sets of module data ports DQ _A0[39:20], DQ _A1 [19:0], DQ B0[39:20], and DQ _B 1 [19:0] supporting like- identified links to controller 410, the host in this example. Memory module 405 can include other components, such as a power-management IC, a serial-presence detect IC, resistors, and capacitors.

[0027] Ten data buffers 120, five of which are shown, communicate data signals between controller 410 and memory components 115. The resulting reduction on the number of data interfaces reduces the load on controller 410 and is responsible for the “load-reduced” namingconvention for module 405. A registered clock driver (RCD) 440, sometimes called an addressbuffer integrated circuit, similarly manages command, address, and clock signals from module command ports DCA_A[6:0] and DCA_B[6:0] to reduce signal loading and distribute command and address signals as needed to collections of memory components 115 via four secondary command / address (CA) ports CA0_A[13:0], CAl_A[13:0], CA0_B[13:0], and CAl_B[13:0] serving like-identified links to memory components 115.

[0028] Module 405 supports four memory channels, left and right frontside and backside channels. Left and right are designated "A" and "B", front and back "0" and "1". Signals directed to the different channels are designated using a suffix that combines left / right and front / back designations. Only components of the front / left channel are shown and discussed because the other three are operationally identical.

[0029] RCD 440 controls DRAMs 115 and data-buffer components 120 of the front / left channel via command-and-address signal CA_0A[13:0] and chip-select signal CS0A. Timing is provided via a clock signal CK0A. Data-buffer components 120 each service four memory components 115, a frontside pair and a backside pair. Half of each component 120 is shaded to indicate that it is in service of backside memory components 115 that are omitted from view.

[0030] Each memory component 115 can have multiple independently accessible memory dies, or chips, a stack of dynamic, random-access memory (DRAM) chips in this embodiment. Memory components 115 respond to commands that communicate values to a set of inputs within the DRAM chips. Common and well-understood DRAM commands include activate, precharge, read, write, and refresh. In the example of Figure 4, RCD 440 intermediates between controller 410 and memory components 115. To distinguish between commands to and from RCD 440, which can be formatted the same or differently, host-side memory commands from controller 410 to RCD 440 are termed “primary memory commands” or “host commands” and memory commands from RCD 440 to memory components 115 are termed “secondary memory commands” or just “memory commands.”

[0031] Controller 410 issues host commands via CA channel DCA_A[6:0] to access a rank of ten DRAM chips, one in each of ten memory components 115 associated with one of the four channels. Host commands to the frontside and backside channels are interleaved on each of the two host-side CA channels in this embodiment, but each channel could be provided with a separate host-side CA connection. RCD 440 responds to host commands by sending theappropriate command and address signals to ten memory components 1 15 via one of four secondary command interfaces CA_0A, CA_1A, CA_0B, and CA_1B, asserting a corresponding chip-select signal (e.g. CSOA) to one DRAM chip in each device 115 to select ten DRAM chips for read or write access to specified address locations. RCD 440 also controls data buffers 120, via one of control signals BCOM_A and BCOM_B, to communicate twenty data signals DQ_0A[19:0], four per data-buffer component 120 in the manner detailed above in connection with Figures 1-3.

[0032] Data signals are conveyed in sixteen-bit bursts in this example, with each memory transaction communicating 640 bits (40x16b), or 80 eight-bit bytes. The data to be written to or read from memory is 64 bytes, leaving the remaining sixteen bytes for error detection and correction (EDC). This quantum of data is commonly referred to as a "cacheline." Controller 410 can issue host commands that RCD 440 directs to any and all four of the back and right-side CA channels. All four channels are independent, meaning that they can communicate data at the same or different times in the same or different directions, and each can be independently programmed such that the respective memory components operate in either one or the other of the two modes. Thus, bandwidth throttling due to power or thermal concerns can be done with channel granularity. Switching between modes does not change memory contents. For illustrative purposes, in one embodiment the DRAM cores operate at 250MHz for a maximum data bandwidth of 32GB / s on each of four host channels and a total of 128GB / x for the module.

[0033] The x2 mode is the default mode in some implementations and can provide overall power optimization. During initial calibration, the x2 mode may show a higher bit-error rate between memory components 115 and data-buffer components 120. In that case, switching to the x4 mode to reduce the interface speed between memory components 115 and data-buffer components 120 can lower the error rate, which can be confirmed by error testing while keeping the host-side bandwidth of data buffers 120 the same as in the x2 mode.

[0034] Controller 410 can load register 450 with a mode value that places module 405 in one of the two modes noted previously. The stored mode value can be used to alter control signals to one or both memory components 115 and data-buffer components 120, or to load mode values in registers at those remote chips.

[0035] Figure 5 depicts a memory system 500 in accordance with another embodiment. Data-buffer components 120 are as detailed previously. Each of two DRAMs 505 supports twochannels, left- and right-side hy-four (x4) data interfaces DQ0A0[3:0] and DQ0A1 [3:0], that share a strobe signal DQS but have separate chip-select signals CS. The uppermost DRAM 505, for example, receives CA signals CA_0A and a clock signal CK that are common to both cores 130, and receives CS signals CS_0A0 and CS_OA1 to separately select the respective right and left cores 130. The lowermost DRAM 505 shares clock signal CK but the CA and CS signals are designated with the suffix " 1A0" rather than "0A0". Each x4 data interface can communicate sixteen-bit bursts at half the host bitrate in the mode described in connection with Figure 2. Data- buffer component 120 combines the lower-speed DRAM channels onto a single x4 host channel DQ_H[3:0] / DQS_H[l:0],

[0036] Figure 6 depicts a memory system 600 with a memory module 605 incorporating DRAMs 505 of Figure 5 on a PCB 610 routed to receive them. Data-buffer components 620 are like components 120 except that all four of their x4 DQ interfaces are connected to memory components on the front of PCB 610. Additional data and timing interfaces can be provided to support DRAMs on the back. For example, the twenty front-side DRAMs 505 can support one rank and another twenty back-side DRAMs a second rank. Multi-rank modules can increase bandwidth because the host can access one rank while the other is being precharged or refreshed, effectively doubling the data rate under certain conditions.

[0037] Memory-device channels are not limited to the x2 and x4 modes detailed here. Another serdes level can support an additional xl mode, for example, or a memory-device with a wider data channel can support still more widths. In one embodiment, a memory component with a x8 channel supports a 1 :4 speed ratio between DRAM side and host side of a data buffer to enable an eight-channel 256GB / s DIMM with Chipkill support and reduced power consumption.

[0038] While the present invention has been described in connection with specific embodiments, after reading this disclosure variations of these embodiments will be apparent to those of ordinary skill in the art. For example, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or "coupling," establishes some desired electrical communication between two or more circuit nodes, or terminals. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art.Therefore, the spirit and scope of the appended claims should not be limited to the foregoingdescription. Only those claims specifically reciting "means for" or "step for" should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.

Claims

CLAIMSWhat is claimed is:

1. A memory module comprising: first and second random-access memory components, each memory component including: a data port having data pads to communicate data to and from the memory component; a memory core to store the data, the memory core including a memory-core port to communicate the data in bursts of data bits; a multi-level serializer coupled between the data port and the memory-core port, the multi-level serializer to communicate each of the bursts of data bits over the data port in each of a first mode and a second mode, wherein the serializer: in the first mode, communicates each of the bursts of data bits to the data port over a burst duration as data of width W 1 and burst length LI ; and in the second mode, communicates each of the bursts of data bits to the data port over the burst duration as data of width W2 less than the width W 1 and a burst length L2 greater than the length LI, where the product of W1 and LI equals the product of W2 and L2; and a data-buffer component separate from the memory components and coupled to the data pads of the first and second memory components, the data-buffer component to combine the bursts of data from first and second data ports in the first mode and the second mode.

2. The memory module of claim 1, wherein the data-buffer component communicates the combined bursts of data over the burst duration in the first mode and the second mode.

3. The memory module of claim 1, wherein the width W1 is a factor of two the width W2.

4. The memory module of claim 3. wherein the width W1 is four.

5. The memory module of claim 4, wherein the burst length LI is sixteen.

6. The memory module of claim 1, wherein each of the memory components issues a timing signal with the respective bursts of data bits, and wherein the data-buffer componentincludes data-alignment circuitry to align the bursts of data bits responsive to the timing signals.

7. The memory module of claim 1, further comprising a printed-circuit board with traces connecting the data-buffer component to the data pads.

8. The memory module of claim 1, further comprising: an address-buffer component having a first command port coupled to the first memory component, a second command port coupled to the second memory component, and a third command port coupled to the data-buffer component.

9. The memory module of claim 8, further comprising at least one mode register to store a mode value selecting one of the first and second modes.

10. The memory module of claim 9, each of the memory components including one of the mode registers.

11. The memory module of claim 1, each memory component further including: a second data port having second data pads to communicate second data to and from the memory component; a second memory core to store the second data, the second memory core including a second memory-core port to communicate the second data in bursts of second data bits; and a second multi-level serializer coupled between the second data port and the second memory-core port, the second multi-level serializer to communicate each of the bursts of second data bits over the second data port in each of the first mode and the second mode.

12. The memory module of claim 11, wherein the second serializer: in the first mode, communicates each of the bursts of second data bits to the second data port over the burst duration as data of width W 1 and burst length LI ; and in the second mode, communicates each of the bursts of second data bits to the second data port over the burst duration as data of width W2 and burst length L2.

13. An integrated-circuit memory device comprising: a data port having data pads to communicate data to and from the memory device;a memory core having a memory-core port, the memory core to store data and communicate the data as parallel bitstreams of a burst length from the memory-core port; and a multi-level serializer coupled to between the data port and the memory-core port, the multi-level serializer to serialize the parallel bitstreams from the memory core to the data pads, wherein the serializer: in a first mode, serializes the parallel bitstreams to at least one burst of data bits on the data port over a burst duration as data of width W1 and burst length LI; and in a second mode, serializes the parallel bitstreams to at least one burst of data bits on the data port over the burst duration as data of width W2 and burst length L2 greater than the burst length LI, where the product of W1 and LI equals the product of W2 and L2.

14. The memory device of claim 13. wherein the width W1 is four and the burst length LI is sixteen.

15. The memory device of claim 14, further comprising at least one mode register to store a mode value selecting one of the first and second modes.

16. The memory device of claim 15 , each memory component further including: a second data port having second data pads to communicate second data to and from the memory component; a second memory core to store the second data, the second memory core including a second memory-core port to communicate the second data in bursts of second data bits; and a second multi-level serializer coupled between the second data port and the second memory-core port, the second multi-level serializer to communicate each of the bursts of second data bits over the second data port in each of the first mode and the second mode.

17. The memory device of claim 16, wherein the second serializer: in the first mode, communicates each of the bursts of second data bits to the second data port over the burst duration as data of width W1 and burst length LI; and in the second mode, communicates each of the bursts of second data bits to the second data port over the burst duration as data of width W2 and burst length L2.

18. A data-buffer component supporting first and second mode in support of memory devices, the data buffer comprising: first and second memory-side data ports to receive, from the memory devices, respective first and second data bursts of a first data width W 1 and a first burst length LI in the first mode and third and fourth data bursts of a second data width W2 less than the first data width W 1 and a second burst length L2 greater than the first burst length LI in the second mode, wherein the products L1*W1 and L2*W2 are equal; data- alignment circuitry coupled to the first and second memory- side data ports to receive and temporally align the first and second data bursts in the first mode and the third and fourth data bursts in the second mode; and gearbox circuitry coupled to the data-alignment circuitry to combine the aligned first and second data bursts in the first mode and the aligned third and fourth data bursts in the second mode, the gearbox circuitry to combine the aligned first and second data bursts and the aligned third and fourth data burst into fifth data bursts of the first data width Wl.

19. The data-buffer component of claim 18, wherein the combined first and second data bursts and the combined third and fourth data bursts of an equal burst duration.

20. The data-buffer component of claim 18, wherein the first width Wl is twice the second width W2.

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