Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel (10) comprises pixel circuits (100) and signal lines (200), wherein the signal lines (200) comprise data signal lines (210), and a plurality of data signal lines (210) extend in a first direction (X1) and are arranged in a second direction (X2); a plurality of pixel circuits (100) arranged in the first direction (X1) are electrically connected to the same data signal line (210); and the signal lines (200) further comprise a plurality of auxiliary lines (220). The display panel (10) further comprises a display area (AA) and a non-display area (NA), wherein the display area (AA) comprises a first display area (AA1) and a second display area (AA2), and the non-display area (NA) comprises a fan-out area (A1), which comprises a plurality of fan-out traces (S0). The auxiliary lines (220) comprise auxiliary data lines (221), wherein the data signal lines (210) located in the second display area (AA2) are electrically connected to the fan-out traces (S0) by means of the auxiliary data lines (221); the auxiliary data lines (221) comprise first data connection line segments (222) extending in the first direction (X1); and m first data connection line segments (222) are provided in an area in which n pixel circuits (100) consecutively arranged in the second direction (X2) are correspondingly provided, with n≠m .

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411255015.2, filed on September 6, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the display technical field, for example, to a display panel and a display device. BACKGROUND

[0003] With the continuous development of display technology, display panels have been widely used in people's production and life. In order to better meet people's needs, the display panel can be adjusted, for example, part of the wiring is adjusted, so as to improve the overall effect of the display panel.

[0004] SUMMARY

[0005] Embodiments of the present application provide a display panel and a display device, by adjusting the setting mode of the data auxiliary line, the yield loss can be reduced or the display effect of the display panel can be improved, etc.

[0006] In a first aspect, embodiments of the present application provide a display panel, comprising a plurality of pixel circuits and a plurality of signal lines; the signal lines comprise data signal lines, a plurality of the data signal lines extend along a first direction and are arranged along a second direction; a plurality of the pixel circuits arranged along the first direction are electrically connected with the same data signal line; the first direction and the second direction intersect; the signal lines further comprise a plurality of auxiliary lines, the auxiliary lines extend along the first direction; the display panel further comprises a display area and a non-display area at least partially surrounding the display area, the display area comprises a first display area and a second display area, the second display area is located at least one side of the first display area along the second direction; the first display area and the second display area both comprise a plurality of the data signal lines; the non-display area comprises a fan-out area located at one side of the display area along the first direction, the fan-out area comprises a plurality of fan-out wires; the auxiliary lines comprise data auxiliary lines, the data signal lines located in the second display area are electrically connected with the fan-out wires through the data auxiliary lines; the data auxiliary lines comprise first data connection line segments extending along the first direction; in a region corresponding to n pixel circuits arranged continuously along the second direction, m first data connection line segments are arranged; wherein n≠m, and n and m are both positive integers.

[0007] In a second aspect, embodiments of the present application provide a display device comprising the display panel of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, will be described below. Obviously, the drawings are only a part of the accompanying drawings in this application, and other drawings can be obtained by those ordinarily skilled in the art without creative effort, based on these drawings.

[0009] FIG. 1 is a structural schematic diagram of a first display panel according to an embodiment of the present application;

[0010] FIG. 2 is a structural schematic diagram of a second display panel according to an embodiment of the present application;

[0011] FIG. 3 is a structural schematic diagram of a third display panel according to an embodiment of the present application;

[0012] FIG. 4 is a structural schematic diagram of a first pixel circuit according to an embodiment of the present application;

[0013] FIG. 5 is a timing diagram of an embodiment of signals provided to the pixel circuit shown in FIG. 4 in a driving cycle according to an embodiment of the present application;

[0014] FIG. 6 is a schematic diagram of a film layer structure of the pixel circuit shown in FIG. 4;

[0015] FIG. 7 is a schematic diagram of a film layer structure of the first display panel according to an embodiment of the present application;

[0016] FIG. 8 is a schematic diagram of a partial film layer structure of the first display panel according to an embodiment of the present application;

[0017] FIG. 9 is a schematic diagram of a first partial structure in FIG. 7;

[0018] FIG. 10 is a schematic diagram of a second partial structure in FIG. 7;

[0019] FIG. 11 is a schematic diagram of a third partial structure in FIG. 7;

[0020] FIG. 12 is a schematic diagram of a fourth partial structure in FIG. 7;

[0021] FIG. 13 is a schematic diagram of a fifth partial structure in FIG. 7;

[0022] FIG. 14 is a schematic diagram of a sixth partial structure in FIG. 7;

[0023] FIG. 15 is a schematic diagram of a fourth partial structure in FIG. 12 according to the related art;

[0024] FIG. 16 is a schematic diagram of a fifth partial structure in FIG. 13 according to the related art;

[0025] FIG. 17 is a schematic diagram of a film layer structure of a second display panel according to an embodiment of the present application;

[0026] FIG. 18 is a schematic view of a partial film layer structure of a second display panel according to an embodiment of the present application;

[0027] FIG. 19 is a schematic view of a first partial structure of FIG. 17;

[0028] FIG. 20 is a schematic view of a second partial structure of FIG. 17;

[0029] FIG. 21 is a schematic view of a third partial structure of FIG. 17;

[0030] FIG. 22 is a schematic view of a fourth partial structure of FIG. 17;

[0031] FIG. 23 is a schematic view of a fifth partial structure of FIG. 17;

[0032] FIG. 24 is a schematic view of a sixth partial structure of FIG. 27;

[0033] FIG. 25 is a schematic view of a film layer structure of a third display panel according to an embodiment of the present application;

[0034] FIG. 26 is a schematic view of a partial film layer structure of the third display panel according to an embodiment of the present application;

[0035] FIG. 27 is a schematic view of a first partial structure of FIG. 25;

[0036] FIG. 28 is a schematic view of a second partial structure of FIG. 25;

[0037] FIG. 29 is a schematic view of a third partial structure of FIG. 25;

[0038] FIG. 30 is a schematic view of a fourth partial structure of FIG. 25;

[0039] FIG. 31 is a schematic view of a fifth partial structure of FIG. 25;

[0040] FIG. 32 is a schematic view of a sixth partial structure of FIG. 25;

[0041] FIG. 33 is a schematic view of a structure of a second pixel circuit according to an embodiment of the present application;

[0042] FIG. 34 is a schematic view of a film layer structure of a fourth display panel according to an embodiment of the present application;

[0043] FIG. 35 is a schematic view of a partial film layer structure of the fourth display panel according to an embodiment of the present application;

[0044] FIG. 36 is a schematic view of a first partial structure of FIG. 34;

[0045] FIG. 37 is a schematic view of a second partial structure of FIG. 34;

[0046] FIG. 38 is a schematic view of a third partial structure of FIG. 34;

[0047] FIG. 39 is a schematic diagram of a fourth partial structure in FIG. 34;

[0048] FIG. 40 is a schematic diagram of a fifth partial structure in FIG. 34;

[0049] FIG. 41 is a schematic diagram of a sixth partial structure in FIG. 34;

[0050] FIG. 42 is a schematic diagram of a fourth partial structure in FIG. 39 according to the related art;

[0051] FIG. 43 is a schematic diagram of a fifth partial structure in FIG. 40 according to the related art;

[0052] FIG. 44 is a schematic diagram of a film layer structure of a fifth display panel according to an embodiment of the present application;

[0053] FIG. 45 is a schematic diagram of a partial film layer structure of the fifth display panel according to an embodiment of the present application;

[0054] FIG. 46 is a schematic diagram of a first partial structure in FIG. 44;

[0055] FIG. 47 is a schematic diagram of a second partial structure in FIG. 44;

[0056] FIG. 48 is a schematic diagram of a third partial structure in FIG. 44;

[0057] FIG. 49 is a schematic diagram of a fourth partial structure in FIG. 44;

[0058] FIG. 50 is a schematic diagram of a fifth partial structure in FIG. 44;

[0059] FIG. 51 is a schematic diagram of a sixth partial structure in FIG. 44;

[0060] FIG. 52 is a schematic diagram of a structure of a third pixel circuit according to an embodiment of the present application;

[0061] FIG. 53 is a timing of an embodiment of signals provided to the pixel circuit shown in FIG. 52 in a driving period according to an embodiment of the present application;

[0062] FIG. 54 is a schematic diagram of a film layer structure of the pixel circuit shown in FIG. 52;

[0063] FIG. 55 is a schematic diagram of a film layer structure of a sixth display panel according to an embodiment of the present application;

[0064] FIG. 56 is a schematic diagram of a partial film layer structure of the sixth display panel according to an embodiment of the present application;

[0065] FIG. 57 is a schematic diagram of a first partial structure in FIG. 55;

[0066] FIG. 58 is a schematic diagram of a second partial structure in FIG. 55;

[0067] FIG. 59 is a schematic diagram of a third partial structure in FIG. 55;

[0068] FIG. 60 is a schematic diagram of a fourth partial structure in FIG. 55;

[0069] FIG. 61 is a schematic diagram of a fifth partial structure in FIG. 55;

[0070] FIG. 62 is a schematic diagram of a sixth partial structure in FIG. 55;

[0071] FIG. 63 is a schematic diagram of a seventh partial structure in FIG. 55;

[0072] FIG. 64 is a schematic diagram of an eighth partial structure in FIG. 55;

[0073] FIG. 65 is a schematic diagram of a fifth partial structure in FIG. 61 in the related art;

[0074] FIG. 66 is a schematic diagram of a sixth partial structure in FIG. 62 in the related art;

[0075] FIG. 67 is a schematic diagram of a seventh partial structure in FIG. 63 in the related art;

[0076] FIG. 68 is a schematic diagram of a partial structure of a first display panel provided by an embodiment of the present application;

[0077] FIG. 69 is a schematic diagram of a partial structure of a second display panel provided by an embodiment of the present application;

[0078] FIG. 70 is a schematic diagram of a partial structure of a third display panel provided by an embodiment of the present application;

[0079] FIG. 71 is a schematic diagram of a partial structure of a fourth display panel provided by an embodiment of the present application;

[0080] FIG. 72 is a schematic diagram of a partial structure of a fifth display panel provided by an embodiment of the present application;

[0081] FIG. 73 is a schematic diagram of a partial structure of a sixth display panel provided by an embodiment of the present application;

[0082] FIG. 74 is a schematic diagram of a partial structure of a seventh display panel provided by an embodiment of the present application;

[0083] FIG. 75 is a schematic diagram of a partial structure of an eighth display panel provided by an embodiment of the present application;

[0084] FIG. 76 is a schematic diagram of a partial structure of a ninth display panel provided by an embodiment of the present application;

[0085] FIG. 77 is a schematic diagram of a partial structure of a tenth display panel provided by an embodiment of the present application;

[0086] FIG. 78 is a partial structure diagram of a tenth display panel according to an embodiment of the present application;

[0087] FIG. 79 is a diagram of a film layer structure of a seventh display panel according to an embodiment of the present application;

[0088] FIG. 80 is a partial film layer structure diagram of the seventh display panel according to an embodiment of the present application;

[0089] FIG. 81 is a diagram of a fourth partial structure of FIG. 79;

[0090] FIG. 82 is a diagram of a fifth partial structure of FIG. 79;

[0091] FIG. 83 is a diagram of a film layer structure of an eighth display panel according to an embodiment of the present application;

[0092] FIG. 84 is a diagram of a film layer structure of the eighth display panel according to an embodiment of the present application;

[0093] FIG. 85 is a diagram of a fourth partial structure of FIG. 83;

[0094] FIG. 86 is a diagram of a fifth partial structure of FIG. 83;

[0095] FIG. 87 is another diagram of a film layer structure of the pixel circuit shown in FIG. 4;

[0096] FIG. 88 is a diagram of a structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0097] The present application will be described with reference to the accompanying drawings and embodiments. It is to be understood that the embodiments described herein are merely illustrative of the present application and should not be taken as limiting the present application. For the sake of brevity and clarity, only the portions of the drawings that are needed to describe the present application are included herein.

[0098] The terms "first", "second", and the like, in the description and in the claims of the present application and the above drawings, are used for distinguishing between similar objects and not necessarily for describing a specific sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the present application described herein are capable of operation in other sequences than described or illustrated herein. Moreover, the terms "include", "have", and any variations thereof, are intended to cover a non-exclusive inclusion, such that a system, a product, or an apparatus that comprises a list of components does not include only those components but can include other components not expressly listed or inherent to such system, product or apparatus.

[0099] FIG. 1 is a structural schematic diagram of a first display panel provided in an embodiment of the present application, FIG. 2 is a structural schematic diagram of a second display panel provided in an embodiment of the present application, and FIG. 3 is a structural schematic diagram of a third display panel provided in an embodiment of the present application. Referring to FIGS. 1-3, the present application provides a display panel 10, which includes a plurality of pixel circuits 100 and a plurality of signal lines 200. The signal lines 200 include data signal lines 210, and the plurality of data signal lines 210 extend along a first direction X1 and are arranged along a second direction X2. The plurality of pixel circuits 100 arranged along the first direction X1 are electrically connected to the same data signal line 210. The first direction X1 and the second direction X2 intersect. The signal lines 200 further include a plurality of auxiliary lines 220. The display panel 10 further includes a display area AA and a non-display area NA at least partially surrounding the display area AA. The display area AA includes a first display area AA1 and a second display area AA2, and the second display area AA2 is located at least one side of the first display area AA1 along the second direction X2. The first display area AA1 and the second display area AA2 each include a plurality of data signal lines 210. The non-display area NA includes a fan-out area A1 located at one side of the display area AA along the first direction X1, and the fan-out area A1 includes a plurality of fan-out lines S0. The auxiliary lines 220 include data auxiliary lines 221, and the data signal lines 210 located in the second display area AA2 are electrically connected to the fan-out lines S0 through the data auxiliary lines 221. The data auxiliary lines 221 include first data connection line segments 222 extending along the first direction X1. In a region corresponding to n pixel circuits 100 arranged continuously along the second direction X2, m first data connection line segments 222 are arranged. n≠m, and n and m are positive integers.

[0100] Referring to FIG. 1, the display panel 10 includes the pixel circuit 100, which is electrically connected to a light emitting element 300 in the display panel 10 to drive the light emitting element 300 and ensure light emitting display of the light emitting element 300. The display panel 10 further includes the signal line 200, which is configured to provide a voltage signal and / or a current signal to the pixel circuit 100, thereby driving the light emitting element 300 by the pixel circuit 100.

[0101] The signal line 200 includes a data signal line 210 configured to provide a data signal for the pixel circuit 100. The pixel circuit 100 can be arranged in various ways, and the structure of the pixel circuit 100 is not shown in FIG. 1, and the electrical connection positions of the transistors in the pixel circuit 100 are not explicitly shown. Therefore, the electrical connection relationship between the data signal line 210 and the pixel circuit 100 is only schematically shown in the figure by the overlapping manner of the data signal line 210 and the pixel circuit 100, but is not intended to limit the overlapping positions and the overlapping area. The plurality of data signal lines 210 extend along a first direction X1, and the plurality of data signal lines 210 are arranged along a second direction X2, thereby embodying the arrangement and arrangement of the plurality of data signal lines 210. Meanwhile, as shown in FIG. 1, the plurality of pixel circuits 100 arranged along the first direction X1 are electrically connected to the same data signal line 210, that is, the plurality of pixel circuits 100 arranged along the same column receive the data signal provided by the same data signal line 210. It can be understood that the pixel circuits 100 arranged along the same column are electrically connected to the same data signal line 210.

[0102] Referring to FIGS. 2 and 3, the display panel 10 includes a display area AA and a non-display area NA. The display area AA includes light emitting elements (not shown in the figure) and data signal lines 210 connected to the light emitting elements, and is configured to realize the display function of the display panel 10. The non-display area NA includes a display controller, such as a driving chip (not shown in the figure), connected to the data signal line 210. The display controller provides a data signal to the data signal line 210, thereby driving the display panel 10 to realize the display function. The non-display area NA surrounds at least part of the display area AA, and the positions of the display area AA and the non-display area NA are not limited in the embodiments of the present application.

[0103] Referring to FIGS. 2 and 3, the non-display area NA further includes a fan-out area A1, and the fan-out area A1 includes a plurality of fan-out wires S0 electrically connected to the plurality of data signal lines 210. That is, the display controller can transmit the data signal to the data signal line 210 through the fan-out wire S0, thereby ensuring stable transmission of the data signal.

[0104] The display region AA includes a first display region AA1 and a second display region AA2, the second display region AA2 is located on both sides of the first display region AA1, and the second display region AA2 is closer to the boundary of the display region AA than the first display region AA1. The data signal lines 210 in the first display region AA1 extend along the first direction X1 and are arranged along the second direction X2, and the data signal lines 210 can be directly electrically connected with the fan-out wire S0; the data signal lines 210 in the second display region AA2 also extend along the first direction X1 and are arranged along the second direction X2, but the data signal lines 210 are not directly electrically connected with the fan-out wire S0. Referring to FIGS. 2 and 3, the signal line 200 further includes an auxiliary line 220, the auxiliary line 220 includes a data auxiliary line 221 configured to transmit a data signal; the auxiliary line 220 further includes other wires, for example, wires configured to transmit other fixed potentials, etc., which are not described one by one in the embodiments of the present application. As for the data auxiliary line 221, it electrically connects the data signal line 210 located in the second display region AA2 with the fan-out wire S0, and the data signal is transmitted to the data signal line 210 located in the first display region AA1 through the fan-out wire S0 and the data auxiliary line 221, so that the data signal line 210 located in the first display region AA1 can be avoided to be directly electrically connected with the fan-out wire S0, the occupied space of the fan-out wire S0 can be reduced, and then the setting area of the fan-out region A1 can be reduced, the proportion of the non-display region NA can be effectively reduced, the proportion of the display region AA of the display panel 10 can be increased, and the display effect of the display panel 10 can be increased. It should be noted that the setting mode of the data auxiliary line 221 has diversity, and FIGS. 2 and 3 only exemplify, and do not show all the wire modes of the data auxiliary line 221.

[0105] Referring to FIGS. 2 and 3, the data auxiliary line 221 includes a first data connection line segment 222, the extension mode of the first data connection line segment 222 is the same as the extension direction of the data signal line 210, and the setting mode between the first data connection line segment 222 and the data signal line 210 has flexibility, which can be adaptively adjusted according to different display panels 10.

[0106] In the region corresponding to the n pixel circuits 100 arranged continuously along the second direction X2, the number of the first data connection line segments 222 is m, where m and n are different positive integers. It can be understood that in the region corresponding to the n pixel circuits 100 arranged continuously along the second direction X2, there are first data connection line segments 222 with different numbers of pixel circuits 100, so that the setting of the first data connection line segments 222 has flexibility, which can be adaptively adjusted according to different display panels 10.

[0107] FIG. 4 is a structure diagram of a first pixel circuit according to an embodiment of the present application, FIG. 5 is a timing of an embodiment of signals provided to the pixel circuit shown in FIG. 4 in a driving period according to an embodiment of the present application, and FIG. 6 is a film layer structure diagram of the pixel circuit shown in FIG. 4. Referring to FIGS. 4 to 6, the pixel circuit 100 can have various setting modes, and thus the display panel 10 can have various setting types. For example, referring to FIG. 4, the pixel circuit 100 is exemplified as "7T1C". Based on the setting mode of the pixel circuit 100, those skilled in the art can make adaptive adjustment according to requirements. Referring to FIG. 4, the pixel circuit 100 can include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emitting control transistor T6, an anode reset transistor T7, and a storage capacitor Cst. Optionally, the types of the transistors in the pixel circuit 100 can be various. The transistors can include low temperature poly-silicon transistors (LTPS) which have advantages of high switching speed, high carrier mobility, and small power consumption, etc.

[0108] For the timing operation of the pixel circuit 100, referring to FIG. 5, the scan signal line (shown as S1 in the figure) connected to the control terminal of the initialization reset transistor T5 can control the on and off of the initialization reset transistor T5, and write the reset signal in the initialization reset signal line (shown as Vref1 in the figure) connected to the input terminal of the initialization reset transistor T5 to the gate of the driving transistor T3 when the initialization reset transistor T5 is on, to reset the first node N1. The storage capacitor Cst can ensure the stability of the potential of the first node N1. The scan signal line (shown as SP in the figure) connected to the control terminal of the data writing transistor T2 can control the on and off of the data writing transistor T2, and write the data signal on the data signal line (shown as Vdata in the figure) to the first electrode of the driving transistor T3 when the data writing transistor T2 is on. The scan signal line (shown as S2 in the figure) connected to the control terminal of the threshold compensation transistor T4 can control the on and off of the threshold compensation transistor T4, and compensate the threshold voltage of the driving transistor T3 when the threshold compensation transistor T4 is on; at the same time, the scan signal line (shown as SP in the figure) connected to the control terminal of the anode reset transistor T7 can control the on and off of the anode reset transistor T7, and reset the anode of the light emitting element 300 connected to the pixel circuit 100 when the anode reset transistor T7 is on, i.e. write the reset signal on the anode reset signal line (shown as Vref2 in the figure) to the anode of the light emitting element 300. The light emitting control signal line (shown as Emit in the figure) connected to the control terminal of the first light emitting control transistor T1 and the control terminal of the second light emitting control transistor T6 can control the on and off of the control terminal of the first light emitting control transistor T1 and the second light emitting control transistor T6, and write the power supply signal transmitted by the power supply signal line PVDD to the light emitting element 300 when the first light emitting control transistor T1 and the second light emitting control transistor T6 are on, so as to realize the display and light emission of the light emitting element 300. Referring to FIG. 5, one frame time of the display panel 10 at least includes an initialization writing stage P1, a data writing stage P2 and a light emitting stage P3. In the initialization stage P1, the initialization reset transistor T5 is turned on under the control of the scan signal line (shown as S1 in the figure), and the reset signal in the initialization reset signal line (shown as Vref1 in the figure) is written to the first node N1 electrically connected to the gate of the driving transistor T3 to initialize the gate of the driving transistor T3, and at the same time, since the threshold compensation transistor T4 is on, the reset signal in the initialization reset signal line (shown as Vref1 in the figure) is also written to the second electrode of the driving transistor T3, i.e. the N3 node.In the data writing stage P2, the data writing transistor T2 is turned on under the control of a scan signal line (shown as SP in the figure), and the threshold compensation transistor T4 is turned on under the control of a scan signal line (shown as S2 in the figure), so that the data signal Vdata is written into the gate of the drive transistor T3 through the data writing transistor T2, the drive transistor T3 and the threshold compensation transistor T4 in turn. At the same time, in the data writing stage P2, the anode reset transistor T7 is turned on under the control of a scan signal line (shown as SP in the figure), and a reset signal in the anode reset signal line (shown as Vref2 in the figure) is written into the anode of the light emitting element 300 to initialize the anode of the light emitting element 300. In the light emitting stage P3, the first light emitting transistor T1 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal Emit, so that the drive current generated by the drive transistor T3 can be transmitted to the anode of the light emitting element 300, thereby driving the light emitting element 300 to emit light.

[0109] The display panel 10 is provided by overlapping a plurality of film layers. Referring to FIG. 6, the film layer structure of the pixel circuit 100 shown in FIG. 6 can be the pixel circuit 100 provided in FIG. 4. The film layer structure of the pixel circuit 100 can be, from bottom to the light emitting side of the display panel 10, a substrate 400, a buffer layer 410, a first semiconductor layer 420, a first insulating layer 430, a first metal layer 440, an interlayer insulating layer 450, a second metal layer 460, a second insulating layer 470, a first source-drain electrode layer 480, a third insulating layer 490, a second source-drain electrode layer 4100, a planarization layer 4110, and an anode layer 4120. For the film layer structure of the pixel circuit 100, adaptive adjustments such as adding or removing part of the film layer can be made according to actual needs, and any one of the above film layers can include at least one sublayer, which is not limited in the embodiments of the present application.

[0110] FIG. 7 is a schematic diagram of a film layer structure of a first display panel provided in an embodiment of the present application, FIG. 8 is a schematic diagram of part of the film layer structure of the first display panel provided in the embodiment of the present application, FIG. 9 is a schematic diagram of a first part of structure in FIG. 7, FIG. 10 is a schematic diagram of a second part of structure in FIG. 7, FIG. 11 is a schematic diagram of a third part of structure in FIG. 7, FIG. 12 is a schematic diagram of a fourth part of structure in FIG. 7, FIG. 13 is a schematic diagram of a fifth part of structure in FIG. 7, and FIG. 14 is a schematic diagram of a sixth part of structure in FIG. 7. Referring to FIGS. 4 to 14, if the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in FIG. 4, the film layer structure relationship of the display panel 10 can be shown with reference to FIGS. 7 and 8, and FIGS. 9 to 13 are used to show different film layers in FIG. 8 from bottom to top, and FIGS. 9 to 14 are used to show different film layers in FIG. 7 from bottom to top.

[0111] Referring to FIGS. 9-14, in the corresponding film layer structure of the pixel circuit 100, for the mentioned along the second direction X2, the area corresponding to the arrangement of the n pixel circuits 100 can be understood as shown in the area B1 in FIG. 7, i.e., the area corresponding to the arrangement of the two pixel circuits 100 arranged along the first direction X1. Referring to FIG. 7, area B1 and FIG. 9, area B2, the area corresponding to the arrangement of the pixel circuit 100 is understood along the first direction X1 as the area where the active layer 420 of the pixel circuit 100 arranged along the first direction X1 is located, and the area corresponding to the arrangement of the pixel circuit 100 is understood along the second direction X2 as the active layer 420 of the two groups of pixel circuits 100 arranged along the second direction X2; or, referring to FIG. 7, area B1 and FIG. 13, area B3, the area corresponding to the arrangement of the pixel circuit 100 is understood along the second direction X2 as the area between the adjacent two data signal lines 210 or the adjacent two power signal lines (such as the positive power signal line PVDD) along the second direction X2, referring to FIG. 7, area B1 and FIG. 13, area B3, i.e., the frame of the area corresponding to the arrangement of the pixel circuit 100 is located in the middle of the power signal line, i.e., the areas corresponding to the arrangement of the pixel circuits 100 on both sides can share a power signal line; or, referring to FIG. 7, area B1 and FIG. 14, area B4, the area corresponding to the arrangement of the pixel circuit 100 is understood along the first direction X1 as the area where the anode of the light emitting element 300 arranged along the first direction X1 is located.

[0112] Referring to FIG. 13, in the area corresponding to the arrangement of the two pixel circuits 100 arranged continuously along the second direction X2, four first data connection line segments 222 are arranged. That is, in this area, the number of data signal lines 210 arranged and the number of first data connection line segments 222 arranged are different. The larger number of first data connection line segments 222 can ensure the electrical connection relationship between the data signal line 210 and the fan-out wire S0 in the second display area AA2, so as to ensure that the pixel circuit 100 in the second display area AA2 obtains stable data signals, so as to ensure the uniformity of the brightness of the display panel 10 in the display area AA, thereby ensuring the overall display effect of the display panel 10. The larger number of first data connection line segments 222 can ensure the acquisition of data signals in the pixel circuit 100 in the edge area of the display panel 10, so as to increase the size of the second display area AA2 along the second direction X2, thereby reducing the size of the first display area AA1 along the second direction X2, thereby further reducing the area of the fan-out area A1, effectively reducing the proportion of the non-display area NA, increasing the proportion of the display area AA of the display panel 10, and increasing the display effect of the display panel 10.

[0113] FIG. 15 is a schematic diagram of a fourth portion of FIG. 12 in the related art, and FIG. 16 is a schematic diagram of a fifth portion of FIG. 13 in the related art. As shown in FIG. 15 and FIG. 16, for example, as shown in FIG. 16, in the film layer structure of the pixel circuit 100 shown in FIG. 4 in the related art, in the region corresponding to the pixel circuit 100 and arranged in the second direction X2, two first data connection line segments 222 are arranged. Alternatively, it can be understood that the number of the data signal line 210 and the first data connection line segment 222 is one-to-one, that is, the number of the first data connection line segment 222 is not reduced or redundant compared with the number of the data signal line 210. By comparison with FIG. 13 and FIG. 16, in the display panel 10 provided by the embodiment of the present application, the number of the first data connection line segment 222 in the region corresponding to the pixel circuit 100 can be more than the number of the data signal line 210, so as to ensure the display effect of the first display area AA1 and the second display area AA2, and ensure the display balance of the display panel 10 as a whole.

[0114] FIG. 17 is a schematic diagram of a film layer structure of a second display panel provided by the embodiment of the present application, FIG. 18 is a schematic diagram of a partial film layer structure of the second display panel provided by the embodiment of the present application, FIG. 19 is a schematic diagram of a first partial structure of FIG. 17, FIG. 20 is a schematic diagram of a second partial structure of FIG. 17, FIG. 21 is a schematic diagram of a third partial structure of FIG. 17, FIG. 22 is a schematic diagram of a fourth partial structure of FIG. 17, FIG. 23 is a schematic diagram of a fifth partial structure of FIG. 17, and FIG. 24 is a schematic diagram of a sixth partial structure of FIG. 17. As shown in FIG. 4 to FIG. 6 and FIG. 17 to FIG. 24, if the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in FIG. 4, the film layer structure relationship of the display panel 10 can be shown in FIG. 17 and FIG. 18, and FIG. 19 to FIG. 23 are used to show different film layers from bottom to top in FIG. 18, and FIG. 19 to FIG. 24 are used to show different film layers from bottom to top in FIG. 19.

[0115] Referring to FIGS. 19-24, in the corresponding film layer structure of the pixel circuit 100, two auxiliary wires 220 are arranged between the two data signal lines 210, one of which can be configured to transmit other fixed potential signals, such as reset signals in the anode reset signal line (shown as Vref2 in the figure), and the other is the first data connection line segment 222, which is configured to transmit data signals of the fan-out wire S0 to the pixel circuit 100 in the second display area AA2. In combination with FIG. 17, the area where the two data signal lines 210 are located can be understood as an area corresponding to the arrangement of two pixel circuits 100 arranged continuously in the second direction X2, and referring to FIG. 17, the number of first data connection line segments 222 included in this area is one. That is, in this area, the number of data signal lines 210 and the number of first data connection line segments 222 are different. For a high-resolution display panel 10 or a display panel 10 with high space requirements for the pixel circuit 100, the number of first data connection line segments 222 can be reduced to meet the normal display of the second display area AA2, improve the use of space of the pixel circuit 100, and reduce the process preparation difficulty of the first data connection line segment 222, thereby ensuring the yield of the display panel 10. By comparing FIGS. 23 and 16, in the display panel 10 provided by the embodiment of the present application, the number of first data connection line segments 222 arranged in the corresponding arrangement area of the pixel circuit 100 can be less than the number of data signal lines 210 arranged. By reducing the number of first data connection line segments 222, the process preparation difficulty of the data auxiliary line 221 can be simplified, thereby also ensuring the use of space of the pixel circuit 100, thereby ensuring the overall display effect of the display panel 10.

[0116] FIG. 25 is a schematic diagram of a film layer structure of a third display panel provided by an embodiment of the present application, FIG. 26 is a schematic diagram of a partial film layer structure of the third display panel provided by an embodiment of the present application, FIG. 27 is a schematic diagram of a first partial structure in FIG. 25, FIG. 28 is a schematic diagram of a second partial structure in FIG. 25, FIG. 29 is a schematic diagram of a third partial structure in FIG. 25, FIG. 30 is a schematic diagram of a fourth partial structure in FIG. 25, FIG. 31 is a schematic diagram of a fifth partial structure in FIG. 25, and FIG. 32 is a schematic diagram of a sixth partial structure in FIG. 25. Referring to FIGS. 4-6 and 25-32, if the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in FIG. 4, the film layer structure relationship of the display panel 10 can be shown in FIGS. 25 and 26, and FIGS. 27-31 are used to show different film layers in FIG. 26 from bottom to top, and FIGS. 27-32 are used to show different film layers in FIG. 25 from bottom to top.

[0117] Referring to FIGS. 27-32, in the corresponding film layer structure of the pixel circuit 100, in combination with FIG. 25, the region where the two data signal lines 210 are located can be understood as a region where two pixel circuits 100 are arranged in the second direction X2, and referring to FIG. 25, the number of first data connection line segments 222 included in the region is one. That is, in the region, the number of data signal lines 210 and the number of first data connection line segments 222 are different. For a high-resolution display panel 10 or a display panel 10 with high space requirements for the pixel circuit 100, the number of first data connection line segments 222 can be reduced while meeting the normal display of the second display area AA2, improving the use of space of the pixel circuit 100, and reducing the process preparation difficulty of the first data connection line segment 222, thereby ensuring the yield of the display panel 10. By comparing FIGS. 31 and 16, in the display panel 10 provided by the embodiments of the present application, the number of first data connection line segments 222 in the region where the pixel circuit 100 is arranged can be less than the number of data signal lines 210. By reducing the number of first data connection line segments 222 while ensuring the normal display of the first display area AA1 and the second display area AA2, the process preparation difficulty of the data auxiliary line 221 can be simplified, thereby also ensuring the use of space of the pixel circuit 100, thereby ensuring the overall display effect of the display panel 10.

[0118] FIG. 33 is a structural schematic diagram of a second pixel circuit provided by the embodiments of the present application. Referring to FIG. 33, the pixel circuit 100 can also be exemplified as “8T1C”. Based on the arrangement of the pixel circuit 100, those skilled in the art can make adaptive adjustments according to needs. Referring to FIG. 33, the pixel circuit 100 can include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, a bias transistor T8, and a storage capacitor Cst. The working process of the pixel circuit 100 is similar to that of the pixel circuit 100 corresponding to FIG. 4, and is not repeated here. Meanwhile, the working timing of the pixel circuit 100 is similar to that of the pixel circuit 100 corresponding to FIG. 5, and is not repeated here. For the film layer structure schematic diagram of the pixel circuit 100 shown in FIG. 33, reference can be made to FIG. 6.

[0119] FIG. 34 is a schematic view of a film layer structure of a fourth display panel according to an embodiment of the present application, FIG. 35 is a schematic view of a partial film layer structure of the fourth display panel according to an embodiment of the present application, FIG. 36 is a schematic view of a first partial structure in FIG. 34, FIG. 37 is a schematic view of a second partial structure in FIG. 34, FIG. 38 is a schematic view of a third partial structure in FIG. 34, FIG. 39 is a schematic view of a fourth partial structure in FIG. 34, FIG. 40 is a schematic view of a fifth partial structure in FIG. 34, and FIG. 41 is a schematic view of a sixth partial structure in FIG. 34. Referring to FIGS. 6, 33-41, if the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in FIG. 33, the film layer structure relationship of the display panel 10 can be shown with reference to FIGS. 34 and 35, and FIGS. 36-40 are used to show different film layers in FIG. 35 from bottom to top, and FIGS. 36-41 are used to show different film layers in FIG. 34 from bottom to top.

[0120] Referring to FIGS. 36-41, in the corresponding film layer structure of the pixel circuit 100, in combination with FIG. 34, the area where the two data signal lines 210 are located can be understood as an area corresponding to the arrangement of two pixel circuits 100 arranged continuously along the second direction X2, and referring to FIG. 34, the number of first data connection line segments 222 included in the area is four. That is, in this area, the number of data signal lines 210 arranged and the number of first data connection line segments 222 arranged are different. The larger number of first data connection line segments 222 can ensure the electrical connection relationship between the data signal line 210 and the fan-out wire S0 in the second display area AA2, so as to ensure that the pixel circuit 100 in the second display area AA2 obtains stable data signals, so as to ensure the uniformity of brightness of the display panel 10 in the display area AA, thereby ensuring the overall display effect of the display panel 10. The larger number of first data connection line segments 222 can ensure the acquisition of data signals in the pixel circuit 100 in the edge area of the display panel 10, so as to increase the size of the second display area AA2 along the second direction X2, thereby reducing the size of the first display area AA1 along the second direction X2, thereby further reducing the size of the fan-out area A1, effectively reducing the proportion of the non-display area NA, increasing the proportion of the display area AA of the display panel 10, and increasing the display effect of the display panel 10.

[0121] FIG. 42 is a schematic diagram of a fourth portion of FIG. 39 in the related art, and FIG. 43 is a schematic diagram of a fifth portion of FIG. 40 in the related art. Referring to FIG. 42 and FIG. 43, for example, referring to FIG. 43, in the film layer structure of the pixel circuit 100 shown in FIG. 33 in the related art, in the region corresponding to the pixel circuit 100 and arranged in the second direction X2, two first data connection line segments 222 are arranged. Alternatively, it can be understood that the number of the data signal line 210 and the first data connection line segment 222 is one-to-one, that is, the number of the first data connection line segment 222 is not reduced or redundant compared with the number of the data signal line 210. By comparing FIG. 40 and FIG. 43, in the display panel 10 provided in the embodiments of the present application, the number of the first data connection line segment 222 in the region corresponding to the pixel circuit 100 can be greater than the number of the data signal line 210, so as to ensure the display effect of the first display area AA1 and the second display area AA2, and ensure the display balance of the display panel 10 as a whole.

[0122] FIG. 44 is a schematic diagram of a film layer structure of a fifth display panel provided in the embodiments of the present application, FIG. 45 is a schematic diagram of a partial film layer structure of the fifth display panel provided in the embodiments of the present application, FIG. 46 is a schematic diagram of a first portion of FIG. 44, FIG. 47 is a schematic diagram of a second portion of FIG. 44, FIG. 48 is a schematic diagram of a third portion of FIG. 44, FIG. 49 is a schematic diagram of a fourth portion of FIG. 44, FIG. 50 is a schematic diagram of a fifth portion of FIG. 44, FIG. 51 is a schematic diagram of a sixth portion of FIG. 44, and referring to FIG. 6, FIG. 33, FIG. 44 to FIG. 51, if the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in FIG. 37, the film layer structure relationship of the display panel 10 can be shown in FIG. 48 and FIG. 49, and FIG. 50 to FIG. 54 are used to show different film layers from bottom to top in FIG. 49, and FIG. 50 to FIG. 55 are used to show different film layers from bottom to top in FIG. 48.

[0123] Referring to FIGS. 46-51, in the corresponding film layer structure of the pixel circuit 100, in combination with FIG. 44, the area where the two data signal lines 210 are located can be understood as an area corresponding to the arrangement of two pixel circuits 100 arranged continuously along the second direction X2, and referring to FIG. 44, the number of first data connection line segments 222 included in the area is one. That is, in this area, the number of data signal lines 210 and the number of first data connection line segments 222 are different. For a high-resolution display panel 10 or a display panel 10 with high space requirements for the pixel circuit 100, the number of first data connection line segments 222 can be reduced to meet the normal display of the second display area AA2, improve the use of space of the pixel circuit 100, and reduce the process preparation difficulty of the first data connection line segment 222, thereby ensuring the yield of the display panel 10. Further, by comparing FIGS. 50 and 43, in the display panel 10 provided by the embodiment of the application, the number of first data connection line segments 222 in the area corresponding to the arrangement of the pixel circuit 100 can be less than the number of data signal lines 210. By reducing the number of first data connection line segments 222, the process preparation difficulty of the data auxiliary line 221 can be simplified, thereby also ensuring the use of space of the pixel circuit 100, thereby ensuring the overall display effect of the display panel 10.

[0124] FIG. 52 is a structural schematic diagram of a third pixel circuit provided by an embodiment of the application, FIG. 53 is a timing of an embodiment of signals provided to the pixel circuit shown in FIG. 52 in a driving cycle, and FIG. 54 is a film layer structure schematic diagram of the pixel circuit shown in FIG. 52. Referring to FIGS. 52-54, the arrangement of the pixel circuit 100 is diverse, thereby the arrangement of the display panel 10 is also diverse. For example, the pixel circuit 100 is exemplified as “8T1C”. The pixel circuit 100 can include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emitting control transistor T6, an anode reset transistor T7, a bias transistor T8, and a storage capacitor Cst. Optionally, for the pixel circuit 100 shown in FIG. 52, low-temperature polysilicon transistors and oxide transistors (Indium Gallium Zinc Oxide, IGZO) can also be included. The oxide transistor has the advantages of small leakage current, and the low-temperature polysilicon transistor has the advantages of high switching speed, high carrier mobility, and small power.

[0125] The operation of the pixel circuit 100 of Fig. 52 is similar to that of the pixel circuit 100 of Fig. 4, and thus the description thereof is not repeated. In the pixel circuit 100 of Fig. 52, a scan signal line (indicated by Sp in the figure) connected to the control terminal of the bias transistor T8 can control the on and off of the bias transistor T8, and write the bias signal transmitted from a bias adjustment signal line (indicated by DVH in the figure) to the bias transistor T8 when the bias transistor T8 is on, and perform bias adjustment on the second node N2.

[0126] Referring to FIG. 53, in one driving period Q of the pixel circuit 100, the driving period Q includes a data writing stage Q1, a light emitting stage Q2, and a light emitting maintaining stage Q3. The data writing stage Q1 includes a non-enabling stage of the light emitting control signal Emit. The light emitting stage Q2 includes an enabling stage of the light emitting control signal Emit. The light emitting maintaining stage Q3 includes a plurality of non-enabling stages and at least one enabling stage (one enabling stage is exemplified in FIG. 53). The biasing signal line (DVH in the figure) in the data writing stage Q1 and the light emitting stage Q2 can have the same level as the biasing signal line (DVH in the figure) in the light emitting maintaining stage Q3. The data writing stage Q1 includes a first biasing adjusting stage Q11. In the first biasing adjusting stage Q11, the signal transmitted by the scan signal line (SP in the figure) includes at least one low level period, and the signal transmitted by the scan signal line (S2N in the figure) includes at least one high level period. In other words, in the first biasing adjusting stage Q11, at least the biasing transistor T8 and the threshold compensation transistor T4 are turned on, the biasing signal of the biasing signal line (DVH in the figure) is transmitted to the driving transistor T3 through the biasing transistor T8, and is further transmitted to the gate of the driving transistor T3 through the threshold compensation transistor T4. In the first biasing adjusting stage Q11, the biasing signal can perform biasing adjustment on the first node N1, the second node N2, and the third node N3. The data writing stage Q1 further includes an initialization and second biasing adjusting stage Q12. In the initialization and second biasing adjusting stage Q12, the signal transmitted by the scan signal line (S2N in the figure) includes at least one high level period, and the signal transmitted by the scan signal line (S2N in the figure) includes at least one high level period. In other words, in the initialization and second biasing adjusting stage Q12, the initialization transistor T5 is turned on, and the threshold compensation transistor T4 is also turned on in the later period. The initialization reset signal line (Vref1 in the figure) can adjust the gate of the driving transistor T3 through the initialization transistor T5, and the initialization reset signal line (Vref1 in the figure) can also adjust the third node N3 through the initialization transistor T5 and the threshold compensation transistor T4.The data write stage Q1 further includes a data signal write stage Q13, in which the signal transmitted by the scan signal line (shown as S2N in the figure) includes a period of high level, and the signal transmitted by the scan signal line (shown as SP* in the figure) includes at least one period of low level, in other words, in the data signal write stage Q13, the data write transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal (shown as Vdata in the figure) can be transmitted to the gate of the driving transistor T3 through the data write transistor T2 and the threshold compensation transistor T4. The data write stage Q1 further includes a third bias adjustment stage Q14, in which the signal transmitted by the scan signal line (shown as SP in the figure) includes at least one period of low level, and the second stage N2 can be further biased and adjusted through the bias transistor T8 in the period.

[0127] FIG. 54 is a schematic diagram of a film layer structure of the pixel circuit 100 corresponding to FIG. 52. The film layer structure of the pixel circuit 100 can be, from bottom to the light-emitting side of the display panel 10, the substrate 500, the buffer layer 510, the first semiconductor layer 520, the first insulating layer 530, the first metal layer 540, the interlayer insulating layer 550, the second metal layer 560, the second insulating layer 570, the second semiconductor layer 580, the third insulating layer 590, the third metal layer 5100, the fourth insulating layer 5110, the first source-drain electrode layer 5120, the fifth insulating layer 5130, the second source-drain electrode layer 5140, the planarization layer 5150, and the anode layer 5160. For the film layer structure of the pixel circuit 100, adaptive adjustments such as adding or removing part of the film layer can be made according to actual needs, and any one of the above film layers can include at least one sublayer, which is not limited in the embodiments of the present application.

[0128] FIG. 55 is a schematic diagram of a film layer structure of a sixth display panel according to an embodiment of the present application, FIG. 56 is a schematic diagram of part of the film layer structure of the sixth display panel according to an embodiment of the present application, FIG. 57 is a schematic diagram of a first part of structure in FIG. 55, FIG. 58 is a schematic diagram of a second part of structure in FIG. 55, FIG. 59 is a schematic diagram of a third part of structure in FIG. 55, FIG. 60 is a schematic diagram of a fourth part of structure in FIG. 55, FIG. 61 is a schematic diagram of a fifth part of structure in FIG. 55, FIG. 62 is a schematic diagram of a sixth part of structure in FIG. 55, FIG. 63 is a schematic diagram of a seventh part of structure in FIG. 55, and FIG. 64 is a schematic diagram of an eighth part of structure in FIG. 55. Referring to FIGS. 52 to 64, if the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in FIG. 52, the film layer structure relationship of the display panel 10 can be shown with reference to FIGS. 55 and 56, and FIGS. 57 to 63 are used to show different film layers in FIG. 56 from bottom to top, and FIGS. 57 to 64 are used to show different film layers in FIG. 55 from bottom to top.

[0129] Referring to FIGS. 57-64, in the corresponding film layer structure of the pixel circuit 100, referring to FIG. 63, two auxiliary wires 220 are arranged between the two data signal lines 210, one of which can be configured to transmit other fixed potential signals, such as reset signals or bias signals in the anode reset signal line or the bias adjustment signal line (shown as Vref2 or DVH in the figure), and the other is a first data connection line segment 222, which is configured to transmit data signals of the fan-out wire S0 to the pixel circuit 100 in the second display area AA2. It should be noted that, referring to FIG. 63, along the second direction X2, the auxiliary wires 220 can be arranged in the following order: the first data connection line segment 222, the bias adjustment signal line, the first data connection line segment 222, and the anode reset signal line, i.e., the bias adjustment signal line and the anode reset signal line are arranged alternately. Alternatively, it can be understood that two adjacent data signal lines 210 are divided into one arrangement area, which includes the first data connection line segment 222 and also includes an auxiliary wire 220 that transmits other fixed potential signals. The fixed potential signal transmitted by the auxiliary wire 220 can be a reset signal or a bias signal, i.e., the fixed potential signal transmitted by the auxiliary wire 220 in one arrangement area is a reset signal, and the fixed potential signal transmitted by the auxiliary wire 220 in an adjacent arrangement area is a bias signal. In combination with FIG. 55, the area where the two data signal lines 210 are located can be understood as an area where two pixel circuits 100 corresponding to the two data signal lines 210 are arranged continuously along the second direction X2, and referring to FIG. 55, the number of first data connection line segments 222 included in the area is one. That is, in this area, the number of data signal lines 210 arranged and the number of first data connection line segments 222 arranged are different. For a high-resolution display panel 10 or a display panel 10 with high space requirements for the pixel circuit 100, the number of first data connection line segments 222 can be reduced while meeting the normal display requirements of the second display area AA2, and the process preparation difficulty of the first data connection line segment 222 is reduced, thereby improving the use space of the pixel circuit 100 and ensuring the yield of the display panel 10.

[0130] FIG. 65 is a schematic view of a fifth part of FIG. 61 in the related art, FIG. 66 is a schematic view of a sixth part of FIG. 62 in the related art, and FIG. 67 is a schematic view of a seventh part of FIG. 63 in the related art. In the related art, in the film layer structure of the pixel circuit 100 shown in FIG. 67, in the region corresponding to the arrangement of two pixel circuits 100 arranged continuously along the second direction X2, two first data connection line segments 222 are arranged. Alternatively, it can be understood that the number of data signal lines 210 and the number of first data connection line segments 222 are arranged one-to-one, that is, the number of first data connection line segments 222 is not reduced or redundant compared to the number of data signal lines 210. By comparing FIG. 63 and FIG. 67, in the display panel 10 provided by the embodiment of the present application, the number of first data connection line segments 222 arranged in the region corresponding to the arrangement of the pixel circuit 100 can be less than the number of data signal lines 210 arranged. By reducing the number of first data connection line segments 222, the process difficulty of the data auxiliary line 221 can be simplified, thereby ensuring the use space of the pixel circuit 100, and thus ensuring the overall display effect of the display panel 10.

[0131] In the region corresponding to the arrangement of n pixel circuits 100 arranged continuously along the second direction X2, the data signal line 210 and the first data connection line segment 222 can be arranged in the same layer. Referring to FIG. 7, FIG. 13, FIG. 17, FIG. 23, FIG. 25, FIG. 31, FIG. 34, FIG. 40, FIG. 44, FIG. 50, FIG. 55, and FIG. 63, the data signal line 210 and the first data connection line segment 222 are arranged in the same layer, which can ensure the thin type arrangement of the display panel 10. For example, referring to FIG. 7, FIG. 13, FIG. 17, FIG. 23, FIG. 25, FIG. 31, FIG. 34, FIG. 40, FIG. 44, and FIG. 50, the data signal line 210 and the first data connection line segment 222 are located in the second source-drain electrode layer 4100, and referring to FIG. 55 and FIG. 63, the data signal line 210 and the first data connection line segment 222 are located in the second source-drain electrode layer 5140. The film layer arrangement position of the data signal line 210 and the first data connection line segment 222 can also be adaptively adjusted according to different display panels 10.

[0132] In summary, the display panel provided in the embodiments of the present application can have different numbers of first data connection line segments in the region corresponding to n pixel circuits arranged in the second direction, that is, m first data connection line segments are arranged in the region corresponding to n pixel circuits arranged in the second direction, where n≠m, for example, n>m or n<m. The number of first data connection line segments is diverse, thereby embodying a flexible arrangement of auxiliary lines in the display panel. The arrangement of first data connection line segments can be adjusted in diversity according to different requirements of the display panel, thereby reducing yield loss, reducing the process preparation cost of the display panel, or improving the overall display effect of the display panel.

[0133] FIG. 68 is a partial structure diagram of a first display panel provided in the embodiments of the present application, and FIG. 69 is a partial structure diagram of a second display panel provided in the embodiments of the present application. As shown in FIGS. 68 and 69, n

[0134] The display panel 10 includes a plurality of first pixel circuit groups 100A and a plurality of first data signal line groups 210A in the first display area AA1 and the second display area AA2. The plurality of first pixel circuit groups 100A are arranged along the second direction X2, and the plurality of first data signal line groups 210A are arranged along the second direction X2. The first pixel circuit group 100A includes a plurality of pixel circuits 100 arranged adjacent to each other along the second direction X2, that is, a plurality of adjacent pixel circuit groups 100 arranged along the second direction X2 form the first pixel circuit group 100A. The first data signal line group 210A includes a plurality of data signal lines 210 arranged adjacent to each other along the second direction X2, that is, a plurality of adjacent data signal line groups 210 arranged along the second direction X2 form the first data signal line group 210A. It should be noted that in the first data signal line group 210A, the plurality of data signal lines 210 are arranged adjacent to each other, which can be understood as that there is no additional data signal line 210 between the adjacent data signal lines 210, and there can be other signal lines 200, for example, a data auxiliary line 221 exists between the adjacent data signal lines 210 arranged along the second direction X2. The weight and number of the signal lines 200 that can exist between the adjacent data signal lines 210 are not limited in the embodiments of the present application.

[0135] The plurality of pixel circuits 100 arranged along the first direction X1 are electrically connected to the same data signal line 210. Correspondingly, in the first pixel circuit group 100A and the first data signal line group 210A, the data signal line 210 in the same first data signal line group 210A is electrically connected to the pixel circuit 100 in the same first pixel circuit group 100A. For example, as shown in region c1 in FIG. 68, the region c1 includes one first pixel circuit group 100A, and the first pixel circuit group 100A shown in the region c1 includes two pixel circuits 100 arranged along the second direction X2. Correspondingly, the region c1 includes one first data signal line group 210A, and the first data signal line group 210A shown in the region c1 includes two data signal lines 210 arranged along the second direction X2, that is, along the second direction X2, the number of data signal lines 210 arranged is consistent with the number of pixel circuits 100 arranged, which can ensure that the plurality of pixel circuits 100 arranged along the first direction X1 are electrically connected to the same data signal line 210.

[0136] The first display area AA1 further includes a plurality of first data connection line segment groups 222A arranged along the second direction X2. The first data connection line segment groups 222A include a plurality of first data connection line segments 222. For the plurality of first data connection line segments 222 in the first data connection line segment groups 222A, the first data connection line segments 222 are located within the defined range of the n data signal lines 210 in the same first data signal line group 210A. It can be understood that the first data signal line group 210A is not only located in the second display area AA2 but also in the first display area AA1, and the first display area AA1 further includes the first data connection line segment groups 222A. The first data connection line segment groups 222A are located in an area that overlaps with the location of the first data signal line group 210A, and the plurality of first data connection line segments 222 in the first data connection line segment groups 222A are located within the defined range of the data signal lines 210 in the first data signal line group 210A that overlaps with the first data connection line segment groups 222A. For example, referring to the area c2 shown in FIG. 68, the first pixel circuit group 100A in the area c2 includes two pixel circuits 100 arranged along the second direction X2, and the first data signal line group 210A in the area c2 includes two data signal lines 210 arranged adjacent to each other along the second direction X2. For the plurality of first data connection line segments 222 in the first data connection line segment groups 222A in the area c2, the first data connection line segments 222 are located within the defined range of the two data signal lines 210.

[0137] Referring to FIGS. 68 and 69, the first pixel circuit group 100A includes two pixel circuits 100 arranged along the second direction X2, and the first data signal line group 210A includes two data signal lines 210 arranged adjacent to each other along the second direction X2, which is an example with n being 2. Referring to FIGS. 68 and 69, the first data connection line segment groups 222A include four first data connection line segments 222, which is an example with m being 4; that is, n < m.

[0138] For the first data connection line segment 222 in the same first data connection line segment group 222A and the data signal line 210 in the second display area AA2, since the number of the first data connection line segment 222 in the first data connection line segment group 222A is greater than the number of the data signal line 210 in the first data signal line group 210A, the first data connection line segment 222 in one first data connection line segment group 222A is electrically connected with the data signal lines 210 in at least two first data signal line groups 210A which are arranged adjacently in the second direction X2. For example, referring to FIG. 68, the first data connection line segment 222 in one first data connection line segment group 222A is electrically connected with the data signal lines 210 in two first data signal line groups 210A which are arranged adjacently in the second direction X2; referring to FIG. 69, the first data connection line segment 222 in one first data connection line segment group 222A is electrically connected with the data signal lines 210 in three first data signal line groups 210A which are arranged adjacently in the second direction X2.

[0139] The first data connection line segment 222 in the first data connection line segment group 222A and the data signal line 210 in the first data signal line group 210A can be arranged in the same layer, i.e., the first data connection line segment 222 and the data signal line 210 are arranged in the same film layer. For example, referring to FIGS. 7-14 and 34-41, e.g., referring to FIGS. 13 and 40, the first data connection line segment 222 and the data signal line 210 are arranged in the same film layer. The first data connection line segment 222 and the data signal line 210 can also be arranged in different film layers. The film layer arrangement position of the data signal line 210 and the first data connection line segment 222 can also be adjusted according to different display panels 10.

[0140] FIG. 70 is a partial structure diagram of a third display panel according to an embodiment of the present application. Referring to FIGS. 68-70, the first data connection line segment 222 in the same first data connection line segment group 222A is electrically connected with the data signal lines 210 in x first data signal line groups 210A which are arranged adjacently in the second direction X2; wherein, x is an integer.

[0141] Since the number of first data connection line segments 222 in the first data connection line segment group 222A is greater than the number of data signal lines 210 in the first data signal line group 210A, the data signal lines 210 in the second display area AA2 need to be electrically connected with the first data connection line segments 222, so the first data connection line segments 222 in one first data connection line segment group 222A need to be electrically connected with the data signal lines 210 in multiple first data signal line groups 210A arranged adjacently in the second direction X2, i.e. the first data connection line segments 222 in the same first data connection line segment group 222A are electrically connected with x data signal lines 210 in x first data signal line groups 210A arranged adjacently in the second direction X2.

[0142] The value of x is adjusted according to the number of first data connection line segments 222 in the first data connection line segment group 222A and the number of data signal lines 210 in the first data signal line group 210A. For example, if the first data connection line segment group 222A includes m first data connection line segments 222 and the first data signal line group 210A includes n data signal lines 210 arranged adjacently in the second direction X2, then the following equation is satisfied: and x is an integer, wherein, It can be understood that the ratio of m to n is rounded up.

[0143] For example, as shown in FIGS. 68-70, if the first data connection line segment group 222A includes four first data connection line segments 222 and the first data signal line group 210A includes two data signal lines 210 arranged adjacently in the second direction X2, then 1≤x≤3. As shown in FIG. 68, an example is shown in which the first data connection line segments 222 in one first data connection line segment group 222A are electrically connected with two data signal lines 210 in two first data signal line groups 210A arranged adjacently in the second direction X2; as shown in FIG. 69, an example is shown in which the first data connection line segments 222 in one first data connection line segment group 222A are electrically connected with three data signal lines 210 in three first data signal line groups 210A arranged adjacently in the second direction X2; and as shown in FIG. 70, an example is shown in which the first data connection line segments 222 in one first data connection line segment group 222A are electrically connected with four data signal lines 210 in four first data signal line groups 210A arranged adjacently in the second direction X2.

[0144] Figure 71 is a partial structure diagram of a fourth display panel according to an embodiment of the present application. Referring to Figure 71, n = 2 and m ≥ 3. The first data signal line group 210A includes a first data signal line 211 and a second data signal line 212 arranged along the second direction X2. The data auxiliary line 221 further includes a second data connection line segment 223 extending along the second direction X2. In a second display area AA2, the second display area AA2 includes A first data signal line groups 210A along a direction from the first display area AAl to the second display area AA2. Along a direction from the display area AA to the fan-out area Al, 2*A second data connection line segments 223 are arranged in sequence. Along a direction from the first display area AAl to the second display area AA2, the first display area AAl includes C first data connection line segment groups 222A. A ≥ 1 and is an integer, 1 ≤ C ≤ A, and C is an integer. The first data signal line 211(a) in the a-th first data signal line group 210A(a) of the second display area AA2 is electrically connected to the b-th second data connection line segment 223(b), and the b-th second data connection line segment 223(b) is electrically connected to the i-th first data connection line segment 222(i) in the c-th first data connection line segment group 222A(c) of the first display area AAl. Here, a, b, c, and i are positive integers, and a ≤ A, b ≤ 2*A-1, c ≤ C, and i ≤ m-1. The second data signal line 212(a) in the a-th first data signal line group 210A(a) of the second display area AA2 is electrically connected to the (b+1)-th second data connection line segment 223(b+1), and the (b+1)-th second data connection line segment 223(b+1) is electrically connected to the (i+1)-th first data connection line segment 222(i+1) in the c-th first data connection line segment group 222A(c) of the first display area AAl.

[0145] The first data signal line group 210A includes two data signal lines 210 arranged adjacent along the second direction X2, and the first data connection line segment group 222A includes m first data connection line segments 222, where m ≥ 3, i.e., the m first data connection line segments 222 are located within an area defined by the two data signal lines 210. The m first data connection line segments 222 can be arranged in the same layer as the data signal lines 210, or can be arranged in a different layer from the data signal lines 210.

[0146] Referring to Figure 71, the first data connection line segment group 222A can include four first data connection line segments 222, and the first data signal line group 210A can include two data signal lines 210, i.e., the four first data connection line segments 222 are located within an area defined by the two data signal lines 210 in the area where the first data connection line segments 222 are arranged.

[0147] The first data signal line group 210A includes two data signal lines 210, for example, includes a first alpha data signal line 211 and a first beta data signal line 212 arranged along the second direction X2. The data auxiliary line 221 also includes a second data connection line segment 223 extending along the second direction X2. The data signal lines 210 in the second display area AA2 are electrically connected to the fan-out wires through the second data connection line segment 223 and the first data connection line segment 222, so that the data signal lines 210 in the second display area AA2 can obtain data signals.

[0148] The electrical connection between the data signal lines 210 in the second display area AA2 and the first data connection line segment 222 in the first display area AA1 is implemented as follows:

[0149] In the first display area AA2, along the direction from the first display area AA1 to the second display area AA2, the second display area AA2 includes A first data signal line groups 210A (one first data signal line group 210A is shown in FIG. 71, i.e., A is 2). Since each first data signal line group 210A includes two data signal lines 210 (for example, the first data signal line group 210A includes two data signal lines 210 in FIG. 71), there are 2*A data signal lines 210 that need to be electrically connected to the first data connection line segment 222. The first data connection line segment 222 and the data signal lines 210 both extend along the first direction X1, so the first data connection line segment 222 and the data signal lines 210 need to be electrically connected through the second data connection line segment 223 extending along the second direction X2. Therefore, the number of second data connection line segments 223 should be 2*A, and along the direction from the display area AA to the fan-out area (the fan-out area is not shown in FIG. 71, and the setting position of the fan-out area can be referred to FIG. 2 and FIG. 3), the 2*A second data connection line segments 223 are arranged in sequence.

[0150] Along the direction from the first display area AA1 to the second display area AA2, the first display area AA1 includes C first data connection line segment groups 222A (one first data connection line segment group 222A is shown in FIG. 71, i.e., C is 1), and the first data connection line segment group 222A includes m first data connection line segments 222 (for example, the first data connection line segment group 222A includes four first data connection line segments 222 in FIG. 71), and in the case of m≥3, the number of first data connection line segment groups 222A can be less than or equal to the number of first data signal line groups 210A, i.e., 1≤C≤A.

[0151] For example, referring to FIG. 71, taking A as 2 for example, i.e. two first data signal line groups 210A in the second display area AA2, and each first data signal line group 210A includes two data signal lines 210 (first alpha data signal line 211 and first beta data signal line 212), i.e. the second display area AA2 includes four data signal lines 210. The corresponding display panel 10 should include four second data connection line segments 223. The four data signal lines 210 in the second display area AA2 are respectively electrically connected to the four first data connection line segments 222 through the four second data connection line segments 223. m can be equal to 4, i.e. taking C as 1 for example, the four data signal lines 210 are electrically connected to the four first data connection lines 222 in one first data connection line group 222A through the corresponding second data connection line segments 223. That is, the two first data signal line groups 210A in the second display area AA2 can be electrically connected to the multiple first data connection line segments 222 in one first data signal line group 222A in the first display area AA1 through the second data connection line segments 223. The actual film layer diagram corresponding to the above signal line 200 setting quantity can be referred to FIGS. 7-14 and 34-41, and the display panel 10 is taken as an example in which four first data connection line segments 222 are arranged between two data signal lines 210.

[0152] Referring to FIG. 71, the first alpha data signal line 211(a) in the a-th first data signal line group 210A(a) in the second display area AA2 is electrically connected to the b-th second data connection line segment 223(b), and the first beta data signal line 212(a) in the a-th first data signal line group 210A(a) in the second display area AA2 is electrically connected to the (b+1)-th second data connection line segment 223(b+1). That is, the data signal lines 210 in the second display area AA2 are electrically connected to the corresponding second data connection line segments 223.

[0153] The bth second data connection line segment 223(b) is electrically connected with the ith first data connection line segment 222(i) in the cth first data connection line segment group 222A(c) of the first display area AA1, and the (b+1)th second data connection line segment 223(b+1) is electrically connected with the (i+1)th first data connection line segment 222(i+1) in the cth first data connection line segment group 222A(c) of the first display area AA1. That is, the data signal line 210 in the second display area AA2 is electrically connected with the first data signal line segment 222 through the second data signal line segment 223. And as shown in FIG. 71, the first alpha data signal line 211(a) and the first beta data signal line 212(a) in the ath first data signal line group 210A(a) are respectively electrically connected with the ith first data connection line segment 222(i) and the (i+1)th first data connection line segment 222(i+1) in the same first data connection line segment group 222A. In other words, when the number of first data connection line segments 222 in the first data connection line segment group 222A is greater than the number of first data signal lines 210 in the first data signal line group 210A, the data signal lines 210 in the same first data signal line group 210A can be electrically connected with different first data connection line segments 222 in the same first data connection line segment group 222A.

[0154] The second display area AA2 includes A first data signal line groups 210A, so the ath first data signal line group 210A(a) in the display panel 10 is also located in the second display area AA2, so a≤A; similarly, c≤C. The second display area AA2 includes A first data signal line groups 210A, and in the case that the first data signal line group 210A includes the first alpha data signal line 211 and the first beta data signal line 212, that is, the first data signal line group 210A includes 2 data signal lines 210, so the second display area AA2 includes a total of 2*A data signal lines 210, and the bth second data connection line segment 223(b) is b≤2*A-1, and similarly, i≤m-1.

[0155] Figure 72 is a partial structure schematic view of a fifth display panel according to an embodiment of the present application. Referring to Figure 72, n = 2 and m ≥ 3. The first data signal line group 210A includes the first data signal line 211 and the second data signal line 212 arranged along the second direction X2. The data auxiliary line 221 further includes the second data connection line segment 223 extending along the second direction X2. In a second display area AA2, along a direction from the first display area AAl to the second display area AA2, the second display area AA2 includes A first data signal line groups 210A. Along a direction from the display area AA to the fan-out area Al, 2*A second data connection line segments 223 are arranged in sequence. Along a direction from the first display area AAl to the second display area AA2, the first display area AAl includes C first data connection line segment groups 222A. A is an integer greater than or equal to 1, and C is an integer greater than or equal to 1 and less than or equal to A. The first data signal line 211(a) in the athfirst data signal line group 210A(a) of the second display area AA2 is electrically connected to the bthsecond data connection line segment 223(b), and the bthsecond data connection line segment 223(b) is electrically connected to the mthfirst data connection line segment 222(m) in the cthfirst data connection line segment group 222A(c) of the first display area AAl. Here, a, b, and c are positive integers, a ≤ A, b ≤ 2*A-1, and c ≤ C. The second data signal line 212(a) in the athfirst data signal line group 210A(a) of the second display area AA2 is electrically connected to the (b+1)thsecond data connection line segment 223(b+1), and the (b+1)thsecond data connection line segment 223(b+1) is electrically connected to the first first data connection line segment 222(1) in the (c+1)thfirst data connection line segment group 222A(c+1) of the first display area AAl.

[0156] There are various ways to electrically connect the data signal line 210 in the second display area AA2 to the first data connection line segment 222 in the first display area AAl. In the first display area AAl, along a direction from the first display area AAl to the second display area AA2, the second display area AA2 includes A first data signal line groups 210A. Since each first data signal line group 210A includes two data signal lines 210, 2*A data signal lines 210 need to be electrically connected to the first data connection line segment 222. Since the first data connection line segment 222 and the data signal line 210 both extend along the first direction Xl, the first data connection line segment 222 and the data signal line 210 need to be electrically connected through the second data connection line segment 223 extending along the second direction X2. Therefore, the number of second data connection line segments 223 should be 2*A, and along a direction from the display area AA to the fan-out area (not shown in Figure 72, and the position of the fan-out area can be referred to as shown in Figure 2 and Figure 3), 2*A second data connection line segments 223 are arranged in sequence.

[0157] In the direction from the first display area AA1 to the second display area AA2, the first display area AA1 includes C first data connection line segment groups 222A, each of which includes m first data connection line segments 222, and in the case of m≥3, the number of first data connection line segment groups 222A can be less than or equal to the number of first data signal line groups 210A, i.e. 1≤C≤A.

[0158] For example, referring to FIG. 72, an example is given with A being 1, i.e. the first data signal line group 210A shown in the second display area AA2, and the first data signal line group 210A includes two data signal lines 210 (first alpha data signal line 211 and first beta data signal line 212). The corresponding display panel 10 should include two second data connection line segments 223. The two data signal lines 210 in the second display area AA2 are respectively electrically connected to the two first data connection line segments 222 through the two second data connection line segments 223. m can be equal to 4, i.e. an example is given with C being 1, i.e. the two data signal lines 210 in the same first data signal line group 210A can be electrically connected to different first data connection line segments 222 in one first data connection line segment group 222A in the first display area AA1, as shown in FIG. 71, or can be electrically connected to the first data connection line segments 222 in two first data connection line segment groups 222A in the first display area AA1, as shown in FIG. 72. The actual film layer diagram corresponding to the number of signal lines 200 described above can be referred to FIGS. 7-14 and 34-41, and an example is given with the display panel 10 having four first data connection line segments 222 arranged between the two data signal lines 210.

[0159] Referring to FIG. 72, the first alpha data signal line 211(a) in the a-th first data signal line group 210A(a) in the second display area AA2 is electrically connected to the b-th second data connection line segment 223(b), and the first beta data signal line 212(a) in the a-th first data signal line group 210A(a) in the second display area AA2 is electrically connected to the (b+1)-th second data connection line segment 223(b+1). That is, the data signal lines 210 in the second display area AA2 are electrically connected to the corresponding second data connection line segments 223.

[0160] The bth second data connection line segment 223(b) is electrically connected with the mth first data connection line segment 222(m) in the cth first data connection line segment group 222A(c) of the first display area AA1. There are m first data connection line segments 222 in the first data connection line segment group 222A(c), so the mth first data connection line segment 222(m) can be understood as the last first data connection line segment 222 in the first display area AA1 pointing to the second display area AA2.

[0161] The (b+1)th second data connection line segment 223(b+1) is electrically connected with the 1st first data connection line segment 2221 in the (c+1)th first data connection line segment group 222A(c+1) of the first display area AA1. The first data connection line segment group 222A(c+1) is in a layer closer to the second display area AA2 than the first data connection line segment group 222A(c), and all the first data connection line segments 222 in the first data connection line segment group 222A(c) have been electrically connected with the data signal lines 210, so the first data signal line 212(a) should be electrically connected with the 1st first data connection line segment 2221 in the first data connection line segment group 222A(c+1). That is, different data signal lines 210 in the first data signal line group 210A are connected to different first data connection line segments 222 in different first data connection line segment groups 222A in the first display area AA1 in the second display area AA2.

[0162] And as shown in FIG. 72, the first data signal line 211(a) in the ath first data signal line group 210A(a) and the first data signal line 212(a) are respectively electrically connected with the mth first data connection line segment 222(m) in one first data connection line segment group 222A and the 1st first data connection line segment 222(1) in another first data connection line segment group 222A. In other words, the data signal lines 210 in the same first data signal line group 210A can be electrically connected with different first data connection line segments 222 in different first data connection line segment groups 222A.

[0163] FIG. 73 is a partial structure diagram of a sixth display panel according to an embodiment of the present application, and FIG. 74 is a partial structure diagram of a seventh display panel according to an embodiment of the present application. Referring to FIGS. 73 and 74, n > m; along the second direction X2, the first display area AA1 and the second display area AA2 each include a plurality of second pixel circuit groups 100B and a plurality of second data signal line groups 210B, and the plurality of second data signal line groups 210B are arranged along the second direction X2; the second pixel circuit group 100B includes n pixel circuits 100 arranged adjacent along the second direction X2; the second data signal line group 210B includes n data signal lines 210 arranged adjacent along the second direction X2, and the data signal lines 210 in the same second data signal line group 210B are electrically connected to the pixel circuits 100 in the same second pixel circuit group 100B; the first display area AA1 further includes a plurality of second data connection line segment groups 222B, the plurality of second data connection line segment groups 222B are arranged along the second direction X2, and the second data connection line segment group 222B includes m first data connection line segments 222; the data signal line 210 in the same second data signal line group 210B is electrically connected to the first data connection line segments 222 in at least two second data connection line segment groups 222B arranged adjacent along the second direction X2.

[0164] The display panel 10 includes a plurality of second pixel circuit groups 100B and a plurality of second data signal line groups 210B in the first display area AA1 and the second display area AA2, the plurality of second pixel circuit groups 100B are arranged along the second direction X2, and the plurality of second data signal line groups 210B are arranged along the second direction X2. The second pixel circuit group 100A includes a plurality of pixel circuits 100 arranged adjacent along the second direction X2, that is, a plurality of adjacent pixel circuit groups 100 arranged along the second direction X2 form the second pixel circuit group 100B. The second data signal line group 210B includes a plurality of data signal lines 210 arranged adjacent along the second direction X2, that is, a plurality of adjacent data signal line groups 210 arranged along the second direction X2 form the second data signal line group 210B. It should be noted that in the second data signal line group 210B, the plurality of data signal lines 210 are arranged adjacent, which can be understood as that there is no additional data signal line 210 between the adjacent data signal lines 210, and there can be other signal lines 200, for example, there is a data auxiliary line 221 between the adjacent data signal lines 210 arranged along the second direction X2, and the weight and number of the signal lines 200 that can exist between the adjacent data signal lines 210 are not limited in the embodiments of the present application.

[0165] The plurality of pixel circuits 100 arranged along the first direction X1 are electrically connected with the same data signal line 210. Correspondingly, in the second pixel circuit group 100B and the second data signal line group 210B, the data signal lines 210 in the same second data signal line group 210B are electrically connected with the pixel circuits 100 in the same second pixel circuit group 100B. For example, referring to the area c3 shown in FIG. 73, the area c3 includes one second pixel circuit group 100B, and the second pixel circuit group 100B shown in the area c3 includes two pixel circuits 100 arranged along the second direction X2. Correspondingly, the area c3 includes one second data signal line group 210B, and the second data signal line group 210B shown in the area c3 includes two data signal lines 210 arranged along the second direction X2. That is, along the second direction X2, the number of data signal lines 210 arranged is consistent with the number of pixel circuits 100 arranged, which can ensure that the plurality of pixel circuits 100 arranged along the first direction X1 are electrically connected with the same data signal line 210.

[0166] The first display area AA1 further includes a plurality of second data connection line segment groups 222B arranged along the second direction X2. The second data connection line segment group 222B includes a plurality of first data connection line segments 222. For the plurality of first data connection line segments 222 in the second data connection line segment group 222B, the first data connection line segments 222 are located within the defined range of the n data signal lines 210 in the same second data signal line group 210B. It can be understood that the second data signal line group 210B is not only located in the second display area AA2 but also in the first display area AA1, and the first display area AA1 further includes the second data connection line segment group 222B. The second data connection line segment group 222B is located in an area that overlaps with the second data signal line group 210B, and the plurality of first data connection line segments 222 in the second data connection line segment group 222B are located within the defined range of the data signal lines 210 in the second data signal line group 210B that overlaps with the second data connection line segment group 222B. For example, referring to the area c4 shown in FIG. 73, the second pixel circuit group 100B included in the area c4 includes two pixel circuits 100 arranged along the second direction X2, and the second data signal line group 210B included in the area c4 includes two data signal lines 210 arranged along the second direction X2. For the first data connection line segment 222 in the second data connection line segment group 222B included in the area c4, the first data connection line segment 222 is located within the defined range of the two data signal lines 210.

[0167] Referring to FIG. 73, the second pixel circuit group 100B includes two pixel circuits 100 arranged along the second direction X2, and the second data signal line group 210B includes two data signal lines 210 arranged adjacent along the second direction X2, for example, with n being 2. Referring to FIG. 73, the second data connection line segment group 222B includes one first data connection line segment 222, for example, with m being 1; that is, n > m. Alternatively, referring to FIG. 74, the second pixel circuit group 100B includes six pixel circuits 100 arranged along the second direction X2, and the second data signal line group 210B includes six data signal lines 210 arranged adjacent along the second direction X2, for example, with n being 6. Referring to FIG. 74, the second data connection line segment group 222B includes two first data connection line segments 222, for example, with m being 2, and again, n > m.

[0168] For the electrical connection between the first data connection line segment 222 in the same second data connection line segment group 222B and the data signal line 210 in the second display area AA2, since the number of the first data connection line segments 222 in the second data connection line segment group 222B is less than the number of the data signal lines 210 in the second data signal line group 210B, one data signal line 210 in the second data signal line group 210B in the second display area AA2 is electrically connected to at least two first data connection line segments 222 in the second data connection line segment groups 222B arranged adjacent along the second direction X2. For example, referring to FIG. 73, one data signal line 210 in the second data signal line group 210B in the second display area AA2 is electrically connected to two first data connection line segments 222 in the second data connection line segment groups 222B arranged adjacent along the second direction X2; and referring to FIG. 74, one data signal line 210 in the second data signal line group 210B in the second display area AA2 is electrically connected to three first data connection line segments 222 in the second data connection line segment groups 222B arranged adjacent along the second direction X2.

[0169] The first data connection line segment 222 of the second data connection line segment group 222B and the data signal line 210 in the second data signal line group 210B can be arranged in the same layer, that is, the first data connection line segment 222 and the data signal line 210 are arranged in the same film layer. For example, as shown in FIGS. 17-24, 25-32, 44-51, and 55-64, the first data connection line segment 222 and the data signal line 210 are arranged in the same film layer. The first data connection line segment 222 and the data signal line 210 can also be arranged in different film layers. The film layer arrangement positions of the data signal line 210 and the first data connection line segment 222 can also be adjusted according to different display panels 10.

[0170] FIG. 75 is a partial structure diagram of an eighth display panel according to an embodiment of the present application, and FIG. 76 is a partial structure diagram of a ninth display panel according to an embodiment of the present application. As shown in FIGS. 73-76, the data signal line 210 in the same second data signal line group 210B is electrically connected to the first data connection line segment 222 in the y second data connection line segment groups 222B arranged adjacent in the second direction X2. and y is an integer.

[0171] Since the number of first data connection line segments 222 in the second data connection line segment group 222B is less than the number of data signal lines 210 in the second data signal line group 210B, the data signal line 210 in the second display area AA2 needs to be electrically connected to the first data connection line segment 222. Therefore, the data signal line 210 in one second data signal line group 210B is electrically connected to the first data connection line segment 222 in the plurality of second data connection line segment groups 222B arranged adjacent in the second direction X2, that is, the data signal line 210 in the same second data signal line group 210B is electrically connected to the first data connection line segment 222 in the y second data connection line segment groups 222B arranged adjacent in the second direction X2.

[0172] The value of y is adjusted according to the number of first data connection line segments 222 in the second data connection line segment group 222B and the number of data signal lines 210 in the second data signal line group 210B. For example, when the second data connection line segment group 222B includes m first data connection line segments 222 and the second data signal line group 210B includes n data signal lines 210 arranged adjacent in the second direction X2, the following conditions are met: and y is an integer, wherein, It can be understood that the ratio of n to m is rounded up.

[0173] For example, referring to FIGS. 73-76, the number of first data connection line segments 222 included in a second data connection line segment group 222B is less than the number of data signal lines 210 included in a second data signal line group 210B that are arranged adjacent to each other in the second direction X2. Referring to FIG. 73, for example, one second data connection line segment group 222B includes one first data connection line segment 222, and one second data signal line group 210B includes two data signal lines 210. In this case, the two data signal lines 210 in the second data signal line group 210B in the second display area AA2 are electrically connected to the first data connection line segment 222 in the two second data connection line segment groups 222B arranged adjacent to each other in the second direction X2, i.e., y = 2, which satisfies 2≤y≤3. Referring to FIG. 74, for example, one second data connection line segment group 222B includes two first data connection line segments 222, and one second data signal line group 210B includes six data signal lines 210. In this case, the six data signal lines 210 in the second data signal line group 210B in the second display area AA2 are electrically connected to the first data connection line segments 222 in the three second data connection line segment groups 222B arranged adjacent to each other in the second direction X2, i.e., y = 3, which satisfies 3≤y≤4. Referring to FIG. 75, for example, one second data connection line segment group 222B includes two first data connection line segments 222, and one second data signal line group 210B includes six data signal lines 210. In this case, the six data signal lines 210 in the second data signal line group 210B in the second display area AA2 are electrically connected to the first data connection line segments 222 in the four second data connection line segment groups 222B arranged adjacent to each other in the second direction X2, i.e., y = 4, which satisfies 3≤y≤4. Referring to FIG. 76 (in which the electrical connection relationship between the first data connection line segment 222 and the data signal line 210 is shown clearly, and the pixel circuit 100 is not shown), for example, one second data connection line segment group 222B includes two first data connection line segments 222, and one second data signal line group 210B includes seven data signal lines 210. In this case, the seven data signal lines 210 in the second data signal line group 210B in the second display area AA2 are electrically connected to the first data connection line segments 222 in the four second data connection line segment groups 222B arranged adjacent to each other in the second direction X2, i.e., y = 4, which satisfies 4≤y≤5. The number of first data connection line segments 222 included in the second data connection line segment group 222B can be various, and the number of data signal lines 210 included in the second data signal line group 210B can also be various, and all embodiments are not shown herein.

[0174] FIG. 77 is a partial structural schematic view of a tenth display panel provided by an embodiment of the present application. Referring to FIG. 77, the data auxiliary line 221 further includes a second data connection line segment 223 extending along the second direction X2; in a second display area AA2, along a direction in which the first display area AA1 points to the second display area AA2, the second display area AA1 includes D second data signal line groups 210B; along a direction in which the display area AA points to the fan-out area A1, D*n second data connection line segments 223 are arranged in sequence; along the direction in which the first display area AA1 points to the second display area AA2, the first display area AA1 includes F second data connection line segment groups 222B; D is an integer greater than or equal to 1, and F is an integer, and the jth data signal line 210(j) in the dth second data signal line group 210B(d) of the second display area AA2 is electrically connected with the e th second data connection line segment 223(e), the e th second data connection line segment 223(e) is electrically connected with the kth first data connection line segment 222(k) in the fth second data connection line segment group 222B(f) of the first display area AA1; the j+hth data signal line 210(j+h) in the dth second data signal line group 210B(d) of the second display area AA2 is electrically connected with the e+hth second data connection line segment 223(e+h), the e+hth second data connection line segment 223(e+h) is electrically connected with the k+hth first data connection line segment 222(k+h) in the fth second data connection line segment group 222B(f) of the first display area AA1; where d, e, f, j, k and h are positive integers, and d≤D, f≤F, j+h≤n, and k+h≤m.

[0175] The second data signal line group 210B includes n data signal lines 210 arranged adjacent along the second direction X2, and the second data connection line segment group 222B includes m first data connection line segments 222, where n>m. The m first data connection line segments 222 can be arranged in the same layer as the data signal lines 210, or can be arranged in a different layer from the data signal lines 210.

[0176] Referring to FIG. 77, the second data connection line segment group 222B can include two first data connection line segments 222, and the second data signal line group 210B can include six data signal lines 210, i.e., in the region in which the first data connection line segments 222 are arranged, the two first data connection line segments 222 are located within the region defined by the six data signal lines 210. The values of m and n can be adaptively adjusted according to different display panels 10, which are not limited by the embodiments of the present application.

[0177] The data auxiliary line 221 further comprises a second data connection line segment 223 extending along the second direction X2. The data signal lines 210 in the second display area AA2 are electrically connected with the fan-out wires through the second data connection line segment 223 and the first data connection line segment 222, so that the data signal lines 210 in the second display area AA2 can obtain data signals.

[0178] The electrical connection between the data signal lines 210 in the second display area AA2 and the first data connection line segment 222 in the first display area AA1 is implemented as follows:

[0179] In the first display area AA2, along the direction from the first display area AA1 to the second display area AA2, the second display area AA2 comprises D second data signal line groups 210B (one second data signal line group 210B is shown in FIG. 77, i.e., D is 1). Since each second data signal line group 210B comprises n data signal lines 210 (6 data signal lines 210 in one second data signal line group 210B are shown in FIG. 7 as an example), n*D data signal lines 210 need to be electrically connected with the first data connection line segment 222. The first data connection line segment 222 and the data signal lines 210 both extend along the first direction X1, so the first data connection line segment 222 and the data signal lines 210 need to be electrically connected through the second data connection line segment 223 extending along the second direction X2. Therefore, the number of the second data connection line segment 223 should be n*D, and along the direction from the display area AA to the fan-out area (the fan-out area is not shown in FIG. 77, and the setting position of the fan-out area can be referred to FIGS. 2 and 3), the n*D second data connection line segments 223 are arranged in sequence.

[0180] In the second data connection line segment group 222B, the number of the first data connection line segment 222 is less than the number of the data signal lines 210 in the second data signal line group 210B, so in order to meet the electrical connection relationship, D≥1, F≥2. For It can be understood that D is the number of the second data signal line group 210B, It can be understood that F is the number of the second data connection line segment 223. In order for each data signal line 210 in the second display area AA2 to be electrically connected with the corresponding first data connection line segment 222, the upper limit value of F should be related to the number of the data signal lines 210 and the first data connection line segment 222. The ratio of n to m is rounded up, i.e., In order to ensure that each data signal line 210 in the second display area AA2 is electrically connected to a corresponding first data connection line segment 222, the first data connection line segments 222 in the second data connection line segment group 222B are electrically connected to the first data signal lines 210 in the second display area AA2. In order to ensure that each data signal line 210 can obtain the data signal transmitted by the first data connection line segment 222, the first data connection line segments 222 in the second data connection line segment group 222B can be adjusted.

[0181] For example, referring to FIG. 77, the second display area AA2 is taken as an example, and the number of data signal lines 210 in each second data signal line group 210B is taken as D=1, i.e., one second data signal line group 210B in the second display area AA2 is shown in FIG. 77, and each second data signal line group 210B includes 6 data signal lines 210. The corresponding display panel 10 should include 6 second data connection line segments 223. The 6 data signal lines 210 in the second display area AA2 are electrically connected to the 6 first data connection line segments 222 through the 6 second data connection line segments 223, respectively. m can be equal to 2, i.e., F=3 is taken as an example, and the 6 data signal lines 210 are electrically connected to the 6 first data connection line segments 222 in the 3 second data connection line segment groups 222B through the corresponding second data connection line segments 223. That is, the second data signal line group 210B in the second display area AA2 can be electrically connected to the multiple first data connection line segments 222 in the 3 second data signal line segment groups 222B in the first display area AA1 through the second data connection line segments 223.

[0182] Referring to FIG. 77, the jth data signal line 210(j) in the dth second data signal line group 210B(d) in the second display area AA2 is electrically connected to the e th second data connection line segment 223(e), and the e+h th second data connection line segment 223(e+h) in the dth second data signal line group 210B(d) in the second display area AA2 is electrically connected to the e+h th second data connection line segment 223(e+h). That is, the data signal line 210 in the second display area AA2 is electrically connected to the corresponding second data connection line segment 223.

[0183] The e-th second data connection line segment 223(e) is electrically connected with the k-th first data connection line segment 222(k) in the f-th second data connection line segment group 222B(f) in the first display area AAl, and the e+h-th second data connection line segment 223(e+h) is electrically connected with the k+h-th first data connection line segment 222(k+h) in the f-th second data connection line segment group 222B(f) in the first display area AAl. That is, the data signal line 210 in the second display area AA2 is electrically connected with the first data signal line segment 222 through the second data signal line segment 223. The second display area AA2 includes D second data signal line groups 210B, and thus the d-th second data signal line group 210B(d) in the display panel 10 is also located in the second display area AA2, and thus d≤D; similarly, f≤F. And j+h≤n, that is, the j-th data signal line 210(j) and the j+h-th data signal line 210(j+h) are both located in the d-th second data signal line group 210B(d); k+h≤m, that is, the k-th first data connection line segment 222(k) and the k+h-th first data connection line segment 222(k+h) are both located in the f-th second data connection line segment group 222B(f).

[0184] As shown in FIG. 77, the j-th data signal line 210(j) and the j+h-th data signal line 210(j+h) in the d-th second data signal line group 210B(d) are electrically connected with the k-th first data connection line segment 222(k) and the k+h-th first data connection line segment 222(k+h) in the same second data connection line segment group 222B (the f-th second data connection line segment group 222B(f)).

[0185] FIG. 78 is a partial structure diagram of a tenth display panel according to an embodiment of the present application. As shown in FIG. 78, the data auxiliary line 221 further includes a second data connection line segment 223 extending along the second direction X2; in a second display area AA2, the first display area AAl includes D second data signal line groups 210B along a direction from the first display area AAl to the second display area AA2; along a direction from the display area AA to the fan-out area A1, D*n second data connection line segments 223 are arranged in sequence; along a direction from the first display area AAl to the second display area AA2, the first display area AAl includes F second data connection line segment groups 222B; D is an integer greater than or equal to 1, and F is an integer greater than or equal to 1, the j-th data signal line 210(j) in the d-th second data signal line group 210B(d) in the second display area AA2 is electrically connected with the e-th second data connection line segment 223(e), and the e-th second data connection line segment 223(e) is electrically connected with the k-th first data connection line segment 222(k) in the f-th second data connection line segment group 222B(f) in the first display area AAl;

[0186] The j+(m-k)th data signal line 210(j+(m-k)) in the dth second data signal line group 210B(d) of the second display area AA2 is electrically connected with the e+(m-k)th second data connection line segment 223(e+(m-k)), and the e+(m-k)th second data connection line segment 223(e+(m-k)) is electrically connected with the mth first data connection line segment 222(m) in the fth second data connection line segment group 222B(f) of the first display area AA1;

[0187] The j+hth data signal line 210(j+h) in the dth second data signal line group 210B(d) of the second display area AA2 is electrically connected with the e+hth second data connection line segment 223(e+h), and the e+hth second data connection line segment 223(e+h) is electrically connected with the mth first data connection line segment 222(m) in the fth second data connection line segment group 222B(f) of the first display area AA1; Wherein, d, e, f, j, k and h are positive integers, and d≤D, f≤F, j+h≤n, and k+h>m.

[0188] The second data signal line group 210B includes n data signal lines 210 arranged adjacent along the second direction X2, and the second data connection line segment group 222B includes m first data connection line segments 222, where n>m. The m first data connection line segments 222 can be arranged in the same layer as the data signal lines 210, or can be arranged in different layers from the data signal lines 210.

[0189] Referring to FIG. 78, the second data connection line segment group 222B can include three first data connection line segments 222, and the second data signal line group 210B includes seven data signal lines 210, i.e., in the arrangement region of the first data connection line segments 222, the three first data connection line segments 222 are located within the region defined by the seven data signal lines 210. The values of m and n can be adaptively adjusted according to different display panels 10, which are not limited in the embodiments of the present application. It should be noted that FIG. 78 clearly shows the electrical connection relationship between the first data connection line segments 222 and the data signal lines 210, and the pixel circuit 100 is not shown.

[0190] ​​​The data auxiliary line 221 further comprises a second data connection line segment 223 extending along the second direction X2. The data signal lines 210 in the second display area AA2 are electrically connected to the fan-out wires through the second data connection line segment 223 and the first data connection line segment 222, so that the data signal lines 210 in the second display area AA2 can obtain data signals.

[0191] The implementation of the electrical connection between the data signal lines 210 in the second display area AA2 and the first data connection line segment 222 in the first display area AA1 has diversity.

[0192] Referring to FIG. 78, in the first display area AA2, along the direction from the first display area AA1 to the second display area AA2, the second display area AA2 comprises D second data signal line groups 210B (only one is shown in FIG. 78), since each second data signal line group 210B comprises n data signal lines 210 (for example, 7 data signal lines 210 are shown in the second data signal line group 210B in FIG. 78), n*D data signal lines 210 need to be electrically connected to the first data connection line segment 222. The first data connection line segment 222 and the data signal lines 210 both extend along the first direction X1, so the first data connection line segment 222 and the data signal lines 210 need to be electrically connected through the second data connection line segment 223 extending along the second direction X2, therefore the number of the second data connection line segment 223 should be n*D, and along the direction from the display area AA to the fan-out area (not shown in FIG. 78, the position of the fan-out area can be referred to FIG. 2 and FIG. 3), the n*D second data connection line segments 223 are arranged in sequence.

[0193] For example, referring to FIG. 78, taking D as 1 for example, that is, one second data signal line group 210B is shown in the second display area AA2 in FIG. 78, and each second data signal line group 210B comprises 7 data signal lines 210. The corresponding display panel 10 should comprise 7 second data connection line segments 223. The 7 data signal lines 210 in the second display area AA2 are electrically connected to the 7 first data connection line segments 222 through the 7 second data connection line segments 223 respectively. m can be equal to 3, that is, taking F as 3 for example, the 7 data signal lines 210 are electrically connected to the 7 first data connection line segments 222 in the three second data connection line segment groups 222B through the corresponding second data connection line segments 223. That is, the second data signal line group 210B in the second display area AA2 can be electrically connected to part of the first data connection line segments 222 in the three second data signal line segment groups 222B in the first display area AA1 through the second data connection line segments 223.

[0194] Referring to FIG. 78, the jth data signal line 210(j) in the dth second data signal line group 210B(d) in the second display area AA2 is electrically connected to the e th second data connection line segment 223(e), that is, the data signal line 210 in the second display area AA2 is electrically connected to the corresponding second data connection line segment 223. The e th second data connection line segment 223(e) is electrically connected to the kth first data connection line segment 222(k) in the f th second data connection line segment group 222B(f), that is, the data signal line 210 in the second display area AA2 is electrically connected to the first data connection line segment 222 through the second data connection line segment 223. The second display area AA2 includes D second data signal line groups 210B, and therefore the dth second data signal line group 210B(d) in the display panel 10 is also located in the second display area AA2, so d≤D; similarly, f≤F.

[0195] In the dth second data signal line group 210B(d), the jth data signal line 210(j) has been electrically connected to the corresponding first data connection line segment 222, that is, the kth first data connection line segment 222(k) in the f th second data connection line segment group 222B(f). In the corresponding f th second data connection line segment group 222B(f), there are (m-k) first data connection line segments 222 left, and the corresponding (m-k) first data connection line segments 222 can each be electrically connected to the data signal line 210 in the dth second data signal line group 210B(d). The mth first data connection line segment 222(m) in the f th second data connection line segment group 222B(f) can be understood as the last first data connection line segment 222 in the f th second data connection line segment group 222B(f) in the direction pointing from the first display area AA1 to the second display area AA2. Then in the dth second data signal line group 210B(d), the j+(m-k)th data signal line 210(j+(m-k)) is electrically connected to the last first data connection line segment 222 in the f th second data connection line segment group 222B(f) through the e+(m-k)th second data connection line segment 223(e+(m-k)). In the dth second data signal line group 210B(d), the j+(m-k)th data signal line 210(j+(m-k)) has been electrically connected to the last first data connection line segment 222 in the f th second data connection line segment group 222B(f), and the next data signal line 210 will be electrically connected to the first data connection line segment 222 in another second data connection line segment group 222B. That is, in the dth second data signal line group 210B(d), there are different data signal lines 210 electrically connected to the first data connection line segments 222 in different second data connection line segment groups 222B.

[0196] The j+hth data signal line 210(j+h) in the dth second data signal line group 210B(d) is electrically connected with the e+hth second data connection line segment 223(e+h), where j+h≤n, i.e., the j+hth data signal line 210(j+h) is still in the dth second data signal line group 210B(d). The e+hth second data connection line segment 223(e+h) is electrically connected with the mth first data connection line segment 222(m) in the fth second data connection line segment group 222B(f) of the first display area AA1. the fth second data connection line segment group the mth first data connection line segment in the fth second data connection line segment group As described above, m-k represents the number of the fth group that is not electrically connected with the data signal line 210, and h-(m-k) represents the number of the first data connection line segment 222 that is needed in addition to the fth group, represents the number of complete second data connection line segment groups 222B that are needed in addition to the fth group. represents the serial number of the last second data connection line segment group 222B. represents the number of the first data connection line segment 222 provided in the fth second data connection line segment group 222B, represents the number of the first data connection line segment 222 provided in the last second data connection line segment group 222B to the data signal line 210 in the dth second data signal line group 210B(d).

[0197] In combination with FIG. 78, the j+(m-k)th data signal line 210(j+(m-k)) and the j+hth data signal line 210(j+h) exemplarily shown in the dth second data signal line group 210B(d) can be electrically connected with different second data connection line segment groups 222B (the mth first data connection line segment 222(m) in the fth second data connection line segment group 222B(f) and the the fth second data connection line segment group the mth first data connection line segment the fth second data connection line segment group the mth first data connection line segment in the fth second data connection line segment group The data signal lines 210 in the second data signal line group 210B and the first data connection line segments 222 in the second data connection line segment group 222B have a variety of settings, and the connection mode of the data signal lines 210 in the second display area AA2 and the first data connection line segments 222 in the first display area AA1 has a variety of settings.

[0198] Referring to FIGS. 1-3, 7-14, 17-32, 34-41, 44-51, 55-64, n is an even number.

[0199] The n pixel circuits 100 arranged in the second direction X2 continuously exist in a region, and the number of the first data connection line segments 222 in the region is different from the number of the pixel circuits 100, so that the number of the first data connection line segments 222 is flexible and can be adjusted adaptively according to different display panels 10. n can be an even number, and in combination with FIGS. 7-14, 17-32, 34-41, 44-51, 55-64, n can be considered to be 2, that is, in a region of two pixel circuits 100 or two data signal lines 210 electrically connected to the pixel circuits 100, there are multiple first data connection line segments 222. Referring to FIGS. 7-14, the two data signal lines 210 include four first data connection line segments 222; referring to FIGS. 17-32, the two data signal lines 210 include one first data connection line segment 222; referring to FIGS. 34-41, the two data signal lines 210 include four first data connection line segments 222; referring to FIGS. 44-51 and 55-64, the two data signal lines 210 include one first data connection line segment 222. The division of n can be understood as a minimum repeating unit of the pixel circuit 100 or the data signal line 210, and the minimum repeating unit can be divided according to the shape of the wire or the arrangement of the wire, which is not limited in the embodiments of the present application. In different display panels 10, n can also take other values, for example, n is 4.

[0200] The m first data connection line segments 222 are located within the range defined by the n data signal lines 210, and the number of the n data signal lines 210 is compared with the number of the m first data connection line segments 222 defined thereby, and the values of m and n are different. At the same time, the n data signal lines 210 can be arranged in the same layer as the m first data connection line segments 222, and the n data signal lines 210 can be arranged in different layers from the m first data connection line segments 222. For the position of the film layer, adaptive adjustment can be made according to different display panels 10, which is not limited in the embodiments of the present application.

[0201] In combination with FIGS. 1-3 and 68-78, along the second direction X2, the length of the first display area AA1 is L1, and the length of the second display area AA2 is L2; along the second direction X2, one side of the first display area AA1 is provided with the second display area AA2, and L1 / L2≥n / m; along the second direction X2, two sides of the first display area AA1 are provided with the second display area AA2, and L1 / L2≥2*(n / m).

[0202] Referring to FIG. 2, along the second direction X2, the length of the first display area AA1 is L1, and the length of the second display AA2 is L2, wherein the first display area AA1 includes a plurality of first data connection line segments 222 arranged along the second direction X2, and the second display area AA2 includes a plurality of data signal lines 210 electrically connected with the first data connection line segments 222. For the length of the first display area AA1 along the second direction X2, there is a corresponding relationship with the arrangement number of the first data connection line segments 222 provided in the first display area AA1; and for the length of the second display area AA2 along the second direction X2, there is a corresponding relationship with the arrangement number of the data signal lines 210 electrically connected with the first data connection line segments 222 provided in the second display area AA2.

[0203] In combination with FIGS. 68-78, one side of the first display area AA1 is provided with the second display area AA2, and the length relationship of the first display area AA1 and the second display area AA2 along the second direction X2 satisfies: L1 / L2≥n / m. Referring to FIGS. 2 and 3, the two sides of the first display area AA1 along the second direction X2 in the display panel 10 can be provided with the second display area AA2, that is, the length relationship of the first display area AA1 and the second display area AA2 along the second direction X2 can satisfy: L1 / L2≥2*(n / m).

[0204] FIG. 79 is a schematic view of a film layer structure of a seventh display panel according to an embodiment of the present application, FIG. 80 is a schematic view of a partial film layer structure of the seventh display panel according to an embodiment of the present application, FIG. 81 is a schematic view of a fourth partial structure in FIG. 79, FIG. 82 is a schematic view of a fifth partial structure in FIG. 79, FIG. 83 is a schematic view of a film layer structure of an eighth display panel according to an embodiment of the present application, FIG. 84 is a schematic view of a film layer structure of the eighth display panel according to an embodiment of the present application, FIG. 85 is a schematic view of a fourth partial structure in FIG. 83, and FIG. 86 is a schematic view of a fifth partial structure in FIG. 83. Referring to FIGS. 1-3, 7-14, 17-24, 34-41, 55-63, 79-86, the auxiliary line 220 further includes a virtual auxiliary line 224. The virtual auxiliary line 224 includes a first virtual auxiliary line segment 225 located in the first display area AA1 and extending along the first direction X1. The first virtual auxiliary line segment 225 is insulated from the first data connection line segment 222.

[0205] Referring to FIGS. 2 and 3, the auxiliary line 220 further includes a virtual auxiliary line 224. The virtual auxiliary line 224 includes a first virtual auxiliary line segment 225 having the same extension direction as the first data connection line segment 222, and the first virtual auxiliary line segment 225 is insulated from the first data connection line segment 222. By providing the first virtual auxiliary line segment 225, the overall wiring of the display panel 10 can be balanced, and the first virtual auxiliary line segment 225 does not affect the normal transmission of signals in the first data connection line segment 222. For example, the first virtual auxiliary line segment 225 can be provided in an unextended area of the first connection line segment L2, or the first virtual auxiliary line segment 225 and the first data connection line segment 222 are arranged along the second direction X2, i.e., the first virtual auxiliary line segment 225 and the first data connection line segment 222 have the same or similar positional relationship, or it is understood that the first virtual auxiliary line segment 225 and the first data connection line segment 222 have the same or similar positional relationship without considering the difference in transmitted signals. By providing the virtual auxiliary line 224, the data auxiliary line 221 has balanced wiring on the overall display panel 10, ensuring that the wiring density in different areas is balanced, thereby avoiding different light reflectivity in the display panel 10 due to unbalanced wiring, and avoiding uneven display of the display panel 10.

[0206] In the display panel 10, in the region corresponding to the n pixel circuits 100 arranged continuously along the second direction X2, m first data connection line segments 222 are arranged; wherein n≠m. That is, in the display panel 10, there is a region as described above, in which region, the number of first data connection line segments 222 and the number of data signal lines 210 arranged in the region defined by the pixel circuits 100 or the corresponding connected data signal lines 210 are inconsistent. Referring to FIGS. 7 and 13, and FIGS. 34 and 40, four first data connection line segments 222 are arranged between two data signal lines 210, although the first dummy auxiliary line segments 225 are not shown in FIGS. 7 and 13 and FIGS. 34 and 40, at least one first dummy auxiliary line segment 225 can also be arranged at the position of the first data connection line segment 222. Referring to FIGS. 17 and 23, or FIGS. 55 and 63, two auxiliary lines 220 are arranged between two data signal lines 210, one of which is a first data connection line segment 222 and the other is a first dummy auxiliary line segment 225.

[0207] In the display panel 10, in the region corresponding to the n pixel circuits 100 arranged continuously along the second direction X2, m first data connection line segments 222 are arranged; wherein n≠m. That is, in the display panel 10, there is a region as described above, in which region, the number of first data connection line segments 222 and the number of data signal lines 210 arranged in the region defined by the pixel circuits 100 or the corresponding connected data signal lines 210 are inconsistent. Referring to FIGS. 7 and 13, and FIGS. 34 and 40, four first data connection line segments 222 are arranged between two data signal lines 210, although the first dummy auxiliary line segments 225 are not shown in FIGS. 7 and 13 and FIGS. 34 and 40, at least one first dummy auxiliary line segment 225 can also be arranged at the position of the first data connection line segment 222. Referring to FIGS. 17 and 23, or FIGS. 55 and 63, two auxiliary lines 220 are arranged between two data signal lines 210, one of which is a first data connection line segment 222 and the other is a first dummy auxiliary line segment 225.

[0208] In general, the first virtual auxiliary line segment 225 can ensure the structural balance of the display panel 10 as a whole and ensure the display effect of the display panel 10 as a whole. Meanwhile, the display panel 10 has diversity in the arrangement of the first virtual auxiliary line segment 225 and the first data connection line segment 222 in the auxiliary wiring 220.

[0209] The first virtual auxiliary line segment 225 is electrically connected with the fixed potential signal line.

[0210] The first virtual auxiliary line segment 225 can be electrically connected with the fixed potential signal line, which can avoid the interference of the first virtual auxiliary line segment 225 with other signals due to the floating coupling of the first virtual auxiliary line segment 225, and can reduce the resistance of the fixed potential signal line and ensure the small loss of the fixed potential signal in the transmission process.

[0211] The pixel circuit 100 includes a reset transistor Ta, the signal line 200 includes a reset signal line 230, and the reset signal line 230 is electrically connected with the first electrode of the reset transistor Ta. The reset signal line 230 includes a first reset line 231, and a plurality of first reset lines 231 extend along a first direction X1 and are arranged along a second direction X2. At least part of the first virtual auxiliary line segment 225 is multiplexed as the first reset line 231.

[0212] The pixel circuit 100 includes a reset transistor Ta, and the reset transistor Ta is electrically connected with the reset signal line 230. The reset signal transmitted in the reset signal line 230 is transmitted to the pixel circuit 100 through the first electrode of the reset transistor Ta, so as to reset the pixel circuit 100 and ensure the reliability of the signal transmission of the display panel 10.

[0213] The reset transistor Ta can include at least one of an initial reset transistor, an anode reset transistor or a bias reset transistor. The type of the reset transistor Ta is adaptively adjusted according to different types of pixel circuits 100, and the present application does not limit this.

[0214] The reset signal line 230 electrically connected with the reset transistor Ta includes the first reset line 231, and the extension direction of the first reset signal line 231 is the same as the extension direction of the first data connection line segment 222, i.e., both extend along the first direction X1, and a plurality of first reset lines 231 are arranged along the second direction X2.

[0215] For example, referring to FIGS. 17-23, the first reset line 231 can be disposed in the same film layer as the first data connection line segment 222, and the first data connection line segment 222 and the first reset line 231 have the same extension direction, i.e., the first reset line 231 has the same or similar positional relationship with the first data connection line segment 222, and thus the first reset line 231 has the same or similar positional relationship with the first virtual auxiliary line segment 225.

[0216] The first virtual auxiliary line segment 225 can be disposed in an unextended region of the first connection line segment L2, or the first virtual auxiliary line segment 225 is arranged along the second direction X2 together with the first data connection line segment 222, i.e., the first virtual auxiliary line segment 225 has the same or similar positional relationship with the first data connection line segment 222. Therefore, referring to FIG. 23, part of the first virtual auxiliary line segment 225 can be multiplexed as the first reset line 231, so that the film layer required by the first reset line 231 can be reduced, the overall film layer thickness of the display panel 10 can be reduced, and the process preparation cost of the display panel 10 can also be reduced. Similarly, referring to FIGS. 23 and 63, at least part of the first reset line 231 is multiplexed by the first virtual auxiliary line segment 225. For different display panels 10, the signal transmitted by the first reset line 231 can transmit different signals according to the adjustment of the pixel circuit 100.

[0217] Continuing to refer to FIG. 4, the reset transistor Ta includes an initial reset transistor T5 and an anode reset transistor T7; the reset signal line 230 includes an initial reset signal line Vref1 and an anode reset signal line Vref2; the pixel circuit 100 further includes a driving transistor T3, and the display panel 10 further includes a light emitting element 300; the initial reset transistor T5 is electrically connected between the initial reset signal line Vref1 and the gate of the driving transistor T3; and the anode reset transistor T7 is electrically connected between the anode reset signal line Vref2 and the light emitting element 300.

[0218] Referring to FIG. 4, the reset transistor Ta in the pixel circuit 100 includes an initial reset transistor T5 and an anode reset transistor T7, the input end of the initial reset transistor T5 is electrically connected with the initial reset signal line Vref1, and the output end is connected with the gate of the driving transistor T3. When the initial reset transistor T5 is turned on, the initial reset signal in the initial reset signal line Vref1 can reset the gate of the driving transistor T3, which can also be understood as resetting the first node N1 in FIG. 4.

[0219] The reset transistor Ta in the pixel circuit 100 further includes an anode reset transistor T7, an input end of the anode reset transistor T7 is electrically connected with the anode reset signal line Vref2, and an output end of the anode reset transistor T7 is electrically connected with the light emitting element 300. When the anode reset transistor T7 is turned on, the anode reset signal in the anode reset signal line Vref2 can reset the anode of the light emitting element 300. It should be noted that in some pixel circuits 100, the initial reset signal line Vref1 can also be multiplexed as the anode reset signal line Vref2, that is, the anode reset transistor T7 and the initial reset transistor T5 are connected to the same reset signal line.

[0220] The first reset line 231 can include at least one of the initial reset signal line Vref1 and the anode reset signal line Vref2.

[0221] The setting of the first reset line 231 can be as follows:

[0222] Optionally, as shown in FIGS. 17-24 and 79-82, the initial reset signal line Vref1 includes a first initial reset line Vref1a, a plurality of first initial reset lines Vref1a extend along the first direction X1 and are arranged along the second direction X2, and the first reset line 231 includes the first initial reset line Vref1a; and / or the anode reset signal line Vref2 includes a first anode reset line Vref2a, a plurality of first anode reset lines Vref2a extend along the first direction X1 and are arranged along the second direction X2, and the first reset line 231 includes the first anode reset line Vref2a.

[0223] Referring to FIGS. 4, 17 and 79, the reset signal line 230 includes the initial reset signal line Vref1 and the anode reset signal line Vref2. Referring to FIGS. 17 and 23, the anode reset signal line Vref2 includes a first anode reset line Vref2a, wherein the first anode reset line Vref2a is arranged along the first direction X1 and extends along the second direction X2, that is, the arrangement direction and the extension direction of the first anode reset line Vref2a are the same as those of the data signal line 210, and then the first reset line 231 includes the first initial reset line Vref1a.

[0224] It should be noted that, as shown in FIGS. 17-24, in combination with FIGS. 21 and 23, the anode reset signal line Vref2 electrically connected with the anode reset transistor T7 is provided in the form of a mesh-shaped trace, that is, part of the anode reset signal line Vref2 is provided to extend along the first direction X1 on the film layer where the second metal layer 460 is located (see FIG. 21), and part of the anode reset signal line Vref2 is provided to extend along the second direction X2 on the film layer where the second source / drain electrode layer 4100 is located (see FIG. 23). The initial reset signal line Vref1 electrically connected with the initial reset transistor T5 is provided to extend along the first direction X1 on the film layer where the second metal layer 460 is located. Therefore, in FIGS. 17-24, only the first reset line 231 is exemplarily shown as including the first anode reset line Vref2a.

[0225] The anode reset signal line Vref2 is provided in the form of a mesh-shaped trace, and the initial reset signal line Vref1 is provided to extend along the second direction X2. This is only one form of the reset signal line 230 in the display panel 10. There can also be a case where the initial reset signal line Vref1 is provided in the form of a mesh-shaped trace, and the anode reset signal line Vref2 is provided to extend along the second direction X2. In this case, the initial reset signal line Vref1 includes the first initial reset line Vref1a which has the same arrangement direction and extension direction as the data signal line 210, and the first reset line 231 includes the first initial reset line Vref1a.

[0226] Referring to FIGS. 79-82, there can also be a case where the anode reset signal line Vref2 is provided in the form of a mesh-shaped trace, and the initial reset signal line Vref1 is also provided in the form of a mesh-shaped trace. In this case, the first reset line 231 includes the first anode reset line Vref2a and the first initial reset line Vref1a, so that the first reset line 231 has flexibility in arrangement.

[0227] Optionally, referring to FIGS. 79-82, the first reset line 231 includes the first initial reset line Vref1a and the first anode reset line Vref2a; along the second direction X2, the first initial reset line Vref1a and the first anode reset line Vref2a are arranged alternately.

[0228] Referring to FIG. 82, when the first reset line 231 includes the first initial reset line Vref1a and the first anode reset line Vref2a, that is, the initial reset signal line Vref1 includes the first initial reset line Vref1a in the same arrangement direction and extension direction as the data signal line 210, and the anode reset signal line Vref2 includes the first anode reset line Vref2a in the same arrangement direction and extension direction as the data signal line 210. It can be understood that the initial reset signal line Vref1 is provided as a mesh trace, and the anode reset signal line Vref2 is also provided as a mesh trace. In this case, along the second direction X2, the first initial reset line Vref1a and the first anode reset line Vref2a are arranged alternately, which can ensure that the initial reset signal line Vref1 and the anode reset signal line Vref2 are balanced in the reset signal transmission effect, and is beneficial to ensuring the display effect of the display panel 10.

[0229] Continuing to refer to FIGS. 33 and 52, the reset transistor Ta further includes a bias reset transistor T8 and a driving transistor T3; the reset signal line 230 further includes a bias reset signal line DVH; and the bias reset transistor T8 is electrically connected between the bias reset signal line DVH and the first electrode and / or the second electrode of the driving transistor T3.

[0230] Referring to FIGS. 33 and 52, the pixel circuit 100 can further include a bias reset transistor T8, an input end of the bias reset transistor T8 is electrically connected with the bias reset signal line DVH, and an output end of the bias reset transistor T8 is connected with the driving transistor T3, so as to bias and adjust the driving transistor T3, ensure the stability of the driving transistor T3, and ensure the working stability of the display panel 10 and the display effect of the display panel 10. The bias reset transistor T8 can be connected at the first electrode (referring to FIGS. 33 and 52) of the driving transistor T3, that is, the second node N2; the bias reset transistor T8 can also be connected at the second electrode (not shown in the figure) of the driving transistor T3, that is, the third node N3; and the bias reset transistor T8 can also be connected at the first electrode and the second electrode of the driving transistor T3. Based on the position of the output end of the bias reset transistor T8, the bias adjustment of the driving transistor T3 can be adaptively adjusted according to the actual situation, and the embodiments of the present application do not limit this.

[0231] In addition to at least one of the initial reset signal line Vref1 and the anode reset signal line Vref2 being the first reset line 231, the bias reset signal line DVH mentioned in the embodiments can also be the first reset line 231.

[0232] The setting of the first reset line 231 can also be as follows:

[0233] Continuing with FIGS. 55-64, 83-86, the bias reset signal line DVH includes a first bias reset line DVHa, and the plurality of first bias reset lines DVHa extend in the first direction X1 and are arranged in the second direction X2; and the first reset line 231 includes the first bias reset line DVHa.

[0234] Referring to FIGS. 33 and 52, the reset signal line 230 also biases the reset signal line DVH, in combination with FIGS. 52, 55-64, referring to FIG. 63, the bias reset signal line DVH includes a first bias reset line DVHa, wherein the first bias reset line DVHa is arranged in the second direction X2 and extends in the first direction X1, i.e., the arrangement direction and the extension direction of the first bias reset line DVHa are the same as those of the data signal line 210, and thus the first reset line 231 can include the first bias reset line DVHa. Similarly, in combination with FIGS. 33, 83-86, referring to FIG. 86, the bias reset signal line DVH includes a first bias reset line DVHa, wherein the first bias reset line DVHa is arranged in the second direction X2 and extends in the first direction X1, i.e., the arrangement direction and the extension direction of the first bias reset line DVHa are the same as those of the data signal line 210, and thus the first reset line 231 can include the first bias reset line DVHa.

[0235] It should be noted that in FIGS. 55-64, the bias reset signal line DVH is provided in the form of a mesh-shaped trace, i.e., part of the bias reset signal line DVH is arranged to extend in the second direction X2 in the film layer where the second metal layer 560 is located (see FIG. 59), and part of the bias reset signal line DVH is arranged to extend in the first direction X1 in the film layer where the second source-drain electrode layer 5140 is located (see FIG. 63).

[0236] The first reset line 231 can be part of the initial reset signal line Vref1 and / or the anode reset signal line Vref2, and can also be part of the bias reset signal line DVH, which better reflects the diversified setting mode of the first reset line 231.

[0237] With reference to FIGS. 63 and 86, the initial reset signal line Vref1 includes a first initial reset line Vref1a, and a plurality of first initial reset lines Vref1a extend along the first direction X1 and are arranged along the second direction X2; the first reset line 231 further includes the first initial reset line Vref1a; along the second direction X2, the first initial reset line Vref1a and the first bias reset line DVHa are arranged alternately. Or, the anode reset signal line Vref2 includes a first anode reset line Vref2a, and a plurality of first anode reset lines Vref2a extend along the first direction X1 and are arranged along the second direction X2; the first reset line 231 further includes the first anode reset line Vref2a; along the second direction X2, the first anode reset line Vref2a and the first bias reset line DVHa are arranged alternately. Or, the initial reset signal line Vref1 includes a first initial reset line Vref1a, and a plurality of first initial reset lines Vref1a extend along the first direction X1 and are arranged along the second direction X2; the anode reset signal line Vref2 includes a first anode reset line Vref2a, and a plurality of first anode reset lines Vref2a extend along the first direction X1 and are arranged along the second direction X2; the first reset line 231 further includes the first initial reset line Vref1a and the first anode reset line Vref2a; the first initial reset line Vref1a, the first anode reset line Vref2a, and the first bias reset line DVHa are arranged along the second direction X2.

[0238] With reference to FIGS. 33 and 52, the reset signal line 230 can include an initial reset signal line Vref1, an anode reset signal line Vref2, and a bias reset signal line DVH, and the reset signal line 230 in different display panels 10 can be arranged flexibly, and the first reset line 231 can also be arranged flexibly.

[0239] As shown in FIGS. 63 and 86, the anode reset signal line Vref2 includes a first anode reset line Vref2a, where the first anode reset line Vref2a extends in the first direction X1 and is arranged in the second direction X2, that is, the arrangement direction and the extension direction of the first anode reset line Vref2a are the same as those of the data signal line 210, and the bias reset signal line DVH includes a first bias reset line DVHa, where the first bias reset line DVHa also extends in the first direction X1 and is arranged in the second direction X2, that is, the arrangement direction and the extension direction of the first bias reset line DVHa are also the same as those of the data signal line 210, and the first reset line 231 can include the first anode reset line Vref2a and the first bias reset line DVHa. As shown in FIGS. 63 and 86, along the second direction X2, the first anode reset line Vref2a and the first bias reset line DVHa can be alternately arranged, that is, one first bias reset line DVHa is arranged between two adjacent first anode reset lines Vref2a, or one first anode reset line Vref2a is arranged between two adjacent first bias reset lines DVHa, which can ensure balanced arrangement of the display panel 10 wires and regularity of the display panel 10.

[0240] The reset signal line 230 can include an initial reset signal line Vref1, an anode reset signal line Vref2, and a bias reset signal line DVH, where the initial reset signal line Vref1 can include a first initial reset line Vref1a, that is, the initial reset signal line Vref1 includes a wire extending in the first direction X1 and arranged in the second direction X2, and the bias reset signal line DVH includes a first bias reset line, where the first bias reset line also extends in the first direction X1 and is arranged in the second direction X2, that is, the arrangement direction and the extension direction of the first bias reset line are also the same as those of the data signal line 210, and the first reset line 231 includes the first initial reset line and the first bias reset line. Along the second direction X2, the first initial reset line and the first bias reset line can be alternately arranged, that is, one first bias reset line is arranged between two adjacent first initial reset lines, or one first initial reset line is arranged between two adjacent first bias reset lines, which can ensure balanced arrangement of the display panel 10 wires and regularity of the display panel 10.

[0241] The reset signal line 230 includes an initial reset signal line Vref1, an anode reset signal line Vref2, and a bias reset signal line DVH. The initial reset signal line Vref1 can include a first initial reset line, i.e., the initial reset signal line Vref1 includes a trace extending in a first direction X1 and arranged in a second direction X2. The anode reset signal line Vref2 includes a first anode reset line, i.e., the first anode reset line is a trace extending in the first direction X1 and arranged in the second direction X2, i.e., the arrangement direction and the extension direction of the first anode reset line are the same as those of the data signal line 210. The bias reset signal line DVH includes a first bias reset line, i.e., the first bias reset line is also a trace extending in the first direction X1 and arranged in the second direction X2, i.e., the arrangement direction and the extension direction of the first bias reset line are also the same as those of the data signal line 210. The first reset line 231 includes the first initial reset line, the first anode reset line, and the first bias reset line. In the second direction X2, the first initial reset line, the first anode reset line, and the first bias reset line can be alternately arranged, which can ensure balanced arrangement of the traces of the display panel 10 and regularity of the display panel 10. When the first reset line 231 includes the first initial reset line, the first anode reset line, and the first bias reset line, the alternately arranged trace mode has diversity. For example, the first initial reset line is denoted by "a", the first anode reset line is denoted by "b", and the first bias reset line is denoted by "c". The arrangement mode of the first reset line 231 can be "abcabc...", "abcacb...", or "abcbac..." and the like. Based on the arrangement mode of the first initial reset line, the first anode reset line, and the first bias reset line in the second direction X2, the arrangement can be adaptively adjusted according to the actual display panel 10, which is not limited in the embodiments of the present application.

[0242] As shown in FIG. 63, n > m; the display area AA further includes a first auxiliary line segment group 240 and a second auxiliary line segment group 250 arranged adjacent to each other in the second direction X2; the first auxiliary line segment group 240 includes a first reset line 241 and a first non-reset line 242 arranged adjacent to each other in the first direction X1, and the first non-reset line 242 includes the first data connection line segment 222 and / or the first power line segment; the second auxiliary line segment group 250 includes a first reset line 251 and a second non-reset line 252 arranged adjacent to each other in the first direction X1, and the second non-reset line 252 includes the first data connection line segment 222 and / or the first power line segment; the first reset line 241 and the first reset line 251 are insulated; the direction in which the first reset line 241 points to the first non-reset line 242 is opposite to the direction in which the first reset line 251 points to the second non-reset line 252.

[0243] The display region AA includes a first auxiliary line segment group 240 and a second auxiliary line segment group 250 arranged adjacent along the second direction X2, the first auxiliary line segment group 240 includes a first reset line 241 and a first non-reset line 242, and the second auxiliary line segment group 250 includes a first reset line 251 and a second non-reset line 252. The first reset line 241, the first non-reset line 242, the first reset line 251 and the second non-reset line 252 all have the same extension direction as the data signal line 210.

[0244] When the first auxiliary line segment group 240 and the second auxiliary line segment group 250 are located in the first display region AA1, the first non-reset line 242 includes the first data connection line segment 222, the second non-reset line 252 includes the first data connection line segment 222, and the first reset line 241 and the first reset line 251 can be the same or different first reset lines 231. For example, as shown in FIG. 63, the first reset line 241 is a first bias reset line DVHa, the first non-reset line 242 is the first data connection line segment 222, the first reset line 251 is a first initial reset line Vref1a, and the second non-reset line 252 is the first data connection line segment 222. It should be noted that in FIG. 63, the first reset line 241 is taken as the first bias reset line DVHa, and the first reset line 251 is taken as the first initial reset line Vref1a for example. In different display panels 10, the first reset line 241 and the first reset line 251 can also be other first reset lines 231, which are not illustrated one by one in the embodiments of the present application.

[0245] The first auxiliary line segment group 240 and the second auxiliary line segment group 250 can also be located in the second display region AA2. When the first auxiliary line segment group 240 and the second auxiliary line segment group 250 are located in the second display region AA2, the first non-reset line 242 includes a first power supply line segment, and the second non-reset line 252 also includes the first power supply line segment. The first power supply line segment can be understood as a part of the power supply signal line electrically connected to the light emitting element in the display panel 10 and extending along the first direction X1. The first reset line 241 and the first reset line 251 can be the same or different first reset lines 231.

[0246] In the display panel 10, one of the first auxiliary line segment group 240 and the second auxiliary line segment group 250 can be arranged in the first display region AA1 and the other in the second display region AA2, which is not limited in the embodiments of the present application. When the first auxiliary line segment group 240 is located in the second display region AA2 and the second auxiliary line segment group 250 is located in the first display region AA1, the first non-reset line 242 includes the first data connection line segment 222, the second non-reset line 252 includes the first data connection line segment 222, and the first reset line 241 and the first reset line 251 can be the same or different first reset lines 231.

[0247] The first reset line 241 points to the direction of the first non-reset line 242, which is opposite to the direction of the second reset line 251 pointing to the second non-reset line 252. In combination with FIG. 63, the first reset line 241 is located on the side of the first non-reset line 242 close to the second auxiliary line segment group 250, and the second reset line 251 is located on the side of the second non-reset line 252 close to the first auxiliary line segment group 240. In this way, the electrical connection effect of the reset transistor Ta electrically connected to the first reset line 241 and the electrical connection effect of the reset transistor Ta electrically connected to the second reset line 251 can be ensured, thereby ensuring the display effect of the display panel 10 as a whole. It can be ensured that there is no interference between different color light emitting elements 300 connected by different pixel circuits 100, thereby further improving the display effect of the display panel 10.

[0248] Continuing to refer to FIGS. 4, 33, 52, and in combination with FIGS. 68-78, the signal line 200 further includes a power signal line, the power signal line includes a first power line segment, a plurality of first power line segments extend along the first direction X1 and are arranged along the second direction X2; the display panel 10 further includes a light emitting element 300, the power signal line is electrically connected to the anode and / or cathode of the light emitting element 300; at least part of the first virtual auxiliary line segment 225 is multiplexed as a first power line segment.

[0249] Referring to FIGS. 4, 33, and 52, the display panel 10 further includes a power signal line, the power signal line is electrically connected to the light emitting element 300, and can provide a driving current to the light emitting element 300 to emit light and display, thereby realizing the display function of the display panel 10.

[0250] The power signal line can include a first power line segment, the first power line segment extends along the first direction X1 and is arranged along the second direction X2, that is, the extension direction of the first power line segment is the same as that of the data signal line 210. Alternatively, it is understood that the power signal line includes a part of the line whose extension direction is the same as that of the data signal line 210, and this part of the line is the first power line segment.

[0251] In combination with FIGS. 2, 3, 68-78, there are part of the first virtual auxiliary line segments 225 in the display panel 10, the first virtual auxiliary line segments 225 have the same extension direction as the data signal line 210, and are insulatively arranged with the first virtual auxiliary line segments 225 and the first data connection line segment 222. In this way, part of the first virtual auxiliary line segments 225 can be multiplexed as the first power line segment, which on the one hand will not interfere with the signals transmitted by the first data connection line segment 222 or other signal lines 200, and on the other hand can reduce the occupied space and film layer of part of the power signal line, thereby reducing the overall film layer thickness and process preparation cost of the display panel 10.

[0252] The power signal lines include a first power signal line PVDD and a second power signal line PVEE, the first power signal line PVDD is electrically connected with the anode of the light emitting element 300, and the second power signal line PVEE is electrically connected with the cathode of the light emitting element 300; the first power signal line PVDD includes a first alpha power line segment, a plurality of first alpha power line segments extend along the first direction X1 and are arranged along the second direction X2, and at least part of the first virtual auxiliary line segment 225 is multiplexed as the first alpha power line segment; and / or, the second power signal line includes a first beta power line segment, a plurality of first beta power line segments extend along the first direction X1 and are arranged along the second direction X2, and at least part of the first virtual auxiliary line segment 225 is multiplexed as the first beta power line segment.

[0253] The power signal lines include a first power signal line PVDD and a second power signal line PVEE, and according to the electrical connection relationship between the components in the pixel circuit 100 shown in FIGS. 4, 33 and 52, the first power signal line PVDD and the second power signal line PVEE are both electrically connected with the light emitting element 300, the first power signal line PVDD is electrically connected with the anode of the light emitting element 300, and the first power signal line PVDD can be understood as a positive power signal line; the second power signal line PVEE is electrically connected with the cathode of the light emitting element 300, and the second power signal line PVEE can be understood as a negative power signal line.

[0254] For the first power signal line PVDD including a first alpha power line segment, the extension direction of the first alpha power line segment is the same as that of the data signal line 210, i.e., the same as that of the first data connection line segment 222 and the first virtual auxiliary line segment 225. The second power signal line PVEE includes a first beta power line segment, and the extension direction of the first beta power line segment is the same as that of the data signal line 210, i.e., the same as that of the first data connection line segment 222 and the first virtual auxiliary line segment 225.

[0255] With reference to FIGS. 2, 3, 68-78, there are partial first virtual auxiliary line segments 225 in the display panel 10, and the partial first virtual auxiliary line segments 225 can be multiplexed as first power supply line segments, which on one hand will not interfere with signals transmitted in the first data connection line segments 222 or other signal lines 200, and on the other hand can reduce the occupied space and film layers of partial power supply signal lines, and can reduce the overall film layer thickness of the display panel 10 and the process preparation cost. In the display panel 10, at least partial first virtual auxiliary line segments 225 can be multiplexed as first alpha power supply line segments; or, in the display panel 10, at least partial first virtual auxiliary line segments 225 can be multiplexed as first beta power supply line segments; or, in the display panel 10, at least partial first virtual auxiliary line segments 225 can be multiplexed as first alpha power supply line segments and first beta power supply line segments. For the case that the first virtual auxiliary line segments 225 are multiplexed as first power supply line segments, adaptive adjustments can be made according to different display panels 10, which are not limited by the embodiments of the present application.

[0256] With continued reference to FIGS. 7-14, 17-32, the reset signal line 230 further includes a second reset line 232, the second reset line 232 extending at least partially along the second direction X2, and the second reset line 232 is disposed in a different layer from the first reset line 231.

[0257] The reset signal line 230 includes the first reset line 231 and the second reset line 232, wherein the first reset line 231 extends along the first direction X1 and is arranged along the second direction X2, the second reset line 232 extends along the second direction X2 and is arranged along the first direction X1, and the first reset line 231 and the second reset line 232 are disposed in different layers, which embodies a flexible setting mode of the reset signal line 230.

[0258] For example, with reference to FIGS. 11 and 13, 21 and 23, 29 and 31, there are the second reset line 232 located in the film layer where the second metal layer 460 is located, and there are the first reset line 231 located in the film layer where the second source-drain electrode layer 4100 is located, in the anode reset signal line Vref2 to which the anode reset transistor T7 in the pixel circuit 10 is connected. Similarly, there are the second reset line 232 located in the film layer where the second metal layer 460 is located, and there are the first reset line 231 located in the film layer where the second source-drain electrode layer 4100 is located, in the initial reset signal line Vref1 to which the initial reset transistor T5 in the pixel circuit 100 is connected.

[0259] In FIGS. 7-14, 17-32, the reset signal line 230 including the first reset line 231 and the second reset line 232 is exemplarily shown as the anode reset signal line Vref2 and the initial reset signal line Vref1. In other embodiments, the reset signal line 230 including the first reset line 231 and the second reset line 232 can also be the bias reset signal line DVH, etc., which is not limited in the embodiments of the present application.

[0260] The first reset line 231 and the second reset line 232 included in the reset signal line 230 can be signal lines transmitting the same signal, which are only parts located in different film layers, for example, the first reset line 231 and the second reset line 232 are respectively the anode reset signal line Vref2 in different film layers. The first reset line 231 and the second reset line 232 included in the reset signal line 230 can also be signal lines transmitting different signals, which are located in different film layers, for example, the first reset line 231 includes the anode reset signal line Vref2, and the second reset line 232 includes the bias reset signal line DVH. The flexibility of the reset signal line 230 is embodied.

[0261] Referring to FIGS. 7-14, 17-32, 34-41, 44-51, 55-64, the second reset line 232 includes the first reset part 233; the first reset part 233 extends along the second direction X2, and along the second direction X2, the first reset part 233 located in the same film layer continuously passes through the display area of the display panel 10.

[0262] The second reset line 222 includes the first reset part 233, wherein the first reset part 233 is continuously arranged at the same film layer and passes through the display area of the display panel 10, which can be understood as that the first reset part 233 is in an unbroken state at the film layer where it is located, and the extension length along the second direction X2 is equivalent to the length of the display area of the display panel 10. The display area is not shown in the figure, which can be understood as the area where the light emitting element 300 performs light emitting display.

[0263] Exemplarily, referring to FIGS. 11, 21, 29, in this embodiment, the second reset line 222 can include the initial reset signal line Vref1 and the anode reset signal line Vref2, and in the film layer shown in FIGS. 11, 21, 29, the initial reset signal line Vref1 and the anode reset signal line Vref2 both extend along the second direction X2 and continuously pass through the display area of the display panel 10, then the first reset part 233 can be the initial reset signal line Vref1 and the anode reset signal line Vref2 under the film layer.

[0264] For example, as shown in FIGS. 38, 48 and 59, in this embodiment, the second reset line 232 can include an initialization reset signal line Vref1, an anode reset signal line Vref2 and a bias reset signal line DVH, and in the film layer where FIGS. 38, 48 and 59 are located, the initialization reset signal line Vref1, the anode reset signal line Vref2 and the bias reset signal line DVH all extend along the second direction X2 and continuously pass through the display area of the display panel 10, and then the first reset part 233 can be the initialization reset signal line Vref1, the anode reset signal line Vref2 and the bias reset signal line DVH under the film layer. The reset signal line 230 has flexibility, and the setting mode has diversity.

[0265] Referring to FIGS. 4, 6-14, 17-41, 44-51, the pixel circuit 100 includes at least one transistor including a first active layer poly, and the pixel circuit 100 further includes a storage capacitor Cst including a first plate M1 and a second plate MC oppositely arranged, the second plate MC being located on a side of the first plate M1 away from the first active layer poly, and the display panel 10 further includes a first semiconductor layer 420, a first metal layer 440 and a second metal layer 460, the first active layer poly being located on the first semiconductor layer 420, the first plate M1 being located on the first metal layer 440, and the second plate being located on the second metal layer 460, and the first reset part 233 being located on at least one of the first semiconductor layer 420, the first metal layer 440 or the second metal layer 460.

[0266] Referring to FIGS. 4, 6 and 33, the transistor of the pixel circuit 100 can include a first active layer poly, and the first active layer poly is located on the first semiconductor layer 420, which can be understood as that the transistor in the pixel circuit 100 is a low-temperature polysilicon transistor. Referring to FIG. 6, in the direction away from the substrate, the film layer structure included in the pixel circuit 100 can be the substrate 400, the buffer layer 410, the first semiconductor layer 420, the first insulating layer 430, the first metal layer 440, the interlayer insulating layer 450, the second metal layer 460, the second insulating layer 470, the first source-drain electrode layer 480, the third insulating layer 490, the second source-drain electrode layer 4100, the planarization layer 4110 and the anode layer 4120. The pixel circuit 100 includes a storage capacitor Cst including a corresponding first plate and a second plate. The film layer where the first plate is located is the film layer where the first metal layer 440 is located, and the film layer where the second plate is located is the film layer where the second metal layer 460 is located.

[0267] In the pixel circuit 100 described above, the first reset sub-portion 233 can be in the same layer as at least one of the first active layer poly, the first plate or the second plate. In this way, the first reset sub-portion 233 can be in the same layer as one of the above-mentioned film layers, or in the same layer as at least two of the above-mentioned film layers, and can be flexibly adjusted based on the film layer position of the first reset sub-portion 233. Moreover, when the first reset sub-portion 233 is arranged in the same layer as at least two of the first active layer poly, the first plate or the second plate, the first reset sub-portion 233 arranged in each film layer can continuously pass through the display area of the display panel 10 in the second direction X2. For example, the first reset sub-portion 233 can be located in the film layer in which the second metal layer 460 is located, i.e., the first reset sub-portion 233 is arranged in the same layer as the second plate, and can refer to the layout shown in FIGS. 11, 21, 29, 38 and 48. Based on the film layer position of the arrangement of the first reset sub-portion 233, the arrangement of the first reset sub-portion 233 can be adaptively adjusted according to actual conditions, and the present application does not limit this, so that the arrangement of the first reset sub-portion 233 can be flexible.

[0268] With continued reference to FIGS. 52 and 54, 55-64, the pixel circuit 100 includes at least one first type transistor and at least one second type transistor, the first type transistor including a first active layer poly and a first gate M1, and the second type transistor including a second active layer igzo, a second top gate Mg and a second bottom gate Mc, the first gate M1 being located on a side of the first active layer poly close to the second active layer igzo or on a side of the first active layer poly away from the second active layer igzo, the second top gate Mc being located on a side of the second active layer igzo away from the first active layer poly, and the second bottom gate Mc being located on a side of the second active layer igzo close to the first active layer poly; the display panel further includes a first semiconductor layer 520, a first metal layer 540, a second metal layer 560, a second semiconductor layer 580 and a third metal layer 5100; the first active layer poly is located on the first semiconductor layer 520, the first gate M1 is located on the first metal layer 540, the second bottom gate Mc is located on the second metal layer 560, the second active layer igzo is located on the second semiconductor layer 580, and the second top gate Mg is located on the third metal layer 5100; and the first reset sub-portion 233 is located on at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580 or the third metal layer 5100.

[0269] The pixel circuit 100 includes a first type transistor and a second type transistor, wherein the first type transistor includes a first active layer poly, and the first active layer poly can include a silicon semiconductor part, and the first type transistor can be understood as a low-temperature polysilicon transistor. The second type transistor includes a second active layer igzo, and the second active layer 380 can include an oxide semiconductor part, and the second type transistor can be understood as an oxide transistor. Further, the pixel circuit 100 simultaneously includes a low-temperature polysilicon transistor and an oxide transistor, and the pixel circuit 100 has the advantages of small leakage current of the oxide transistor, and also has the advantages of high switching speed, high carrier mobility and small power of the low-temperature polysilicon transistor.

[0270] The first type transistor includes a first active layer poly and a first gate M1, and the second type transistor includes a second active layer igzo, a second top gate Mg and a second bottom gate Mc. The first gate M1 is located on the side of the first active layer poly close to the second active layer igzo, the second top gate Mg is located on the side of the second active layer igzo away from the first active layer poly, and the second bottom gate Mc is located on the side of the second active layer igzo close to the first active layer poly. Referring to FIG. 54, the film layer where the first gate M1 is located is located in the film layer where the first metal layer 540 is located, the film layer where the second bottom gate Mc is located is located in the film layer where the second metal layer 560 is located, and the film layer where the second top gate Mg is located is located in the film layer where the third metal layer 5100 is located. At this time, the first gate M1 is located on the side of the first active layer poly away from the substrate 500, and the first type transistor is a transistor in a top gate structure. For the first gate M1, it can also be located on the side of the first active layer poly away from the second active layer igzo (not shown in the figure), and at this time, the first type transistor is a transistor in a bottom gate structure. The present embodiment does not limit the positional relationship between the first gate and the first active layer.

[0271] Referring to FIGS. 55 to 64, in the above-mentioned pixel circuit 100, the first reset sub-part 233 can be in the same layer as at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580 or the third metal layer 5100,

[0272] For example, referring to FIG. 59, the first reset sub-part 233 is located in the film layer where the second metal layer 560 is located, that is, the first reset sub-part 233 is arranged in the same layer as the second bottom gate Mc. Based on the film layer position where the first reset sub-part 233 is arranged, the film layer position can be adaptively adjusted according to actual conditions, and the present embodiment does not limit this. In this way, the arrangement of the first reset sub-part 233 can be flexible.

[0273] Optionally, referring to FIGS. 34-41, the second reset line 232 includes a second reset sub-portion 233a and a third reset sub-portion 233b which are arranged in different layers and electrically connected; the second reset sub-portion 233a extends at least partially along the second direction X2, the third reset sub-portion 233b extends at least partially along the second direction X2, and along the second direction X2, the second reset sub-portion 233a and the third reset sub-portion 233b are arranged alternately.

[0274] The second reset line 232 can also include the second reset sub-portion 233a and the third reset sub-portion 233b, and both the second reset sub-portion 233a and the third reset sub-portion 233b extend at least partially along the second direction X2, i.e., the two sub-portions arranged in different layers extend in the same direction and are electrically connected to each other, so as to ensure that the second reset sub-portion 233a and the third reset sub-portion 233b transmit the same signal. Along the second direction X2, the second reset sub-portion and the third reset sub-portion 233b are arranged alternately, i.e., along the second direction X2, the signal transmitted in the second reset line 232 is transmitted from the second reset sub-portion 233a to the third reset sub-portion 233b, and then to the second reset sub-portion 233a, and so on. The second reset line 232 is designed in layers by the second reset sub-portion 233a and the third reset sub-portion 233b, further embodying the flexible setting mode of the second reset line 232.

[0275] For example, referring to FIGS. 61 and 62, the second reset line 232 can be an anode reset signal line Vref2, the anode reset signal line Vref2 includes the second reset sub-portion 233a and the third reset sub-portion 233b, the second reset sub-portion 233a and the third reset sub-portion 233b arranged in different layers are electrically connected alternately along the second direction X2, so as to realize the transmission of the reset signal to the anode along the second direction X2. Optionally, the second reset sub-portion 233a can be arranged in the film layer where the third metal layer 5100 is located, and the third reset sub-portion 233b can be arranged in the film layer where the first source / drain electrode layer 5120 is located. The positions of the second reset sub-portion and the third reset sub-portion can be adjusted or exchanged adaptively, which is not limited in the embodiments of the present application.

[0276] The above embodiments are exemplified by the anode reset signal line Vref2, and the type of the second reset line 232 is not limited to the anode reset signal line Vref2, and can be adjusted adaptively according to the adjustment of the film layer structure of the display panel 10.

[0277] Optionally, referring to FIGS. 4, 6 and 33, the pixel circuit 100 includes at least one transistor including a first active layer poly, and the pixel circuit 100 further includes a storage capacitor Cst including a first plate M1 and a second plate MC oppositely arranged, the second plate MC being located on a side of the first plate M1 away from the first active layer poly, and the display panel 10 further includes a first semiconductor layer 420, a first metal layer 440, a second metal layer 460 and a first source-drain electrode layer 480, the first active layer poly being located on the first semiconductor layer 420, the first plate M1 being located on the first metal layer 440, the second plate MC being located on the second metal layer 460, and the first source-drain electrode layer 480 being located on a side of the second metal layer 460 away from the first active layer poly, and the second reset sub-portion being located on at least one of the first semiconductor layer 420, the first metal layer 440, the second metal layer 460 or the first source-drain electrode layer 480, and the third reset sub-portion being located on at least one of the first semiconductor layer 420, the first metal layer 440, the second metal layer 460 or the first source-drain electrode layer 480.

[0278] Referring to FIGS. 4, 6 and 33, the transistor of the pixel circuit 100 can include a first active layer poly, and the first active layer poly is located on the first semiconductor layer 420, which can be understood as that the transistor in the pixel circuit 100 is a low-temperature polysilicon transistor. Referring to FIG. 6, along a direction away from the substrate 400, the film layer structure included in the pixel circuit 100 can be the substrate 400, the buffer layer 410, the first semiconductor layer 420, the first insulating layer 430, the first metal layer 440, the interlayer insulating layer 450, the second metal layer 460, the second insulating layer 470, the first source-drain electrode layer 480, the third insulating layer 490, the second source-drain electrode layer 4100, the planarization layer 4110 and the anode layer 4120. The pixel circuit 100 includes a storage capacitor Cst including a corresponding first plate and a second plate. The film layer where the first plate is located is the film layer where the first metal layer 440 is located, and the film layer where the second plate is located is the film layer where the second metal layer 460 is located.

[0279] In the pixel circuit 100, the second reset sub-part can be in the same layer as at least one of the first active layer poly, the first plate or the second plate. In this way, the second reset sub-part can be in the same layer as one of the above-mentioned film layers, or in the same layer as at least two of the above-mentioned film layers, and can be flexibly adjusted based on the film layer position of the second reset sub-part. Similarly, the third reset sub-part can be in the same layer as at least one of the first active layer poly, the first plate or the second plate. In this way, the third reset sub-part can be in the same layer as one of the above-mentioned film layers, or in the same layer as at least two of the above-mentioned film layers, and can be flexibly adjusted based on the film layer position of the third reset sub-part. Based on the film layer positions of the second reset sub-part and the third reset sub-part, the film layer positions can be adaptively adjusted according to actual conditions, and the embodiments of the present application do not limit this. In this way, the setting of the reset signal line 230 can be flexible.

[0280] Optionally, continuing to refer to FIGS. 52 and 54, the pixel circuit 100 includes at least one first type transistor and at least one second type transistor, the first type transistor includes a first active layer poly and a first gate M1, and the second type transistor includes a second active layer igzo, a second top gate Mg and a second bottom gate Mc, the first gate M1 is located on a side of the first active layer poly close to the second active layer igzo or on a side of the first active layer poly away from the second active layer igzo, the second top gate Mc is located on a side of the second active layer igzo away from the first active layer poly, and the second bottom gate Mc is located on a side of the second active layer igzo close to the first active layer poly; the display panel further includes a first semiconductor layer 520, a first metal layer 540, a second metal layer 560, a second semiconductor layer 580, a third metal layer 5100 and a first source-drain electrode layer 5120; the first active layer poly is located on the first semiconductor layer 520, the first gate M1 is located on the first metal layer 540, the second bottom gate Mc is located on the second metal layer 560, the second active layer igzo is located on the second semiconductor layer 580, the second top gate Mg is located on the third metal layer 5100, and the first source-drain electrode layer 5120 is located on a side of the third metal layer 5100 away from the first active layer poly; the second reset sub-part is located on at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580, the third metal layer 5100 or the first source-drain electrode layer 5120, and the third reset sub-part is located on at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580, the third metal layer 5100 or the first source-drain electrode layer 5120.

[0281] The pixel circuit 100 includes a first type transistor and a second type transistor, wherein the first type transistor includes a first active layer poly, and the first active layer poly can include a silicon semiconductor part, and the first type transistor can be understood as a low-temperature polysilicon transistor. The second type transistor includes a second active layer igzo, and the second active layer 380 can include an oxide semiconductor part, and the second type transistor can be understood as an oxide transistor. Further, the pixel circuit 100 simultaneously includes a low-temperature polysilicon transistor and an oxide transistor, and the pixel circuit 100 has the advantages of small leakage current of the oxide transistor, and also has the advantages of high switching speed, high carrier mobility and small power of the low-temperature polysilicon transistor.

[0282] The first type transistor includes a first active layer poly and a first gate M1, and the second type transistor includes a second active layer igzo, a second top gate Mg and a second bottom gate Mc. The first gate M1 is located on a side of the first active layer poly close to the second active layer igzo, the second top gate Mg is located on a side of the second active layer igzo away from the first active layer poly, and the second bottom gate Mc is located on a side of the second active layer igzo close to the first active layer poly. Referring to FIG. 54, the film layer where the first gate M1 is located is located in the film layer where the first metal layer 540 is located, the film layer where the second bottom gate Mc is located is located in the film layer where the second metal layer 560 is located, and the film layer where the second top gate Mg is located is located in the third metal layer 5100. At this time, the first gate M1 is located on a side of the first active layer poly away from the substrate 500, and the first type transistor is a transistor in a top gate structure. The first gate M1 can also be located on a side of the first active layer poly away from the second active layer igzo (not shown in the figure), and at this time, the first type transistor is a transistor in a bottom gate structure. The present application does not limit the positional relationship between the first gate and the first active layer.

[0283] In the pixel circuit 100, the second reset part can be in the same layer as at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580, the third metal layer 5100 or the first source-drain electrode layer 5120; and the third reset part can be in the same layer as at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580, the third metal layer 5100 or the first source-drain electrode layer 5120.

[0284] Exemplarily, the second reset sub-part is located in the film layer where the second metal layer 560 is located, that is, the second reset sub-part 233 is arranged in the same layer as the second bottom gate Mc, and the third reset sub-part is located in the film layer where the first source-drain electrode layer 5120 is located. Based on the film layer positions of the second reset sub-part and the third reset sub-part, adaptive adjustment can be made according to actual conditions, and the embodiments of the present application do not limit this, so that the setting of the reset signal line 230 can be flexible.

[0285] Referring to FIGS. 7-14, 17-32, 34-41, 44-51, 55-64, the second reset line 232 is electrically connected to the first reset line 231 through a via hole.

[0286] When the second reset line 232 and the first reset line 231 transmit the same signal, the two layers can be electrically connected through a via hole. Exemplarily, referring to FIGS. 7-14, 17-32, the reset signal line 230 includes an anode reset signal line Vref2 and an initialization reset signal line Vref1, and the anode reset signal line Vref2 and the initialization reset signal line Vref1 each include the first reset line 231 and the second reset line 232. Referring to FIGS. 34-41, 44-51, 55-64, the reset signal line 230 can include an anode reset signal line Vref2, an initialization reset signal line Vref1, and a bias reset signal line DVH. Exemplarily, the anode reset signal line Vref2 is taken as an example for illustration: referring to FIGS. 11 and 13, the second reset line 232 (configured to transmit the signal of the anode reset signal line Vref2) is located in the film layer where the second metal layer 460 is located, and the first reset line 231 (configured to transmit the signal of the anode reset signal line Vref2) is located in the film layer where the first source-drain electrode layer 480 is located. Referring to FIGS. 21 and 23, the second reset line 232 (configured to transmit the signal of the anode reset signal line Vref2) is located in the film layer where the second metal layer 460 is located, and the first reset line 231 (configured to transmit the signal of the anode reset signal line Vref2) is located in the film layer where the second source-drain electrode layer 4100 is located. The first reset line 231 and the second reset line 232 transmit the same electrical signal, and the second reset line 232 is electrically connected to the first reset line 231 through a via hole. The above only exemplarily illustrates two cases, and all cases are not shown one by one.

[0287] Referring to FIGS. 7-14, 17-32, 34-41, 44-51, 55-64, the second reset line 232 is insulated from the first reset line 231.

[0288] The second reset line 232 and the first reset line 231 transmit different signals, and the two layers are insulated. Thus, the signal transmission in the display panel 10 is stable, and the display effect of the display panel 10 is ensured.

[0289] For example, referring to FIGS. 7-14, 17-32, the reset signal line 230 includes an anode reset signal line Vref2 and an initialization reset signal line Vref1, and the anode reset signal line Vref2 and the initialization reset signal line Vref1 each include a first reset line 231 and a second reset line 232. Referring to FIGS. 34-41, 44-51, 55-64, the reset signal line 230 can include an anode reset signal line Vref2, an initialization reset signal line Vref1, and a bias reset signal line DVH. For example, the anode reset signal line Vref2 and the initialization reset signal line Vref1 are described as follows: referring to FIGS. 11 and 13, the display panel 10 includes a second reset line 232 configured to transmit a signal of the anode reset signal line Vref2 and a second reset line 232 configured to transmit a signal of the initialization reset signal line Vref1, and the second reset line 232 is located in the film layer of the second metal layer 460; the display panel 10 includes a first reset line 231 configured to transmit a signal of the anode reset signal line Vref2 and a first reset line 231 configured to transmit a signal of the initialization reset signal line Vref1, and the first reset line 231 is located in the film layer of the first source-drain electrode layer 480. Referring to FIGS. 21 and 23, the display panel 10 includes a second reset line 232 configured to transmit a signal of the anode reset signal line Vref2 and a second reset line 232 configured to transmit a signal of the initialization reset signal line Vref1, and the second reset line 232 is located in the film layer of the second metal layer 460; the display panel 10 includes a first reset line 231 configured to transmit a signal of the anode reset signal line Vref2 and a first reset line 231 configured to transmit a signal of the initialization reset signal line Vref1, and the first reset line 231 is located in the film layer of the second source-drain electrode layer 4100. The first reset line 231 and the second reset line 232 for transmitting the same signal are electrically connected, that is, the first reset line 231 and the second reset line segment 232 for transmitting a signal of the anode reset signal line Vref2 are electrically connected, and the first reset line 231 and the second reset line 232 for transmitting different signals are insulated, that is, the first reset line 231 for transmitting a signal of the anode reset signal line Vref2 and the second reset line 232 for transmitting a signal of the initialization reset signal line Vref1 are insulated, so that the signal transmission in the display panel 10 is stable, and the display effect of the display panel 10 is ensured.

[0290] With reference to FIGS. 4, 6-14, 33-41, the pixel circuit 100 includes a reset transistor, the signal line 200 includes a reset signal line 230, and the reset signal line 230 is electrically connected to a first electrode of the reset transistor Ta; the reset signal line 230 includes a first reset line 231, and a plurality of first reset lines 231 extend along a first direction X1 and are arranged along a second direction X2; the first reset line 231 includes a fourth reset subpart 234 and a fifth reset subpart 235 which are disposed in different layers and are electrically connected; the fourth reset subpart 234 extends at least partially along the first direction X1, the fifth reset subpart 235 extends at least partially along the first direction X1, and along the first direction X1, the fourth reset subpart 234 and the fifth reset subpart 235 are alternately disposed.

[0291] The pixel circuit 100 includes a reset transistor Ta, and the reset signal line 230 electrically connected to the reset transistor Ta includes the first reset line 231, the extension direction of the first reset signal line 231 is the same as that of the first data connection line segment 222, that is, both extend along the first direction X1, and a plurality of first reset lines 231 are arranged along the second direction X2. Part of the first virtual auxiliary line segment 225 can be multiplexed as the first reset line 231, so that the film layer required by the first reset line 231 can be reduced, the film layer thickness of the display panel 10 as a whole can be reduced, and the process preparation cost of the display panel 10 can also be reduced.

[0292] The first reset line 231 can include the fourth reset subpart 234 and the fifth reset subpart 235 which are disposed in different layers and are electrically connected, and the extension directions of the fourth reset subpart 234 and the fifth reset subpart 235 are the same, both extending along the first direction X1. The fourth reset subpart 234 and the fifth reset subpart 235 are located at different film layers and are electrically connected, that is, the first reset line 231 as a whole extends along the first direction X1, which can be composed of a plurality of fourth reset subparts 234 and fifth reset subparts 235 which are alternately electrically connected and located at different film layers.

[0293] For example, referring to FIG. 12 and FIG. 13, the display panel 10 includes a first reset line 231 for transmitting a signal of an initialization reset signal line Vref1 and a first reset line 231 for transmitting a signal of an anode reset signal line Vref2. The first reset line 231 for transmitting the signal of the anode reset signal line Vref2 includes a fourth reset sub-portion 234a located at the first source-drain electrode layer 480 and a fifth reset sub-portion 235a located at the second source-drain electrode layer 4100; and the first reset line 231 for transmitting the signal of the initialization reset signal line Vref1 includes a fourth reset sub-portion 234b located at the first source-drain electrode layer 480 and a fifth reset sub-portion 235b located at the second source-drain electrode layer 4100. The fourth reset sub-portion 234a and the fifth reset sub-portion 235a are arranged in different layers and are electrically connected, thereby ensuring the transmission effect of the anode reset signal line Vref2; and the fourth reset sub-portion 234b and the fifth reset sub-portion 235b are arranged in different layers and are electrically connected, thereby ensuring the transmission effect of the initialization reset signal line Vref1. For example, referring to FIG. 39 and FIG. 40, the display panel 10 includes a first reset line 231 for transmitting a signal of a bias reset signal line DVH and a first reset line 231 for transmitting a signal of an anode reset signal line Vref2, and the connection mode is the same as above, which will not be repeated here.

[0294] Referring to FIG. 4, FIG. 6 and FIG. 33, the pixel circuit 100 includes at least one transistor including a first active layer poly; the pixel circuit 100 further includes a storage capacitor Cst including a first plate M1 and a second plate MC arranged oppositely, the second plate MC being located on a side of the first plate M1 away from the first active layer poly; the display panel 10 further includes a first semiconductor layer 420, a first metal layer 440, a second metal layer 460, a first source-drain electrode layer 480 and a second source-drain electrode layer 4100; the first active layer poly is located at the first semiconductor layer 420, the first plate M1 is located at the first metal layer 440, the second plate MC is located at the second metal layer 460, the first source-drain electrode layer 480 is located at a side of the second metal layer 460 away from the first active layer poly, and the second source-drain electrode layer 4100 is located at a side of the first source-drain electrode layer 480 away from the first active layer poly; a fourth reset sub-portion 234 is located at at least one of the first semiconductor layer 420, the first metal layer 440, the second metal layer 460, the first source-drain electrode layer 480 or the second source-drain electrode layer 4100; and a fifth reset sub-portion 235 is located at at least one of the first semiconductor layer 420, the first metal layer 440, the second metal layer 460, the first source-drain electrode layer 480 or the second source-drain electrode layer 4100.

[0295] Referring to FIGS. 4, 6 and 33, the transistors in the pixel circuit 100 can include a first active layer poly, and the first active layer poly is located in the first semiconductor layer 420. It can be understood that the transistors in the pixel circuit 100 are low-temperature polysilicon transistors. Referring to FIG. 6, along the direction away from the substrate 400, the film layer structure included in the pixel circuit 100 can be the substrate 400, the buffer layer 410, the first semiconductor layer 420, the first insulating layer 430, the first metal layer 440, the interlayer insulating layer 450, the second metal layer 460, the second insulating layer 470, the first source-drain electrode layer 480, the third insulating layer 490, the second source-drain electrode layer 4100, the planarization layer 4110 and the anode layer 4120. The pixel circuit 100 includes a storage capacitor Cst, and the storage capacitor Cst includes a corresponding first plate and a second plate. The film layer where the first plate is located is the film layer where the first metal layer 440 is located, and the film layer where the second plate is located is the film layer where the second metal layer 460 is located.

[0296] In the pixel circuit 100 described above, the fourth reset sub-portion 234 can be in the same layer as at least one of the first semiconductor layer 420, the first metal layer 440, the second metal layer 460, the first source-drain electrode layer 480 or the second source-drain electrode layer 4100. In this way, the fourth reset sub-portion 234 can be in the same layer as one of the film layers mentioned above, or can be in the same layer as at least two of the film layers mentioned above, and can be flexibly adjusted based on the film layer position where the fourth reset sub-portion 234 is located. Similarly, the fifth reset sub-portion 235 can be in the same layer as at least one of the first semiconductor layer 420, the first metal layer 440, the second metal layer 460, the first source-drain electrode layer 480 or the second source-drain electrode layer 4100. In this way, the fifth reset sub-portion 235 can be in the same layer as one of the film layers mentioned above, or can be in the same layer as at least two of the film layers mentioned above, and can be flexibly adjusted based on the film layer position where the fifth reset sub-portion 235 is located.

[0297] The film layer positions of the fourth reset sub-portion 234 and the fifth reset sub-portion 235 can be adaptively adjusted according to actual conditions, and the embodiments of the present application do not limit this. In this way, it can be shown that the reset signal line 230 has flexibility in setting.

[0298] Optionally, continuing to refer to FIG. 54, the pixel circuit 100 includes at least one first type transistor and at least one second type transistor, the first type transistor includes a first active layer poly and a first gate M1, the second type transistor includes a second active layer igzo, a second top gate Mg and a second bottom gate Mc, the first gate M1 is located on a side of the first active layer poly close to the second active layer igzo or a side of the first active layer poly away from the second active layer igzo, the second top gate Mc is located on a side of the second active layer igzo away from the first active layer poly, and the second bottom gate Mc is located on a side of the second active layer igzo close to the first active layer poly; the display panel further includes a first semiconductor layer 520, a first metal layer 540, a second metal layer 560, a second semiconductor layer 580, a third metal layer 5100, a first source-drain electrode layer 5120 and a second source-drain electrode layer 5140; the first active layer poly is located on the first semiconductor layer 520, the first gate M1 is located on the first metal layer 540, the second bottom gate Mc is located on the second metal layer 560, the second active layer igzo is located on the second semiconductor layer 580, the second top gate Mg is located on the third metal layer 5100, the first source-drain electrode layer 5120 is located on a side of the third metal layer 5100 away from the first active layer poly, and the second source-drain electrode layer 5140 is located on a side of the first source-drain electrode layer 5120 away from the first active layer poly; the fourth reset sub-part 234 is located on at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580, the third metal layer 5100, the first source-drain electrode layer 5120 or the second source-drain electrode layer 5140, and the fifth reset sub-part 235 is located on at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580, the third metal layer 5100, the first source-drain electrode layer 5120 or the second source-drain electrode layer 5140.

[0299] The pixel circuit 100 includes the first type transistor and the second type transistor, the first type transistor includes the first active layer poly, and the first active layer poly can include a silicon semiconductor part, so the first type transistor can be understood as a low-temperature polysilicon transistor. The second type transistor includes the second active layer igzo, and the second active layer 380 can include an oxide semiconductor part, so the second type transistor can be understood as an oxide transistor. Further, the pixel circuit 100 simultaneously includes the low-temperature polysilicon transistor and the oxide transistor, so the pixel circuit 100 has the advantages of small leakage current of the oxide transistor, and also has the advantages of high switching speed, high carrier mobility and small power of the low-temperature polysilicon transistor.

[0300] The first type transistor comprises a first active layer poly and a first gate M1, and the second type transistor comprises a second active layer igzo, a second top gate Mg and a second bottom gate Mc. The first gate M1 is located on one side of the first active layer poly close to the second active layer igzo, the second top gate Mg is located on one side of the second active layer igzo away from the first active layer poly, and the second bottom gate Mc is located on one side of the second active layer igzo close to the first active layer poly. Referring to FIG. 54, the film layer where the first gate M1 is located is located in the film layer where the first metal layer 540 is located, the film layer where the second bottom gate Mc is located is located in the film layer where the second metal layer 560 is located, and the film layer where the second top gate Mg is located is located in the film layer where the third metal layer 5100 is located. At this time, the first gate M1 is located on one side of the first active layer poly away from the substrate 500, and the first type transistor is a transistor in a top gate structure. The first gate M1 can also be located on one side of the first active layer poly away from the second active layer igzo (not shown in the figure), and at this time, the first type transistor is a transistor in a bottom gate structure. The present embodiment does not limit the positional relationship between the first gate and the first active layer.

[0301] In the pixel circuit 100, the fourth reset part 234 can be in the same layer as at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580, the third metal layer 5100, the first source-drain electrode layer 5120 and the second source-drain electrode layer 5140. Similarly, the fifth reset part 235 can be in the same layer as at least one of the first semiconductor layer 520, the first metal layer 540, the second metal layer 560, the second semiconductor layer 580, the third metal layer 5100, the first source-drain electrode layer 5120 and the second source-drain electrode layer 5140. Based on the film layer positions of the fourth reset part 234 and the fifth reset part 235, the film layer positions can be adaptively adjusted according to actual conditions, and the present embodiment does not limit this. In this way, the setting of the reset signal line 230 can be flexible.

[0302] With reference to FIGS. 2, 6-14, 17-32, 33-41, 44-51, the pixel circuit 100 includes at least one transistor including a first active layer poly, and the pixel circuit further includes a storage capacitor Cst including a first plate M1 and a second plate MC oppositely arranged, the second plate MC being located on a side of the first plate M1 away from the first active layer poly, and the display panel 10 further includes a first semiconductor layer 420, a first metal layer 440, a second metal layer 460, a first source-drain electrode layer 480, and a second source-drain electrode layer 4100; the first active layer poly is located on the first semiconductor layer 420, the first plate M1 is located on the first metal layer 440, the second plate MC is located on the second metal layer 460, the first source-drain electrode layer 480 is located on a side of the second metal layer 460 away from the first active layer poly, and the second source-drain electrode layer 4100 is located on a side of the first source-drain electrode layer 480 away from the first active layer poly; the display panel 10 further includes a first power supply line segment extending along a first direction X1; the first power supply line segment is located on the first source-drain electrode layer 480 and / or the second source-drain electrode layer 4100; the data signal line 210 is located on the first source-drain electrode layer 480 and / or the second source-drain electrode layer 4100; the data auxiliary line 221 further includes a second data connection line segment 226 extending along a second direction X2; the first data connection line segment 222 is located on the second source-drain electrode layer 4100, and the second data connection line segment 226 is located on the first source-drain electrode layer 480.

[0303] With reference to FIGS. 4, 6, and 33, the transistor of the pixel circuit 100 can include a first active layer poly, and the first active layer poly is located on the first semiconductor layer 420, which can be understood as that the transistor in the pixel circuit 100 is a low-temperature polysilicon transistor. With reference to FIG. 6, along a direction away from the substrate 400, the film layer structure included in the pixel circuit 100 can be the substrate 400, the buffer layer 410, the first semiconductor layer 420, the first insulating layer 430, the first metal layer 440, the interlayer insulating layer 450, the second metal layer 460, the second insulating layer 470, the first source-drain electrode layer 480, the third insulating layer 490, the second source-drain electrode layer 4100, the planarization layer 4110, and the anode layer 4120. The pixel circuit 100 includes a storage capacitor Cst including a corresponding first plate and a second plate. The film layer where the first plate is located is the film layer where the first metal layer 440 is located, and the film layer where the second plate is located is the film layer where the second metal layer 460 is located.

[0304] The display panel 10 comprises a power signal line electrically connected with the light emitting element 300. The power signal line comprises a first power line segment extending along the first direction X1. Taking a positive power signal PVDD transmitted by the first power line segment as an example, reference is made to FIGS. 7-14, 17-32, 33-41, 44-51. The first power line segment is located at the first source-drain electrode layer 480 and the second source-drain electrode layer 4100, and the data signal line 210 can be located at the second source-drain electrode layer 4100. Alternatively, the first power line segment and the data signal line 210 can also be arranged as follows: the first power line segment is located at the first source-drain electrode layer 480 and the second source-drain electrode layer 4100, and the data signal line 210 is located at the first source-drain electrode layer 480; or the first power line segment is located at the first source-drain electrode layer 480 and the second source-drain electrode layer 4100, and the data signal line 210 is located at the first source-drain electrode layer 480 and the second source-drain electrode layer 4100; or the first power line segment is located at the first source-drain electrode layer 480 or the second source-drain electrode layer 4100 only. That is, the film layer arrangement position of the first power line and the data signal line 210 can be adjusted according to the overall film layer arrangement of the display panel 10, that is, the arrangement of the first power line and the data signal line 210 has diversity.

[0305] The data auxiliary line 221 can further comprise a second data connection line segment 226 extending along the second direction X2. For example, the first data connection line segment 222 is electrically connected with the data signal line 210 in the second display area AA2 through the second data connection line segment 226, as shown in FIG. 2. The first data connection line segment 222 can be located at the second source-drain electrode layer 4100, and the second data connection line segment 226 can be located at the first source-drain electrode layer 480, as shown in FIGS. 12 and 13. The film layer arrangement of the first data connection line segment 222 and the second data connection line segment 226 can be adjusted according to the overall film layer arrangement of the display panel 10, and the film layer arrangement position of the data auxiliary line 221 is related to the film layer arrangement position of the data signal line 210, and the film layer arrangement position of the first data connection line segment 222 and the second data connection line segment 226 can be adjusted adaptively according to the adjustment of the data signal line 210, that is, the film layer arrangement of the data auxiliary line 221 has flexibility.

[0306] FIG. 87 is another schematic view of a film layer structure of the pixel circuit shown in FIG. 4. Referring to FIGS. 4, 33 and 87, the pixel circuit 100 includes at least one transistor including a first active layer poly. The pixel circuit 100 further includes a storage capacitor Cst including a first plate M1 and a second plate MC oppositely arranged, the second plate MC being located on a side of the first plate M1 away from the first active layer poly. The display panel 10 further includes a first semiconductor layer 420, a first metal layer 440, a second metal layer 460, a first source-drain electrode layer 480, a second source-drain electrode layer 4100 and a third source-drain electrode layer 4140. The first active layer poly is located on the first semiconductor layer 420, the first plate M1 is located on the first metal layer 440, the second plate MC is located on the second metal layer 460, the first source-drain electrode layer 480 is located on a side of the second metal layer 460 away from the first active layer poly, the second source-drain electrode layer 4100 is located on a side of the first source-drain electrode layer 480 away from the first active layer poly, and the third source-drain electrode layer 4140 is located on a side of the second source-drain electrode layer 4100 away from the first active layer poly. The display panel 10 further includes a first power supply line segment extending along a first direction X1. The first power supply line segment is located on the second source-drain electrode layer 4100 and / or the third source-drain electrode layer 4140. The data signal line 210 is located on the second source-drain electrode layer 4100 and / or the third source-drain electrode layer 4160. The data auxiliary line 221 further includes a second data connection line segment 226 extending along a second direction X2. The first data connection line segment 222 is located on the third source-drain electrode layer 4140, and the second data connection line segment 226 is located on the second source-drain electrode layer 4100.

[0307] The display panel 10 includes a power supply signal line electrically connected with the light emitting element 300. The power supply signal line includes a first power supply line segment extending along the first direction X1. Taking the first power supply line segment transmitting a positive power supply signal PVDD as an example for illustration. The first power supply line segment is located on the second source-drain electrode layer 4100 or the third source-drain electrode layer 4140. Meanwhile, the data signal line 210 can be located on the second source-drain electrode layer 4100 or the third source-drain electrode layer 4140. Optionally, the arrangement mode of the first power supply line segment and the data signal line 210 can also be that the first power supply line segment is located on the second source-drain electrode layer 4100 and the third source-drain electrode layer 4140, and the data signal line 210 is located on the second source-drain electrode layer 4100 and the third source-drain electrode layer 4140. That is, the film layer arrangement position of the first power supply line and the data signal line 210 can be adjusted according to the overall film layer adjustment of the display panel 10, that is, the arrangement mode of the first power supply line and the data signal line 210 has diversity. It should be noted that the insulating layer is not shown in FIG. 87.

[0308] The data auxiliary line 221 can further include a second data connection line segment 226, and the second data connection line segment 226 extends along a second direction X2. For example, as shown in FIG. 2, the first data connection line segment 222 is electrically connected to the data signal line 210 in the second display area AA2 through the second data connection line segment 226. The first data connection line segment 222 can be located in the third source-drain electrode layer 4140, and the second data connection line segment 226 can be located in the second source-drain electrode layer 4100. The film layer arrangement of the first data connection line segment 222 and the second data connection line segment 226 can be adjusted according to the overall film layer arrangement of the display panel 10, and the film layer arrangement position of the data auxiliary line 221 is related to the film layer arrangement position of the data signal line 210. The film layer arrangement position of the first data connection line segment 222 and the second data connection line segment 226 can be adjusted adaptively according to the adjustment of the data signal line 210, that is, the film layer arrangement of the data auxiliary line 221 is flexible.

[0309] Referring to FIG. 24, the display panel 10 further includes light emitting elements 300 electrically connected to the pixel circuit 100; the light emitting elements 300 include first color light emitting elements 300A, second color light emitting elements 300B, and third color light emitting elements 300C, the first color light emitting elements 300A, the second color light emitting elements 300B, and the third color light emitting elements 300C are one of red light emitting elements, blue light emitting elements, and green light emitting elements and are different from each other; a plurality of first color light emitting elements 300A and second color light emitting elements 300B form a first virtual quadrilateral 21, the first color light emitting elements 300A are at first vertices of the first virtual quadrilateral 21, centers of the second color light emitting elements 300B are at second vertices of the first virtual quadrilateral 21, the first vertices and the second vertices are alternately and spaced apart, and the third color light emitting elements 300C are inside the first virtual quadrilateral 21; a plurality of third color light emitting elements 300C form a second virtual quadrilateral 22, centers of the plurality of third color light emitting elements 300C are at vertices of the second virtual quadrilateral 22 respectively, and the first color light emitting elements 300A or the second color light emitting elements 300B are inside the second virtual quadrilateral.

[0310] Referring to FIG. 24, the display panel 10 further includes light emitting elements 300 electrically connected to the pixel circuit 100; the light emitting elements 300 include first color light emitting elements 300A, second color light emitting elements 300B, and third color light emitting elements 300C, the first color light emitting elements 300A, the second color light emitting elements 300B, and the third color light emitting elements 300C are one of red light emitting elements, blue light emitting elements, and green light emitting elements and are different from each other; a plurality of first color light emitting elements 300A and second color light emitting elements 300B form a first virtual quadrilateral 21, the first color light emitting elements 300A are at first vertices of the first virtual quadrilateral 21, centers of the second color light emitting elements 300B are at second vertices of the first virtual quadrilateral 21, the first vertices and the second vertices are alternately and spaced apart, and the third color light emitting elements 300C are inside the first virtual quadrilateral 21; a plurality of third color light emitting elements 300C form a second virtual quadrilateral 22, centers of the plurality of third color light emitting elements 300C are at vertices of the second virtual quadrilateral 22 respectively, and the first color light emitting elements 300A or the second color light emitting elements 300B are inside the second virtual quadrilateral.

[0311] The plurality of third color light emitting elements 300C can also constitute a second virtual quadrilateral 22, in which the first color light emitting element 300A can be located at the center or the second color light emitting element 300B can be located at the center. The overall arrangement mode is similar to the "diamond" pixel arrangement.

[0312] The first color, the second color and the third color correspond to one of red, blue and green respectively. Through the arrangement mode of the light emitting element 300 described above, the rendering effect of the light emitting element 300 can be better, and the color display effect of the display panel 10 is further ensured.

[0313] The display panel provided by the embodiment of the present application includes a signal line, the signal line includes a data signal line and a data auxiliary line, the data signal line located in the first display area is electrically connected with the fan-out wire, and the data signal line located in the second display area is electrically connected with the fan-out wire through the data auxiliary line. In this way, the data signal line in the second display area can be avoided from being directly electrically connected with the fan-out wire, the area of the fan-out area can be avoided from being increased due to the setting of the fan-out wire, the area ratio of the display area is improved, and the screen ratio of the display panel is improved. The data auxiliary line includes a first data connection line segment in the same first direction as the data signal line, a plurality of pixel circuit setting areas arranged continuously in a second direction, and the number of the first data connection line segments is different from the number of the pixel circuits, that is, in the area corresponding to the n pixel circuits arranged continuously in the second direction, m first data connection line segments are arranged, n≠m, for example, n>m or n<m, that is, the number of the first data connection line segments is diverse, so that the flexible setting mode of the auxiliary line in the display panel is embodied, and the setting mode of the first data connection line segment in the display panel can be adjusted diversely. When n>m, the number of the first data connection line segments is less than the number of the corresponding pixel circuits, so that the number of the first data connection line segments is small, the setting mode of the first data connection line segment is simple, the process of the display panel can be avoided from being complicated due to the increase of the first data connection line segment, so that the yield loss can be reduced, and the process preparation cost of the display panel is reduced. When n<m, more first data connection line segments can be connected with more data signal lines located in the second display area, that is, more data signal lines can be connected to the fan-out wire through the data auxiliary line, the number of the data signal lines directly connected with the fan-out wire can be reduced, the number of the fan-out wires can be reduced, the space of the non-display area occupied by the fan-out wire can be reduced, the area ratio of the display area is improved, and the screen ratio of the display panel is improved.

[0314] Based on the same inventive concept, the embodiment of the present application further provides a display device. FIG. 88 is a structural schematic diagram of a display device provided by the embodiment of the present application. As shown in FIG. 88, the display device 1 includes the display panel 10 described in any of the above embodiments, which will not be repeated here. For example, the display device 1 can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), a vehicle-mounted display device, and the like, and the embodiment of the present application is not limited thereto.

Claims

1. A display panel, comprising a plurality of pixel circuits and a plurality of signal lines; the signal lines comprise data signal lines, a plurality of the data signal lines extend along a first direction and are arranged along a second direction; a plurality of the pixel circuits arranged along the first direction are electrically connected to a same data signal line; the first direction and the second direction intersect; the signal lines further comprise a plurality of auxiliary lines; the display panel further comprises a display area and a non-display area at least partially surrounding the display area, the display area comprises a first display area and a second display area, the second display area is located at least one side of the first display area along the second direction; the first display area and the second display area each comprise a plurality of the data signal lines; the non-display area comprises a fan-out area located at one side of the display area along the first direction, the fan-out area comprises a plurality of fan-out wires; the auxiliary lines comprise data auxiliary lines, the data signal lines in the second display area are electrically connected to the fan-out wires through the data auxiliary lines; the data auxiliary lines comprise first data connection line segments extending along the first direction; in a region corresponding to n pixel circuits arranged continuously along the second direction, m first data connection line segments are arranged; wherein n≠m, and n and m are positive integers.

2. The display panel of claim 1, wherein, n along the second direction, the first display area and the second display area each comprise a plurality of first pixel circuit groups and a plurality of first data signal line groups, a plurality of the first data signal line groups are arranged along the second direction; the first pixel circuit group comprises n pixel circuits arranged adjacently along the second direction; the first data signal line group comprises n data signal lines arranged adjacently along the second direction, and the data signal lines in a same first data signal line group are electrically connected to the pixel circuits in a same first pixel circuit group; the first display area further comprises a plurality of first data connection line segment groups, a plurality of the first data connection line segment groups are arranged along the second direction, and the first data connection line segment group comprises m first data connection line segments; along the second direction, m first data connection line segments in a same first data connection line segment group are located within a limited range of n data signal lines in a same first data signal line group; at least part of the first data connection line segments in a same first data connection line segment group are electrically connected to the data signal lines in at least two first data signal line groups arranged adjacently along the second direction.

3. The display panel of claim 2, wherein, the first data connection line segments in a same first data connection line segment group are electrically connected to the data signal lines in x first data signal line groups arranged adjacently along the second direction; wherein and x is an integer.

4. The display panel of claim 2, wherein, n=2, m≥3; the first data signal line group comprises a first alpha data signal line and a first beta data signal line arranged along the second direction; the data auxiliary lines further comprise second data connection line segments extending along the second direction; In the second display area, along the direction from the first display area to the second display area, the second display area includes A first data signal line groups; along the direction from the display area to the fan-out area, 2*A second data connection line segments are arranged in sequence; along the direction from the first display area to the second display area, the first display area includes C first data connection line segment groups; A is an integer greater than or equal to 1, and C is an integer greater than or equal to 1 and less than or equal to A; The first alpha data signal line in the a-th first data signal line group of the second display area is electrically connected with the b-th second data connection line segment, and the b-th second data connection line segment is electrically connected with the i-th first data connection line segment in the c-th first data connection line segment group of the first display area; wherein a, b, c and i are positive integers, and a is less than or equal to A, b is less than or equal to 2*A-1, c is less than or equal to C, and i is less than or equal to m-1; The first beta data signal line in the a-th first data signal line group of the second display area is electrically connected with the (b+1)-th second data connection line segment, and the (b+1)-th second data connection line segment is electrically connected with the (i+1)-th first data connection line segment in the c-th first data connection line segment group of the first display area.

5. The display panel of claim 2, wherein, n=2, m≥3; the first data signal line group includes first alpha data signal lines and first beta data signal lines arranged along the second direction; The data auxiliary line further includes a second data connection line segment extending along the second direction; In the second display area, along the direction from the first display area to the second display area, the second display area includes A first data signal line groups; along the direction from the display area to the fan-out area, 2*A second data connection line segments are arranged in sequence; along the direction from the first display area to the second display area, the first display area includes C first data connection line segment groups; A is an integer greater than or equal to 1, and C is an integer greater than or equal to 1 and less than or equal to A; The first alpha data signal line in the a-th first data signal line group of the second display area is electrically connected with the b-th second data connection line segment, and the b-th second data connection line segment is electrically connected with the m-th first data connection line segment in the c-th first data connection line segment group of the first display area; wherein a, b and c are positive integers, and a is less than or equal to A, b is less than or equal to 2*A-1, and c is less than or equal to C; The first beta data signal line in the a-th first data signal line group of the second display area is electrically connected with the (b+1)-th second data connection line segment, and the (b+1)-th second data connection line segment is electrically connected with the first first data connection line segment in the (c+1)-th first data connection line segment group of the first display area. n>m; 6. The display panel of claim 1, wherein, Along the second direction, the first display area and the second display area each include a plurality of second pixel circuit groups and a plurality of second data signal line groups, and the plurality of second data signal line groups are arranged along the second direction; ​ The second pixel circuit group comprises n pixel circuits arranged adjacently along the second direction; the second data signal line group comprises n data signal lines arranged adjacently along the second direction, and the data signal lines in the same second data signal line group are electrically connected with the pixel circuits in the same second pixel circuit group; The first display area further comprises a plurality of second data connection line segment groups, the plurality of second data connection line segment groups are arranged along the second direction, and the second data connection line segment group comprises m first data connection line segments; The data signal lines in the same second data signal line group are electrically connected with the first data connection line segments in at least two second data connection line segment groups arranged adjacently along the second direction.

7. The display panel of claim 6, wherein, The data signal lines in the same second data signal line group are electrically connected with the first data connection line segments in y second data connection line segment groups arranged adjacently along the second direction; wherein, And y is an integer.

8. The display panel of claim 6, wherein, The data auxiliary line further comprises a second data connection line segment extending along the second direction; In one of the second display areas, along the direction of the first display area pointing to the second display area, the second display area includes D groups of the second data signal lines; along the direction of the display area pointing to the fan-out area, D*n second data connection line segments are arranged in sequence; along the direction of the first display area pointing to the second display area, the first display area includes F groups of the second data connection line segments; D≥1 and is an integer, And F is an integer. The jth data signal line in the dth second data signal line group of the second display area is electrically connected with the e th second data connection line segment, and the e th second data connection line segment is electrically connected with the kth first data connection line segment in the f th second data connection line segment group of the first display area; The j+hth data signal line in the dth second data signal line group of the second display area is electrically connected with the e+hth second data connection line segment, and the e+hth second data connection line segment is electrically connected with the k+hth first data connection line segment in the f th second data connection line segment group of the first display area; wherein d, e, f, j, k and h are positive integers, and d≤D, f≤F, j+h≤n, k+h≤m. The data auxiliary line further comprises a second data connection line segment extending along the second direction; 9. The display panel of claim 6, wherein, And F is an integer. In the second display area, along the direction of the first display area pointing to the second display area, the second display area includes D groups of the second data signal lines; along the direction of the display area pointing to the fan-out area, D*n second data connection line segments are arranged in sequence; along the direction of the first display area pointing to the second display area, the first display area includes F groups of the second data connection line segments; D≥1 and is an integer, The jth data signal line in the dth second data signal line group of the second display area is electrically connected with the e th second data connection line segment, and the e th second data connection line segment is electrically connected with the kth first data connection line segment in the f th second data connection line segment group of the first display area; The j+(m-k)th data signal line in the dth second data signal line group of the second display area is electrically connected with the e+(m-k)th second data connection line segment, and the e+(m-k)th second data connection line segment is electrically connected with the mth first data connection line segment in the f th second data connection line segment group of the first display area; The j+(m-k)th data signal line in the dth second data signal line group of the second display area is electrically connected with the e+(m-k)th second data connection line segment, and the e+(m-k)th second data connection line segment is electrically connected with the mth first data connection line segment in the f th second data connection line segment group of the first display area; wherein d, e, f, j, k and h are positive integers, and d≤D, f≤F, j+h≤n, k+h>m. The j+hth data signal line in the dth second data signal line group of the second display area is electrically connected with the e+hth second data connection line segment, the e+hth second data connection line segment is electrically connected with the f+hth data signal line in the e th data signal line group of the first display area, and the f+hth data signal line in the e th data signal line group of the first display area is electrically connected with the g+hth data signal line in the fth data signal line group of the first display area. a first data connection line segment group of the second data connection line segment group n is an even number.

10. The display panel of claim 6, wherein, Along the second direction, the length of the first display area is L1, and the length of the second display area is L2; 11. The display panel of claim 6, wherein, ​ Along the second direction, one side of the first display area is provided with the second display area, and L1 / L2≥n / m; or Along the second direction, two sides of the first display area are provided with the second display area, and L1 / L2≥2*(n / m).

12. The display panel of claim 1, wherein, The auxiliary line further includes a virtual auxiliary line, the virtual auxiliary line includes a first virtual auxiliary line segment located in the first display area and extending along the first direction, and the first virtual auxiliary line segment is insulated from the first data connection line segment; At least part of the first virtual auxiliary line segment is located between the data signal line and the first data connection line segment arranged adjacent along the second direction.

13. The display panel of claim 12, wherein, The first virtual auxiliary line segment is electrically connected with a fixed potential signal line.

14. The display panel of claim 13, wherein, The pixel circuit includes a reset transistor, the signal line includes a reset signal line, and the reset signal line is electrically connected with a first electrode of the reset transistor; The reset signal line includes a first reset line, and a plurality of first reset lines extend along the first direction and are arranged along the second direction; At least part of the first virtual auxiliary line segment is multiplexed as the first reset line.

15. The display panel of claim 14, wherein, The reset transistor includes an initial reset transistor and an anode reset transistor; The reset signal line includes an initial reset signal line and an anode reset signal line; The pixel circuit further includes a driving transistor, and the display panel further includes a light emitting element; The initial reset transistor is electrically connected between the initial reset signal line and a gate electrode of the driving transistor; and the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element.

16. The display panel of claim 15, wherein, The initial reset signal line includes a first initial reset line, and a plurality of first initial reset lines extend along the first direction and are arranged along the second direction, and the first reset line includes the first initial reset line; or The anode reset signal line includes a first anode reset line, and a plurality of first anode reset lines extend along the first direction and are arranged along the second direction, and the first reset line includes the first anode reset line; or The initial reset signal line includes a first initial reset line, and a plurality of first initial reset lines extend along the first direction and are arranged along the second direction, and the anode reset signal line includes a first anode reset line, and a plurality of first anode reset lines extend along the first direction and are arranged along the second direction, and the first reset line includes the first initial reset line and the first anode reset line.

17. The display panel of claim 16, wherein, The first reset line includes the first initial reset line and the first anode reset line; Along the second direction, the first initial reset line and the first anode reset line are alternately arranged.

18. The display panel of claim 15, wherein, The reset transistor further includes a bias reset transistor and a driving transistor; The reset signal line further includes a bias reset signal line; The bias reset transistor is electrically connected between the bias reset signal line and at least one of a first electrode and a second electrode of the driving transistor.

19. The display panel of claim 18, wherein, The bias reset signal line includes a first bias reset line, and a plurality of first bias reset lines extend along the first direction and are arranged along the second direction; The first reset line includes the first bias reset line.

20. The display panel of claim 19, wherein, The initial reset signal line includes a first initial reset line, and a plurality of the first initial reset lines extend along the first direction and are arranged along the second direction; the anode reset signal line includes a first anode reset line, and a plurality of the first anode reset lines extend along the first direction and are arranged along the second direction; the first reset line further includes the first initial reset line and the first anode reset line; the first initial reset line, the first anode reset line and the first bias reset line are arranged along the second direction. Or, The anode reset signal line includes a first anode reset line, and a plurality of the first anode reset lines extend along the first direction and are arranged along the second direction, and the first reset line further includes the first anode reset line; along the second direction, the first anode reset line and the first bias reset line are arranged alternately. Or, The initial reset signal line includes a first initial reset line, and a plurality of the first initial reset lines extend along the first direction and are arranged along the second direction; the anode reset signal line includes a first anode reset line, and a plurality of the first anode reset lines extend along the first direction and are arranged along the second direction; the first reset line further includes the first initial reset line and the first anode reset line; the first initial reset line, the first anode reset line and the first bias reset line are arranged along the second direction.

21. The display panel of claim 20, wherein, n > m; The display area further includes a first auxiliary line segment group and a second auxiliary line segment group arranged adjacent along the second direction; the first auxiliary line segment group includes a first alpha reset line and a first non-reset line arranged adjacent along the first direction and along the second direction, and the first non-reset line includes at least one of the first data connection line segment and the first power line segment; the second auxiliary line segment group includes a first beta reset line and a second non-reset line arranged adjacent along the first direction and along the second direction, and the second non-reset line includes at least one of the first data connection line segment and the first power line segment; the first alpha reset line and the first beta reset line are insulated; The direction in which the first alpha reset line points to the first non-reset line is opposite to the direction in which the first beta reset line points to the second non-reset line.

22. The display panel of claim 13, wherein, The signal line further includes a power signal line, and the power signal line includes a first power line segment, and a plurality of the first power line segments extend along the first direction and are arranged along the second direction; The display panel further includes a light emitting element, and the power signal line is electrically connected to an anode of the light emitting element, or the power signal line is electrically connected to a cathode of the light emitting element, or a part of the power signal line is electrically connected to the anode of the light emitting element and another part of the power signal line is electrically connected to the cathode of the light emitting element; At least part of the first virtual auxiliary line segment is multiplexed as the first power line segment.

23. The display panel of claim 22, wherein, The power signal line includes a first power signal line and a second power signal line, the first power signal line is electrically connected to the anode of the light emitting element, and the second power signal line is electrically connected to the cathode of the light emitting element; The first power signal line includes a first alpha power line segment, a plurality of the first alpha power line segments extend along the first direction and are arranged along the second direction, and at least part of the first virtual auxiliary line segment is multiplexed as the first alpha power line segment; or the second power signal line includes a first beta power line segment, a plurality of the first beta power line segments extend along the first direction and are arranged along the second direction, and at least part of the first virtual auxiliary line segment is multiplexed as the first beta power line segment; or the first power signal line includes a first alpha power line segment, a plurality of the first alpha power line segments extend along the first direction and are arranged along the second direction, and the second power signal line further includes a first beta power line segment, a plurality of the first beta power line segments extend along the first direction and are arranged along the second direction, and at least part of the first virtual auxiliary line segment is multiplexed as the first alpha power line segment and the first beta power line segment.

24. The display panel of claim 14, wherein, The reset signal line further includes a second reset line, the second reset line extends at least partially along the second direction, and the second reset line is arranged in a layer different from the first reset line.

25. The display panel of claim 24, wherein, The second reset line includes a first reset subpart; The first reset subpart extends along the second direction, and along the second direction, the first reset subparts located in the same film layer continuously pass through the display area of the display panel.

26. The display panel of claim 25, wherein, The pixel circuit includes at least one transistor, and the transistor includes a first active layer; The pixel circuit further includes a storage capacitor, and the storage capacitor includes a first plate and a second plate arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer; The display panel further includes a first semiconductor layer, a first metal layer, and a second metal layer, the first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, and the second plate is located in the second metal layer; The first reset subpart is located in at least one of the first semiconductor layer, the first metal layer, or the second metal layer. The pixel circuit includes at least one first type transistor and at least one second type transistor, the first type transistor includes a first active layer and a first gate, the second type transistor includes a second active layer, a second top gate, and a second bottom gate, the first gate is located on a side of the first active layer close to the second active layer or on a side of the first active layer away from the second active layer, the second top gate is located on a side of the second active layer away from the first active layer, and the second bottom gate is located on a side of the second active layer close to the first active layer; 27. The display panel of claim 25, wherein, The display panel further includes a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, and a third metal layer; the first active layer is located in the first semiconductor layer, the first gate is located in the first metal layer, the second bottom gate is located in the second metal layer, the second active layer is located in the second semiconductor layer, and the second top gate is located in the third metal layer; ​ The first reset sub-part is located in at least one of the first semiconductor layer, the first metal layer, the second metal layer, the second semiconductor layer, or the third metal layer.

28. The display panel of claim 24, wherein, The second reset line comprises a second reset sub-part and a third reset sub-part which are arranged in different layers and electrically connected. The second reset sub-part extends at least partially along the second direction, the third reset sub-part extends at least partially along the second direction, and along the second direction, the second reset sub-part and the third reset sub-part are arranged alternately.

29. The display panel of claim 28, wherein, The pixel circuit comprises at least one transistor, and the transistor comprises a first active layer. The pixel circuit further comprises a storage capacitor, and the storage capacitor comprises a first plate and a second plate which are arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer. The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, and a first source-drain electrode layer. The first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, the second plate is located in the second metal layer, and the first source-drain electrode layer is located on a side of the second metal layer away from the first active layer. The second reset sub-part is located in at least one of the first semiconductor layer, the first metal layer, the second metal layer, or the first source-drain electrode layer, and the third reset sub-part is located in at least one of the first semiconductor layer, the first metal layer, the second metal layer, or the first source-drain electrode layer.

30. The display panel of claim 28, wherein, The pixel circuit comprises at least one first type transistor and at least one second type transistor, the first type transistor comprises a first active layer and a first gate, the second type transistor comprises a second active layer, a second top gate, and a second bottom gate, the first gate is located on a side of the first active layer close to the second active layer or on a side of the first active layer away from the second active layer, the second top gate is located on a side of the second active layer away from the first active layer, and the second bottom gate is located on a side of the second active layer close to the first active layer. The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, and a first source-drain electrode layer. The first active layer is located in the first semiconductor layer, the first gate is located in the first metal layer, the second bottom gate is located in the second metal layer, the second active layer is located in the second semiconductor layer, the second top gate is located in the third metal layer, and the first source-drain electrode layer is located on a side of the third metal layer away from the first active layer. The second reset sub-part is located in at least one of the first semiconductor layer, the first metal layer, the second metal layer, the second semiconductor layer, the third metal layer, or the first source-drain electrode layer, and the third reset sub-part is located in at least one of the first semiconductor layer, the first metal layer, the second metal layer, the second semiconductor layer, the third metal layer, or the first source-drain electrode layer.

31. The display panel of claim 24, wherein, The second reset line is electrically connected to the first reset line through a via.

32. The display panel of claim 24, wherein, The second reset line is insulated from the first reset line.

33. The display panel of claim 1, wherein, The pixel circuit includes a reset transistor, and the signal line includes a reset signal line electrically connected to a first electrode of the reset transistor. The reset signal line includes a first reset line, and a plurality of first reset lines extend along the first direction and are arranged along the second direction. The first reset line includes a fourth reset sub-portion and a fifth reset sub-portion which are disposed in different layers and electrically connected. The fourth reset sub-portion extends at least partially along the first direction, and the fifth reset sub-portion extends at least partially along the first direction, and along the first direction, the fourth reset sub-portion and the fifth reset sub-portion are alternately arranged.

34. The display panel of claim 33, wherein, The pixel circuit includes at least one transistor, and the transistor includes a first active layer. The pixel circuit further includes a storage capacitor including a first plate and a second plate arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer. The display panel further includes a first semiconductor layer, a first metal layer, a second metal layer, a first source-drain electrode layer, and a second source-drain electrode layer. The first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, the second plate is located in the second metal layer, the first source-drain electrode layer is located on a side of the second metal layer away from the first active layer, and the second source-drain electrode layer is located on a side of the first source-drain electrode layer away from the first active layer. The fourth reset sub-portion is located in at least one of the first semiconductor layer, the first source-drain electrode layer, or the second source-drain electrode layer; and the fifth reset sub-portion is located in at least one of the first semiconductor layer, the first source-drain electrode layer, or the second source-drain electrode layer.

35. The display panel of claim 33, wherein, The pixel circuit includes at least one first type transistor and at least one second type transistor, the first type transistor includes a first active layer and a first gate, and the second type transistor includes a second active layer, a second top gate, and a second bottom gate, the first gate is located on a side of the first active layer close to the second active layer or on a side of the first active layer away from the second active layer, the second top gate is located on a side of the second active layer away from the first active layer, and the second bottom gate is located on a side of the second active layer close to the first active layer. The display panel further includes a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a first source-drain electrode layer, and a second source-drain electrode layer. The first active layer is located in the first semiconductor layer, the first gate is located in the first metal layer, the second bottom gate is located in the second metal layer, the second active layer is located in the second semiconductor layer, the second top gate is located in the third metal layer, the first source-drain electrode layer is located on a side of the third metal layer away from the first active layer, and the second source-drain electrode layer is located on a side of the first source-drain electrode layer away from the first active layer. The fourth reset sub-part is located in at least one of the first semiconductor layer, the second semiconductor layer, the first source-drain electrode layer or the second source-drain electrode layer, and the fifth reset sub-part is located in at least one of the first semiconductor layer, the second semiconductor layer, the first source-drain electrode layer or the second source-drain electrode layer.

36. The display panel of claim 1, wherein, The pixel circuit comprises at least one transistor, and the transistor comprises a first active layer; The pixel circuit further comprises a storage capacitor, and the storage capacitor comprises a first plate and a second plate arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer; The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a first source-drain electrode layer and a second source-drain electrode layer; The first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, the second plate is located in the second metal layer, the first source-drain electrode layer is located on a side of the second metal layer away from the first active layer, and the second source-drain electrode layer is located on a side of the first source-drain electrode layer away from the first active layer; The display panel further comprises a first power line segment, and the first power line segment extends along the first direction; the first power line segment is located in at least one of the first source-drain electrode layer and the second source-drain electrode layer; and the data signal line is located in at least one of the first source-drain electrode layer and the second source-drain electrode layer; The data auxiliary line further comprises a second data connection line segment extending along the second direction; The first data connection line segment is located in the second source-drain electrode layer, and the second data connection line segment is located in the first source-drain electrode layer. The pixel circuit comprises at least one transistor, and the transistor comprises a first active layer; 37. The display panel of claim 1, wherein, The pixel circuit further comprises a storage capacitor, and the storage capacitor comprises a first plate and a second plate arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer; The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a first source-drain electrode layer, a second source-drain electrode layer and a third source-drain electrode layer; the first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, the second plate is located in the second metal layer, the first source-drain electrode layer is located on a side of the second metal layer away from the first active layer, the second source-drain electrode layer is located on a side of the first source-drain electrode layer away from the first active layer, and the third source-drain electrode layer is located on a side of the second source-drain electrode layer away from the first active layer; The display panel further comprises a first power line segment, and the first power line segment extends along the first direction; the first power line segment is located in at least one of the second source-drain electrode layer and the third source-drain electrode layer; and the data signal line is located in at least one of the second source-drain electrode layer and the third source-drain electrode layer; The data auxiliary line further comprises a second data connection line segment extending along the second direction; The first data connection line segment is located in the second source-drain electrode layer, and the second data connection line segment is located in the first source-drain electrode layer. The first data connection line segment is located at the third source-drain electrode layer, and the second data connection line segment is located at the second source-drain electrode layer.

38. The display panel of claim 1, further comprising light emitting elements electrically connected with the pixel circuit. The light emitting elements comprise first color light emitting elements, second color light emitting elements and third color light emitting elements, the first color light emitting elements, the second color light emitting elements and the third color light emitting elements are one of red light emitting elements, blue light emitting elements and green light emitting elements and are different from each other; A plurality of the first color light emitting elements and a plurality of the second color light emitting elements constitute a first virtual quadrilateral, the first color light emitting elements are at first vertices of the first virtual quadrilateral, centers of the second color light emitting elements are at second vertices of the first virtual quadrilateral, the first vertices and the second vertices are alternated and spaced apart, and the third color light emitting elements are inside the first virtual quadrilateral; A plurality of the third color light emitting elements constitute a second virtual quadrilateral, centers of the plurality of the third color light emitting elements are at vertices of the second virtual quadrilateral respectively, and the first color light emitting elements or the second color light emitting elements are inside the second virtual quadrilateral.

39. A display device comprising the display panel of any one of claims 1-38.

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