Heap data structure for a field programmable gate array

Abstract

A circuit includes: a plurality of multi-port look-up table random access memory levels (LUTRAM levels); and a first controller of a plurality of controllers for a first LUTRAM level at a root heap level is configured to, for a new data value to insert into the heap, in a first clock cycle, at a first comparison circuit of the first controller: compare the new data value with a data value at a root node of the root heap level; provide a first comparison result for writing to a root node memory index of the first LUTRAM level; and provide a second comparison result to write to a first wiredata register.

Description

Attorney Docket No. 24-2517 WOHEAP DATA STRUCTURE FOR A FIELD PROGRAMMABLE GATE ARRAYCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This PCT International Patent Application claims the benefit of and priority to U.S. Provisional Patent Application Serial No. 63 / 691,586 filed September 6, 2024, the contents of which are incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure generally relates to an implementation of a heap data structure for a binary minimum heap (“heap”) in a field-programmable gate array (FPGA) that reduces latency during heap updating and memory usage for storing data of the heap.BACKGROUND

[0003] A heap data structure may be used, for example, in connection with an electronic financial asset trading platform that receives orders from multiple clients, and distributes the orders to trading exchanges in a chronological order based on time stamps that the platform determines for the respective orders.SUMMARY

[0004] An aspect of the disclosed embodiments includes a programmable integrated circuit that includes a field-programmable gate array (FPGA) that implements a heap data structure. The programmable integrated circuit further includes: a plurality of memory levels; a plurality of first- in-first out (FIFO) memories (“FIFO levels”) for respective heap levels of a heap instantiated by the heap data structure; and a controller that, in response to a new data value for insertion into the heap arriving at the circuit, is configured to: in a clock cycle corresponding to the new data value arriving, (i) determine, based on status information from respective FIFO levels, a destination heapAttorney Docket No. 24-2517 WO level to fill and a node to fill in the destination heap level to fill, and (ii) determine update nodes for the heap, based on the node to fill in the destination heap level to fill and insertion information stored in a memory; and update the heap at the update nodes, wherein, in response to a first update node being filled and, in response to the first update node continuing to be filled after the first update node is updated, first status information for a first FIFO level corresponding to a first heap level including the first update node is maintained; and wherein second status information for a second FIFO level corresponding to a second heap level including a second update node is changed in response to at least one of (i) the second update node not being filled and, after the second update node is updated, the second update node is filled, and (ii) the second update node is filled and, after the second update node is updated, the second update node is not filled.

[0005] Another aspect of the disclosed embodiments includes a circuit configured to implement a heap data structure. The circuit includes: a plurality of multi-port look-up table random access memory levels (LUTRAM levels), each of the LUTRAM levels corresponding to respective heap levels of a heap instantiated by the heap data structure; and a first controller of a plurality of controllers each corresponding to respective LUTRAM levels. The first controller may be configured to, for a first LUTRAM level at a root heap level and after a data value is available for output from a root node of the heap in a first clock cycle, in a same second clock cycle: receive, from a second LUTRAM level, data values, if any, of left and right child nodes in the second LUTRAM level, which are relative to a root parent node in the first LUTRAM level; compare the data values respectively of the left and right child nodes, to determine a comparison result; provide the comparison result for writing to a root node memory index in the first LUTRAM level in a third clock cycle; and provide, to a second controller of the plurality of controllers for the second LUTRAM level, a child node memory index corresponding to the comparison result.Attorney Docket No. 24-2517 WO

[0006] Another aspect of the disclosed embodiments includes a circuit including an FPGA that implements a heap data structure. The circuit includes: a plurality of multi-port look-up table random access memory levels (LUTRAM levels); and a first controller of a plurality of controllers for a first LUTRAM level at a root heap level is configured to, for a new data value to insert into a heap instantiated by the heap data structure, in a first clock cycle, at a first comparison circuit of the first controller: compare the new data value with a data value at a root node of the root heap level; provide a first comparison result for writing to a root node memory index of the first LUTRAM level; and provide a second comparison result to write to a first wiredata register.

[0007] These and other aspects of the present disclosure are disclosed in the following detailed description of the embodiments, the appended claims, and the accompanying figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to-scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity.

[0009] FIG. 1 generally illustrates a heap data structure implemented in an FPGA, according to the principles of the present disclosure.

[0010] FIG. 1A generally illustrates an exemplary schematic of a FIFO for use in a heap data structure implemented in a FPGA, according to the principles of the present disclosure.

[0011] FIGs. 2-7 generally illustrate various aspects of a heap data structure implemented in an FPGA, according to the principles of the present disclosure.

[0012] FIG. 8A generally illustrates an update node calculation results table, according to the principles of the present disclosure.Attorney Docket No. 24-2517 WO

[0013] FIG. 8B generally illustrates an example of a heap update for a data insertion, according to the principles of the present disclosure.

[0014] FIGs. 9 and 10 are flow diagrams generally illustrating a process for determining update nodes for each node to fill, according to the principles of the present disclosure.

[0015] FIG. 11-Al generally illustrates a LUTRAM of a multi-port LUTRAM, according to the principles of the present disclosure.

[0016] FIG. 11-A2 generally illustrates a block diagram of a multiple port LUTRAM, according to the principles of the present disclosure.

[0017] FIG. 11 generally illustrates circuitry of a heap data structure, according to the principles of the present disclosure.

[0018] FIGs. 12A and 12AA are flow diagrams generally illustrating a process for data insertion into a heap, according to the principles of the present disclosure.

[0019] FIGs. 12B and 12C generally illustrate clocking controls and operations corresponding to updating a heap for new data insertions, according to the principles of the present disclosure.

[0020] FIG. 13 generally illustrates circuitry of a heap data structure, according to the principles of the present disclosure.

[0021] FIGs. 14-Al to 14- A4 generally illustrate flow diagrams of a process for updating a heap for a data deletion, according to the principles of the present disclosure.

[0022] FIGs. 14A and 14B generally illustrate clocking controls and operations corresponding to updating a heap for data deletions, according to the principles of the present disclosure.

[0023] FIGs. 15A and 15B generally illustrate memory space usage for a heap data structure on a FGPA, according to the principles of the present disclosure.DETAILED DESCRIPTIONAttorney Docket No. 24-2517 WO

[0024] The following discussion is directed to various embodiments of the disclosure. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

[0025] As described, a heap data structure may be used, for example, in connection with an electronic financial asset trading platform that receives orders from multiple clients, and distributes the orders to trading exchanges in a chronological order based on time stamps that the platform determines for the respective orders.

[0026] According to the systems and methods described herein, a heap data structure may implement a binary minimum heap where the time stamps of orders constitute data values in the heap. The heap data structure facilitates sequencing the orders based on respective time stamps with reduced latency, to provide for timely and fair distribution of the orders in a chronological order based on the time stamps represented as data values at nodes in the heap.

[0027] In some embodiments, a field-programmable gate array (FPGA) may include first-in first-out (FIFO) memories (e.g., which may be referred to herein as FIFOs) and multiple port Lookup Table Random Access Memories (multi-port LUTRAMs) configured to instantiate the heap data structure.

[0028] In some embodiments, FIFOs may be configured to monitor a status of all nodes in a heap, which may include monitoring whether a node is filled (i.e., contains data) or unfilled (i.e., does not contain data). The FIFOs may manage data insertion into and data removal from nodesAttorney Docket No. 24-2517 WO of the heap. The FIFOs provide, to a controller of the FPGA, status information of a state (e.g., filled or unfilled) of all nodes in a heap.

[0029] The heap data structure includes a FIFO (“FIFO level”) for each heap level. Additionally, or alternatively, the heap data structure may include a memory level for each FIFO level. Each FIFO level provides to the controller status information for the nodes of a heap level corresponding to the FIFO level. The status information for each FIFO level is continuously or substantially continuously available at the controller. Based on the status information for the FIFOs levels, the controller may begin updating the heap with new data for insertion into the heap in response to (e.g., immediately or substantially immediately) the new data arriving at the FPGA. In some embodiments, heap updating may begin in a same clock cycle in which the new data arrives.

[0030] A FIFO level is configured to provide available memory addresses (“available spaces”) of a corresponding memory level in which to store data for nodes in a heap level corresponding to the FIFO level. The nodes of a heap level correspond to respective memory addresses of a memory level that are provided at a corresponding FIFO level. Based on the configuration of the FIFO levels to provide available memory addresses for respective memory levels, insertion information indicating nodes of a heap to update (“update nodes”) when new data arrives, may be pre-computed (as described below) for all potential heap states that include an unfilled node(s). The insertion information is stored in a memory of the FPGA. When new data arrives for insertion into the heap, the status information for the FIFO levels, which indicates nodes of respective heap levels that are filled or unfilled, may be used to determine a destination heap level to fill and a node to fill in the destination heap level to fill. Based on a determination of the node to fill in the destination heap level to fill, update nodes may be identified immediately from the insertion information, and inAttorney Docket No. 24-2517 WO turn updating of the heap may be immediately commenced on the same clock cycle that the new data arrives.

[0031] Thus, the immediate identification of a node to fill and update nodes for the node to fill when new data arrives for insertion, advantageously provides for low latency heap updating that commences in a same clock cycle that the new data arrives. Stated another way, for insertion of new data, low latency heap updating may be performed, because the status information for all FIFO levels, i.e., for all nodes of all heap levels, is continuously available at the controller to immediately determine update nodes.

[0032] Unlike a prior art heap updating implementation, the controller does not need to perform additional checking operations, which require additional clock cycles, to obtain the status information needed to determine update nodes for a new data insertion. Typically, multiple clock cycles of processor operations to check the presence of data at memory addresses of respective memory levels are required to determine the status of all nodes in a heap. In addition, typical heap data structures, such as implemented in an FPGA, include complex wiring and logic circuitry to facilitate checking the presence of data at all memory addresses respectively of memory levels, to determine status (e.g., filled or unfilled) of all nodes of the heap.

[0033] Referring to FIG. 1, in an exemplary heap data structure implemented in an FPGA, each FIFO level corresponds to a respective heap level of a heap and a memory level. Each FIFO level may store one or more memory addresses of a corresponding memory level. Each memory address in a FIFO level corresponds to a predetermined node in a heap level corresponding to the FIFO level. The memory addresses of a memory level are used to store data for predetermined nodes of a corresponding heap level. The memory addresses for a FIFO level are accessed to store data, inAttorney Docket No. 24-2517 WOFIFO order of the memory addresses of the FIFO level that are made available to store data for nodes of a heap level corresponding to the FIFO level.

[0034] For ease of reference herein, memory addresses of a memory level may be referred to as nodes of the memory level or node memory addresses of the memory level, where the nodes are of a heap level corresponding to the memory level and the nodes correspond to respective memory addresses in the memory level.

[0035] The memory addresses for a FIFO level are made available in FIFO order to store data of nodes in a corresponding heap level, based on whether a node of the corresponding heap level is filled or unfilled.

[0036] Each FIFO level, at output ports, provides status information of the nodes for a corresponding heap level. The status information includes pointer information indicating a next available memory address in a FIFO level to which a pointer points. In one embodiment, referring to FIG. 1A, a FIFO level includes empty, full, write enable (wr_en), read enable (rd_en), read data (dout) and write data ports (din). The read data port indicates a memory address that the pointer for the FIFO level points to, i.e., the next available memory address in a queue of the FIFO level which corresponds to an unfilled node of the FIFO level. When the FIFO level is full, i.e., includes all available memory addresses for a corresponding memory level, the empty port is at a high (1) value. When the FIFO level is empty, i.e., there are no available memory addresses for a corresponding memory level, the full port is at a high (1) value. When all nodes of a heap level are filled, all the memory addresses of the corresponding memory level contain data values, and the corresponding FIFO level does not have any available memory addresses. When a FIFO level has at least one available memory address, as indicated above the read data port indicates theAttorney Docket No. 24-2517 WO memory address pointed to by the pointer, which corresponds to an unfilled node of the corresponding heap level.

[0037] For purposes of describing a heap including multiple heap levels and the availability of memory addresses at FIFO levels for respective memory levels corresponding to heap levels of the heap, the root level is heap level 1 and the highest heap level of a heap, and heap levels 2, 3, 4..., etc. are consecutive lower levels of the heap that are below the root heap level 1. For example, a heap having four levels includes levels 1-4, where level 1 is the highest level and levels 2, 3 and 4 are consecutive lower levels, such that heap level 4 is the lowest heap level. As discussed below, when new data for insertion arrives, available memory addresses of unfilled nodes at respective lower heap levels are filled, starting at a lower heap level that is closest in proximity to the root heap level and has an available memory address, which a corresponding FIFO level provides. Stated another away, node filling priority is from a lower level of the heap which has an available memory address at a corresponding memory level and is closest to the root level. For example, when LI memory for the highest heap level (level 1) and the next lower memory level, L2 memory (heap level 2), are completely filled, and the lower heap levels 3 and 4 have available memory addresses indicated at respective FIFO levels, the available memory addresses for heap level 3 are filled in FIFO order, before the available memory addresses for heap level 4 are filled in FIFO order.

[0038] The controller receives the status information from respective FIFO levels, and based on the pointer information, determines a destination heap level to fill and a node to fill in the destination heap level to fill. The pointer information indicates a next available memory address pointed to by a pointer in a FIFO level corresponding to the destination heap level to fill. The next available memory address corresponds to the node to fill in the destination heap level to fill. TheAttorney Docket No. 24-2517 WO next available memory is the first available memory address in FIFO order of memory addresses corresponding to any unfilled nodes in the destination heap level to fill. A data value will be stored at the memory address of a next available memory address of the corresponding memory level that is at a destination heap level to fill, based on heap updating to insert new data into the heap. When an available memory address of a FIFO level has been used to store data in a memory level, the pointer is updated to indicate a next available memory address, if any, in FIFO order at the FIFO level, and the pointer information supplied from the FIFO level to the controller is updated to reflect the update to the pointer.

[0039] FIG. 1 shows an example four level heap for which a heap data structure is configured in an FPGA including four FIFO levels and four memory levels. The FIFO levels and memory levels are coupled to a controller (not shown) of the FPGA. The controller receives the status information from the FIFO levels, and provides for writing data at memory addresses indicated at respective FIFO levels and updating memory addresses of memory levels to store different data or no longer store data. FIG. 1 illustrates an initial state of the FPGA where no memory addresses are stored at respective FIFO levels and the memory levels are empty.

[0040] Referring to FIG. 2, when a FPGA is configured with FIFO levels and memory levels as a heap data structure for implementing a heap, each FIFO level is initially filled with a specific order, i.e., FIFO order, of available memory addresses for a corresponding memory level at which data for nodes in a heap level corresponding to the FIFO level can be stored. Before any data is inserted into the heap, all FIFO levels are filled with all available memory addresses for the nodes of the heap.

[0041] For example, FIFOL1, FIFOL2, FIFOL3 and FIFOL4 respectively may store 1, 2, 4 and 8 memory addresses respectively for memory levels 1-4, which correspond to heap levels 1-4.Attorney Docket No. 24-2517 WOFIF0L1 has 1 memory address that corresponds to node 1 of heap level 1 ; FIFOL2 has 2 memory addresses that correspond respectively to nodes 2 and 3 of heap level 2; FIFOL3 has 4 memory addresses that correspond respectively to nodes 4-7 of heap level 3; and FIFOL4 has 8 memory addresses that correspond respectively to nodes 8-15 of heap level 4.

[0042] FIFO levels and corresponding memory addresses may be initialized as shown in FIG.2, for example. FIFOL1 has a memory address 1, which corresponds to node 1 of heap level 1 and is for LI memory. FIFOL2 has memory addresses 2 and 3, which respectively correspond to nodes 2 and 3 of heap level 2 and are for L2 memory.

[0043] The memory addresses of corresponding memory levels made available in FIFOL3 and FIFOL4 respectively for heap level 3 and heap level 4 may correspond, for example, to addresses 4-7 and 8-15.

[0044] When new data arrives at the FPGA for insertion into a heap, a node to fill of a destination heap level to fill of a heap is identified. Based on heap updating of update nodes that are determined based on identification of the node to fill, an available space (memory address) is allocated (“popped out”) from the FIFO level that corresponds to the destination heap level to fill including the node to fill, and the memory address corresponds to the node to fill of the destination heap level to fill. The memory address will store data after heap updating for the new data is completed. Stated another way, one available space (memory address) from a FIFO level is popped out, such that a node in the heap level corresponding to the memory address popped out is no longer available, because data is inserted at the node to fill in the destination heap level to fill corresponding to the FIFO level. The available memory addresses (i.e., available spaces in the corresponding memory level) are popped out of a FIFO level, in FIFO order of the memory addresses placed in the FIFO level. For each FIFO level, the available spaces are initially madeAttorney Docket No. 24-2517 WO available in a predetermined FIFO order corresponding to memory addresses of the corresponding memory level. For example, for FIFOL3, the memory addresses 4-7 of L3 memory are initially made available in FIFO order of addresses 4-7 respectively for nodes 4, 5, 6 and 7.

[0045] For example, referring to FIGs. 3 and 4, when the heap is empty and data values 5, 14 and 3 in sequence arrive at the FPGA for insertion, the nodes to fill are determined as nodes 1, 2 and 3, in sequence. Update nodes for each of the nodes to fill are determined based on insertion information, which is pre-computed as discussed below. For data value 5, the node to fill and update node is node 1. The memory address 1 is popped out of FIFOL1, and the data value 5 is stored at memory address 1 in LI memory. These operations correspond to updating node 1, namely, store data value 5 at node 1. For data value 14, the node to fill is node 2 and the update nodes are nodes 1 and 2. As data value 14 is greater than data value 5, the memory address 2 in FIFOL2 is popped out, and the data value 14 is stored at the memory address 2 of L2 memory. These operations correspond to updating nodes 1 and 2, namely, node 1 is unchanged and data value 14 is stored at node 2.

[0046] For data value 3, the node to fill is node 3 and the update nodes are nodes 1 and 3. As data value 5 is greater than data value 3, the memory address 3 is popped out of FIFOL2 and the data value 5 from memory address 1 is stored at the memory address 3 in L2 memory. The data value 3 is stored at memory address 1 of LI memory. These operations correspond to updating nodes 1 and 3, namely, store data value 5 at node 3 and store data value 3 at node 1.

[0047] At the heap state illustrated in FIG. 4, FIFOL1 and FIFOL2 do not contain any available spaces (memory addresses), i.e., the nodes of heap levels LI and L2 are filled, and the LI and L2 memories are filled with the data of the nodes of heap levels LI and L2, respectively. The status information for FIFOL1 and FIFOL2, namely, the full ports of FIFOL1 and FIFOL2, indicates noAttorney Docket No. 24-2517 WO available memory spaces in these FIFO levels. In addition, the pointer information for FIFOL3 indicates a next available memory space is memory address 4. Based on the pointer information, when new data arrives for the current state of the heap, the destination heap level to fill is heap level 3 and the node to fill is node 4, which corresponds to the next available memory address 4 in FIFOL3. As the node to fill is node 4, the update nodes are determined as nodes 1, 2 and 4, based on the insertion information (see update node identification process below).

[0048] FIG. 5 illustrates data at nodes of the heap, memory addresses of FIFO levels popped out and memory levels filled with the data at the memory addresses popped out from corresponding FIFO levels. Data provided in the sequence of data values 41, 87, 90, 50, 64, 53 and 41 are inserted into the nodes of respective heap levels and memory levels as shown in FIG. 5. Following the insertion of these data values, FIFOL4 has memory addresses 12-15 in FIFO order available, which correspond to unfilled nodes 12-15 of heap level 4. Memory addresses 12-15 of L4 memory do not store any data for the nodes 12-15, respectively.

[0049] When all the FIFO levels for a heap are empty, i.e., all memory addresses in the FIFO levels are popped out, all memory levels for the heap are full. In this heap state, all nodes of the heap correspond to data values which are stored in memory levels corresponding to the respective heap levels, and the data values are stored at memory addresses of the memory levels obtained from corresponding FIFO levels.

[0050] As discussed above, when data for insertion into the heap arrives, the controller checks the status information including the pointer information from the FIFO levels, to determine a destination heap level to fill and a node to fill in a destination heap level to fill. A lower heap level having a filled node and closest in proximity to the root level is prioritized for filling, when new data arrives. This lower heap level is identified as a destination heap level to fill. Stated anotherAttorney Docket No. 24-2517 WO way, when several heap levels each have an unfilled node (e.g., available space), a destination heap level to fill is a lower heap level which has an unfilled node and is closest in proximity to the root level. In the destination heap level to fill, higher priority is given to the available space (memory address) that is placed first (i.e., FIFO order) into the FIFO level corresponding to the destination heap level to fdl.[00511 Based on the identification of a node to fill in a destination heap level to fill, update nodes in the heap are determined from the insertion information corresponding to the node to fill. The insertion information indicates, for each node of the heap that may be a node to fill for a data insertion, the nodes of the heap to update (“update nodes”). The update nodes include a single node in each heap level that needs to be updated for a given node to fill. When new data arrives, at least the node of the root level is updated, and then nodes in respective lower heap levels are updated, in the order of heap levels 2, 3, 4... etc., based on the update nodes determined from the insertion information.

[0052] A process to determine update nodes for each node to fill, and store the update nodes for a node to fill as insertion information in a memory, is described below with reference to FIGs. 9 and 10. As further described below, the process to determine update nodes for each node to fill uses memory index information for the heap levels, which corresponds to memory addresses of respective memory levels, to determine update nodes in respective heap levels that are below the root heap level.

[0053] When data is deleted from the heap, the nodes of the heap are updated consistent with minimum heap deletion rules, and the corresponding FIFO levels and memory levels are updated as follows, such as illustrated in FIGS. 5 and 6. The data value 3 of node 1 (see FIG. 5) at the root level of the heap is popped off first, and output. After the root level data is removed (popped off),Attorney Docket No. 24-2517 WO lower levels of the heap are updated (heap levels 2, 3, etc.), as needed based on status of the heap. The controller compares values of the child nodes of a lower heap level that are relative to a parent node whose data is popped off and is in a heap level immediately above the lower heap level containing the child nodes. When both child nodes contain valid data (non-zero data values), the data of the child node with the lesser value based on the comparison is stored in the parent node. Referring to FIG. 5, data values 14 and 5 of the right and left child nodes (nodes 2 and 3 of heap level 2) of the parent root node 1 are compared, and a minimum value of the comparison, data value 5, replaces the data value 3 popped off from the parent node (node 1) at the root level. The value 5 is now stored at the memory address 1 of LI memory. FIFOL1 remains unchanged. This comparison of child nodes of a parent node whose data was moved up to a next higher level in the heap, and filling the parent node with a result of the comparison, is continued similarly for the child nodes 6 and 7 of heap level 3 which are relative to the parent node 3 of heap level 2.

[0054] Data values 87 and 90 of the right and left child nodes 6 and 7 of heap level 3 (which are child nodes of the parent node 3) are compared, and a minimum value of the comparison, data value 87, replaces the data value 5 popped off from the parent node 3 (FIG. 6) in L2 memory at memory address 3. Although the contents in L2 memory changes, FIFOL2 remains unchanged, as the nodes 2-3 of the heap level 2 all remained filled. As the next parent node 6 does not have any child nodes, in other words, a leaf node is reached (i.e., there are no child node values to compare), the updating of the heap for the deletion is completed. The memory address 6 of L3 memory that contained the data value 87 is now empty and will not be filled with a data value based on the deletion. As a result, FIFOL3 is updated to make memory address 6 a next available memory address for heap level 3. The FIFO order of available memory addresses in the FIFOL3 is now memory address 6 alone. Memory address 6 of L3 memory, which corresponds to node 6Attorney Docket No. 24-2517 WO of the heap level 3, is the next available memory address of the heap that is filled, when a new data value arrives for insertion into the heap (assuming no deletions in between for simplicity).

[0055] Thus, in the example, after the heap is updated following a deletion of the value of the root node, a node at a lower level 3 of the heap, which previously was filled, is now unfilled. At the FIFO level corresponding to the lower level of the heap at which a node is now unfilled, a new available memory address is added. The new available memory address is the memory address of the memory level which no longer contains data because the corresponding node became unfilled based on heap updating for the deletion. This memory address is now a last available memory address, in FIFO order, in the corresponding FIFO level. In the example, if FIFOL3 included another available memory address when heap updating was performed based on deleting a data value 3 from the root node, the memory address for node 6 would become the last available memory address in FIFO order of available memory addresses at FIFOL3.

[0056] In one embodiment, the controller of the FPGA issues a command to a FIFO level corresponding to a heap level at which a node became unfilled during a deletion operation, to cause a memory address from which the data was deleted, to become available and move to the end of a queue of available memory addresses for the FIFO level. The pointer information for this FIFO level, however, remains unchanged, when previously there was at least one available memory address for this FIFO level.

[0057] Referring to FIG. 7, following a deletion as described in FIG. 6, the FIFO priority of available spaces is memory address 6 in FIFOL3, and in FIFOL4, the FIFO priority of available spaces is memory addresses 12, 13, 14 and 15. When a new data value 9 for insertion arrives, the pointer information for FIFOL3 indicates that heap level 3 is a destination heap level to fill and a node to fill is node 6 of heap level 3, and the next available memory address is memory address 6Attorney Docket No. 24-2517 WO of L3 memory, which corresponds to node 6. Based on the determination that the node to fill is node 6 from the pointer information, update nodes 1, 3 and 6 are determined from the insertion information, and heap updating follows in the order of nodes 1, 3 and 6. After heap updating of node 1 is completed (node 1 is unchanged), the available memory address 6 of the FIFOL3 is popped off, and the data value 87, which is a larger of a comparison of the value of node 2 of level 2 (data value 87) and the value pushed down from the updating of node 1 of level 1 (data value 9), is stored at memory address 6 of L3 memory, which corresponds to node 6 of heap level 3. In addition, the data value 9 (previously of node 1) is stored at memory address 3 of L2 memory, which corresponds to node 3.

[0058] In some embodiments, an update node identification process may be performed in advance to determine insertion information that identifies update nodes for each node to fill state for a heap. As discussed above, for determining update nodes for insertion of new data, the controller may determine a node to fill in a destination heap level to fill, based on status information including pointer information provided from respective FIFO levels. A node to fill in a destination heap level to fill corresponds to a next available memory address of a corresponding memory level, and a FIFO level that corresponds to the destination heap level to fill containing the node to fill provides the next available memory address.

[0059] In the update node identification process, for a given heap level, a value of index_in is a memory index that corresponds to a memory address of a memory level for the given heap level, and the memory address corresponds to a node of the given heap level. For example, for a heap having four heap levels: heap level 1 has an index_in value equal to 0, which corresponds to node 1 and memory address 1 of LI memory; heap level 2 has index_in values equal to 0 and 1, which respectively correspond to nodes 2 and 3 of heap level 2 and memory addresses 2 and 3 of L2Attorney Docket No. 24-2517 WO memory; heap level 3 has index_in values equal to 0, 1 , 2 and 3, which respectively correspond to nodes 4, 5, 6 and 7 of heap level 3 and memory addresses 4, 5, 6 and 7 of L3 memory; and heap level 4 has index_in values equal to 0, 1, 2, 3, 4, 5, 6 and 7, which respectively correspond to nodes 8, 9, 10, 11, 12, 13, 14 and 15 of heap level 4 and memory addresses 8, 9, 10, 11, 12, 13, 14 and 15 of L4 memory. A controller, such as the FPGA controller, by performing the update node identification process, determines, for a given node to fill, the values of index_in for respective given heap levels and, based on the values of index_in, memory addresses of memory levels indicated by the index_in values and update nodes corresponding respectively to the values of index_in.

[0060] FIGs. 9 and 10 set forth an exemplary update node identification process 100. For the root level, there is always only one node to fill and only one update node, namely, node 1.

[0061] In block 102, for a given node to fill in a destination heap level to fill that is other than the root level, a binary representation of the node to fill is determined. The bits of the binary representation, e.g., wxyz, correspond to bits 0, 1, 2 and 3 from right to left, e.g., z is bit 0, y is bit 1, x is bit 2 and w is bit 3. For example, where the node to fill is node 11, the binary representation is 1011.

[0062] In block 104, index_in is initialized to zero. The value of index_in at block 104 corresponds to the single node at the root level, namely, node 1 of heap level 1, which corresponds to memory address 1 of LI memory. Node 1 is always an update node for a new data insertion. A check bit calculation (see block 110) is not performed for determining an update node at the root heap level.

[0063] In block 106, lvl_current, which corresponds to a current level to fill of the heap, is set equal to 1, which is the value of the root level (level 1).Attorney Docket No. 24-2517 WO

[0064] In block 108, lvl_to_fill is set equal to the destination heap level to fill. For the example, for the node to fill 11 which is in heap level 4 as the destination heap level to fill, lvl_to_fill is set equal to 4.

[0065] In block 110, a check bit is determined as equal to (lvl_to_fill - lvl_current)-l . The check bit is utilized to determine an update node in a heap level that is a next lower heap level relative to the heap level corresponding to lvl_current. For the example, when lvl_current is equal to 1 (the root heap level), and the destination heap level to fill (lvl_to_fill) is equal to 4, the check bit is 2. (See FIG. 8A)

[0066] In block 112, the value of the check bit in a binary representation of the node to fill is determined. For the example, when the check bit is 2, the value is 0 from the binary representation 1011 of node 11.

[0067] In block 114, if the value of the check bit in the binary representation is 0, index_out for lvl_current is equal to 2*index_in +0. When the value of the check bit is 0, an update node in a next lower heap level is a left child node of a node (parent node) in the heap level corresponding to lvl_current. For the example, where the node to fill is node 11, lvl_current is 1, lvl_to_fill is equal to 4, the binary representation of the node to fill is 1011, and the value of the check bit is (4- 1)- 1=2, the value of the check bit 2 in the binary representation is 0. As a result, index_out is equal to (2*0)+0, or zero.

[0068] In block 116, if the value of the check bit in the binary representation is 1, index_out for lvl_current is equal to 2*index_in +1 . When the value of the check bit is 1 , a node to update in a next lower heap level is a right child node of a parent node in the heap level corresponding to the lvl_current.Attorney Docket No. 24-2517 WO

[0069] In block 1 18, index_in for a next lower heap level, lvl_current +1 , is set equal to index_out for the heap level corresponding to lvl_current. Stated another way, an updated value of index_in is determined, and corresponds to an update node in a next lower heap level, namely, lvl_current +1. For the example of node 11 as the node to fill, for heap level 2, node 2 is the update node as index_in is 0 for lvl_current equal to 2.

[0070] In block 120, the value of index_in is stored as a memory index for a memory level corresponding to a next lower heap level, namely, lvl_current +1. In addition, the node in the next lower heap level corresponding to the memory index for the next lower heap level is stored as an update node for the next lower heap level. Continuing with the example, index_in is equal to 0 where lvl_current+l is equal to 2 (heap level 2). Therefore, node 2, which corresponds to memory index 0 of heap level 2 and memory address 2 of memory L2, is identified as an update node for heap level 2 and stored in memory.

[0071] In block 122, the value of lvl_current is increased by 1, to allow for potential identification of an update node in a next lower heap level. Continuing with the example, lvl_current is equal to 2, after lvl_current is increased by 1 in block 122.

[0072] In block 124, if lvl_current (which was increased by 1 in block 122) is equal to lvl_to_fill, processing stops. Otherwise, processing continues in block 110 in FIG. 9, to identify an update node in the heap level lvl_current, which is the next lower heap level. Continuing with the example, update nodes continue to be identified for each of heap levels 3 and 4, because the destination heap level to fdl is heap level 4.

[0073] FIG. 8A illustrates a table showing an example of calculations performed and results obtained according to the process 100. Referring to the table, where the given node to fill is node 11 which is in heap level 4 as the destination heap level to fill, an index_in value for each heapAttorney Docket No. 24-2517 WO level that has an update node is determined. The index_in value for each heap level corresponds to an update node for the heap level.

[0074] Referring to FIG. 8A, based on performing the identification process 100 for node to fill 11, update nodes 2, 5 and 11 are determined. The updates nodes 2, 5 and 11 correspond respectively to memory index values 0, 1 and 3 for heap levels 2-4, which respectively correspond to memory addresses 2, 5 and 11 of L2, L3 and L4 memories which are associated with FIFOL2, FIFOL3 and FIFOL4. As a result, the insertion information for node to fill 11 includes update nodes 1, 2, 5 and 11. Therefore, for a new data insertion where the node to fill is node 11 of heap level 4 (as determined based on the status information of the FIFO levels), the heap is updated by updating nodes 1, 2, 5 and 11, in this order, according to minimum heap updating rules.

[0075] FIG. 8B illustrates an example of updating a heap based on the insertion information indicated in the table of FIG. 8A. Referring to FIGs. 8A and 8B, when a new data value 41 for insertion arrives and the node to fill is node 11, the FIFO levels at heap levels 1, 2 and 3 remain unchanged when nodes 1, 2 and 5 undergo heap updating, and memory address 11 of FIFOL4, which corresponds to memory index 3 of L4 memory and node 11 , is popped out, and the data value 41 is stored at memory address 11 of L4 memory.

[0076] A multi-port LUTRAM emulates a single write port and multiple read ports RAM, and is configured by combining at least two LUTRAMs together. Each LUTRAM in a multi-port LUTRAM may access (i.e., read) one or more data values from the same look-up table memory of a FPGA. In some embodiments, an FPGA may include multi-port LUTRAMs to store data of nodes of respective levels of a heap, advantageously providing for multiple port read data access from a respective multi-port LUTRAM during heap updating. FIG. 11-Al shows an exampleAttorney Docket No. 24-2517 WOLUTRAM that may be included in a multi-port LUTRAM, and FIG. 11 -A2 shows a block diagram of an example multi-port LUTRAM.

[0077] A multi-port LUTRAM may provide simultaneous multiple port read functionalities, and a single-write functionality. Also, multi-port LUTRAMs desirably occupy less area of an FPGA to store data of nodes of a heap, than the area that registers would occupy on an FPGA to store the same data of nodes of the heap. FIGs. 15A-15B illustrate an example of memory space savings that may be obtained on a FGPA, based on use of multi-port LUTRAMs (see shaded portion on FIG. 15B) on the FPGA instead of memory registers (see shaded portion on FIG. 15A), to implement a heap data structure according to the principles of the present disclosure, as described below. In addition, multi-port LUTRAMs achieve improved latency performance in comparison to multiple port Block RAMs (BRAMs), although a multi-port LUTRAM occupies more area of an FPGA than a multi-port BRAM, which has a data storage capacity that is the same as that of the multi-port LUTRAM, occupies on an FPGA.

[0078] Multi-port LUTRAMs provide for less latency during heap updating, in particular for a data deletion, because multiple stored data values of nodes of a heap level can be read from a corresponding multi-port LUTRAM at a same time, i.e., in a same clock cycle. By use of a multiport LUTRAM to store data for nodes of a heap level, during heap updating based on deletion of data from the heap, data of left and right child nodes of a multi-port LUTRAM corresponding to a heap level can be read in a same clock cycle.

[0079] In a heap data structure implementation on an FPGA including multi-port LUTRAMs as heap memories, a single multi-port LUTRAM (“LUTRAM level”) is provided as a memory respectively for each heap level. A LUTRAM level corresponds to a heap level, and stores data of node(s) of the heap level at respective memory addresses of the LUTRAM level. A single FIFOAttorney Docket No. 24-2517 WO level on an FPGA, configured similarly as described above, may be provided for a respective LUTRAM level of a heap data structure. The FIFO level indicates memory address(es) for the corresponding LUTRAM level, similarly as described above for a memory level of a heap. Data of nodes stored at multiple memory addresses of a LUTRAM level may be accessed at respective read data ports of the LUTRAM level during heap updating, and in particular during a single clock cycle, which reduces latency during heap updating.

[0080] For ease of reference, updating a memory corresponding to a node of a heap may be referred to below as updating the node, and writing update data to a node in a clock cycle may be referred to below as completing the updating of the node in the clock cycle. In some embodiments, based on the use of LUTRAM levels to store data for nodes of a heap in a heap data structure of an FPGA:1) New data may be inserted into a heap in each consecutive clock cycle, i.e., every clock cycle. For a given new data value insertion, update data intended for an update of the root node is determined in a same clock cycle that the given new data value arrives at the heap for insertion. The update data is written to (i.e., appears at) the memory address corresponding to the root node in the next clock cycle. In other words, the update to the root node with the update data is completed in the next clock cycle. Thus, the throughput for data insertion into the heap is a single data value per clock cycle. In addition, when new data is inserted into the heap that will result in filling an unfilled node (node to fill) in a destination heap level to fill that is other than the root level, the number of clock cycles to settle the heap, i.e., complete heap updating of all update nodes identified for the node to fill, is equal to the level of the destination heap level to fill. For example, for insertion of new data that results in filling a node to fill in levelAttorney Docket No. 24-2517 WO3 of a heap, heap updating is completed in a third clock cycle after the clock cycle in which the new data arrives at the FPGA, and where three nodes of respective heap levels 1-3 are updated in the three clock cycles. (See discussion of multi-port LUTRAM data insertion operations below); and ) A new data value is available for output from the root node every other clock cycle. After a valid data value of the root node is available for output in a first clock cycle, when data is requested from the heap by a user, the FPGA controller provides a delete command and a write enable pulse in a second clock cycle. As a result, a new data value is written to the root node in a third clock cycle, i.e., the root node is updated two clock cycles after the prior data value at the root node is made available for output. The new data value, thus, is available for output from the root node in the third clock cycle. Further, to complete heap updating after a valid data value is available for output based on a user request, a node at each lower heap level whose data value is moved to a parent node must be updated. For each heap level below the root level that has a node that must be updated, updating for the node at the next lower heap level requires an additional clock cycle. The heap data structure is configured in a pipeline architecture that provides for updating nodes of the heap after a valid data value is available for output as follows. For example, if heap updating involves updating nodes at three heap levels and data is available for output in a first clock cycle, the root node in level 1 has an updated value in a 3rd clock cycle, a node in level 2 has an updated value in a 4th clock cycle, and a node in level 3 has an updated value in a 5th clock cycle. In other words, updating of the heap is settled (completed) at heap level 3 in a 5th clock cycle,Attorney Docket No. 24-2517 WO(e.g., as described herein with respect to multi-port LUTRAM data deletion operations).

[0081] Referring to FIG. 11, for each level in a heap, the FPGA may include a controller and a LUTRAM level. The controller may include compare logic and associated circuitry (Compare) and a Wiredata Temporary Register (Wiredata_Reg). The interconnections of the Compare, Wiredata_Reg and LUTRAM level for a heap level, and the connections of components of a given heap level with components of a heap level immediately below the given heap level, are illustrated in FIG. 11. FIG. 11 shows levels 1-3 of a heap having more than three heap levels.

[0082] Controller LI 10 may include a Compare 1 12 which includes a first input port connected to a read data port of LUTRAM_L1 16, and a first outport port connected to a write data port of LUTRAM_L1 16. Comparel 12 includes a second output port connected to a write data port of Wiredata_Regl 14. In addition, Comparel 12 has a second input port to receive new data which arrives at the FPGA. Wiredata_Regl 14 has a read data port connected to a second input port of Compare220 of controller L2 18.

[0083] Compare2 20 has a first input port connected to a read data port of LUTRAM_L2 22, and a first output port connected to a write data port of LUTRAM_L2 22. Compare2 20 includes a second output port connected to a write data port of Wiredata_Reg2 24. Wiredata_Reg224 has a read data port connected to a second input port of Compares 28 of controller L3 26.

[0084] Compares 28 has a first input port connected to a read data port of LUTRAM_L3 32, and a first output port connected to a write data port of LUTRAM_L3 32. Compare3 28 includes a second output port connected to a write data port of Wiredata_Reg3 30.

[0085] The components in heap levels below heap level 3 would be connected similarly as described for heap levels 2 and 3.Attorney Docket No. 24-2517 WO

[0086] In addition, each Compare is coupled to a read address port and a write address port of a LUTRAM level in the same heap level as the Compare.

[0087] Each Compare performs a compare operation between data values at the first and second input ports. The Compare provides a greater of the values of valid data at the first and second input ports to the second output port, and a lesser of the values of valid data at the first and second input ports to the first output port. In addition, each Compare provides for writing data on the first output port, to a memory address of a LUTRAM level that is the same memory address from which data is read from the LUTRAM level. Also, when no valid data (i.e., a data value is equal to 0, such as at a node to fill as an update node) is provided at the first input port of a Compare, and valid data (i.e., data of Wiredata_Reg from a next higher heap level or a new data value) is provided at the second input port of the Compare, the data at the second input port is provided as write data to write to the address of an update node in the corresponding LUTRAM level.

[0088] FIGs. 12A and 12AA illustrate a process 200 for data insertion into a heap implemented as a heap data structure in a FPGA including LUTRAM levels, such as shown in FIG. 11, and where the FPGA includes FIFO levels (not shown) for respective LUTRAM levels of heap levels, similarly as described above.

[0089] In block 202, in a first clock cycle, new data for insertion into the heap arrives at the FPGA. The controller determines, from the status information from the FIFO levels (not shown in FIG. 11) and insertion information in the memory, update nodes. For purposes of illustrating the process 200, in an example new data insertion into a heap, the update nodes are nodes 1 , 2 and 4, i.e., node 4 is the node to fill.

[0090] In block 204, also in the first clock cycle, data from LUTRAM_L1 16 (node 1) is provided at the first input port of Compare 1 12, and the new data is provided at the second inputAttorney Docket No. 24-2517 WO port of Compare 1 12. Comparel 12 compares the node 1 data with the new data. Comparel 12 provides Compare l_rslt at the second output port. Compare l_rslt is (i) a larger data value of the two data values at the two input ports, or (ii) the new data, when the new data and the node 1 data are the same. In addition, when the new data value is smaller than the node 1 data, Comparel 12 provides the new data as Compare l_sml at the first output port.[00911 In block 206, also in the first clock cycle, Compare l_rslt is provided to the input port of Wiredata_Regl 14.

[0092] In block 208, also in the first clock cycle, when the new data is less than the data read from node 1, Compare l_sml is provided as LUTRAM_Ll_wrdata to a write data port of LUTRAM_L1 16, for writing at the node 1 memory address of LUTRAM_L1 16.

[0093] In block 209, also in the first clock cycle, the controller LI 10 provides a command to write the data on LUTRAM_Ll_wrdata to the node 1 memory address of LUTRAM_L1 16. As a result, Comparel_sml appears as data at (i.e., is written to) the node 1 memory address of LUTRAM_L1 16 on the next (second) clock cycle.

[0094] It is noted that, for an alternative heap state where the controller determines from the status information that the heap is empty, Compare l_sml is the new data, such that the new data is on the LUTRAM_Ll_wrdata port and appears at the node 1 memory address of LUTRAM_L1 16 on the next clock cycle.

[0095] In block 210, in a second clock cycle, the data on LUTRAM_Ll_wrdata appears as the node 1 data, i.e., at the memory address of LUTRAM_L1 16 corresponding to node 1.

[0096] In block 212, also in the second clock cycle, Wiredata_Reg 1 14 is updated to store Compare l_rslt.Attorney Docket No. 24-2517 WO

[0097] In blocks 214, 216 and 218, heap update operations are performed at a next lower heap level X, if any, containing an update node. The heap update operations in blocks 214, 216 and 218 are performed in a second clock cycle for heap level 2 (X=2), and in a same additional consecutive clock cycle(s) when a next lower level(s) (e.g., levels 3, 4, etc. (X=3, 4, etc.)) of the heap contains an update node.

[0098] In block 214, the controller LX, for a heap level X, causes data from an update node of a LUTRAM_LX to be provided on a read port of LUTRAM_LX, and thus be provided at the first input port of CompareX. CompareX compares the update node data at the first input port with the data from Wiredata_Reg(X-l) (the Wiredata_Reg of the heap level X-l previously updated), and determines CompareX_rslt and CompareX_sml. CompareX_rslt is (i) the larger of the data values at the two input ports of CompareX, or (ii) the data from Wiredata_Reg(X- 1), where the data from Wiredata_Reg(X-l) and data of the update node of LUTRAM_LX are the same. CompareX_sml is the smaller of the data at the two inputs of CompareX, or the data from Wiredata_Reg(X-l) when the update node of LUTRAM_LX is the node to fill and does not have valid data.

[0099] In the example, in block 214, in the second clock cycle, Compare2 20 is provided with the node 2 data read from LUTRAM_L222. Compare220 compares the node 2 data with the data supplied from Wiredata_Reg 1 14, and determines a larger data value (Compare2_rslt).

[0100] In block 216, also in the same clock cycle as for block 214, CompareX provides CompareX_rslt to Wiredata_Reg(X).

[0101] In block 218, also in the same clock cycle as for block 214, CompareX provides CompareX_sml as LUTRAM_LX_wrdata on a write data port of LUTRAM_LX for writing to the update node address of LUTRAM_LX. In the example, Compare2_sml is Wiredata_Reg 1 14,Attorney Docket No. 24-2517 WO such that Wiredata_Reg 1 14 is provided for writing to the node 2 memory address of LUTRAM_L2 22.

[0102] In block 220, in a next consecutive clock cycle after the clock cycle for blocks 214, 216 and 218, LUTRAM_LX_wrdata appears at the memory address of LUTRAM_LX for the update node for the heap level X. In the example, data from Wiredata_Regl 14 appears at the node 2 memory address of LUTRAM_L2 22.

[0103] In block 222, also in the clock cycle of block 220, Wiredata_RegX is updated to store CompareX_rslt.

[0104] In block 224, also in the clock cycle of block 220, the controller LX determines whether a next lower heap level contains an update node for the data insertion, based on the update nodes for the data insertion.

[0105] In block 226, also in the clock cycle of block 220, if a next lower heap level contains an update node, the controller in the next lower heap level continues heap updating for an update node in the next lower heap level. For purposes of the operations indicated in the blocks of the process 400, in block 226, X is incremented by one (X-X+ 1 ), to represent that a next lower heap level X is now a heap level for updating. After block 226, blocks 214, 216 and 218 are performed for the next lower heap level X in the same clock cycle as block 226, for updating an update node at the next lower heap level X.

[0106] In block 228, if a next lower heap level does not contain an update node, heap updating for the new data insertion is completed.

[0107] Therefore, in the example data insertion for updating nodes 1 , 2 and 4, the data supplied from Wiredata_Reg2 24 to the Compare3 28 is stored (appears) at the node 4 memory address of LUTRAM_L3 32, three clock cycles after the clock cycle in which the new data for insertionAttorney Docket No. 24-2517 WO arrives. Stated another way, in the example when new data arrives at a first clock cycle, data appears at the node 4 memory address (i.e., the node to fill is now filled) in a fourth clock cycle.

[0108] Another example new data insertion is illustrated in FIGs. 12B and 12C, which show clocking controls and operations at LUTRAM_L1 16 and LUTRAM_L2 22. In this example, when a heap initially is empty, datal, data 2 and data 3 are provided in sequence for insertion into the heap in three consecutive clock cycles. In addition, data 3 is greater than data 2, and data 2 is greater than data 1. The operations in connection with the heap data structure, by implementing the process 200, may be illustrated according to:1) In a first clock cycle: Data 1 is provided at the write data port of LUTRAM_L1 16, namely, LUTRAM_Ll_wrdata, for writing at the node 1 memory address of LUTRAM_L1 16, and a write enable command is provided to LUTRAM_L1 16. In other words, update data (data 1) intended for updating the node 1, based on the data 1 insertion, is determined in the first clock cycle.2) In a second clock cycle: Data 1 appears at (i.e., is written to) the node 1 memory address of LUTRAM_L1 16. Thus, updating of node 1 for the data 1 insertion is completed in the second clock cycle. In addition, data 1 is read from LUTRAM_L1 16 on LUTRAM_Ll_rddata.Data 2 is provided for insertion into the heap. Based on the status information for the heap, the destination heap level to fill is heap level 2 and the node to fill is node 2 of heap level 2. Based on the insertion information, node 1 of heap level 1 and node 2, which is in the next lower level (heap level 2), are the update nodes. Comparel 12 is provided with the node 1 data (data 1) from LUTRAM_L1 16 (which is on LUTRAM_Ll_rddata) and data 2. Compare l_rslt, which is data 2 (the larger of the data read from LUTRAM_L1Attorney Docket No. 24-2517 WO16 (data 1) and data 2), is provided to Wiredata_Regl 14. As a result, at the end of the second clock cycle, update data, if any, intended to update node 1 has been determined. As data 2 exceeds data 1 , the updating for node 1 based on the insertion of data 2 would not change the data of node 1 on the next (third) clock cycle.3) In a third clock cycle: Node 1 is unchanged, based on completion of the updating of node 1 for the data 2 insertion. Compare2 20 provides data 2 from Wiredata_Regl 14 for writing to the node 2 memory address of LUTRAM_L2 22, and a write enable command is provided to LUTRAM_L2 22.Data 3 is provided for insertion into the heap. Based on the status information from the FIFO levels, the destination heap level to fill is heap level 2 and the node to fill is node 3 of heap level 2, such that the update nodes are nodes 1 and 3. Compare 1 12 is provided with data 1 from LUTRAM_L1 16 (which is on LUTRAM_Ll_rddata) and data 3. Compare l_rs It, which is data 3 (the larger of data read from LUTRAM_L1 16 (data 1) and data 3), is provided to Wiredata_Reg 1 14. As a result, at end of the third clock cycle, update data intended for updating node 2 of heap level 2 in the next clock cycle has been determined, based on Compare2 20 providing data 2 for writing to the node 2 memory address of LUTRAM_L222 during the third clock cycle. Also, at the end of the third clock cycle, update data, if any, intended for updating node 1 is determined for the insertion of data 3, and the value of node 1 will not change in the next (fourth) clock cycle.4) In a fourth clock cycle: Data 2 appears in the node 2 memory address of LUTR AM_L2 22. Node 2, thus, has been updated based on the insertion of data 2 in the second clock cycle. Also, node 1 has been updated based on the insertion of data 3, and node 1 is unchanged. Compare2 20 provides data 3 from Wiredata_Regl 14 for writing to the nodeAttorney Docket No. 24-2517 WO3 memory address of LUTRAM_L2 22, and a write enable command is provided to LUTRAM_L2 22.5) In a fifth clock cycle: Data 3 appears at the node 3 memory address of LUTRAM_L2 22. Node 3 has been updated, based on the insertion of data 3 at the third clock cycle.

[0109] Thus, the heap may be updated for new data insertions in a pipeline manner, by performing a process 200 for each new data value that arrives starting at a clock cycle at which the new data arrives. Stated another way, heap updating for new data 1, data 2 and data 3 that arrive in sequence at consecutive first, second and third clock cycles, begins on the clock cycle during which each of the new data arrives, while heap updating of lower heap levels of the heap continues for the prior received new data.

[0110] Additionally, or alternatively, heap settling for insertion of new data is completed at the end of a number of clock cycles that is equal to the destination heap level to fill. For example, for a new data for insertion arriving during a clock cycle X, where the destination heap level to fill is heap level 2, the heap is settled at the clock cycle X+2. Thus, at the clock cycle X+2, a data value appears at the node to fill in the destination heap level to fill of heap level 2, and the node to fill (previously unfilled) is now filled based on the new data for insertion arriving in clock cycle X.

[0111] Referring to the example above, heap updating for new data 1 begins in a clock cycle 1 when new data 1 arrives. Heap updating for new data 2 begins immediately for root node 1 in a clock cycle 2 when data 2 arrives, because in clock cycle 2 the root node 1 already is updated and the new data 1 that arrived in clock cycle 1 may be read from node 1 for updating node 1 . Pipeline updating continues similarly in lower heap levels, when the heap contains additional data in lower heap levels such that update nodes exist in multiple lower heap levels.Attorney Docket No. 24-2517 WO

[0112] Advantageously, when a new data value arrives for insertion, the number of clock cycles to settle the heap based on the insertion of the new data value is equal to a destination level of the heap to fill including a node to fill. Furthermore, heap updating for new data values arriving in consecutive clock cycles can be performed starting at the clock cycle in which the new data values arrive, and then pipeline updating of heap levels continues for the respective new data values, based on the update nodes identified for respective insertions of the new data values.

[0113] In some embodiments, in the heap data structure implemented on the FGPA including LUTRAM levels for respective heap levels, data may be read from multiple ports of a LUTRAM level in a same clock cycle to reduce latency during heap updating for a data deletion. For example, when a parent node in a heap level X is updated based on a data deletion from a heap, the following data may be read in a same clock cycle from read ports of a LUTRAM_X+1 of a next lower heap level X+ 1 : (i) from a first read port of the LUTRAM_X+ 1 , a data value of a left child node relative to the parent node of the heap level X, and (ii) from a second read port of the LUTRAM_X+1, a data value of a right child node of the parent node.

[0114] In some embodiments, a first data value at the root node of the heap is available for output in a first clock cycle. When data is requested from the heap by a user, a write command and delete command are provided in a second clock cycle, and a second data value is written to the root node in a third clock cycle, which effectively deletes the first data value from the root node in the third clock cycle. As a result, the second data value is available for output from the root node in the third clock cycle. Thus, a new data value is available for output from the heap (root node) every other clock cycle.

[0115] FIG. 13 illustrates circuitry of a heap data structure of a FPGA configured to implement data deletion operations. For each heap level implemented by the heap data structure, the FPGAAttorney Docket No. 24-2517 WO includes a controller and a LUTRAM level that stores data values for nodes of the heap level. The controller is connected to ports of the LUTRAM level which is at the heap level of the controller, and ports of a LUTRAM level that is of a next lower heap level, if any. In addition, the controller includes compare logic circuitry (CompareSm).

[0116] For each subject heap level, CompareSm has two data input ports connected to two read data ports of the LUTRAM level of the next lower heap level. In addition, CompareSm is connected to two read address ports of the LUTRAM level of the next lower heap level. As discussed below, the two data input ports are provided with data values of child nodes in a next lower heap level. Each CompareSm includes a CS_rslt port and an index_del_next_L port as respective output ports. The CS_rslt port is connected to a write data port of the LUTRAM level at the subject heap level.

[0117] The CS_rslt port provides, as CS_rslt, (i) when the two child nodes have valid data values, a smaller data value of the data values at the two input ports of CompareSm; and (ii) when only one child node has a valid (i.e., non-zero) data value, the value of the one child node. The index_del_next_L port provides a memory index, index_del_next, which corresponds to a memory address of the LUTRAM level (for the next lower heap level) containing the data of the child node provided at the CS_rslt port. Index_del_next is provided to a controller at the next lower heap level.

[0118] The controller at the next lower heap level, based on index_del_next, determines whether heap updating should continue in a still a further lower heap level. Updating of the heap continues in a further lower heap level, if the value of any of the child nodes for the further lower heap level is valid. Otherwise, updating of the heap based on a deletion of the root node value is stopped at the next lower heap level.Attorney Docket No. 24-2517 WO

[0119] For example, for the heap level 1 , the two input ports of CompareSm_l 34 are connected to two read data ports of LUTRAM_L2 22, which provide data at memory addresses of the LUTRAM_L2 22 corresponding to two child nodes (nodes 2 and 3). CompareSm_l 34 provides, on CS_rsltl port, for writing to LUTRAM_L1 16, (i) the smaller value of the valid data at the two input ports, or (ii) a value of the single child node providing valid data at one of the two inputs. In addition, index_del_next_Ll, which is the memory index corresponding to the child node data, namely, CS_rsltl, that will be written to the node 1 address of LUTRAM_L1 16, is provided to the controller L2 18 for heap level 2.

[0120] Additionally, or alternatively, for heap level 2, CompareSm_2 36 has two input ports connected to two read data ports of LUTRAM_L3 32. The two read data ports include data from (i) memory indexes LUTRAM_13_rdaddr_0 and LUTRAM_13_rdaddr_l which correspond to nodes 4 and 5, or (ii) memory indexes LUTRAM_13_rdaddr_2 and LUTRAM_13_rdaddr_3 which correspond to nodes 6 and 7.

[0121] The controller L2 18 uses index_del_in, which is set equal to index_del_next_Ll, to select the memory indexes of child nodes of LUTRAM_L3 32 in heap level 3 from which to read child node data. When index_del_in for heap level 2 corresponds to node 2, the two inputs of CompareSm_236 are provided data from memory indexes corresponding to nodes 4 and 5. When index_del_in for heap level 2 corresponds to node 3, the two inputs of ComparcSm_2 36 are provided data from memory indexes corresponding to nodes 6 and 7. CompareSm_2 36 provides for writing CS_rslt2 to the memory index index_del_in of LUTRAM_L2 22, and CS_rslt 2 is provided at the CS_rslt2_port of CompareSm_2 36 and is: (i) the smaller value of the two input ports of CompareSm_2 36, or (ii) the single child node value at one of the two input ports of CompareSm_236. CompareSm_236 provides index_del_next_L2 to the controller L3 at the nextAttorney Docket No. 24-2517 WO lower heap level (not shown). The controllers of respective next lower heap levels continue propagating delete commands, and updating a node of the respective next lower heap level, as long as one child node relative to the parent node of a subject heap level has valid data.

[0122] FIGS. 14-Al, 14- A2, 14- A3 and 14- A4 illustrate a process 400 for updating a heap when a data value is output from the root level, using a heap data structure of a FPGA including LUTRAM levels and controllers with respective CompareSms as illustrated in FIG. 13.

[0123] For the process 400, the heap data structure has the following configuration: index_in equal to 0 for LUTRAM_L1 16 corresponds to node 1 and memory address 1 of LUTRAM_L1 16; index_in equal to 0 and 1 for LUTRAM_L2 22 corresponds to nodes 2 and 3 and memory addresses 2 and 3 of LUTRAM_L3 22; index_in equal to 0, 1, 2 and 3 for LUTRAM_L3 32 corresponds to nodes 4, 5, 6 and 7 and memory addresses 4, 5, 6 and 7 of LUTRAM_L3 32, etc. Also, a controller LX of the FPGA is for a corresponding heap level X and LUTRAM_LX. Index_del_in corresponds to the memory address of a node of a subject heap level to update, and is used to determine memory indexes of child node data, if any, for a next lower heap level.

[0124] Referring to FIG. 14-Al and also to FIG. 14A, in a clock cycle 0 (e.g., blocks 402 and 403) in block 402, a request to output a valid data value from the heap, i.e., from node 1 (the root node) of LUTRAM_L1 16, is provided to the controller LI. For heap level 1, index_del_in is equal to 0, which corresponds to the node 1 memory address. Valid data, if any, on a read data port of LUTRAM LI 16, which corresponds to node 1, is provided on a data output line of the FPGA.

[0125] In block 403, the controller LI 10 determines whether data at index_in of LUTRAM_L1 16 is valid, in other words, whether node 1 contains a data value.Attorney Docket No. 24-2517 WO

[0126] If the node 1 address of LUTRAM_L1 16 does not contain valid data, i.e., node 1 does not include a data value other than zero, no further heap updating is performed.

[0127] If node 1 data of LUTRAM_L1 16 is other than the value 0, the node 1 data is valid, and processing continues in block 404 in a next clock cycle, which is clock cycle 1. In addition, when processing continues in block 404, a delete command and a write enable pulse high arc propagated in clock cycle 1 for the LUTRAM_L1 16.

[0128] Referring to FIG. 14-A2, blocks 404, 404-1, 405, 406, 408, 410 and 412 are performed in a same clock cycle Y for a heap level X, so long as one or both of the child nodes of the heap level X contain valid data. If neither of the child nodes contain valid data, only blocks 404, 404- 1 and 405 are performed for the heap level X, and heap updating is not performed for heap levels lower than heap level X.

[0129] In block 404, in a clock cycle Y, the controller LX determines child node memory indices for LUTRAM_X+1, by calculating 2*index_del_in and 2*index _del_in+l. In block 404, when heap level X is heap level 1 (X=l), index_del_in equals 0. For example, in the clock cycle Y=1 (clock cycle 1), heap level X=l. In clock cycle Y=l, controller LI 10 determines memory indices 0 and 1 for LUTRAM_L2 22, which correspond to memory addresses 2 and 3 of LUTRAM_L2 22 and respectively child nodes 2 and 3.

[0130] In block 404, for heap levels X other than heap level 1, index_del_in is equal to index_del_next from a heap level previously updated in blocks 404-412. For example, in block 404 when X=3 such that a node in heap level 3 is being updated, index_del_next is the value determined in the controller L2 18 for heap level 2, which is the heap level previously updated.

[0131] In block 404-1, controller LX requests data from LUTRAM_X+1 at the child node memory indices determined in block 404. In response, the LUTRAM_X+1 provides, on two readAttorney Docket No. 24-2517 WO data ports of LUTRAM_X+1 , the child node data at the memory indices of LUTRAM_X+1 determined in block 404. In addition, in block 404-1, the controller LX reads the child node data on the two read data ports of LUTRAM_X+1. For example, controller LI 10 reads the data values of child nodes 2 and 3 on the two read data ports of LUTRAM_L2 22.

[0132] In block 405, the controller LX determines, based on the child node data read from the LUTRAM_X+1, whether any of the child nodes contain valid data, namely, a data value other than 0. If neither of the two child nodes contain valid data, processing continues in block 600.

[0133] Referring to FIG. 14-A4, in block 600, the controller LX provides a value of zero on a write data input port of LUTRAM_X for writing at index_del_in of LUTRAM_X. For example, where X=1 and the root node 1 does not have child nodes with valid data, a value of zero is placed on a write data input port of LUTRAM_L1 16 for writing to index_del_in equal to zero (memory address 1) of LUTRAM_L1 16.

[0134] In block 602, in a next clock cycle Y+l, the value of zero appears in (i.e., is written to) the memory address corresponding to index_del_in in LUTRAM_X. Continuing with the example where the root node does not contain child nodes with valid data, in a clock cycle 2 (Y=2), the value zero appears in the memory address of LUTRAM_L1 16 corresponding to node 1. After block 602, no further heap updating is performed, hi the example, controller LI does not provide for propagating the delete command in the clock cycle Y=2.

[0135] Referring again to FIG. 14-A2, in block 405, if controller LX determines that any of the two child nodes in LUTRAM_X+1 contain valid data, processing continues in block 406.

[0136] In block 406, the two input ports of CompareSm_X are provided with data from the two read data ports of LUTRAM_X+1 (see block 404-1), which correspond to data stored at the memory addresses of LUTRAM_X+1 for the child nodes in LUTRAM_X+1. The data for theAttorney Docket No. 24-2517 WO two child nodes in LUTRAM_X+1 is immediately at the read data ports LUTRAM_X+1 and also at the two input ports of the CompareSm_X, advantageously because the node data for a heap level is stored in a look-up table in a LUTRAM level. No additional clock cycle of processing is needed to provide the data of the two child nodes from the look-up table in a LUTRAM level, to the two inputs of the ComparcSm. For example, when X=l, the two input ports of CompareSm_l 34 are provided with the data of the left and right child nodes 2 and 3 respectively from two read data ports of LUTRAM_L222.

[0137] In block 408, CompareSm_X determines whether one or both of the two input ports contain a data value other than zero. When the two input ports contain data values other than zero, CompareSm_X provides a comparison data result (CS_rsltX) that is the smaller data value of the two input ports of CompareSm_X. When only one input port of the two input ports contains a data value other than zero, CompareSm_X provides a comparison data result (CS_rsltX) that is the data at the single node corresponding to the one input port. For example, when X=l, and the data of node 2 is the smaller value of nodes 2 and 3, CS_rsltl is the node 2 data.

[0138] In block 410, CompareSm_X provides CS_rsltX at the first output port, CS_rsltX port, which is connected to a write data port of LUTRAM_X. CompareSm_X provides for writing the data of CS-rsltX at index_del_in of LUTRAM_X. For the example, controller LI 10 provides CS_rstll (node 2 data) at the write data port of LUTRAM_L1 16, and index_del_in equal to zero at the write address port of LUTRAM_L1 16.

[0139] In block 412, CompareSm_X provides index_del_next, which corresponds to the memory index of the child node data having the data value CS_rsltX, to controller L(X+1). For the example, where X=1 and the data of node 2 corresponds to CS_rsltl, index_del_next_Ll is equal to zero and provided to controller L2 18.Attorney Docket No. 24-2517 WO

[0140] After block 412, heap update processing continues in a next clock cycle Y+l in blocks 414, 416 and 418. For example, when heap updating at block 412 is for heap level 1 (X- 1 ) and in a clock cycle 1 (Y=l), in block 414 heap updating of heap level 1 continues in a clock cycle 2 (Y=2).

[0141] In block 414, the controller LX provides that a delete command pulse and write enable high pulse are propagated for updating a node of a next lower heap level in the clock cycle Y (see block 418).

[0142] In block 416, the data of CS_rsltX, which is provided at the write address port of LUTRAM_X in block 410, appears at memory index index_del_in of LUTRAM_X. Thus, an updated data value, namely, CS_rsltX, appears at the update node of LUTRAM_X, and the prior data value at index_del_in of LUTRAM_X has been deleted. For example, the data of node 2 appeal’s at the node 1 address of LUTRAM_L1 16, and is available for output. As evident from the example, updating of the root node is completed two clock cycles after a clock cycle when a prior data value is available for output from the root node. See FIGS. 14A-14B.

[0143] In block 418, the controller L(X+1) of the next lower heap level starts heap updating from block 404, to update an update node in the next lower heap level X+l having the memory index index_del_next (see block 412). For the process 400, which describes operations for each heap level that is updated, the value of X is incremented by 1 in block 418, such that references to components and variables in blocks 404-412 are with reference to a subject next lower heap level X. For example, when X=1 in block 416, in block 418 X is incremented by 1 such that X becomes equal to 2, and as a result heap updating as described in blocks 404-412 is with reference to heap level X=2.Attorney Docket No. 24-2517 WO

[0144] For example, after block 418, in clock cycle Y=2 at block 404, X is equal to 2 and controller L2 18 sets index_del_in equal to 0, which is the value of index_del_next from CompareSm_l 34 of heap level 1.

[0145] Continuing with the example, where only child node 2 data has valid data in LUTRAM_L2 22, in clock cycle Y=2 (blocks 404, 404-2 and 405), the controller L2 18 is provided with the data of nodes 4 and 5 from LUTRAM_L3 32 and determines that only child node 4 data has valid data.

[0146] In blocks 406, 408 and 410 during clock cycle Y=2, CS_rslt2, which is the child node 4 data, is provided for writing to index_del_in, which is equal to zero, of LUTRAM_2 22.

[0147] In block 412, in clock cycle Y=2, controller L3 26 (not shown in FIG. 13) is provided index_del_next equal to zero, which corresponds to the node 4 memory index of LUTRAM_L3 32.

[0148] In a next clock cycle Y=3, in blocks 414 and 416, the delete command pulse and write enable high pulse are propagated for updating a next lower heap level, and child node 4 data appears at the node 2 memory address of LUTRAM_L222.

[0149] Also, heap updating for the heap level 3 is initiated in block 418 during clock cycle Y=3. In blocks 404, 404-1 and 405, the controller L3 26 determines that the child nodes of node 4 do not have valid data. As result, data value 0 appears in node 4 at the next clock cycle Y=4, which completes the heap updating for node 4.

[0150] FIGS. 14A and 14B illustrate an example data deletion from the heap by performing the process 400 with a heap data structure such as illustrated in FIG. 13. In the example of FIG. 14A, a data ready pulse is always high, which corresponds to a user always requesting data from the heap. Also, a data valid pulse is high only when the root node has a valid data value available forAttorney Docket No. 24-2517 WO output. Furthermore, in the example data deletion from the heap, the heap contains data 1 at node 1 of LUTRAM_L1 16 and data 2 and data 3 respectively at nodes 2 and 3 of LUTRAM_L2 22, and data 2 is less than data 3. As described below, based on the user always requesting valid data from the heap, the FPGA controller provides that the three valid data values of data 1, data 2 and data 3, are available consecutively for output from the heap.

[0151] Referring to FIG. 14A, in clock cycle 0, a data valid pulse is high and data 1 is available for output from the root node. Since the user requests more data from the heap, the FPGA controller provides a delete command and a write enable high pulse in a clock cycle 1. Based on the delete command and the write enable high pulse in the clock cycle 1 , a new value (data 2) is written to the root node in a clock cycle 2. The writing of data 2 to the root node deletes data 1 from the root node. In the second clock cycle, the data valid pulse is high and data 2 is available for output from the root node.

[0152] Since the user requests more data from the heap, the controller provides a delete command and a write enable pulse high in a clock cycle 3. Based on the delete command and the write enable high pulse in the third clock cycle, a new value (data 3) is written to the root node in a clock cycle 4. In the clock cycle 4, the data valid pulse is high and data 3 is available for output from the root node. Since the user requests more data from the heap, the controller provides a delete command and a write enable pulse high in a clock cycle 5.

[0153] Based on the delete command and the write enable pulse high in the fifth clock cycle, and also a determination in clock cycle 5 that the child nodes of the root node do not have valid data, a data value equal to 0 is written to the root node in clock cycle 6. For example, and as is generally illustrated in FIG. 14A, data is available for output from the root node (i.e., the heap) every other clock cycle, e.g., data 1 is available in clock cycle 0, data 2 is available in clock cycleAttorney Docket No. 24-2517 WO2 and data 3 is available in clock cycle 4, because data values of child nodes of a parent node may be read from a lower LUTRAM in a same clock cycle.

[0154] In some embodiments, a programmable integrated circuit includes a field-programmable gate array (FPGA) that implements a heap data structure. The programmable integrated circuit further includes: a plurality of memory levels; a plurality of first- in-first out (FIFO) memories (“FIFO levels”) for respective heap levels of a heap instantiated by the heap data structure; and a controller that, in response to a new data value for insertion into the heap arriving at the circuit, is configured to: in a clock cycle corresponding to the new data value arriving, (i) determine, based on status information from respective FIFO levels, a destination heap level to fill and a node to fill in the destination heap level to fill, and (ii) determine update nodes for the heap, based on the node to fill in the destination heap level to fill and insertion information stored in a memory; and update the heap at the update nodes, wherein, in response to a first update node being filled and, in response to the first update node continuing to be filled after the first update node is updated, first status information for a first FIFO level corresponding to a first heap level including the first update node is maintained; and wherein second status information for a second FIFO level corresponding to a second heap level including a second update node is changed in response to at least one of (i) the second update node not being filled and, after the second update node is updated, the second update node is filled, and (ii) the second update node is filled and, after the second update node is updated, the second update node is not filled.

[0155] In some embodiments, responsive to the destination heap level to fill including a plurality of unfilled nodes, an available memory address at a corresponding destination FIFO level is prioritized. In some embodiments, status information from a destination FIFO level for theAttorney Docket No. 24-2517 WO destination heap level to fill indicates a first available memory address in a FIFO order of available memory addresses at the destination FIFO level. In some embodiments, the destination heap level to fill includes a heap level below a root heap level having an unfilled node. In some embodiments, the heap level to fill is closest to the root heap level. In some embodiments, a respective memory address for a respective FIFO level corresponds to a node in a respective heap level. In some embodiments, the respective memory address corresponds to a respective memory level of the respective heap level. In some embodiments, each FIFO level is configured to provide status information indicating an available memory address at each respective FIFO level. In some embodiments, the second status information indicates a next available memory address for a respective second memory level. In some embodiments, the second status information indicates the next available memory address based on a FIFO order of available memory addresses for the respective second FIFO level.

[0156] In some embodiments, a circuit configured to implement a heap data structure includes: a plurality of multi-port look-up table random access memory levels (LUTRAM levels), each of the LUTRAM levels corresponding to respective heap levels of a heap instantiated by the heap data structure; and a first controller of a plurality of controllers each corresponding to respective LUTRAM levels. The first controller may be configured to, for a first LUTRAM level at a root heap level and after a data value is available for output from a root node of the heap in a first clock cycle, in a same second clock cycle: receive, from a second LUTRAM level, data values, if any, of left and right child nodes in the second LUTRAM level, which are relative to a root parent node in the first LUTRAM level; compare the data values respectively of the left and right child nodes, to determine a comparison result; provide the comparison result for writing to a root node memory index in the first LUTRAM level in a third clock cycle; and provide, to a second controller of theAttorney Docket No. 24-2517 WO plurality of controllers for the second LUTRAM level, a child node memory index corresponding to the comparison result.

[0157] In some embodiments, in the third clock cycle, the comparison result appears at the root node in the first LUTRAM level. In some embodiments, the third clock cycle is two clock cycles after the first clock cycle when the data value at the root node is available for output. In some embodiments, the first controller includes a first comparison circuit configured to compare data values of the left and right child nodes. In some embodiments, the first comparison circuit is further configured to provide the child node memory index corresponding to the comparison result to the second controller.

[0158] In some embodiments, a circuit including an FPGA that implements a heap data structure includes; a plurality of multi-port look-up table random access memory levels (LUTRAM levels); and a first controller of a plurality of controllers for a first LUTRAM level at a root heap level is configured to, for a new data value to insert into a heap instantiated by the heap data structure, in a first clock cycle, at a first comparison circuit of the first controller: compare the new data value with a data value at a root node of the root heap level; provide a first comparison result for writing to a root node memory index of the first LUTRAM level; and provide a second comparison result to write to a first wiredata register.

[0159] In some embodiments, the LUTRAM levels correspond to respective heap levels of the heap. In some embodiments, each controller of the plurality of controllers for each respective LUTRAM level includes a wiredata register. In some embodiments, each controller of the plurality of controllers for each respective LUTRAM level includes a comparison circuit. In some embodiments, in a second clock cycle after the first clock cycle, the first comparison result is written to the root node memory index of the first LUTRAM level, and the second comparisonAttorney Docket No. 24-2517 WO result is written to the first wiredata register and provided to a second comparison circuit of a second controller for a second LUTRAM level.

[0160] Clause 1 : A programmable integrated circuit includes a field-programmable gate array (FPGA) that implements a heap data structure. The programmable integrated circuit further includes: a plurality of memory levels; a plurality of first-in-first out (FIFO) memories (“FIFO levels”) for respective heap levels of a heap instantiated by the heap data structure; and a controller that, in response to a new data value for insertion into the heap arriving at the circuit, is configured to: in a clock cycle corresponding to the new data value arriving, (i) determine, based on status information from respective FIFO levels, a destination heap level to fill and a node to fill in the destination heap level to fill, and (ii) determine update nodes for the heap, based on the node to fill in the destination heap level to fill and insertion information stored in a memory; and update the heap at the update nodes, wherein, in response to a first update node being filled and, in response to the first update node continuing to be filled after the first update node is updated, first status information for a first FIFO level corresponding to a first heap level including the first update node is maintained; and wherein second status information for a second FIFO level corresponding to a second heap level including a second update node is changed in response to at least one of (i) the second update node not being filled and, after the second update node is updated, the second update node is filled, and (ii) the second update node is filled and, after the second update node is updated, the second update node is not filled.

[0161] Clause 2: The programmable integrated circuit of any clause herein, wherein, responsive to the destination heap level to fill including a plurality of unfilled nodes, an available memory address at a corresponding destination FIFO level is prioritized.Attorney Docket No. 24-2517 WO

[0162] Clause 3: The programmable integrated circuit of any clause herein, wherein status information from a destination FIFO level for the destination heap level to fill indicates a first available memory address in a FIFO order of available memory addresses at the destination FIFO level.

[0163] Clause 4: The programmable integrated circuit of any clause herein, wherein the destination heap level to fill includes a heap level below a root heap level having an unfilled node.

[0164] Clause 5: The programmable integrated circuit of any clause herein, wherein the heap level to fill is closest to the root heap level.

[0165] Clause 6: The programmable integrated circuit of any clause herein, wherein a respective memory address for a respective FIFO level corresponds to a node in a respective heap level.

[0166] Clause 7: The programmable integrated circuit of any clause herein, wherein the respective memory address corresponds to a respective memory level of the respective heap level.

[0167] Clause 8: The programmable integrated circuit of any clause herein, wherein each FIFO level is configured to provide status information indicating an available memory address at each respective FIFO level.

[0168] Clause 9: The programmable integrated circuit of any clause herein, wherein the second status information indicates a next available memory address for a respective second memory level.

[0169] Clause 10: The programmable integrated circuit of any clause herein, wherein the second status information indicates the next available memory address based on a FIFO order of available memory addresses for the respective second FIFO level.

[0170] Clause 11: A circuit configured to implement a heap data structure includes: a plurality of multi-port look-up table random access memory levels (LUTRAM levels), each of theAttorney Docket No. 24-2517 WOLUTRAM levels corresponding to respective heap levels of a heap instantiated by the heap data structure; and a first controller of a plurality of controllers each corresponding to respective LUTRAM levels. The first controller may be configured to, for a first LUTRAM level at a root heap level and after a data value is available for output from a root node of the heap in a first clock cycle, in a same second clock cycle: receive, from a second LUTRAM level, data values, if any, of left and right child nodes in the second LUTRAM level, which are relative to a root parent node in the first LUTRAM level; compare the data values respectively of the left and right child nodes, to determine a comparison result; provide the comparison result for writing to a root node memory index in the first LUTRAM level in a third clock cycle; and provide, to a second controller of the plurality of controllers for the second LUTRAM level, a child node memory index corresponding to the comparison result.

[0171] Clause 12: The circuit of any clause herein, wherein, in the third clock cycle, the comparison result appears at the root node in the first LUTRAM level.

[0172] Clause 13: The circuit of any clause herein, wherein the third clock cycle is two clock cycles after the first clock cycle when the data value at the root node is available for output.

[0173] Clause 14: The circuit of any clause herein, wherein the first controller includes a first comparison circuit configured to compare data values of the left and right child nodes.

[0174] Clause 15: The circuit of any clause herein, wherein the first comparison circuit is further configured to provide the child node memory index corresponding to the comparison result to the second controller.

[0175] Clause 16: A circuit including an FPGA that implements a heap data structure includes: a plurality of multi-port look-up table random access memory levels (LUTRAM levels); and a first controller of a plurality of controllers for a first LUTRAM level at a root heap level is configuredAttorney Docket No. 24-2517 WO to, for a new data value to insert into a heap instantiated by the heap data structure, in a first clock cycle, at a first comparison circuit of the first controller: compare the new data value with a data value at a root node of the root heap level; provide a first comparison result for writing to a root node memory index of the first LUTRAM level; and provide a second comparison result to write to a first wiredata register.[01761 Clause 17: The circuit of any clause herein, wherein the LUTRAM levels correspond to respective heap levels of the heap.

[0177] Clause 18: The circuit of any clause herein, wherein each controller of the plurality of controllers for each respective LUTRAM level includes a wiredata register.

[0178] Clause 19: The circuit of any clause herein, wherein each controller of the plurality of controllers for each respective LUTRAM level includes a comparison circuit.

[0179] Clause 20: The circuit of any clause herein, wherein, in a second clock cycle after the first clock cycle, the first comparison result is written to the root node memory index of the first LUTRAM level, and the second comparison result is written to the first wiredata register and provided to a second comparison circuit of a second controller for a second LUTRAM level.

[0180] The word “example” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” is not necessarily to be constmed as preferred or advantageous over other aspects or designs. Rather, use of the word “example” is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a”Attorney Docket No. 24-2517 WO and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an implementation” or “one implementation” throughout is not intended to mean the same embodiment or implementation unless described as such.

[0181] Implementations the systems, algorithms, methods, instructions, etc., described herein can be realized in hardware, software, or any combination thereof. The hardware can include, for example, computers, intellectual property (IP) cores, application-specific integrated circuits (ASICs), programmable logic arrays, optical processors, programmable logic controllers, microcode, microcontrollers, servers, microprocessors, digital signal processors, or any other suitable circuit. In the claims, the term “processor” should be understood as encompassing any of the foregoing hardware, either singly or in combination. The terms “signal” and “data” are used interchangeably.

[0182] As used herein, the term module can include a packaged functional hardware unit designed for use with other components, a set of instructions executable by a controller (e.g., a processor executing software or firmware), processing circuitry configured to perform a particular function, and a self-contained hardware or software component that interfaces with a larger system. For example, a module can include an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a circuit, digital logic circuit, an analog circuit, a combination of discrete circuits, gates, and other types of hardware or combination thereof. In other embodiments, a module can include memory that stores instructions executable by a controller to implement a feature of the module.

[0183] Further, in one aspect, for example, systems described herein can be implemented using a general-purpose computer or general-purpose processor with a computer program that, whenAttorney Docket No. 24-2517 WO executed, carries out any of the respective methods, algorithms, and / or instructions described herein. In addition, or alternatively, for example, a special purpose computer / processor can be utilized which can contain other hardware for carrying out any of the methods, algorithms, or instructions described herein.

[0184] Further, all or a portion of implementations of the present disclosure can take the form of a computer program product accessible from, for example, a computer-usable or computer- readable medium. A computer-usable or computer-readable medium can be any device that can, for example, tangibly contain, store, communicate, or transport the program for use by or in connection with any processor. The medium can be, for example, an electronic, magnetic, optical, electromagnetic, or a semiconductor device. Other suitable mediums are also available.

[0185] The above-described embodiments, implementations, and aspects have been described in order to allow easy understanding of the present disclosure and do not limit the present disclosure. On the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation to encompass all such modifications and equivalent structure as is permitted under the law.

Claims

Attorney Docket No. 24-2517 WOCLAIMSWhat is claimed is:

1. A programmable integrated circuit including a field-programmable gate array(FPGA) that implements a heap data structure, the programmable integrated circuit comprising: a plurality of memory levels; a plurality of first-in-first out (FIFO) memories (“FIFO levels”) for respective heap levels of a heap instantiated by the heap data structure; and a controller that, in response to a new data value for insertion into the heap arriving at the circuit, is configured to: in a clock cycle corresponding to the new data value arriving, (i) determine, based on status information from respective FIFO levels, a destination heap level to fill and a node to fill in the destination heap level to fill, and (ii) determine update nodes for the heap, based on the node to fill in the destination heap level to fill and insertion information stored in a memory; and update the heap at the update nodes, wherein, in response to a first update node being filled and, in response to the first update node continuing to be filled after the first update node is updated, first status information for a first FIFO level corresponding to a first heap level including the first update node is maintained; and wherein second status information for a second FIFO level corresponding to a second heap level including a second update node is changed in response to at least one of (i) the second update node not being filled and, after the second update node is updated, the second update node is filled, and (ii) the second update node is filled and, after the second update node is updated, the second update node is not filled.Attorney Docket No. 24-2517 WO2. The programmable integrated circuit of claim 1, wherein, responsive to the destination heap level to fill including a plurality of unfilled nodes, an available memory address at a corresponding destination FIFO level is prioritized.

3. The programmable integrated circuit of claim 1, wherein status information from a destination FIFO level for the destination heap level to fill indicates a first available memory address in a FIFO order of available memory addresses at the destination FIFO level.

4. The programmable integrated circuit of claim 1, wherein the destination heap level to fill includes a heap level below a root heap level having an unfilled node.

5. The programmable integrated circuit of claim 4, wherein the heap level to fill is closest to the root heap level.

6. The programmable integrated circuit of claim 1, wherein a respective memory address for a respective FIFO level corresponds to a node in a respective heap level.

7. The programmable integrated circuit of claim 6, wherein the respective memory address corresponds to a respective memory level of the respective heap level.Attorney Docket No. 24-2517 WO8. The programmable integrated circuit of claim 7, wherein each FIFO level is configured to provide status information indicating an available memory address at each respective FIFO level.

9. The programmable integrated circuit of claim 1, wherein the second status information indicates a next available memory address for a respective second memory level.

10. The programmable integrated circuit of claim 9, wherein the second status information indicates the next available memory address based on a FIFO order of available memory addresses for the respective second FIFO level.

11. A circuit configured to implement a heap data structure, the circuit comprising: a plurality of multi-port look-up table random access memory levels (LUTRAM levels), each of the LUTRAM levels corresponding to respective heap levels of a heap instantiated by the heap data structure; and a first controller of a plurality of controllers each corresponding to respective LUTRAM levels, the first controller being configured to, for a first LUTRAM level at a root heap level and after a data value is available for output from a root node of the heap in a first clock cycle: in a same second clock cycle: receive, from a second LUTRAM level, data values, if any, of left and right child nodes in the second LUTRAM level, which are relative to a root parent node in the first LUTRAM level; compare the data values respectively of the left and right child nodes, to determine a comparison result;Attorney Docket No. 24-2517 WO provide the comparison result for writing to a root node memory index in the first LUTRAM level in a third clock cycle; and provide, to a second controller of the plurality of controllers for the second LUTRAM level, a child node memory index corresponding to the comparison result.

12. The circuit of claim 11, wherein, in the third clock cycle, the comparison result appears at the root node in the first LUTRAM level.

13. The circuit of claim 12, wherein the third clock cycle is two clock cycles after the first clock cycle when the data value at the root node is available for output.

14. The circuit of claim 11, wherein the first controller includes a first comparison circuit configured to compare data values of the left and right child nodes.

15. The circuit of claim 14, wherein the first comparison circuit is further configured to provide the child node memory index corresponding to the comparison result to the second controller.

16. A circuit including a field-programmable gate array (FPGA) that implements a heap data structure, the circuit comprising: a plurality of multi-port look-up table random access memory levels (LUTRAM levels); andAttorney Docket No. 24-2517 WO a first controller of a plurality of controllers for a first LUTRAM level at a root heap level configured to, for a new data value to insert into a heap instantiated by the heap data structure, in a first clock cycle, at a first comparison circuit of the first controller: compare the new data value with a data value at a root node of the root heap level; provide a first comparison result for writing to a root node memory index of the first LUTRAM level; and provide a second comparison result to write to a first wiredata register.

17. The circuit of claim 16, wherein the LUTRAM levels correspond to respective heap levels of the heap.

18. The circuit of claim 16, wherein each controller of the plurality of controllers for each respective LUTRAM level includes a wiredata register.

19. The circuit of claim 16, wherein each controller of the plurality of controllers for each respective LUTRAM level includes a comparison circuit.

20. The circuit of claim 16, wherein, in a second clock cycle after the first clock cycle, the first comparison result is written to the root node memory index of the first LUTRAM level, and the second comparison result is written to the first wiredata register and provided to a second comparison circuit of a second controller for a second LUTRAM level.

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