Display device, manufacturing method thereof, and electronic device including same

Abstract

A display device is provided. The display device comprises: a plurality of insulating layers; a light-emitting element; and a pixel circuit electrically connected to the light-emitting element. The pixel circuit includes a first transistor for controlling a driving current of the light-emitting element and a second transistor for outputting a data voltage. A first semiconductor pattern of the first transistor includes a crystalline indium gallium oxide (IGO) semiconductor, and a second semiconductor pattern of the second transistor includes an amorphous indium tin gallium zinc oxide (ITGZO) semiconductor.

Description

Display device, method of manufacturing the same, electronic device including the same

[0001] The present invention relates to a display device, a method for manufacturing the same, and an electronic device including the same. Specifically, it relates to a display device equipped with an oxide transistor, a method for manufacturing the same, and an electronic device including the same.

[0002] The display device includes a plurality of pixels and a driving circuit that controls the plurality of pixels (e.g., a scan driving circuit and a data driving circuit). Each of the plurality of pixels includes a display element and a pixel circuit that controls the display element. The pixel circuit may include a plurality of organically connected transistors.

[0003] Multiple transistors may include silicon semiconductors or metal oxide semiconductors.

[0004] The object of the present invention is to provide a display device comprising an oxide transistor with a wide driving voltage range.

[0005] The object of the present invention is to provide a method for manufacturing the above-mentioned display device.

[0006] The object of the present invention is to provide an electronic device including the above-mentioned display device.

[0007] A display device according to one embodiment of the present invention comprises a plurality of insulating layers, a light-emitting element, and a pixel circuit electrically connected to the light-emitting element. The pixel circuit comprises a first semiconductor pattern including a crystalline indium gallium oxide (IGO) semiconductor, a first transistor for controlling the driving current of the light-emitting element, a second semiconductor pattern including an amorphous indium tin gallium zinc oxide (ITGZO) semiconductor, and a second transistor for outputting a data voltage.

[0008] The first semiconductor pattern and the second semiconductor pattern can come into contact with the upper surface of the same insulating layer among the plurality of insulating layers.

[0009] The first transistor may further include a first gate electrode and a second gate electrode. The first semiconductor pattern may include a first channel region, a first input region, and a first output region. The first gate electrode may be positioned above the first channel region, and the second gate electrode may be positioned below the first channel region and electrically connected to the first output region.

[0010] It may further include a third transistor including a third semiconductor pattern including a silicon semiconductor.

[0011] The third semiconductor pattern may be in contact with the upper surface of any one of the plurality of insulating layers, and the first semiconductor pattern and the second semiconductor pattern may be in contact with the upper surface of another insulating layer among the plurality of insulating layers.

[0012] It may further include a voltage line disposed on the lower side of the first semiconductor pattern and receiving a power supply voltage. The third transistor may further include a gate electrode disposed on the upper side of the third semiconductor pattern. The gate electrode is disposed spaced apart from the voltage line in a plane and may contact the upper surface of the same insulating layer among the plurality of insulating layers.

[0013] It may further include a conductive pattern disposed between the first semiconductor pattern and the voltage line. The conductive pattern may overlap the first semiconductor pattern and the voltage line, respectively. The output region of the first semiconductor pattern and the conductive pattern may be electrically connected.

[0014] A display device according to one embodiment of the present invention may further include a third transistor capable of electrically connecting a voltage line receiving a first voltage and the gate electrode of the first transistor, a fourth transistor capable of electrically connecting a voltage line receiving a second voltage and the first electrode of the light-emitting element, and a fifth transistor capable of electrically connecting a voltage line receiving a first power supply voltage and the first transistor.

[0015] The second electrode of the light-emitting element can receive a second power supply voltage different from the first power supply voltage.

[0016] A display device according to one embodiment of the present invention may further include a sixth transistor capable of electrically connecting the first transistor and the first electrode of the light-emitting element.

[0017] Each of the third transistor and the fourth transistor may include a semiconductor identical to the second semiconductor pattern.

[0018] The semiconductor pattern of each of the third transistor and the fourth transistor can be in contact with the upper surface of the same insulating layer among the second semiconductor pattern and the plurality of insulating layers.

[0019] The above-mentioned fifth transistor may include a third semiconductor pattern comprising a silicon semiconductor.

[0020] An electronic device according to one embodiment of the present invention may include a display device and an input device that receives commands, inputs, or data from the outside. The display device may include a plurality of insulating layers, a light-emitting element, and a pixel circuit electrically connected to the light-emitting element. The pixel circuit may include a first semiconductor pattern comprising a crystalline indium gallium oxide (IGO) semiconductor, a first transistor that controls the driving current of the light-emitting element, a second semiconductor pattern comprising an amorphous indium tin gallium zinc oxide (ITGZO) semiconductor, and a second transistor that outputs a data voltage.

[0021] The above input device may be an input sensor, a keyboard, or a mouse.

[0022] The first semiconductor pattern and the second semiconductor pattern can come into contact with the upper surface of the same insulating layer among the plurality of insulating layers.

[0023] The first transistor further includes a first gate electrode and a second gate electrode, and

[0024] The first semiconductor pattern may include a first channel region, a first input region, and a first output region. The first gate electrode is disposed on the upper side of the first channel region, and the second gate electrode is disposed on the lower side of the first channel region and may be electrically connected to the first output region.

[0025] A third transistor may further include a third semiconductor pattern comprising the silicon semiconductor. The third semiconductor pattern may be in contact with the upper surface of any one of the plurality of insulating layers, and the first semiconductor pattern and the second semiconductor pattern may be in contact with the upper surface of another insulating layer among the plurality of insulating layers.

[0026] A method for manufacturing a display device according to one embodiment of the present invention may include the steps of forming a first semiconductor pattern on an insulating layer, crystallizing the first semiconductor pattern, forming a second semiconductor layer covering the first semiconductor pattern on the insulating layer, and forming a second semiconductor pattern spaced apart from the first semiconductor pattern in a planar manner from the second semiconductor layer. The first semiconductor pattern may include an indium gallium oxide (IGO) semiconductor, and the second semiconductor pattern may include an indium tin gallium zinc oxide (ITGZO) semiconductor.

[0027] A method for manufacturing a display device according to one embodiment of the present invention may further include the step of forming a first gate electrode on the first semiconductor pattern and the step of forming a second gate electrode on the second semiconductor pattern.

[0028] A method for manufacturing a display device according to one embodiment of the present invention may further include the step of forming an insulating pattern that exposes parts of the first semiconductor pattern between the first semiconductor pattern and the first gate electrode.

[0029] As described above, the low-current driving voltage range of the first transistor is widened, so the current-voltage-luminance characteristics can be improved. In addition, the low-gradation display quality can be improved.

[0030] The mobility of the second transistor is increased, allowing for the implementation of a short-channel transistor. The area occupied by the second transistor is reduced, which can improve the design freedom of the pixel circuit.

[0031] FIGS. 1a and FIGS. 1b are perspective views of an electronic device according to one embodiment of the present invention.

[0032] FIG. 1c is a block diagram of an electronic device according to one embodiment of the present invention.

[0033] FIG. 2 is a block diagram of a display device according to one embodiment of the present invention.

[0034] FIG. 3a is an equivalent circuit diagram of a pixel according to one embodiment of the present invention.

[0035] FIG. 3b is a waveform diagram of driving signals for driving the pixel shown in FIG. 3a.

[0036] FIG. 4a is an equivalent circuit diagram of a pixel according to one embodiment of the present invention.

[0037] FIG. 4b is a waveform diagram of driving signals for driving the pixel shown in FIG. 4a.

[0038] FIG. 5 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0039] Figure 6a is a graph showing the voltage-current characteristics of an oxide transistor according to a comparative example.

[0040] FIG. 6b is a graph showing the voltage-current characteristics of an oxide transistor according to one embodiment of the present invention.

[0041] FIG. 6c is a graph showing the voltage-current characteristics of an oxide transistor according to one embodiment of the present invention.

[0042] FIGS. 7a to 7h are cross-sectional views illustrating the manufacturing process of a display panel according to one embodiment of the present invention.

[0043] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0044] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. "And / or" includes all one or more combinations that the associated components may define.

[0045] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0046] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0047] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0049] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0050] FIGS. 1a and 1b are perspective views of an electronic device (ED) according to one embodiment of the present invention. FIG. 1c is a block diagram of an electronic device (ED) according to one embodiment of the present invention.

[0051] An electronic device (ED) according to one embodiment of the present invention includes a display device (DD). An electronic device (ED) according to one embodiment of the present invention may be a tablet as in FIG. 1a or a notebook as in FIG. 1b.

[0052] An electronic device (ED) according to an embodiment of the present disclosure may be an image display electronic device such as a smartphone, a television (TV), or a desk monitor, a wearable electronic device including a display module such as smart glasses, a head-mounted display, or a smart watch, and an electronic device for a vehicle including a display module such as a center information display (CID) placed on an instrument panel, a center fascia, or a dashboard, or a rearview mirror display of a vehicle.

[0053] As illustrated in FIG. 1c, the electronic device (ED) outputs various information through the display module (140) within the operating system. The display device (DD) described with reference to FIG. 1a and FIG. 1b may include the display module (140). When the processor (110) executes an application stored in memory (120), the display module (140) provides application information to the user through the display panel (141).

[0054] The processor (110) obtains an external input through the input module (130) or the sensor module (161) and executes an application corresponding to the external input. For example, if a user selects a camera icon displayed on the display panel (141), the processor (110) obtains user input through the input sensor (161-2) and activates the camera module (171). The processor (110) transmits image data corresponding to the captured image obtained through the camera module (171) to the display module (140). The display module (140) can display an image corresponding to the captured image through the display panel (141).

[0055] As another example, when personal information authentication is performed in the display module (140), the fingerprint sensor (161-1) acquires the input fingerprint information as input data. The processor (110) compares the input data acquired through the fingerprint sensor (161-1) with the authentication data stored in the memory (120) and executes an application based on the comparison result. The display module (140) can display the executed information through the display panel (141) according to the logic of the application.

[0056] As another example, when a music streaming icon displayed on the display module (140) is selected, the processor (110) obtains user input through the input sensor (161-2) and activates the music streaming application stored in the memory (120). When a music execution command is input from the music streaming application, the processor (110) activates the sound output module (163) to provide sound information corresponding to the music execution command to the user.

[0057] The operation of the electronic device (ED) has been briefly described above. The configuration of the electronic device (ED) will be described in detail below. Some of the configurations of the electronic device (ED) described below may be integrated and provided as a single configuration, or a single configuration may be separated into two or more configurations.

[0058] Referring to FIG. 1c, the electronic device (ED) can communicate with an external electronic device (102) through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device (ED) may include a processor (110), memory (120), an input module (130), a display module (140), a power module (150), an internal module (160), and an external module (170). According to one embodiment, at least one of the above-described components may be omitted from the electronic device (ED), or one or more other components may be added. According to one embodiment, some of the above-described components (e.g., a sensor module (161), an antenna module (162), or an acoustic output module (163)) may be integrated into another component (e.g., a display module (140)).

[0059] The processor (110) can execute software to control at least one other component (e.g., a hardware or software component) of an electronic device (ED) connected to the processor (110) and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (110) stores commands or data received from other components (e.g., an input module (130), a sensor module (161), or a communication module (173)) in a volatile memory (121), processes the commands or data stored in the volatile memory (121), and the resulting data can be stored in a non-volatile memory (122).

[0060] The processor (110) may include a main processor (111) and an auxiliary processor (112). The main processor (111) may include one or more of a central processing unit (111-1, CPU) or an application processor (AP). The main processor (111) may further include one or more of a graphic processing unit (111-2, GPU), a communication processor (CP), and an image signal processor (ISP). The main processor (111) may further include a neural processing unit (111-3, NPU). The neural processing unit is a processor specialized for processing artificial intelligence models, and the artificial intelligence model may be generated through machine learning. The artificial intelligence model may include a plurality of artificial neural network layers. An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially. At least two of the processing unit and processor described above may be implemented as a single integrated configuration (e.g., a single chip), or each may be implemented as an independent configuration (e.g., multiple chips).

[0061] The auxiliary processor (112) may include a controller (112-1). The controller (112-1) may include an interface conversion circuit and a timing control circuit. The controller (112-1) receives a video signal from the main processor (111), converts the data format of the video signal to match the interface specifications with the display module (140), and outputs video data. The controller (112-1) may output various control signals required for driving the display module (140).

[0062] The auxiliary processor (112) may further include a data conversion circuit (112-2), a gamma correction circuit (112-3), a rendering circuit (112-4), etc. The data conversion circuit (112-2) receives image data from the controller (112-1) and can compensate the image data so that the image is displayed at a desired brightness according to the characteristics of the electronic device (ED) or the user's settings, etc., or can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit (112-3) can convert image data or gamma reference voltage, etc. so that the image displayed on the electronic device (ED) has desired gamma characteristics. The rendering circuit (112-4) receives image data from the controller (112-1) and can render the image data by considering the pixel arrangement of the display panel (141) applied to the electronic device (ED). At least one of the data conversion circuit (112-2), gamma correction circuit (112-3), and rendering circuit (112-4) may be integrated into another component (e.g., main processor (111) or controller (112-1)). At least one of the data conversion circuit (112-2), gamma correction circuit (112-3), and rendering circuit (112-4) may also be integrated into the data driver (143) described later.

[0063] The memory (120) can store various data used by at least one component of the electronic device (ED) (e.g., a processor (110) or a sensor module (161)) and input or output data for related commands. The memory (120) may include at least one of a volatile memory (121) and a non-volatile memory (122).

[0064] The input module (130) can receive commands or data to be used for components of the electronic device (ED) (e.g., processor (110), sensor module (161) or sound output module (163)) from outside the electronic device (ED) (e.g., user or external electronic device (102)).

[0065] The input module (130) may include a first input module (131) into which commands or data are input from a user and a second input module (132) into which commands or data are input from an external electronic device (102). The first input module (131) may include a microphone, a mouse, a keyboard, a key (e.g., a button), or a pen (e.g., a passive pen or an active pen). The second input module (132) may support a specified protocol that can be connected to the external electronic device (102) via a wired or wireless connection. According to one embodiment, the second input module (132) may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface. The second input module (132) may include a connector that can be physically connected to the external electronic device (102), such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0066] The display module (140) provides visual information to the user. The display module (140) may include a display panel (141), a scan driver (142), and a data driver (143). The display module (140) may further include a window, a chassis, and a bracket for protecting the display panel (141).

[0067] The display panel (141) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of the display panel (141) is not particularly limited. The display panel (141) may be a rigid type, or a flexible type that is rollable or foldable. The display module (140) may further include a supporter, a bracket, or a heat dissipation member that supports the display panel (141).

[0068] The scan driver (142) can be mounted on the display panel (141) as a driving chip. Additionally, the scan driver (142) can be integrated into the display panel (141). For example, the scan driver (142) may include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT Gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) embedded in the display panel (141). The scan driver (142) receives a control signal from the controller (112-1) and outputs scan signals to the display panel (141) in response to the control signal.

[0069] The display panel (141) may further include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal to the display panel (141) in response to a control signal received from the controller (112-1). The light-emitting driver may be formed separately from the scan driver (142) or may be integrated into the scan driver (142).

[0070] The data driver (143) receives a control signal from the controller (112-1), converts the image data into an analog voltage (e.g., data voltage) in response to the control signal, and then outputs the data voltages to the display panel (141).

[0071] The data driver (143) may be integrated into other components (e.g., the controller (112-1)). The functions of the interface conversion circuit and the timing control circuit of the controller (112-1) described above may also be integrated into the data driver (143).

[0072] The display module (140) may further include a light-emitting driver and a voltage generating circuit, etc. The voltage generating circuit can output various voltages required for driving the display panel (141).

[0073] The power module (150) supplies power to the components of the electronic device (ED). The power module (150) may include a battery that charges the power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power module (150) may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and the modules described below. The power module (150) may include a wireless power transceiver electrically connected to the battery. The wireless power transceiver may include a plurality of coil-shaped antenna radiators.

[0074] The electronic device (ED) may further include an internal module (160) and an external module (170). The internal module (160) may include a sensor module (161), an antenna module (162), and an audio output module (163). The external module (170) may include a camera module (171), a light module (172), and a communication module (173).

[0075] The sensor module (161) can detect input by the user's body or input by a pen of the first input module (131) and generate an electrical signal or data value corresponding to the input. The sensor module (161) may include at least one of a fingerprint sensor (161-1), an input sensor (161-2), and a digitizer (161-3). The input module (130) and the sensor module (161) that receive commands, inputs, or data from the outside may be collectively referred to as an input device.

[0076] The fingerprint sensor (161-1) can generate a data value corresponding to the user's fingerprint. The fingerprint sensor (161-1) may include either an optical or capacitive fingerprint sensor.

[0077] The input sensor (161-2) can generate a data value corresponding to coordinate information of input by the user's body or input by a pen. The input sensor (161-2) generates a data value of the amount of change in capacitance due to the input. The input sensor (161-2) can detect input by a passive pen or transmit and receive data with an active pen.

[0078] The input sensor (161-2) may measure biosignals such as blood pressure, water content, or body fat. For example, if a user contacts a part of their body to the sensor layer or sensing panel and does not move for a certain period of time, the input sensor (161-2) may detect biosignals based on changes in the electric field caused by the part of the body and output information desired by the user to the display module (140).

[0079] The digitizer (161-3) can generate a data value corresponding to the coordinate information of the input by the pen. The digitizer (161-3) generates the amount of electromagnetic change caused by the input as a data value. The digitizer (161-3) can detect input by a passive pen or transmit and receive data with an active pen.

[0080] At least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be implemented as a sensor layer formed on the display panel (141) through a continuous process. The fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be positioned on the upper side of the display panel (141), and any one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3), such as the digitizer (161-3), may be positioned on the lower side of the display panel (141).

[0081] At least two of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) can be formed to be integrated into a single sensing panel through the same process. When integrated into a single sensing panel, the sensing panel can be positioned between the display panel (141) and a window positioned above the display panel (141). According to one embodiment, the sensing panel may be positioned on the window, and the position of the sensing panel is not particularly limited.

[0082] At least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be embedded in the display panel (141). That is, at least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be formed simultaneously through a process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel (141).

[0083] Additionally, the sensor module (161) may generate an electrical signal or data value corresponding to an internal or external state of the electronic device (ED). The sensor module (161) may further include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0084] The antenna module (162) may include one or more antennas for transmitting a signal or power to the outside or receiving it from the outside. According to one embodiment, the communication module (173) may transmit a signal to an external electronic device or receive it from an external electronic device through an antenna suitable for a communication method. The antenna pattern of the antenna module (162) may be integrated with one component of the display module (140) (e.g., a display panel (141)) or an input sensor (161-2), etc.

[0085] The sound output module (163) is a device for outputting a sound signal to the outside of an electronic device (ED), and may include, for example, a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for telephone reception. According to one embodiment, the receiver may be formed integrally with or separately from the speaker. The sound output pattern of the sound output module (163) may be integrated with the display module (140).

[0086] The camera module (171) can capture still images and video. According to one embodiment, the camera module (171) may include one or more lenses, image sensors, or image signal processors. The camera module (171) may further include an infrared camera capable of measuring the presence or absence of a user, the location of the user, the user's gaze, etc.

[0087] The light module (172) can provide light. The light module (172) may include a light-emitting diode or a xenon lamp. The light module (172) may operate in conjunction with the camera module (171) or operate independently.

[0088] The communication module (173) can support the establishment of a wired or wireless communication channel between an electronic device (ED) and an external electronic device (102), and the performance of communication through the established communication channel. The communication module (173) may include one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a GNSS (global navigation satellite system) communication module, and a wired communication module such as a LAN (local area network) communication module or a power line communication module. The communication module (173) can communicate with the external electronic device (102) through a short-range communication network such as Bluetooth, WiFi Direct, or IrDA (infrared data association), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., LAN or WAN). The various types of communication modules (173) described above may be implemented as a single chip or each as a separate chip.

[0089] The input module (130), sensor module (161), camera module (171), etc., can be used to control the operation of the display module (140) in conjunction with the processor (110).

[0090] The processor (110) outputs commands or data to the display module (140), sound output module (163), camera module (171), or light module (172) based on input data received from the input module (130). For example, the processor (110) may generate image data in response to input data applied via a mouse or active pen, and output it to the display module (140), or generate command data in response to input data and output it to the camera module (171) or light module (172). If the processor (110) does not receive input data from the input module (130) for a certain period of time, it may switch the operating mode of the electronic device (ED) to a low-power mode or sleep mode to reduce the power consumed by the electronic device (ED).

[0091] The processor (110) outputs commands or data to the display module (140), sound output module (163), camera module (171), or light module (172) based on the sensing data received from the sensor module (161). For example, the processor (110) can compare the authentication data authorized by the fingerprint sensor (161-1) with the authentication data stored in the memory (120) and then execute an application based on the comparison result. The processor (110) can execute commands or output corresponding image data to the display module (140) based on the sensing data detected by the input sensor (161-2) or the digitizer (161-3). If the sensor module (161) includes a temperature sensor, the processor (110) receives temperature data regarding the temperature measured from the sensor module (161) and can further perform brightness correction, etc., on the image data based on the temperature data.

[0092] The processor (110) can receive measurement data regarding the presence or absence of a user, the location of the user, the user's gaze, etc. from the camera module (171). The processor (110) can further perform brightness correction on the image data based on the measurement data. For example, the processor (110), having determined the presence or absence of a user through input from the camera module (171), can output image data with corrected brightness to the display module (140) through the data conversion circuit (112-2) or the gamma correction circuit (112-3).

[0093] Some of the above components may be connected to each other via a communication method between peripheral devices, such as a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface), or UPI (Ultra path interconnect) link, to exchange signals (e.g., commands or data) with each other. The processor (110) may communicate with the display module (140) via an interface agreed upon with each other, and may, for example, use any of the communication methods described above, but is not limited to the communication methods described above.

[0094] The electronic device (ED) according to the various embodiments disclosed in this document may be of various forms. The electronic device (ED) may include, for example, at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device (ED) according to the embodiments of this document is not limited to the aforementioned devices.

[0095] FIG. 2 is a block diagram of a display device (DD) according to an embodiment of the present invention. The display device (DD) may include a controller (112-1), a display panel (141), a scan driver (142), and a data driver (143). In this embodiment, the display panel (141) is described as a light-emitting display panel. The light-emitting display panel may include an organic light-emitting display panel or an inorganic light-emitting display panel.

[0096] The controller (112-1) converts the data format of the input video signals to match the interface specifications with the scan driver (142) and generates video data (D-RGB). The controller (112-1) outputs the video data (D-RGB) and various control signals (DCS, SCS).

[0097] The scan driver (142) receives a scan control signal (SCS) from the controller (112-1). The scan control signal (SCS) may include a vertical start signal that initiates the operation of the scan driver (142), a clock signal that determines the timing of the output of signals, etc. The scan driver (142) generates a plurality of scan signals and outputs them sequentially to the corresponding scan signal lines (SL11 to SL1n). In addition, the scan driver (142) generates a plurality of light emission control signals in response to the scan control signal (SCS) and outputs a plurality of light emission control signals to the corresponding light emission signal lines (EL1 to ELn).

[0098] Although FIG. 2 illustrates that a plurality of scan signals and a plurality of light emission control signals are output from a single scan driver (142), the present invention is not limited thereto. In one embodiment of the present invention, the display device (DD) may include a plurality of scan driving circuits. In addition, in one embodiment of the present invention, a driving circuit that generates and outputs a plurality of scan signals and a driving circuit that generates and outputs a plurality of light emission control signals may be formed separately.

[0099] The data driver (143) receives a data control signal (DCS) and image data (D-RGB) from the controller (112-1). The data driver (143) converts the image data (D-RGB) into data signals and outputs the data signals to a plurality of data lines (DL1 to DLm) described later. The data signals are analog voltages corresponding to the grayscale values ​​of the image data (D-RGB).

[0100] The display panel (141) may include a plurality of groups of scan lines. FIG. 2 illustrates, by way of example, a first group of scan signal lines (SL11 to SL1n). The display panel (141) further includes light emission signal lines (EL1 to ELn), data lines (DL1 to DLm), a first voltage line (VL1), a second voltage line (VL2), a third voltage line (VL3), a fourth voltage line (VL4), and a plurality of pixels (PX).

[0101] The scan signal lines of the first group (SL11 to SL1n) may be extended in a first direction (DR1) and arranged in a second direction (DR2). Data lines (DL1 to DLm) may intersect with the scan signal lines of the first group (SL11 to SL1n).

[0102] The first voltage line (VL1) receives the first power supply voltage (ELVSS). The second voltage line (VL2) receives the second power supply voltage (ELVDD). The second power supply voltage (ELVDD) has a higher level than the first power supply voltage (ELVSS). The third voltage line (VL3) receives the reference voltage (Vref, hereinafter referred to as the first voltage). The fourth voltage line (VL4) receives the initialization voltage (Vint, hereinafter referred to as the second voltage). The first voltage (Vref) has a lower level than the second power supply voltage (ELVDD). The second voltage (Vint) has a lower level than the second power supply voltage (ELVDD). In this embodiment, the second voltage (Vint) may have a lower level than the first voltage (Vref) and the first power supply voltage (ELVSS).

[0103] At least one of the first voltage line (VL1), the second voltage line (VL2), the third voltage line (VL3), and the fourth voltage line (VL4) may include at least one of a line extended in the first direction (DR1) and a line extended in the second direction (DR2). The line extended in the first direction (DR1) and the line extended in the second direction (DR2) of the voltage lines may be electrically connected to each other even if they are placed on different layers among the plurality of insulating layers (10 to 40) shown in FIG. 5.

[0104] Although a display device (DD) according to one embodiment has been described with reference to FIG. 2, the display device (DD) of the present invention is not limited thereto. Depending on the configuration of the pixel circuit, signal lines may be added or omitted. In addition, the electrical connection relationship between a single pixel (PX) and the signal lines may also be changed.

[0105] A plurality of pixels (PX) may include a plurality of groups that generate different colored light. For example, they may include red pixels that generate red colored light, green pixels that generate green colored light, and blue pixels that generate blue colored light. The light-emitting elements of the red pixels, the light-emitting elements of the green pixels, and the light-emitting elements of the blue pixels may include light-emitting layers of different materials.

[0106] The pixel circuit may include a plurality of transistors and at least one capacitor. At least one of the scan driver (142) and the data driver (143) may include a plurality of transistors formed through the same process as the pixel circuit.

[0107] FIG. 3a is an equivalent circuit diagram of a pixel (PXij) according to an embodiment of the present invention. FIG. 3b is a waveform diagram of driving signals for driving the pixel (PXij) shown in FIG. 3a. FIG. 4a is an equivalent circuit diagram of a pixel (PXij) according to an embodiment of the present invention. FIG. 4b is a waveform diagram of driving signals for driving the pixel (PXij) shown in FIG. 4a.

[0108] FIG. 3a illustrates a pixel (PXij) that is connected to the i-th scanline (SL1i) of the first group of scanlines (SL11 to SL1n, see FIG. 2) and to the j-th data line (DLj) of the plurality of data lines (DL1 to DLm, see FIG. 2). The pixel (PXij) is connected to the i-th scanline (SL2i) of the second group of scanlines and to the i-th scanline (SL3i) of the third group of scanlines.

[0109] In this embodiment, the pixel circuit may include first to fifth transistors (T1 to T5), a first capacitor (C1) to a third capacitor (C3), and a light-emitting element (OLED). In this embodiment, the first to fourth transistors (T1 to T4) are described as N-type, and the fifth transistor (T5) is described as P-type. In one embodiment of the present invention, the third capacitor (C3) may be omitted.

[0110] In this embodiment, the first transistor (T1) is shown to include two gates, and each of the second to fifth transistors (T2 to T5) is shown to include one gate, but is not limited thereto. At least one of the second to fifth transistors (T2 to T5) may include two gates.

[0111] In this embodiment, the first transistor (T1) may be a driving transistor, and the second transistor (T2) may be a switching transistor. The node connected to the gate (G1-1, hereinafter the first upper gate) of the first transistor (T1) is defined as the first node (ND1), and the node connected to the source (S1) of the first transistor (T1) may be defined as the second node (ND2). The first capacitor (C1) is electrically connected to the first node (ND1), and the light-emitting element (OLED) is electrically connected to the second node (ND2).

[0112] The light-emitting element (OLED) includes a first electrode electrically connected to a second node (ND2), a second electrode electrically connected to a first voltage line (VL1) that receives a first power supply voltage (ELVSS), and a light-emitting layer disposed between the first electrode and the second electrode. A detailed description of the light-emitting element (OLED) will be provided later.

[0113] The first transistor (T1) is electrically connected between a second voltage line (VL2) that receives a second power supply voltage (ELVDD) and a second node (ND2). The first transistor (T1) may include a source (S1, hereinafter referred to as the first source), a drain (D1, hereinafter referred to as the first drain), a channel region (or semiconductor region), and a first upper gate (G1-1) connected to the second node (ND2). The first transistor (T1) may further include a gate (G1-2, hereinafter referred to as the first lower gate) connected to the second node (ND2). The first transistor (T1) controls the driving current of the light-emitting element (OLED) based on the charge capacity of the first capacitor (C1).

[0114] The second transistor (T2) is electrically connected between the first data line (DLj) and the first node (ND1). The second transistor (T2) may include a source (S2, hereinafter referred to as the second source) connected to the first node (ND1), a drain (D2, hereinafter referred to as the second drain) connected to the first data line (DLj), a channel region, and a gate (G2) connected to the i-th scanline (SL1i) of the first group. The second transistor (T2) outputs a data voltage. The first capacitor (C1) receives the data voltage.

[0115] The third transistor (T3) is electrically connected between the first node (ND1) and the third voltage line (VL3) that receives the first voltage (Vref). The third transistor (T3) may include a drain (D3, hereinafter referred to as the third drain) connected to the first node (ND1), a source (S3, hereinafter referred to as the third source) connected to the third voltage line (VL3), a channel region, and a third gate (G3) connected to the i-th scan line (SL2i) of the second group.

[0116] The fourth transistor (T4) is electrically connected between the fourth voltage line (VL4) receiving the second voltage (Vint) and the second node (ND2). The fourth transistor (T4) may include a drain (D4, hereinafter referred to as the fourth drain) connected to the second node (ND2), a source (S4, hereinafter referred to as the fourth source) connected to the fourth voltage line (VL4), a channel region, and a fourth gate (G4) connected to the i-th scan line (SL3i) of the third group.

[0117] The fifth transistor (T5) is electrically connected between the second voltage line (VL2) and the first drain (D1) or the first source (S1). In this embodiment, the fifth transistor (T5) may include a source (S5, hereinafter referred to as the fifth source) connected to the second voltage line (VL2), a drain (D5, hereinafter referred to as the fifth drain) connected to the first drain (D1), a channel region, and a fifth gate (G5) connected to the i-th light emission signal line (ELi).

[0118] The first capacitor (C1) is electrically connected between the first node (ND1) and the second node (ND2). The first capacitor (C1) includes a first electrode (E1-1) connected to the first node (ND1) and a second electrode (E1-2) connected to the second node (ND2).

[0119] The second capacitor (C2) is electrically connected between the second voltage line (VL2) and the second node (ND2). The second capacitor (C2) includes a first electrode (E2-1) connected to the second voltage line (VL2) and a second electrode (E2-2) connected to the second node (ND2).

[0120] The third capacitor (C3) is electrically connected between the first electrode and the second electrode of the light-emitting element (OLED). The third capacitor (C3) includes a first electrode (E3-1) connected to the first electrode of the light-emitting element (OLED) and a second electrode (E3-2) connected to the second electrode of the light-emitting element (OLED).

[0121] The operation of the pixel (PXij) is described in more detail with reference to FIGS. 3a and 3b. A display device (DD, see FIG. 2) displays an image for each frame interval. The signal lines of the first group of scan lines, the second group of scan lines, the third group of scan lines, and the light-emitting signal lines are each scanned sequentially during the frame interval. FIG. 3b illustrates a portion of the frame interval.

[0122] Referring to FIG. 3b, each of the signals (Ei, GRi, GWi, GIi) may have a high level (V-HIGH) for a portion of the time and a low level (V-LOW) for a portion of the time. The N-type first to fourth transistors (T1 to T4) described above are turned on when the corresponding control signal has a high level (V-HIGH). The P-type fifth transistor (T5) described above is turned on when the corresponding control signal has a low level (V-LOW).

[0123] During the initialization period (IP), the third transistor (T3) and the fourth transistor (T4) are turned on. The first node (ND1) is initialized to the first voltage (Vref). The second node (ND2) is initialized to the second voltage (Vint). The first capacitor (C1) is initialized to the difference between the first voltage (Vref) and the second voltage (Vint). The second capacitor (C2) is initialized to the difference between the second power supply voltage (ELVDD) and the second voltage (Vint). The third capacitor (C3) is initialized to the difference between the first power supply voltage (ELVSS) and the second voltage (Vint).

[0124] During the compensation period (CPP), the third transistor (T3) and the fifth transistor (T5) are turned on. The first voltage (Vref) is supplied to the first node (ND1), and the second power supply voltage (ELVDD) is supplied to the first drain region (D1) of the first transistor (T1) so that the first transistor (T1) can be turned on. When the voltage of the first source region (S1) of the first transistor (T1) reaches the difference between the first voltage (Vref) and the threshold voltage (Vth) of the first transistor (T1), the first transistor (T1) can be turned off. The voltage corresponding to the threshold voltage (Vth) of the first transistor (T1) is stored in the first capacitor (C1) so that the threshold voltage (Vth) of the first transistor (T1) can be compensated to the first capacitor (C1).

[0125] During the write interval (WP), the second transistor (T2) is turned on. The second transistor (T2) outputs a voltage (or data voltage) corresponding to the data signal (DS). Consequently, the first capacitor (C1) is charged with a voltage level corresponding to the data signal (DS). The first capacitor (C1) is charged with the data signal (DS) compensated for the threshold voltage of the first transistor (T1). The threshold voltages of the driving transistors may differ for each pixel (PX, see FIG. 2), and the pixel (PXij) illustrated in FIG. 2 and FIG. 3a can supply a current of a magnitude proportional to the data signal (DS) to the light-emitting element (OLED) regardless of the deviation in the threshold voltages of the driving transistors.

[0126] Subsequently, during the light emission period, the fifth transistor (T5) is turned on. The first transistor (T1) provides a current to the light-emitting element (OLED) corresponding to the charge capacity stored in the first capacitor (C1). The light-emitting element (OLED) can emit light with a brightness corresponding to the data signal (DS).

[0127] The pixel (PXij) illustrated in FIG. 4a is described focusing on the differences from the pixel (PXij) illustrated in FIG. 3a. The pixel circuit of FIG. 4a may further include a sixth transistor (T6). In this embodiment, the sixth transistor (T6) may be a P-type transistor, but is not particularly limited. Additionally, the connection relationship of the fourth transistor (T4) to other transistors in the pixel circuit of FIG. 4a is different from that of the pixel circuit of FIG. 3a.

[0128] The sixth transistor (T6) is electrically connected between the second node (ND2) and the first electrode of the light-emitting element (OLED). In this embodiment, the sixth transistor (T6) may include a source (S6, hereinafter referred to as the sixth source) connected to the second node (ND2), a drain (D6, hereinafter referred to as the sixth drain) connected to the first electrode of the light-emitting element (OLED), a channel region, and a sixth gate (G6) connected to the i-th light-emitting signal line (EMLi). When the i-th light-emitting signal line (ELi) connected to the fifth gate (G5) is defined as the light-emitting signal line of the first group, the i-th light-emitting signal line (EMLi) connected to the sixth gate (G6) may be defined as the light-emitting signal line of the second group. The drain (D4) of the fourth transistor (T4) may be connected to the first electrode of the light-emitting element (OLED) and the sixth drain (D6).

[0129] Referring to FIG. 4b, during the initialization period (IP), the third transistor (T3), the fourth transistor (T4), and the sixth transistor (T6) are turned on. The first capacitor (C1) is initialized to the difference between the first voltage (Vref) and the second voltage (Vint).

[0130] The period during which both the third transistor (T3) and the fifth transistor (T5) are turned on corresponds to the compensation period (CPP). The first electrode of the light-emitting device (OLED) can be initialized from the time the fourth transistor (T4) is turned on until it is turned off. The EL initialization period (EIP) is located after the write period (WP). During the EL initialization period (EIP), the fourth transistor (T4) and the sixth transistor (T6) are turned on. The first electrode and the second node (ND2) of the light-emitting device (OLED) are initialized to the second voltage (Vint).

[0131] FIG. 5 is a cross-sectional view of a display panel (141) according to an embodiment of the present invention. The cross-section of FIG. 5 is illustrated centering on the first, second, and fifth transistors (T1, T2, and T5) of FIG. 3a.

[0132] Referring to FIG. 5, the display panel (141) may include a base layer (BS), a circuit element layer (141-CL) disposed on the base layer (BS), a display element layer (141-OLED), and a thin film encapsulation layer (TFE). Although not shown, the display panel (141) may further include functional layers, such as an anti-reflective layer or a refractive index control layer, disposed on the thin film encapsulation layer (TFE).

[0133] The base layer (BS) may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material thereof is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylate resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer (BS) may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc. The base layer (BS) may include a first polyimide layer, a second polyimide layer, and an inorganic layer disposed between them.

[0134] A buffer layer (BFL) comprising at least one inorganic layer is disposed on the upper surface of a base layer (BS). The buffer layer (BFL) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The buffer layer (BFL) can prevent foreign substances from entering from the outside. The buffer layer (BFL) improves the bonding strength between the base layer (BS) and a semiconductor pattern and / or a conductive pattern disposed on the upper side.

[0135] A silicon semiconductor layer is disposed on the buffer layer (BFL). The silicon semiconductor layer may include a plurality of semiconductor patterns. In this embodiment, the semiconductor pattern may be a silicon semiconductor pattern (SP5). The silicon semiconductor pattern (SP5) may be a semiconductor pattern of the fifth transistor (T5).

[0136] The silicon semiconductor pattern (SP5) may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon, etc. For example, the silicon semiconductor pattern (SP5) may include polysilicon crystallized at low temperature (hereinafter, crystalline polysilicon).

[0137] The silicon semiconductor pattern (SP5) may have different electrical properties depending on whether it is doped. The fifth source (S5), fifth drain (D5), and channel region described with reference to FIG. 3a may be formed from the silicon semiconductor pattern (SP5). The fifth source (S5), fifth drain (D5), and channel region may correspond to the fifth source region (S5), fifth drain region (D5), and fifth channel region (A5) of FIG. 5. The fifth source region (S5) and the fifth drain region (D5) may extend in opposite directions from the fifth channel region (A5). Hereinafter, for convenience of explanation, the silicon semiconductor pattern (SP5) may be defined as the third semiconductor pattern (SP5). In this embodiment, the fifth source region (S5) may be defined as the fifth input region, and the fifth drain region (D5) may be defined as the fifth output region. Although a P-type fifth transistor (T5) has been described as an example, if the properties of the fifth transistor (T5) are N-type, it may be defined in the opposite way.

[0138] Although not separately illustrated, the semiconductor pattern of the sixth transistor (T6), described with reference to FIG. 4a, may also be placed on the same layer as the third semiconductor pattern (SP5). The semiconductor pattern of the sixth transistor (T6) is formed through the same process as the third semiconductor pattern (SP5) and may include the same semiconductor. The third semiconductor pattern (SP5) is placed on an insulating layer different from the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) described later. Here, being placed on a different insulating layer means contacting the upper surface of different insulating layers among the insulating layers placed on the base layer.

[0139] In FIG. 3a, the response speed of the fifth transistor (T5) and the sixth transistor (T6) can be increased by including a crystalline polysilicon semiconductor pattern. This is because the crystalline polysilicon semiconductor pattern has a faster mobility compared to other semiconductors.

[0140] A first insulating layer (10) covering a third semiconductor pattern (SP5) is disposed on a buffer layer (BFL). In this embodiment, the first insulating layer (10) may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. In this embodiment, the first insulating layer (10) may include silicon oxide, silicon nitride, or silicon oxynitride.

[0141] A conductive layer (hereinafter, the first conductive layer) is disposed on the first insulating layer (10). The first conductive layer may include a plurality of conductive patterns (hereinafter, the first conductive patterns). In FIG. 5, a fifth gate electrode (G5) and a second voltage line (VL2) are shown as examples of the first conductive patterns. The fifth gate electrode (G5) corresponds to the fifth gate (G5) of FIG. 3a and may have substantially the same area as the fifth channel region (A5).

[0142] FIG. 5 shows a second voltage line (VL2) separated into two parts, but is not limited thereto. The second voltage line (VL2) separated into two parts may have a single shape. Additionally, it is sufficient that a conductive pattern receiving the second power supply voltage (ELVDD) is disposed on the first insulating layer (10), and the second voltage line (VL2) does not necessarily need to be disposed on the first insulating layer (10).

[0143] A second insulating layer (20) covering the first conductive layer is disposed on the first insulating layer (10). In this embodiment, the second insulating layer (20) may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. In this embodiment, the second insulating layer (20) may include silicon oxide, silicon nitride, or silicon oxynitride.

[0144] A conductive layer (hereinafter referred to as the second conductive layer) is disposed on the second insulating layer (20). The second conductive layer may include a plurality of conductive patterns (hereinafter referred to as the second conductive patterns). In FIG. 5, one conductive pattern (CP) is shown as an example of the second conductive pattern. The conductive pattern (CP) may correspond to the first lower gate (G1-2) and the second electrode (E2-2) of the second capacitor (C2) in FIG. 3a. The conductive pattern (CP) may define the second voltage line (VL2) disposed on the lower side and the second capacitor (C2) in FIG. 3a.

[0145] A third insulating layer (30) covering the second conductive layer is disposed on the second insulating layer (20). In this embodiment, the third insulating layer (30) may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. In this embodiment, the third insulating layer (30) may include silicon oxide, silicon nitride, or silicon oxynitride.

[0146] A metal oxide semiconductor layer is disposed on the third insulating layer (30). The metal oxide semiconductor layer may include a plurality of semiconductor patterns. In this embodiment, a first semiconductor pattern (SP1) and a second semiconductor pattern (SP2) containing different metal oxide semiconductors may be disposed on the third insulating layer (30). The first semiconductor pattern (SP1) may be the semiconductor pattern of the first transistor (T1) of FIG. 3a, and the second semiconductor pattern (SP2) may be the semiconductor pattern of the second transistor (T2) of FIG. 3a. Although not separately illustrated, the semiconductor patterns of the third and fourth transistors (T3, T4) described with reference to FIG. 3a may also be formed through the same process as the second semiconductor pattern (SP2) and may include the same semiconductor.

[0147] The first semiconductor pattern (SP1) may include a crystalline oxide semiconductor, and the second semiconductor pattern (SP2) may include an amorphous oxide semiconductor. The first semiconductor pattern (SP1) may include a crystalline indium gallium oxide (IGO) semiconductor, and the second semiconductor pattern (SP2) may include an amorphous indium tin gallium zinc oxide (ITGZO) semiconductor. A transistor including an oxide semiconductor has the advantage of having a lower leakage current compared to a transistor including a silicon semiconductor.

[0148] Each of the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) may include multiple regions distinguished by whether or not the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, the reduced region) has greater conductivity than the region where it is not reduced (hereinafter, the non-reduced region). The reduced region substantially serves as the source region, drain region, or signal transmission region of the transistor. The non-reduced region substantially corresponds to the channel region (or semiconductor region, or non-reduced region) of the transistor. In other words, a part of the semiconductor pattern may be the channel region of the transistor, another part may be the source region or drain region of the transistor, and yet another part may be the signal transmission region.

[0149] The first source (S1), first drain (D1), and channel region described with reference to FIG. 3a can be formed from the first semiconductor pattern (SP1). The first source (S1), first drain (D1), and channel region may correspond to the first source region (S1), first drain region (D1), and first channel region (A1) of FIG. 5. The first source region (S1) and the first drain region (D1) may extend in opposite directions from the first channel region (A1). In this embodiment, the first drain region (D1) may be defined as the first input region, and the first source region (S1) may be defined as the first output region. Although an N-type first transistor (T1) has been described as an example, if the nature of the first transistor (T1) is P-type, it may be defined in the opposite way.

[0150] The second source (S2), second drain (D2), and channel region described with reference to FIG. 3a may be formed from the second semiconductor pattern (SP2). The second source (S2), second drain (D2), and channel region may correspond to the second source region (S2), second drain region (D2), and second channel region (A2) of FIG. 5. The second source region (S2) and the second drain region (D2) may extend in opposite directions from the second channel region (A2). In this embodiment, the second drain region (D2) may be defined as the second input region, and the second source region (S2) may be defined as the second output region. Although an N-type second transistor (T2) has been described as an example, if the nature of the second transistor (T2) is P-type, it may be defined in the opposite way.

[0151] A fourth insulating layer (40) is disposed on the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2). In this embodiment, the fourth insulating layer (40) may include silicon oxide, silicon nitride, or silicon oxynitride.

[0152] In this embodiment, the fourth insulating layer (40) is not formed entirely on the third insulating layer (30) but overlaps only the channel region of the transistor. The fourth insulating layer (40) may include a plurality of insulating patterns. In FIG. 5, a first insulating pattern (40-1) and a second insulating pattern (40-2) are illustrated as examples. In one embodiment of the present invention, the fourth insulating layer (40) may not be patterned and may overlap entirely on the third insulating layer (30).

[0153] A conductive layer (hereinafter referred to as the third conductive layer) is disposed on the fourth insulating layer (40). A first upper gate electrode (G1-1) is disposed on the first insulating pattern (40-1), and a second gate electrode (G2) is disposed on the second insulating pattern (40-2). The first upper gate electrode (G1-1) and the second gate electrode (G2) correspond to the first upper gate (G1-1) and the second gate (G2) of FIG. 3a, respectively.

[0154] Since the insulating layer is etched using the first upper gate electrode (G1-1) and the second gate electrode (G2) after forming them as a mask, the first insulating pattern (40-1) can have substantially the same shape as the first upper gate electrode (G1-1). For the same reason, the second insulating pattern (40-2) can have substantially the same shape as the second gate electrode (G2). The edges of the gate electrodes and the edges of the insulating pattern that overlap each other can be aligned.

[0155] A fifth insulating layer (50) is disposed on the third insulating layer (30). The fifth insulating layer (50) can cover the first upper gate electrode (G1-1) and the second gate electrode (G2). In this embodiment, the fifth insulating layer (50) may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. In this embodiment, the fifth insulating layer (50) may include silicon oxide, silicon nitride, or silicon oxynitride.

[0156] A conductive layer (hereinafter, the fourth conductive layer) is disposed on the fifth insulating layer (50). The fourth conductive layer may include a plurality of conductive patterns (hereinafter, the fourth conductive patterns). In FIG. 5, three types of connecting electrodes (CNE1, CNE2, CNE3) are shown as examples of the fourth conductive patterns.

[0157] A first connecting electrode (CNE1) connected to at least one of a first source region (S1) and a first drain region (D1) may be disposed on the fifth insulating layer (50). FIG. 5 illustrates two first connecting electrodes (CNE1) respectively connected to the first source region (S1) and the first drain region (D1). Each of the first connecting electrodes (CNE1) is connected to the corresponding region of the first source region (S1) and the first drain region (D1) through a contact hole (CH1) penetrating the fifth insulating layer (50).

[0158] One first connecting electrode (CNE1) can electrically connect the first source region (S1) and the conductive pattern (CP). One first connecting electrode (CNE1) can be connected to the conductive pattern (CP) through a contact hole (CH2) penetrating the third insulating layer (30) and the fifth insulating layer (50).

[0159] A second connecting electrode (CNE2) connected to at least one of the second source region (S2) and the second drain region (D2) may be disposed on the fifth insulating layer (50). FIG. 5 illustrates, exemplarily, two second connecting electrodes (CNE2) connected to the second source region (S2) and the second drain region (D2), respectively. Each of the second connecting electrodes (CNE2) is connected to the corresponding region of the second source region (S2) and the second drain region (D2) through a contact hole (CH1) penetrating the fifth insulating layer (50).

[0160] A third connecting electrode (CNE3) connected to at least one of the fifth source region (S5) and the fifth drain region (D5) may be disposed on the fifth insulating layer (50). In FIG. 5, two third connecting electrodes (CNE3) connected to the fifth source region (S5) and the fifth drain region (D5), respectively, are illustrated as examples. Each of the third connecting electrodes (CNE3) is connected to the corresponding region of the fifth source region (S5) and the fifth drain region (D5) through a contact hole (CH3) penetrating the first insulating layer (10), the second insulating layer (20), the third insulating layer (30), and the fifth insulating layer (50). Unlike what is illustrated in FIG. 5, a single connecting electrode may connect the first drain region (D1) and the fifth drain region (D5).

[0161] A sixth insulating layer (60) is disposed on the fifth insulating layer (50). The sixth insulating layer (60) can cover the connecting electrodes (CNE1, CNE2, CNE3). In this embodiment, the sixth insulating layer (60) may be an organic layer and may have a single-layer structure, but is not particularly limited.

[0162] A conductive layer (hereinafter, the fifth conductive layer) is disposed on the sixth insulating layer (60). The fifth conductive layer may include a plurality of conductive patterns. The fifth conductive layer includes a fourth connecting electrode (CNE4). The fourth connecting electrode (CNE4) is connected to the first connecting electrode (CNE1) through a contact hole (CH4) that penetrates the sixth insulating layer (60).

[0163] The fifth conductive layer may further include a data line (DLj) and a first voltage line (VL1). The data line (DLj) may be connected to a second connecting electrode (CNE2) through a contact hole (CH4) penetrating the sixth insulating layer (60). A portion of the first voltage line (VL1) that overlaps with the first electrode (AE) of the light-emitting element (OLED) described later defines the second electrode (E3-2) of the third capacitor (C3) shown in FIG. 3a. A portion of the first electrode (AE) of the light-emitting element (OLED) defines the first electrode (E3-1) of the third capacitor (C3) shown in FIG. 3a.

[0164] A seventh insulating layer (70) covering the fifth conductive layer is disposed on the sixth insulating layer (60). In this embodiment, the seventh insulating layer (70) may be an organic layer and may have a single-layer structure, but is not particularly limited.

[0165] A first electrode (AE) of a light-emitting element (OLED) is disposed on a seventh insulating layer (70). The first electrode (AE) may be an anode. The first electrode (AE) is connected to a fourth connecting electrode (CNE4) through a contact hole (CH5) penetrating the seventh insulating layer (70). A pixel defining film (PDL) is disposed on the seventh insulating layer (70).

[0166] An opening (OP) of the pixel defining film (PDL) exposes at least a portion of the first electrode (AE). An opening (OP) of the pixel defining film (PDL) can define a light-emitting region (LA). For example, a plurality of pixels (PX, see FIG. 2) can be arranged in a certain order on a plane of a display panel (141). The area where the plurality of pixels (PX) are arranged can be defined as a display area, and the display area may include a plurality of light-emitting regions (LA) and a non-light-emitting region (NLA) adjacent to the light-emitting regions (LA). The non-light-emitting region (NLA) can surround the light-emitting region (LA).

[0167] A hole control layer (HCL) can be placed in common in the light-emitting region (LA) and the non-light-emitting region (NLA). A common layer such as the hole control layer (HCL) can be formed in common in a plurality of pixels (PX). The hole control layer (HCL) may include a hole transport layer and a hole injection layer.

[0168] An emitting layer (EML) is disposed on the hole control layer (HCL). The emitting layer (EML) may be disposed only in the area corresponding to the aperture (OP). The emitting layer (EML) may be formed separately on each of the plurality of pixels (PX).

[0169] In this embodiment, a patterned light-emitting layer (EML) is illustrated as an example, but the light-emitting layer (EML) can be commonly disposed across a plurality of pixels (PX). The commonly disposed light-emitting layer (EML) can generate white light or blue light. Additionally, the light-emitting layer (EML) may have a multilayer structure.

[0170] An electronic control layer (ECL) is disposed on the light-emitting layer (EML). The electronic control layer (ECL) may include an electron transport layer and an electron injection layer. A second electrode (CE) is disposed on the electronic control layer (ECL). The electronic control layer (ECL) and the second electrode (CE) are commonly disposed on a plurality of pixels (PX).

[0171] A thin film encapsulation layer (TFE) is disposed on the second electrode (CE). The thin film encapsulation layer (TFE) is disposed in common on a plurality of pixels (PX). In this embodiment, the thin film encapsulation layer (TFE) directly covers the second electrode (CE). In one embodiment of the present invention, a capping layer that directly covers the second electrode (CE) may be further disposed. In one embodiment of the present invention, the stacked structure of the light-emitting element (OLED) may have a structure that is inverted vertically from the structure shown in FIG. 5.

[0172] The thin film encapsulation layer (TFE) comprises at least an inorganic layer or an organic layer. In one embodiment of the present invention, the thin film encapsulation layer (TFE) may comprise two inorganic layers and an organic layer disposed between them. In one embodiment of the present invention, the thin film encapsulation layer may comprise a plurality of inorganic layers and a plurality of organic layers that are alternately stacked.

[0173] FIG. 6a is a graph showing the voltage-current characteristics of an oxide transistor according to a comparative example. FIG. 6b is a graph showing the voltage-current characteristics of an oxide transistor according to an embodiment of the present invention. FIG. 6c is a graph showing the voltage-current characteristics of an oxide transistor according to an embodiment of the present invention.

[0174] Figure 6a shows the voltage-current characteristics of a transistor comprising an amorphous indium gallium zinc oxide (IGZO) semiconductor. A gate voltage range that determines a drain current in the range of 1 μA to 1 μA can be defined as a low-current-drive voltage range. The low-current-drive voltage range calculated from the graph in Figure 6a is 0.49 V. Additionally, a mobility of 28 cm² / Vs can be calculated from the graph in Figure 6a.

[0175] Figure 6b shows the voltage-current characteristics of a transistor containing a crystalline indium gallium oxide (IGO) semiconductor. The low-current-drive voltage range calculated from the graph in Figure 6b is 0.73 V. Additionally, a mobility of 40 cm² / Vs can be calculated from the graph in Figure 6b. Comparing Figure 6a and Figure 6b, it can be seen that the transistor containing the crystalline indium gallium oxide (IGO) semiconductor has increased mobility and a wider low-current-drive voltage range.

[0176] As described with reference to FIGS. 3a to 4b, the low-gradation display quality of the display panel (141) can be improved by including a crystalline indium gallium oxide (IGO) semiconductor in the first semiconductor pattern (SP1) of the first transistor (T1). A wide low-current-drive voltage range means that the low current corresponding to the low gradation can be controlled in steps. A wide low-current-drive voltage range can improve current-voltage-luminance (IVL) characteristics.

[0177] Figure 6c shows the voltage-current characteristics of a transistor containing an amorphous indium tin gallium zinc oxide (ITGZO) semiconductor. The low-current-drive voltage range calculated from the graph in Figure 6c is 0.35 V. Additionally, a mobility of 64 cm² / Vs can be calculated from the graph in Figure 6c. Comparing Figure 6a and Figure 6c, it can be seen that the transistor containing the amorphous indium tin gallium zinc oxide (ITGZO) semiconductor has a low-current-drive voltage range similar to that of the transistor containing the amorphous indium gallium zinc oxide (IGZO) semiconductor, but has more than twice the mobility.

[0178] As described with reference to FIGS. 3a to 4b, the response speed of the second transistor (T2) can be increased by including an amorphous indium tin gallium zinc oxide (ITGZO) semiconductor in the second semiconductor pattern (SP2) of the second transistor (T2). In addition, the area of ​​the second semiconductor pattern (SP2) can be reduced, that is, the second semiconductor pattern (SP2) can be designed as a short channel, thereby reducing the area of ​​the pixel circuit.

[0179] FIGS. 7a to 7h are cross-sectional views illustrating the manufacturing process of a display panel (141) according to an embodiment of the present invention. Hereinafter, a detailed description of a configuration identical to the configuration described with reference to FIG. 5 is omitted.

[0180] As shown in FIG. 7a, a fifth transistor (T5) is formed on a base layer (BS). The fifth transistor (T5) includes a silicon semiconductor pattern (SP5) and a fifth gate (G5), as described with reference to FIG. 5.

[0181] First, a silicon semiconductor pattern (SP5) and a first insulating layer (10) are sequentially formed on a buffer layer (BFL). A silicon semiconductor layer is formed using the CVD (Chemical Vapor Deposition) method. Subsequently, the silicon semiconductor layer is patterned through a photolithography process to form a silicon semiconductor pattern (SP5).

[0182] Next, a first insulating layer (10) is formed through a deposition process. For example, an inorganic material can be deposited using the PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0183] A first conductive layer including first conductive patterns is formed on the first insulating layer (10). A fifth gate electrode (G5) and a second voltage line (VL2) are formed through a photolithography process. Subsequently, a second insulating layer (20) is formed on the first insulating layer (10).

[0184] A second conductive layer including second conductive patterns is formed on the second insulating layer (20). Conductive patterns (CP) are formed through a photolithography process. Subsequently, a third insulating layer (30) is formed on the second insulating layer (20).

[0185] Next, a first oxide semiconductor layer (SP1-P) is formed on the third insulating layer (30). The first oxide semiconductor layer (SP1-P) can be formed using sputtering or MOCVD (Metal Organic Chemical Vapor Deposition). The first oxide semiconductor layer (SP1-P) may include indium gallium oxide (IGO).

[0186] As shown in FIG. 7b, a first semiconductor pattern (SP1) is formed from a first oxide semiconductor layer (SP1-P). The first oxide semiconductor layer (SP1-P) is patterned through a photolithography process.

[0187] As shown in FIG. 7c, the first semiconductor pattern (SP1) is crystallized. Heat is applied to the first semiconductor pattern (SP1) to change the amorphous indium gallium oxide (IGO) into crystalline indium gallium oxide (IGO).

[0188] As illustrated in FIG. 7d, a second oxide semiconductor layer (SP2-P) covering a first semiconductor pattern (SP1) is formed on the second insulating layer (20). The second oxide semiconductor layer (SP2-P) can be formed using sputtering or MOCVD (Metal Organic Chemical Vapor Deposition). The second oxide semiconductor layer (SP2-P) may include indium tin gallium zinc oxide (ITGZO). The indium tin gallium zinc oxide (ITGZO) may be amorphous.

[0189] As illustrated in FIG. 7e, a second semiconductor pattern (SP2) is formed from a second oxide semiconductor layer (SP2-P). The second semiconductor pattern (SP1) may be spaced apart from the first semiconductor pattern (SP1) in cross-section. The second oxide semiconductor layer (SP2-P) is patterned through a photolithography process. At this time, a wet etching process may be performed. The crystalline indium gallium oxide (IGO) may not be damaged by the etchant used in the wet etching process.

[0190] As illustrated in FIG. 7f, a fourth insulating layer (40) and a third conductive layer (CL3) are formed sequentially on the third insulating layer (30). The fourth insulating layer (40) can be formed using the Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The third conductive layer (CL3) can be formed using the sputtering method.

[0191] As shown in FIG. 7g, the third conductive layer (CL3) can be patterned through a photolithography process. The first upper gate electrode (G1-1) and the second gate electrode (G2) are formed from the third conductive layer (CL3).

[0192] As illustrated in FIG. 7h, the first upper gate electrode (G1-1) and the second gate electrode (G2) can be used as masks to pattern the fourth insulating layer (40). A first insulating pattern (40-1) and a second insulating pattern (40-2) can be formed from the fourth insulating layer (40). The first insulating pattern (40-1) exposes a first source region (S1) and a first drain region (D1), and the second insulating pattern (40-2) exposes a second source region (S2) and a second drain region (D2).

[0193] Subsequently, additional subsequent processes can be carried out to complete the display panel (141) described with reference to FIG. 5. A process for forming an additional insulating layer and a process for forming a metal layer may be performed. Additionally, a process for forming a light-emitting element is further carried out. Afterwards, a process for forming a thin film encapsulation layer (TFE) is additionally carried out. These processes are not limited to specific processes.

[0194] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

[0195] A pixel circuit includes multiple transistors. At least one of the multiple transistors may be an oxide transistor. Since the operation of the pixel circuit can be controlled by utilizing the characteristics of oxide transistors, oxide transistors are highly likely to be applied to display devices.

Claims

1. Multiple insulating layers; light-emitting element; and It includes a pixel circuit electrically connected to the light-emitting element, and the pixel circuit, A first transistor comprising a first semiconductor pattern including a crystalline indium gallium oxide (IGO) semiconductor and controlling the driving current of the light-emitting element; and A display device comprising a second semiconductor pattern including an amorphous indium tin gallium zinc oxide (ITGZO) semiconductor and a second transistor that outputs a data voltage.

2. In Paragraph 1, A display device in which the first semiconductor pattern and the second semiconductor pattern are in contact with the upper surface of the same insulating layer among the plurality of insulating layers.

3. In Paragraph 1, The first transistor further includes a first gate electrode and a second gate electrode, and The first semiconductor pattern above includes a first channel region, a first input region, and a first output region, and The first gate electrode is positioned above the first channel region, and A display device in which the second gate electrode is positioned below the first channel region and is electrically connected to the first output region.

4. In Paragraph 1, A display device further comprising a third transistor including a third semiconductor pattern including a silicon semiconductor.

5. In Paragraph 4, A display device in which the third semiconductor pattern contacts the upper surface of one of the plurality of insulating layers, and the first semiconductor pattern and the second semiconductor pattern contact the upper surface of another of the plurality of insulating layers.

6. In Paragraph 4, It further includes a voltage line disposed on the lower side of the first semiconductor pattern and receiving a power supply voltage, and The third transistor further includes a gate electrode disposed on the upper side of the third semiconductor pattern, and A display device in which the gate electrode is spaced apart from the voltage line and positioned in a plane, and contacts the upper surface of the same insulating layer among the plurality of insulating layers.

7. In Paragraph 6, It further includes a conductive pattern disposed between the first semiconductor pattern and the voltage line, and The above challenge pattern is superimposed on the above first semiconductor pattern and the above voltage line, respectively, and A display device in which the output region of the first semiconductor pattern and the conductive pattern are electrically connected.

8. In Paragraph 1, A third transistor between a voltage line receiving a first voltage and the gate electrode of the first transistor; A fourth transistor between a voltage line receiving a second voltage and the first electrode of the light-emitting element; and It further includes a fifth transistor between a voltage line receiving a first power supply voltage and the first transistor, and The second electrode of the light-emitting element is a display device capable of receiving a second power supply voltage different from the first power supply voltage.

9. In Paragraph 8, A display device further comprising a sixth transistor capable of electrically connecting the first transistor and the first electrode of the light-emitting element.

10. In Paragraph 8, A display device in which the semiconductor pattern of each of the third transistor and the fourth transistor includes the same semiconductor as the second semiconductor pattern.

11. In Paragraph 10, A display device in which the semiconductor pattern of each of the third transistor and the fourth transistor contacts the upper surface of the same insulating layer among the second semiconductor pattern and the plurality of insulating layers.

12. In Paragraph 8, The above-mentioned fifth transistor is a display device comprising a third semiconductor pattern including a silicon semiconductor.

13. Display device; and It includes an input device that receives commands, inputs, or data from the outside, and the display device, Multiple insulating layers; light-emitting element; and It includes a pixel circuit electrically connected to the light-emitting element, and the pixel circuit, A first transistor comprising a first semiconductor pattern including a crystalline indium gallium oxide (IGO) semiconductor and controlling the driving current of the light-emitting element; and An electronic device comprising a second semiconductor pattern including an amorphous indium tin gallium zinc oxide (ITGZO) semiconductor and a second transistor that outputs a data voltage.

14. In Paragraph 13, The above input device is an electronic device that is an input sensor, keyboard, or mouse.

15. In Paragraph 13, The first semiconductor pattern and the second semiconductor pattern are in contact with the upper surface of the same insulating layer among the plurality of insulating layers in an electronic device.

16. In Paragraph 13, The first transistor further includes a first gate electrode and a second gate electrode, and The first semiconductor pattern above includes a first channel region, a first input region, and a first output region, and The first gate electrode is positioned above the first channel region, and The second gate electrode is positioned below the first channel region and is an electronic device electrically connected to the first output region.

17. In Paragraph 13, It further includes a third transistor including a third semiconductor pattern including a silicon semiconductor, and An electronic device in which the third semiconductor pattern contacts the upper surface of one of the plurality of insulating layers, and the first semiconductor pattern and the second semiconductor pattern contact the upper surface of another of the plurality of insulating layers.

18. A step of forming a first semiconductor pattern on an insulating layer; A step of crystallizing the first semiconductor pattern; A step of forming a second semiconductor layer covering the first semiconductor pattern on the insulating layer; and The method includes the step of forming a second semiconductor pattern spaced apart from the first semiconductor pattern on a plane from the second semiconductor layer, The first semiconductor pattern above includes an indium gallium oxide (IGO) semiconductor, and The above second semiconductor pattern is a method for manufacturing a display device comprising an indium tin gallium zinc oxide (ITGZO) semiconductor.

19. In Paragraph 18, A step of forming a first gate electrode on the first semiconductor pattern; and A method for manufacturing a display device, further comprising the step of forming a second gate electrode on the second semiconductor pattern.

20. In Paragraph 19, A method for manufacturing a display device further comprising the step of forming an insulating pattern that exposes a portion of the first semiconductor pattern between the first semiconductor pattern and the first gate electrode.

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