Clock synchronization method, terminal station, management station, storage medium, and program product

Abstract

The present application relates to a clock synchronization method, a terminal station (TS), a management station (MS), a storage medium, and a program product. The method is applied to a TS. The method comprises: receiving an MS system time, an uplink timing offset, and indication information of a first reference frame which are sent by an MS, the first reference frame being a radio frame used for measuring the uplink timing offset; and on the basis of the MS system time, the uplink timing offset and the indication information of the first reference frame, determining a TS system time synchronized with the MS. The method can be applied to industrial networks which do not support a TSN function.

Description

Clock synchronization method, terminal station, management station, storage medium and program product

[0001] Related applications

[0002] The present application claims priority to the Chinese patent application No. 202411373029.4, filed on September 29, 2024, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of time synchronization, in particular to a clock synchronization method, a terminal station, a management station, a storage medium and a program product. BACKGROUND

[0004] In order to realize high-precision clock synchronization, a clock synchronization architecture of 5G (5th Generation Mobile Communication Technology) and TSN (Time Sensitive Networking) fusion is introduced in new radio technology. The principle is to add a device side time sensitive translator (DS-TT) on the user equipment (UE) side and a network side time sensitive translator (NW-TT) on the core network side, and to regard the 5G network as a bridge to integrate into the TSN. However, this will not only increase the cost of hardware deployment, but also require the network to support TSN functions. Although the clock synchronization architecture of 5G and TSN fusion can realize high-precision clock synchronization, the architecture not only increases the hardware deployment cost by adding devices, but also requires the network to support TSN functions. For industrial networks that do not support TSN functions, high-precision clock synchronization cannot be achieved. SUMMARY

[0005] Therefore, it is necessary to provide a clock synchronization method, a terminal station, a management station, a storage medium and a program product capable of realizing high-precision clock synchronization in view of the above technical problems.

[0006] In a first aspect, the present application provides a clock synchronization method applied to a terminal station TS, the method comprising:

[0007] receiving the indication information of the MS system time, the uplink timing offset and the first reference frame sent by the management station MS; the first reference frame is a radio frame used to measure the uplink timing offset;

[0008] determine a TS system time synchronized with the MS based on the MS system time, the uplink timing offset, and the indication information of the first reference frame.

[0009] In a second aspect, the present application provides a clock synchronization method applied to an MS, the method comprising:

[0010] sending, to a TS, an MS system time, an uplink timing offset, and indication information of a first reference frame corresponding to the uplink timing offset; the first reference frame being a radio frame used to measure the uplink timing offset;

[0011] The MS system time, the uplink timing offset, and the indication information of the first reference frame are used to determine a TS system time synchronized with the MS.

[0012] In a third aspect, the present application provides a TS, comprising a memory, a transceiver, and a processor.

[0013] The memory is configured to store a computer program; the transceiver is configured to transceive data under control of the processor; and the processor is configured to read the computer program in the memory and execute the method of the first aspect.

[0014] In a fourth aspect, the present application provides an MS, comprising a memory, a transceiver, and a processor.

[0015] The memory is configured to store a computer program; the transceiver is configured to transceive data under control of the processor; and the processor is configured to read the computer program in the memory and execute the method of the second aspect.

[0016] In a fifth aspect, the present application further provides a TS, comprising:

[0017] A receiving module is configured to receive an MS system time, an uplink timing offset, and indication information of a first reference frame sent by an MS of a management station; the first reference frame being a radio frame used to measure the uplink timing offset;

[0018] A synchronizing module is configured to determine a TS system time synchronized with the MS based on the MS system time, the uplink timing offset, and the indication information of the first reference frame.

[0019] In a sixth aspect, the present application further provides an MS, comprising:

[0020] A sending module is configured to send, to a TS, an MS system time, an uplink timing offset, and indication information of a first reference frame; the first reference frame being a radio frame used to measure the uplink timing offset;

[0021] The MS system time, the uplink timing offset, and the indication information of the first reference frame are used to determine a TS system time synchronized with the MS.

[0022] In a seventh aspect, the present application provides a computer readable storage medium, having stored thereon a computer program, which, when executed by a processor, implements the method according to the first aspect or the second aspect.

[0023] In an eighth aspect, the present application provides a computer program product, comprising a computer program, which, when executed by a processor, implements the method according to the first aspect or the second aspect.

[0024] The clock synchronization method is applied to a terminal station TS, and the method comprises: receiving MS system time, an uplink timing offset, and indication information of a first reference frame sent by the MS, the first reference frame being a radio frame used to measure the uplink timing offset; and determining a TS system time synchronized with the MS based on the MS system time, the uplink timing offset, and the indication information of the first reference frame. Through this scheme, when synchronizing the clock of the TS with the MS, not only the MS system time is considered, but also the uplink timing offset and the indication information of the first reference frame used to measure the uplink timing offset are considered. Thus, when synchronizing the clock, the time delay related to the uplink timing offset is considered, which can make the TS system time synchronized with the MS achieve high precision, so that high-precision clock synchronization can be achieved without introducing TSN, the hardware deployment cost is reduced, and the industrial network that does not support the TSN function can be applied. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1 is a schematic diagram of an architecture of a wired-wireless fusion network;

[0026] FIG. 2 is a schematic diagram of a clock synchronization mechanism used in a clock synchronization method according to an embodiment of the present application;

[0027] FIG. 3A is a flowchart of a clock synchronization method;

[0028] FIG. 3B is a schematic diagram of an uplink timing offset;

[0029] FIG. 4 is a flowchart of another clock synchronization method;

[0030] FIG. 5 is a flowchart of a wired clock synchronization mechanism between a TS and a Driver;

[0031] FIG. 6 is a flowchart of a wired clock synchronization mechanism between an MS and a PLC;

[0032] FIG. 7 is a flowchart of a clock distribution method in which a boundary clock itself does not support high-precision timing function.

[0033] FIG. 8 is a schematic diagram of a clock synchronization function realized by interrupting the counting function of a signal;

[0034] FIG. 9 is a flowchart of a clock distribution method in which a boundary clock itself supports a high-precision timing function;

[0035] FIG. 10 is a schematic diagram of a clock synchronization function realized by a local clock;

[0036] FIG. 11 is a schematic diagram of a network topology of a multi-domain clock synchronization scenario;

[0037] FIG. 12 is a schematic diagram of the structure of an electronic device according to an embodiment;

[0038] FIG. 13 is a block diagram of the structure of a TS;

[0039] FIG. 14 is a block diagram of the structure of a MS. DETAILED DESCRIPTION

[0040] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0041] The term "and / or" in the embodiments of the present application describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0042] TSN is a new generation of network technology based on Ethernet, mainly used to meet the transmission needs of time-sensitive data. With the continuous development of industrial automation, intelligent vehicles, audio and video transmission and other fields, the real-time, deterministic and reliable requirements of the network are becoming higher and higher. Traditional Ethernet has certain limitations in these aspects and cannot guarantee low delay and high precision transmission of data. TSN network emerges in such a demand background, aiming to provide an efficient and reliable network communication solution for time-sensitive applications.

[0043] 5G NR supports a clock synchronization architecture for the integration of 5G and TSN in Release 16. The 5G network acts as a virtual bridge for the TSN network, with a DS-TT added on the UE side and a NW-TT added on the User Plane Function (UPF) side of the 5G core network. The two TSN translators, DS-TT and NW-TT, connect the 5G network to the TSN. The 5G network as a TS bridge needs to support the basic protocols related to TSN.

[0044] Although high-precision clock synchronization can be achieved through the 5G and TSN integrated clock synchronization architecture, the architecture not only increases the hardware deployment cost by adding devices, but also requires network support for TSN functions. For industrial networks that do not support TSN functions, high-precision clock synchronization cannot be achieved.

[0045] To solve the above problems, the embodiments of the present application provide a clock synchronization method based on a wired-wireless integrated network of a new type of industrial short-range wireless system. The clock synchronization method can provide a high-precision clock of less than or equal to 1us, meeting the requirements of industrial application scenarios such as motion control that require high-precision clock synchronization.

[0046] As shown in FIG. 1, it is an architecture schematic diagram of a wired-wireless integrated network. As shown in FIG. 1, the network can include: a management station (MS) 11, a terminal station (TS) 12, a next level network element 13 connected to the MS 11 through a wired connection, and a next level network element 14 connected to the TS 12 through a wired connection. Among them, the next level network element 13 connected to the MS 11 can be a controller (PLC) in the industrial network, and the next level network element connected to the TA can be a driver (Driver) in the industrial network.

[0047] Among them, the TS is an important part of the wired-wireless integrated network. In the industrial network environment, it connects the next level network element through a wired connection, and usually connects the driver (Driver). The TS is mainly responsible for receiving and sending data, conveying instructions from the upper device to the next level driver, and feeding back the status information of the driver to the upper network. It plays a terminal node role in data transmission in the entire network architecture, ensuring that the control signals and data in industrial production can be accurately transmitted to the execution device.

[0048] The MS plays a core management and control role in the network. It connects the next level network element through a wired connection, and usually connects other MS or controller (PLC) in the industrial network. The management station is responsible for monitoring, configuring and managing the entire network. It can monitor the status of each terminal station and the next level network element in real time, and send control instructions to adjust the industrial production process. At the same time, the management station also has the functions of data analysis and fault diagnosis, which can timely find out the problems in the network and take corresponding measures to repair, so as to ensure the stable operation of industrial production.

[0049] In the wire-wireless converged network, the clock synchronization method provided by the embodiment of the present application can include a wired clock synchronization mechanism and a wireless clock synchronization mechanism. The wired clock synchronization mechanism is used to achieve high-precision clock synchronization between devices connected by wire, such as between MSs or between an MS and a controller or between a TS and a driver. The wireless clock synchronization mechanism is used to achieve high-precision clock synchronization between devices connected by wire, such as between an MS and a TS.

[0050] For example, as shown in FIG. 2, a schematic diagram of a clock synchronization method provided by the embodiment of the present application using a clock synchronization mechanism. As shown in FIG. 2, the MS and the TS are connected by wire. The MS is a clock source and can serve as a master clock. The TS is a slave clock relative to the MS. When the TS and the MS perform clock synchronization, they can first perform air interface synchronization by using a downlink air interface synchronization mechanism and an uplink air interface synchronization mechanism, and then perform clock synchronization by using a wireless air interface clock synchronization mechanism. After the clock synchronization is completed, the TS can serve as a master clock of a next-level network element connected to the TS by wire. The next-level network element is a slave clock at this time. The TS and the next-level network element connected to the TS by wire can perform clock synchronization by using a wired clock synchronization mechanism. Similarly, after the clock synchronization of the next-level network element connected to the TS by wire is completed, the next-level network element can serve as a master clock of a next-level connected device to perform subsequent clock synchronization. For a next-level network element connected to the MS by wire, the MS is a master clock and the next-level network element connected by wire is a slave clock. The MS and the next-level network element connected to the MS by wire can perform clock synchronization by using a wired clock synchronization mechanism. Similarly, after the clock synchronization of the next-level network element connected to the MS by wire is completed, the next-level network element can serve as a master clock of a next-level connected device to perform subsequent clock synchronization.

[0051] It should be noted that, in the embodiment of the present application, the implementation of the downlink air interface synchronization mechanism or the uplink air interface synchronization mechanism is not limited. The existing conventional air interface synchronization mechanism or any mechanism that can achieve uplink or downlink air interface synchronization can be used.

[0052] In order to describe the clock synchronization method provided by the embodiment of the present application in detail, the wireless air interface clock synchronization mechanism and the wired clock synchronization mechanism are described respectively.

[0053] (1) Wireless air interface clock synchronization mechanism

[0054] For example, as shown in FIG. 3A, a flowchart of a clock synchronization method provided by the embodiment of the present application. The method can include but is not limited to the following steps:

[0055] 301. The MS sends the MS system time, the uplink timing offset, and the indication information of the first reference frame to the TS.

[0056] Correspondingly, the TS receives the MS system time, the uplink timing offset, and the indication information of the first reference frame sent by the MS.

[0057] The first reference frame is a radio frame used for measuring the uplink timing offset.

[0058] In the process of air interface radio clock synchronization mechanism, the TS needs to obtain the MS system time to calibrate the TS system clock, and also needs to consider the time delay caused by air interface transmission to calibrate the TS system clock based on the uplink timing offset and the indication information of the first reference frame.

[0059] In the embodiments of the present application, the MS system time is the system time obtained by the MS itself.

[0060] In the embodiments of the present application, the uplink timing offset refers to the deviation value of the time at which the MS receives the signal sent by the TS relative to the frame boundary of the radio frame. Since the signal will be affected by various factors in the process of wireless transmission, there is a difference between the actual transmission time and the expected time.

[0061] For example, FIG. 3B is a schematic diagram of uplink timing offset. As shown in FIG. 3B, when the TS sends the uplink signal to the MS, the actual time at which the MS receives is the time B shown in the figure, and the deviation value t between the time B and the frame boundary of the radio frame in which the time B is located is the uplink timing offset.

[0062] The indication information of the first reference frame can be the indication information of the radio frame used for measuring the uplink timing offset.

[0063] In some embodiments, the reference frame refers to a reference radio frame, and the indication information of the first reference frame can be the identification of the first reference frame, such as the frame number of the first reference frame.

[0064] In some embodiments, the MS system time can be sent by being carried in a system broadcast message.

[0065] In some embodiments, the uplink timing offset and the indication information of the first reference frame can be sent by being carried in a unicast message.

[0066] In some embodiments, the MS system time, the uplink timing offset, and the indication information of the first reference frame can also be sent by being carried in a unicast message.

[0067] 302、TS determines the TS system time synchronized with the MS based on the MS system time, the uplink timing offset and the indication information of the first reference frame.

[0068] In some embodiments, the TS determines the TS system time synchronized with the MS based on the MS system time, the uplink timing offset and the indication information of the first reference frame, which can include but is not limited to: the TS first determines the time delay from the TS to the MS based on the uplink timing offset and the indication information of the first reference frame, and then the TS determines the TS system time synchronized with the MS according to the MS system time and the time delay from the TS to the MS.

[0069] The time delay from the TS to the MS is the time delay between the time when the uplink timing offset is measured and the time when the TS system time synchronized with the MS is determined.

[0070] In some embodiments, in the process of determining the TS system time synchronized with the MS according to the MS system time and the time delay from the TS to the MS, the MS system time and the time delay from the TS to the MS can be summed to obtain the TS system time synchronized with the MS.

[0071] The TS system time synchronized with the MS can be represented by the following formula (1) for example: Tsys TS = Tsys MS + Tdelay (1)

[0072] In the formula (1), Tsys TS represents the TS system time synchronized with the MS, Tsys MS represents the MS system time, and Tdelay represents the time delay from the TS to the MS.

[0073] In some embodiments, the process of determining the time delay from the TS to the MS based on the uplink timing offset and the indication information of the first reference frame can include but is not limited to: the TS first determines the locally maintained timing advance (TA) corresponding to the first reference frame based on the indication information of the first reference frame, then the TS determines the air interface transmission time delay corresponding to the first reference frame based on the TA and the uplink timing offset, and finally the TS determines the time delay from the TS to the MS according to the air interface transmission time delay corresponding to the first reference frame and the adjustment amount of the downlink timing accumulated from the first reference frame to the second reference frame.

[0074] The second reference frame is the reference frame for recovering the system clock.

[0075] The TS will locally maintain the correspondence between the frame number and the timing advance TA.

[0076] For example, assuming that the frame number of the first reference frame is n, the TS can determine the timing advance TA corresponding to the frame number n maintained locally according to the frame number n of the first reference frame, which can be denoted as TA(n). The uplink timing offset described above is also corresponding to the frame number n of the first reference frame, which can be denoted as TO(n), and then the round-trip transmission delay between the MS and the TS corresponding to the first reference frame can be determined according to the sum of TA(n) and TO(n). The transmission delay corresponding to the first reference frame described above is the single-trip transmission delay between the MS and the TS, which can be considered as half of the sum of TA(n) and TO(n).

[0077] Since the time from the first reference frame to the second reference frame, the downlink timing corresponding to different frames may be adjusted in this process, and thus the cumulative adjustment amount of the downlink timing from the first reference frame to the second reference frame can be calculated. The downlink timing adjustment amount corresponding to each frame can be calculated and summed to obtain the cumulative adjustment amount of the downlink timing from the first reference frame to the second reference frame.

[0078] For example, assuming that the frame number of the second reference frame is n+k, the cumulative adjustment amount of the downlink timing from the first reference frame to the second reference frame can be denoted as where Δt(i) refers to the cumulative amount of the i th downlink timing of the k downlink timings from the first reference frame to the second reference frame.

[0079] The delay from the TS to the MS can be represented by the following formula (2):

[0080] where it is assumed that the frame number of the first reference frame is n and the frame number of the second reference frame is n+k, and the delay from the TS to the MS is obtained by using the Tdelay(n+k) table described above.

[0081] It should be noted that if the downlink timing changes from the first reference frame to the second reference frame, the above is equal to the downlink timing adjustment amount; if the downlink timing does not change from the first reference frame to the second reference frame, the above is 0.

[0082] The clock synchronization method described above not only considers the MS system time when synchronizing the clock of the TS and the MS, but also considers the uplink timing offset and the indication information of the first reference frame. Therefore, the time delay related to the uplink timing offset is considered when the clock is synchronized, which can make the TS system time synchronized with the MS achieve high precision, so that high-precision clock synchronization can be achieved without introducing TSN, reducing the hardware deployment cost, and can be applied to industrial networks that do not support TSN function.

[0083] In the above embodiment, the calculation manner of determining the time delay between the TS and the MS is given by the uplink timing offset and the indication information of the first reference frame. The manner can accurately calculate the time delay between the TS and the MS, so that the finally determined TS system time synchronized with the MS also has high precision, and high-precision clock synchronization is achieved.

[0084] In the embodiment of the application, since some time has elapsed between the MS sending the MS system time and the TS determining the TS system time synchronized with the MS, frame offset exists, therefore, in addition to considering the time delay related to the uplink timing offset, the frame offset in the transmission process can also be considered, so as to determine the TS system time synchronized with the MS more accurately.

[0085] In some embodiments, the TS determines the TS system time synchronized with the MS based on the MS system time, the uplink timing offset and the indication information of the first reference frame, which can include but is not limited to: the TS first determines the frame offset between the third reference frame and the second reference frame, and then the TS determines the TS system time synchronized with the MS based on the frame offset, the MS system time, the uplink timing offset and the indication information of the first reference frame.

[0086] The third reference frame is the reference frame corresponding to the MS system time, and the second reference frame is the current reference frame, wherein the second reference frame is the reference frame of the recovered system clock. That is, the frame offset between the third reference frame and the second reference frame is the frame offset between the MS sending the MS system time and the TS determining the TS system time synchronized with the MS.

[0087] In some embodiments, the indication information of the third reference frame is sent by being carried in a system broadcast message.

[0088] Optionally, in some embodiments, the indication information of the third reference frame can also be sent by being carried in a unicast message.

[0089] In some embodiments, determining the frame offset between the third reference frame and the second reference frame can include but is not limited to: the MS sends the indication information of the third reference frame corresponding to the MS system time to the TS, the TS receives the indication information of the third reference frame corresponding to the MS system time sent by the MS, then the TS determines the number of radio frames between the third reference frame and the second reference frame based on the indication information of the third reference frame, and finally the TS determines the frame offset according to the number of radio frames and the length of the radio frame.

[0090] The indication information of the third reference frame can be an identification of the third reference frame, for example, a frame number of the third reference frame. The frame offset can be a product of a number of radio frames and a length of a radio frame. For example, assuming that the number of radio frames between the third reference frame and the second reference frame is x, and the length of a radio frame is represented as Tframe, which can be in nanoseconds (ns), then according to the above formula (1), the following formula (3) can be obtained: Tsys TS = Tsys MS + Tdelay + x * Tframe (3)

[0091] In the above embodiment, not only the time delay related to the uplink timing offset is considered, but also the frame offset in the transmission process, so that a more accurate TS system time synchronized with the MS can be determined.

[0092] For example, as shown in FIG. 4, a flowchart of another clock synchronization method provided by the embodiment of the application is shown, which can include but is not limited to the following steps:

[0093] 401. The MS and the TS are synchronized through a downlink air interface synchronization mechanism or an uplink air interface synchronization mechanism.

[0094] The MS is a clock source, that is, a master clock, and the TS is a slave clock.

[0095] 402. The MS sends a system broadcast message, which includes the MS system time and the frame number of the third reference frame.

[0096] One MS can be connected to multiple TSs wirelessly, and the MS can send the MS system time and the frame number of the third reference frame through broadcasting, so that the TSs connected to the MS wirelessly receive the MS system time and the frame number of the third reference frame.

[0097] 403. The MS sends a unicast message to the TS, which includes the uplink timing offset and the frame number of the first reference frame.

[0098] Since the uplink timing offset is for one TS, the MS can send the uplink timing offset and the frame number of the first reference frame to each TS through unicast.

[0099] 404. The TS performs system clock calibration to determine the TS system time synchronized with the MS.

[0100] The TS can determine the TS system time synchronized with the MS based on the MS system time, the frame number of the third reference frame, the uplink timing offset, and the frame number of the first reference frame. The determination method has been described in detail in the foregoing process, and will not be described here again.

[0101] The clock synchronization method provided by the above embodiment, the MS informs the TS of the parameters for clock synchronization through broadcast messages and unicast messages, considers the MS system time, the delay related to the uplink timing offset and the frame offset in the transmission process, so that the TS can determine a more accurate TS system time synchronized with the MS through simple information interaction.

[0102] (2) Wired clock synchronization mechanism

[0103] For the above MS and TS, after the TS determines the TS system time synchronized with the MS, the TS can send the TS system time synchronized with the MS to the next-level network element connected by wire, which can act as a master clock and perform a wired clock synchronization mechanism with the next-level network element connected by wire. After the next-level network element completes the clock synchronization, if there is a next-level network element connected by wire to the next-level network element, the next-level network element can continue to perform a wired clock synchronization mechanism with the next-level network element as a master clock.

[0104] For example, it is assumed that the next-level network element connected by wire to the TS is Driver. As shown in FIG. 5, it is a flowchart of a wired clock synchronization mechanism between the TS and the Driver. As shown in FIG. 5, the method can include but is not limited to the following steps:

[0105] 501, TS system clock calibration.

[0106] In step 501, the TS system clock calibration can be calibrated to the TS system time synchronized with the MS through the above-mentioned air interface wireless clock synchronization mechanism.

[0107] 502, calculate the initial clock offset between the TS and the Driver.

[0108] The initial clock offset between the TS and the Driver can refer to the offset between the TS system time and the Driver system time.

[0109] In some embodiments, the TS can send the TS system time to the Driver, and then the Driver can calculate the initial clock offset between the TS and the Driver according to the received TS system time and the current Driver system time.

[0110] For example, the initial clock offset can be determined by the difference between the TS system time and the current Driver system time.

[0111] 503, calculate the transmission delay between the TS and the Driver.

[0112] When the TS transmits a signal to the Driver, there will be a transmission delay, which can include a cable transmission delay and a processing delay.

[0113] The cable transmission delay is the delay caused by the transmission process when the cable connected between the TS and the Driver transmits.

[0114] The processing delay can be understood as the delay in the internal processing of the TS and the Driver. Taking the TS sending the TS system time to the Driver as an example, the delay in the process from determining the TS system time inside the TS to sending the TS system time by the TS is the TS processing delay; the delay in the process from receiving the TS system time by the Driver to calibrating the Driver system clock based on the TS system time is the Driver processing delay. The processing delay can be the sum of the TS processing delay and the Driver processing delay.

[0115] 504. The TS sends the TS system time to the Driver.

[0116] 505. The Driver system clock is calibrated.

[0117] The Driver can calibrate the system clock based on the received TS system time and the transmission delay between the TS and the Driver to obtain the Driver system time synchronized with the TS.

[0118] For the case where the MS is the clock source, the MS can send the MS system time to the next-level network element connected by wire, which can perform the wired clock synchronization mechanism with the next-level network element (other MS or PLC) as the master clock. After the next-level network element completes the clock synchronization, if there is a next-level network element connected to the next-level network element by wire, the next-level network element can continue to perform the wired clock synchronization mechanism with the next-level network element as the master clock.

[0119] For example, assuming that the next-level network element connected to the MS is a PLC. As shown in FIG. 6, it is a flowchart of the wired clock synchronization mechanism between the MS and the PLC. As shown in FIG. 6, the method comprises:

[0120] 601. Calculate the initial clock offset between the MS and the PLC.

[0121] The initial clock offset between the MS and the PLC can refer to the offset between the MS system time and the PLC system time.

[0122] In some embodiments, the MS can send the MS system time to the PLC, and then the PLC can calculate the initial clock offset between the MS and the PLC according to the received MS system time and the current PLC system time.

[0123] For example, the initial clock offset can be determined by the difference between the MS system time and the current PLC system time.

[0124] 602. Calculate the transmission delay between the MS and the PLC.

[0125] When the MS transmits a signal to the PLC, there will be a transmission delay, which can include a cable transmission delay and a processing delay.

[0126] The cable transmission delay is the delay caused by the transmission process when the cable between the MS and the PLC is used for transmission.

[0127] The processing delay can be understood as the delay in the internal processing of the MS and the PLC. For example, when the MS sends the MS system time to the PLC, the delay in the internal processing of the MS is the delay between the determination of the MS system time in the MS and the sending of the MS system time by the MS. The delay in the internal processing of the PLC is the delay between the reception of the MS system time by the PLC and the calibration of the PLC system clock based on the MS system time. The processing delay can be the sum of the MS processing delay and the PLC processing delay.

[0128] 603. The MS sends the MS system time to the PLC.

[0129] 604. Calibrate the PLC system clock.

[0130] The PLC can calibrate the system clock according to the received MS system time and the transmission delay between the MS and the PLC to obtain the PLC system time synchronized with the MS.

[0131] In the above embodiments, the specific implementation process of the wired clock synchronization mechanism is given, and the clock synchronization between devices connected by wire is realized. When the wired clock synchronization mechanism is combined with the air interface wireless clock synchronization mechanism, the clock synchronization of the entire network in the wired and wireless fusion network can be realized.

[0132] In the embodiments of the present application, after the slave clock is clock-synchronized with the master clock, the slave clock needs to determine the TS local system time by itself.

[0133] Some slave clocks do not support high-precision timing function by themselves. Such slave clocks can periodically determine the slave clock system time synchronized with the master clock through the above-mentioned air interface wireless clock synchronization mechanism. Between two determinations of the slave clock system time synchronized with the master clock, the slave clock can update the local system time according to the interrupt signal.

[0134] The time resolution depends on the generation time interval of the interrupt signal. For example, if the interrupt signal is generated once every 1 ms, the resolution of the system time maintained by the slave clock is 1 ms. Therefore, when the slave clock serves as a boundary clock and transmits the system time to the next level as a master clock, the resolution of the system time of the slave clock is also consistent with the generation time interval of the interrupt signal.

[0135] For example, the master clock is MS, the slave clock is TS, and the TS is a boundary clock, and the wired connection driver is taken as an example. The TS periodically determines the TS system time synchronized with the MS through the above-mentioned air interface wireless clock synchronization mechanism. And between two adjacent determinations of the TS system time synchronized with the MS, the interrupt signal is generated according to the preset time period, and the TS local system time is determined according to the TS system time synchronized with the MS and the number of times of generation of the interrupt signal.

[0136] In some embodiments, the TS can send the TS local system time to the next level network element connected by wire according to the preset time period.

[0137] For example, as shown in FIG. 7, it is a flowchart of a clock distribution method in which a boundary clock does not support high-precision timing function by itself. As shown in FIG. 7, the method includes but is not limited to the following steps:

[0138] 701. The air interface wireless clock synchronization mechanism is performed between the MS and the TS.

[0139] 702. The TS system clock is calibrated.

[0140] For the above-mentioned step 701 and step 702, the clock synchronization method described in the above-mentioned part of the air interface wireless clock synchronization mechanism can be referred to, and details are not described herein.

[0141] 703. Interrupt-based clock distribution.

[0142] After the TS system clock is calibrated and the TS system time synchronized with the MS is obtained, the interrupt-based clock distribution can be performed, that is, the interrupt signal is generated according to the preset time period, and the clock distribution is performed according to the preset time period.

[0143] After the TS as a boundary clock completes clock synchronization with the MS as a master clock and calibrates the system time, if the TS does not support a high-precision (ns-level precision) timer function, the TS can keep a snapshot of the current time, align the interrupt signal to the current time, and then implement the clock synchronization function through the counting function of the interrupt signal.

[0144] For example, as shown in FIG. 8, a schematic diagram of implementing the clock synchronization function through the counting function of the interrupt signal is shown. In FIG. 8, the boundary clock can align the interrupt signal to the calibration system time T1, where the interrupts n, n+1,..., n+k are interrupt signals generated at preset time periods starting from T1. The interrupts n+m, n+m+1 are interrupt signals generated at preset time periods starting from T2.

[0145] Before the next calibration of the system time, the boundary clock updates the system time through the interrupts, as shown in FIG. 8, the system time corresponding to the interrupt n+2 is T1+2*interrupt interval. If the interrupt interval of the two interrupts is 1 ms, the corresponding system time is T1+2*1 ms. When the system time is calibrated again, as shown in FIG. 8, the calibrated calibration system time is T2, the corresponding interrupt needs to be adjusted to align to T2, and the subsequent interrupts will also be adjusted accordingly. When the interrupt comes, the system time is updated to T2+s*interrupt interval, where s is the number of interrupts experienced from T2 to the current interrupt. For example, at the interrupt n+m+1, the system time is T2+1*interrupt interval.

[0146] In the above embodiment, for some slave clocks that do not support high-precision timing functions themselves, a clock distribution method based on interrupts is given, so that such clocks can themselves update the TS local system time and distribute the clock.

[0147] Some slave clocks support high-precision timing functions themselves, for example, through a timer or a local clock. After determining the system time of the slave clock synchronized with the master clock through the above-mentioned air interface wireless clock synchronization mechanism, the slave clock can update the local system time based on the timer or the local clock. If the slave clock will periodically determine the system time of the slave clock synchronized with the master clock through the above-mentioned air interface wireless clock synchronization mechanism, the slave clock can update the local system time based on the timer or the local clock between the adjacent two determinations of the system time of the slave clock synchronized with the master clock. Moreover, the slave clock can act as a master clock at any time to distribute its local system time to the next level.

[0148] Exemplarily, taking Driver as an example, MS is a master clock, TS is a slave clock, and the TS is a boundary clock. After the TS determines the TS system time synchronized with the MS through the air interface wireless clock synchronization mechanism, the TS updates the TS system time synchronized with the MS based on a timer or a local clock to obtain the TS local system time.

[0149] The boundary clock (BC) is a clock having multiple Precision Time Protocol (PTP) ports in a domain (the local clocks of all ports of the BC are the same), and maintaining all time scales in the domain. The BC can act as a clock source, i.e., as a master clock, or can be synchronized with another clock, i.e., as a slave clock.

[0150] In some embodiments, the TS can send the TS local system time to a next-level network element connected by wire at any time.

[0151] Exemplarily, as shown in FIG. 9, a flowchart of a clock distribution method in which a boundary clock itself supports high-precision timing function is shown. As shown in FIG. 9, the method includes but is not limited to the following steps:

[0152] 901. The air interface wireless clock synchronization mechanism is performed between the MS and the TS.

[0153] 902. The TS system clock is calibrated.

[0154] For the steps 701 and 702, reference can be made to the description of the clock synchronization method in the part of the air interface wireless clock synchronization mechanism, which will not be repeated here.

[0155] 903. Clock distribution based on a timer or a local clock.

[0156] After the TS system clock is calibrated to obtain the TS system time synchronized with the MS, the TS local system time can be updated through a timer of the TS, or the TS local system time can be updated through a local clock. Moreover, the TS can send the TS local system time to a next-level network element connected by wire at any time.

[0157] Compared with the interrupt-based clock distribution, the clock distribution based on a timer or a local clock can provide a high-precision system time of ns level, and the system time update is not constrained by the interrupt, so that the latest local system time can be obtained at any time. If the slave clock is a boundary clock, the boundary clock can also distribute a high-precision system reference time as a master clock to a next level at any time.

[0158] Exemplarily, as shown in FIG. 10, a schematic diagram of implementing the clock synchronization function by the local clock is shown. After the system clock calibration is completed at T1, the local clock can provide the local system time Tlocal, where Tlocal=T1, and after the local clock is calibrated with the master clock, the local clock can be independently running, and the local clock at any time can obtain the system time synchronized with the master clock, such as after running timer1 after T1, the local system time can be updated as Tlocal'=Tlocal+timer1. The local system time is updated as T1, and at any subsequent time, the local time of the clock is real-time updated and synchronized with the master clock. Until the next system calibration time T2, the local system time Tlocal of the clock is updated as Tlocal=T2, and after running timer2 after T2, the local system time can be updated as Tlocal'=Tlocal+timer2.

[0159] In the implementation of the clock synchronization function by the timer, since the timer only provides the timing function, the method of obtaining the local system time by the timer can be: latching the local system time plus the latched local system time to the timing time of the current timer.

[0160] In the above embodiments, for some cases that the slave clock itself supports high-precision timing function, the clock distribution method based on the timer or the local clock is given, so that the clock can itself implement the update of the TS local system time and the clock distribution.

[0161] The clock synchronization method provided in the embodiments of the present application can be applied to the scenario of multi-domain clock synchronization. The multi-domain clock synchronization refers to that multiple clock domains are synchronized to a master clock, so as to realize the clock synchronization of multiple synchronization domains.

[0162] Exemplarily, as shown in FIG. 11, a network topology schematic diagram of a multi-domain clock synchronization scenario is shown. It can include one or more controllers, one or more MSs, multiple TSs, and multiple drivers. In FIG. 11, one controller is shown; multiple MSs, such as MS0...MSn shown in FIG. 11; multiple TSs, such as TS0_0...TS0_n...TSn_m shown in FIG. 11; and multiple drivers, such as driver0_0_0...driver0_n_0, driver0_n_1...drivern_m_0 shown in FIG. 11.

[0163] The controller and the MS, and the MS and the MS constitute a control synchronization domain, the devices are connected through a wired connection, and precise clock synchronization is achieved using a wired clock synchronization mechanism. In FIG. 11, the controller connected to MS0 takes MS0 as a master clock, and other MSs connected to MS0 also take MS0 as a master clock, such as MSn taking MS0 as a master clock. MC in FIG. 11 represents a master clock, and SC represents a slave clock.

[0164] The MS and the TS constitute an air interface synchronization domain, the devices are connected through a wireless connection, and precise time synchronization is achieved using an air interface wireless clock synchronization mechanism. Among them, the TS connected to MS0 takes MS0 as a master clock, and the TS connected to MSn takes MSn as a master clock. Since MSn has been synchronized with MS0, the TS connected to MSn is also synchronized with MS0, so it can be considered that all TSs are synchronized with MS0.

[0165] The TS and the driver constitute a drive synchronization domain, the devices are connected through a wired connection, and precise clock synchronization is achieved through a wired clock synchronization mechanism. In FIG. 11, the driver n_m_0 connected to TSn_m takes TSn_m as a master clock. Since all TSs have been synchronized with MS0, it can be considered that all drivers are synchronized with MS0.

[0166] Therefore, in the complex network synchronization of wired and wireless fusion, through the precise synchronization of multiple clock domains, the precise clock synchronization of the controller and the driver is finally realized.

[0167] It should be understood that although each step in the flowchart involved in each of the above embodiments is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in each of the above embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0168] Based on the same technical concept, the embodiments of the present application also provide an electronic device. The electronic device can realize the functions of the MS and the TS in the foregoing embodiments.

[0169] For example, FIG. 12 is a structural schematic diagram of an electronic device provided by an embodiment. The electronic device includes a memory 1201, a transceiver 1202, and a processor 1203, wherein the memory 1201, the transceiver 1202, and the processor 1203 are connected through a bus interface.

[0170] The memory 1201 is configured to store a computer program; and the transceiver 1202 is configured to transceive data under control of the processor 1203.

[0171] For the case that the electronic device is a TS, the processor 1203 is configured to read the computer program in the memory 1201 and perform the following operations:

[0172] receive indication information of a MS system time, an uplink timing offset and a first reference frame sent by a management station MS; the first reference frame is a radio frame used for measuring the uplink timing offset;

[0173] determine a TS system time synchronized with the MS based on the indication information of the MS system time, the uplink timing offset and the first reference frame.

[0174] In some embodiments, the processor 1203 is specifically configured to read the computer program in the memory 1201 and perform the following operations:

[0175] The determination of the TS system time synchronized with the MS based on the indication information of the MS system time, the uplink timing offset and the first reference frame includes:

[0176] determine a time delay between the TS and the MS based on the uplink timing offset and the indication information of the first reference frame;

[0177] determine the TS system time synchronized with the MS according to the MS system time and the time delay between the TS and the MS.

[0178] In some embodiments, the processor 1203 is specifically configured to read the computer program in the memory 1201 and perform the following operations:

[0179] The determination of the time delay between the TS and the MS based on the uplink timing offset and the indication information of the first reference frame includes:

[0180] determine a timing advance TA maintained locally corresponding to the first reference frame based on the indication information of the first reference frame;

[0181] determine an air interface transmission time delay corresponding to the first reference frame based on the TA and the uplink timing offset;

[0182] determine the time delay between the TS and the MS according to the air interface transmission time delay corresponding to the first reference frame and an adjustment amount accumulated in downlink timing from the first reference frame to a second reference frame;

[0183] The second reference frame is a reference frame for recovering a system clock.

[0184] In some embodiments, the processor 1203 is specifically configured to read a computer program in the memory 1201 and perform the following operations:

[0185] The TS system time synchronized with the MS is determined based on the MS system time, the uplink timing offset, and the indication information of the first reference frame.

[0186] The frame offset between a third reference frame and a second reference frame is determined, the third reference frame being a reference frame corresponding to the MS system time, and the second reference frame being a reference frame for recovering a system clock.

[0187] The TS system time synchronized with the MS is determined based on the frame offset, the MS system time, the uplink timing offset, and the indication information of the first reference frame.

[0188] In some embodiments, the processor 1203 is specifically configured to read a computer program in the memory 1201 and perform the following operations:

[0189] The frame offset between a third reference frame and a second reference frame is determined, the third reference frame being a reference frame corresponding to the MS system time, and the second reference frame being a reference frame for recovering a system clock.

[0190] The indication information of the third reference frame corresponding to the MS system time is received from the management station MS.

[0191] The number of radio frames between the third reference frame and the second reference frame is determined based on the indication information of the third reference frame.

[0192] The frame offset is determined according to the number of radio frames and a radio frame length.

[0193] In some embodiments, the MS system time is sent by being carried in a system broadcast message.

[0194] In some embodiments, the uplink timing offset and the indication information of the first reference frame are sent by being carried in a unicast message.

[0195] In some embodiments, the indication information of the third reference frame is sent by being carried in a system broadcast message.

[0196] In some embodiments, the processor 1203 is further configured to read a computer program in the memory 1201 and perform the following operations:

[0197] The TS system time is sent to a next-level network element connected by wire, and the TS system time is used for clock synchronization of the next-level network element.

[0198] In some embodiments, the processor 1203 is further configured to read a computer program in the memory 1201 and perform the following operations:

[0199] The TS local system time is determined based on the TS system time synchronized with the MS and the number of times of generation of the interrupt signal.

[0200] In some embodiments, the processor 1203 is further configured to read a computer program in the memory 1201 and perform the following operations:

[0201] The TS local system time is sent to a next network element connected by wire in the preset time period.

[0202] In some embodiments, the processor 1203 is further configured to read a computer program in the memory 1201 and perform the following operations:

[0203] The TS local system time is determined based on the TS system time synchronized with the MS and the number of times of generation of the interrupt signal.

[0204] In some embodiments, the processor 1203 is further configured to read a computer program in the memory 1201 and perform the following operations:

[0205] The TS local system time is sent to a next network element connected by wire.

[0206] In some embodiments, the processor 1203 is further configured to read a computer program in the memory 1201 and perform the following operations:

[0207] The MS system time, the uplink timing offset and the indication information of the first reference frame are sent to the TS, the first reference frame being a radio frame used for measuring the uplink timing offset.

[0208] The MS system time, the uplink timing offset and the indication information of the first reference frame are used for determining the TS system time synchronized with the MS.

[0209] In some embodiments, the processor 1203 is further configured to read a computer program in the memory 1201 and perform the following operations:

[0210] The indication information of the third reference frame corresponding to the MS system time is sent to the TS.

[0211] In some embodiments, the MS system time is sent by being carried in a system broadcast message.

[0212] In some embodiments, the uplink timing offset and the indication information of the first reference frame are sent by being carried in a unicast message.

[0213] In some embodiments, the indication information of the third reference frame is sent by being carried in a system broadcast message.

[0214] In some embodiments, the processor 1203 is further configured to read a computer program in the memory 1201 and perform the following operations:

[0215] sending the MS system time to a next-level network element connected by wire, the MS system time being used by the next-level network element for clock synchronization.

[0216] In one exemplary embodiment, as shown in FIG. 13, a structural block diagram of a TS is provided, comprising:

[0217] A receiving module 1301 is configured to receive the MS system time, the uplink timing offset and the indication information of the first reference frame sent by a management station MS, the first reference frame being a radio frame used for measuring the uplink timing offset;

[0218] A synchronizing module 1302 is configured to determine a TS system time synchronized with the MS based on the MS system time, the uplink timing offset and the indication information of the first reference frame.

[0219] In some embodiments, the synchronizing module 1302 is specifically configured to:

[0220] determine a time delay from the TS to the MS based on the uplink timing offset and the indication information of the first reference frame;

[0221] determine a TS system time synchronized with the MS according to the MS system time and the time delay from the TS to the MS.

[0222] In some embodiments, the synchronizing module 1302 is specifically configured to:

[0223] determine a locally maintained timing advance TA corresponding to the first reference frame based on the indication information of the first reference frame;

[0224] determine an air interface transmission time delay corresponding to the first reference frame based on the TA and the uplink timing offset;

[0225] determining the time delay between the TS and the MS according to the air interface transmission time delay corresponding to the first reference frame and the adjustment amount accumulated by downlink timing from the first reference frame to the second reference frame.

[0226] In some embodiments, the synchronization module 1302 is specifically configured to:

[0227] determining a frame offset between a third reference frame and a second reference frame, the third reference frame being a reference frame corresponding to the MS system time, and the second reference frame being a reference frame for recovering a system clock;

[0228] determining a TS system time synchronized with the MS based on the frame offset, the MS system time, the uplink timing offset and indication information of the first reference frame.

[0229] In some embodiments, the synchronization module 1302 is specifically configured to:

[0230] receiving indication information of the third reference frame corresponding to the MS system time sent by the management station MS;

[0231] determining a number of radio frames between the third reference frame and the second reference frame based on the indication information of the third reference frame;

[0232] determining the frame offset according to the number of radio frames and a radio frame length.

[0233] In some embodiments, the MS system time is sent by being carried in a system broadcast message.

[0234] In some embodiments, the uplink timing offset and the indication information of the first reference frame are sent by being carried in a unicast message.

[0235] In some embodiments, the indication information of the third reference frame is sent by being carried in a system broadcast message.

[0236] In some embodiments, the TS further includes a sending module 1303 configured to send the TS system time to a next-level network element connected by wire, the TS system time being used by the next-level network element for clock synchronization.

[0237] In some embodiments, the TS further includes a clock distribution module 1304 configured to generate an interrupt signal according to a preset time period between two adjacent times of determining the TS system time synchronized with the MS, and determine a TS local system time according to the TS system time synchronized with the MS and a number of times of generation of the interrupt signal.

[0238] In some embodiments, the clock distribution module 1304 is further configured to send the TS local system time to a next-level network element connected by wire at the preset time period.

[0239] In some embodiments, the clock distribution module 1304 is further configured to update the TS system time synchronized with the MS based on a timer or a local clock between two adjacent times of determining the TS system time synchronized with the MS, to obtain the TS local system time.

[0240] In some embodiments, the clock distribution module 1304 is further configured to send the TS local system time to a next-level network element connected by wire.

[0241] In an exemplary embodiment, as shown in FIG. 14, a structural block diagram of an MS is provided, comprising:

[0242] a sending module 1401 configured to send an MS system time, an uplink timing offset, and indication information of a first reference frame to a TS, the first reference frame being a radio frame used to measure the uplink timing offset;

[0243] wherein the MS system time, the uplink timing offset, and the indication information of the first reference frame are used to determine a TS system time synchronized with the MS.

[0244] In some embodiments, the sending module 1401 is further configured to send indication information of a third reference frame corresponding to the MS system time to the TS.

[0245] In some embodiments, the MS system time is sent by being carried in a system broadcast message.

[0246] In some embodiments, the uplink timing offset and the indication information of the first reference frame are sent by being carried in a unicast message.

[0247] In some embodiments, the indication information of the third reference frame is sent by being carried in a system broadcast message.

[0248] In some embodiments, the sending module 1401 is further configured to send the MS system time to a next-level network element connected by wire, the MS system time being used by the next-level network element for clock synchronization.

[0249] It should be noted that the division of the modules in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division manner can be used. In addition, each functional module in each embodiment of the present application can be integrated in one processing module, or each module can be physically present alone, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module.

[0250] When the integrated module is realized in the form of a software functional module and sold or used as an independent product, the integrated module can be stored in a processor-readable storage medium. Based on this understanding, the technical solutions of the present application, essentially or in part, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the methods described in the various embodiments of the present application.

[0251] It should be noted that the above-described apparatus provided by the embodiments of the present application can implement all the method steps achieved by the method embodiments and achieve the same technical effects. Therefore, the same parts and beneficial effects of the method embodiments will not be described in detail.

[0252] In one embodiment, a computer-readable storage medium is provided, and the computer-readable storage medium stores a computer program. The computer program is executed by a processor to implement each method step achieved by the above method embodiments.

[0253] In one embodiment, a computer program product is provided, and the computer program product includes a computer program. The computer program is executed by a processor to implement each method step achieved by the above method embodiments.

[0254] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric memory (Ferroelectric Random Access Memory, FRAM), phase change memory (Phase Change Memory, PCM), graphene memory, etc. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0255] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0256] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for clock synchronization, applied to a terminal station, the method comprising: receiving a management station system time, an uplink timing offset and indication information of a first reference frame sent by a management station; the first reference frame is a radio frame used for measuring the uplink timing offset; determining a terminal station system time synchronized with the management station based on the management station system time, the uplink timing offset and the indication information of the first reference frame. The determining a terminal station system time synchronized with the management station based on the management station system time, the uplink timing offset and the indication information of the first reference frame comprises: determining a time delay between the terminal station and the management station based on the uplink timing offset and the indication information of the first reference frame; and determining the terminal station system time synchronized with the management station according to the management station system time and the time delay between the terminal station and the management station. The determining a time delay between the terminal station and the management station based on the uplink timing offset and the indication information of the first reference frame comprises: determining a timing advance corresponding to the first reference frame based on the indication information of the first reference frame; determining an air interface transmission time delay corresponding to the first reference frame based on the timing advance and the uplink timing offset; and determining the time delay between the terminal station and the management station according to the air interface transmission time delay corresponding to the first reference frame and an adjustment amount accumulated by downlink timing from the first reference frame to a second reference frame; wherein the second reference frame is a reference frame for recovering a system clock. The determining a terminal station system time synchronized with the management station based on the management station system time, the uplink timing offset and the indication information of the first reference frame comprises: determining a frame offset between a third reference frame and a second reference frame, the third reference frame being a reference frame corresponding to the management station system time and the second reference frame being a reference frame for recovering a system clock; and determining the terminal station system time synchronized with the management station based on the frame offset, the management station system time, the uplink timing offset and the indication information of the first reference frame.

2. The method of claim 1, wherein, The determining a frame offset between a third reference frame and a second reference frame comprises: receiving indication information of the third reference frame sent by a management station; determining a number of radio frames between the third reference frame and the second reference frame based on the indication information of the third reference frame; and determining the frame offset according to the number of radio frames and a length of a radio frame. 6.The method of claim 5, wherein the management station system time is sent by being carried in a system broadcast message; and / or the uplink timing offset and the indication information of the first reference frame are sent by being carried in a unicast message; and / or the indication information of the third reference frame is sent by being carried in a system broadcast message. The method further comprises:

3. The method of claim 2, wherein, ​ ​ ​ ​ ​ 4. The method according to any one of claims 1 to 3, wherein, ​ ​ ​ 5. The method of claim 4, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 7. The method of claim 1, wherein, ​ An interrupt signal is generated according to a preset time period between two adjacent determinations of the terminal station system time synchronized with the management station, and a terminal station local system time is determined according to the terminal station system time synchronized with the management station and the number of times of generation of the interrupt signal.

8. A clock synchronization method applied to a management station, the method comprising: sending, to a terminal station, management station system time, uplink timing offset, and indication information of a first reference frame used to measure the uplink timing offset; wherein the management station system time, the uplink timing offset, and the indication information of the first reference frame are used to determine terminal station system time synchronized with the management station.

9. The method of claim 8, wherein, The method further comprises: sending, to the terminal station, indication information of a third reference frame corresponding to the management station system time.

10. The method of claim 9, wherein: the management station system time is sent by being carried in a system broadcast message; and / or, the uplink timing offset and the indication information of the first reference frame corresponding to the uplink timing offset are sent by being carried in a unicast message; and / or, the indication information of the third reference frame is sent by being carried in a system broadcast message.

11. A terminal station comprising: a memory, a transceiver, and a processor: the memory is configured to store a computer program; the transceiver is configured to transceive data under control of the processor; the processor is configured to read the computer program in the memory and perform the method of claims 1-6.

12. A management station comprising: a memory, a transceiver, and a processor: the memory is configured to store a computer program; the transceiver is configured to transceive data under control of the processor; the processor is configured to read the computer program in the memory and perform the method of claims 7-10.

13. A terminal station, comprising: a receiving module configured to receive management station system time, uplink timing offset, and indication information of a first reference frame sent by a management station; the first reference frame is a radio frame used to measure the uplink timing offset; a synchronization module configured to determine terminal station system time synchronized with the management station based on the management station system time, the uplink timing offset, and the indication information of the first reference frame.

14. A management station, comprising: a sending module configured to send, to a terminal station, management station system time, uplink timing offset, and indication information of a first reference frame; the first reference frame is a radio frame used to measure the uplink timing offset; wherein the management station system time, the uplink timing offset, and the indication information of the first reference frame are used to determine terminal station system time synchronized with the management station.

15. A computer readable storage medium, wherein, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the method of any one of claims 1-10.

16. A computer program product, wherein, The computer program product comprises a computer program, and the computer program is executed by the processor to implement the method of any one of claims 1-10.

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