LDPC code-based communication method and communication apparatus

Abstract

A communication method and a communication apparatus. In the method, a device can perform encoding or decoding on the basis of an LDPC matrix, which LDPC matrix is determined on the basis of an exponential matrix of an LDPC base matrix and a lifting size Zc, wherein there is at least one sub-matrix A of three rows and (L+1) columns in the exponential matrix corresponding to the base matrix; and the modulus of Zc is taken after a certain value is added to or subtracted from a shift value of each entire row and each entire column of the submatrix A, respectively, and then the order of each column is permuted, such that elements in the second row are arranged in ascending order, and the resulting matrix A' can be expressed in the following form: [Matrix 1], wherein {(b(1),b(2),…,b(L)} overall exhibits a trend of first decreasing and then increasing. By means of the method, an LDPC code can be flexibly constructed, thereby better adapting to various complex and variable communication environments.

Description

Communication method and communication apparatus based on LDPC code

[0001] The present application claims priority to the Chinese patent application No. 202411351193.5, filed on September 25, 2024, and entitled "Communication method and communication apparatus based on LDPC code", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of coding, and more particularly, to a communication method and communication apparatus based on LDPC code. BACKGROUND

[0003] In the field of channel coding, low-density parity check (LDPC) code is one of the most mature and widely used channel coding schemes. Quasi-cyclic low density parity check (QC-LDPC) code is a structured LDPC code. Due to its unique structure of the check matrix, it can be implemented by using a simple feedback shift register during encoding, which reduces the encoding complexity of the LDPC code.

[0004] In the field of modern communication, an efficient and reliable channel coding scheme is of great significance to ensure the performance and efficiency of information transmission. Girth, as an important parameter of QC-LDPC code, its size will affect the decoding performance of QC-LDPC code. Existing QC-LDPC code construction schemes usually require the girth to be at least 6 or 8. When the girth is required to be 8, in order to avoid 4-cycles and 6-cycles in the Tanner graph corresponding to the check matrix of the LDPC code, the required lifting value is usually large, which makes the code length of the coding scheme longer, and thus the time delay is larger, making it difficult to be applied to application scenarios with high requirements for low time delay. In addition, the existing LDPC code construction schemes are less and lack flexibility, which is difficult to adapt to complex and variable communication environments and application requirements. SUMMARY

[0005] Embodiments of the present application provide a communication method and communication apparatus based on LDPC code, which can flexibly construct LDPC code, thereby better adapting to various complex and variable communication environments.

[0006] In a first aspect, a communication method based on an LDPC code is provided, which can be performed by a sending end device. In the present application, the "sending end device" can refer to the sending end device itself (e.g., a network device, a terminal device), a component (e.g., a processor, a chip, or a chip system) in the sending end device, or a logic module or software capable of realizing all or part of the functions of the sending end device.

[0007] The method comprises: obtaining an information bit sequence; determining an LDPC matrix, the LDPC matrix being determined based on an exponent matrix of an LDPC base matrix and a lifting value Zc, wherein the exponent matrix of the base matrix contains at least one 3-row (L+1)-column submatrix A, L is an integer greater than or equal to 2, any element in the submatrix A has a value in the range of [0, Zc-1], and the submatrix A is:

[0008] There exist positive integers k, x, y, and z, such that the set Q1{mod(z π(1) -x π(1) -z π(0) +x π(0) , Zc), mod(z π(2) -x π(2) -z π(0) +x π(0) , Zc), …, mod(z π(L) -x π(L) -z π(0) +x π(0) , Zc)} satisfies at least one of the following features: Feature 1, Feature 2, and Feature 3, the set Q1 is determined based on the indices π(i) corresponding to the elements in the set Q2{mod(y π(0) -x π(0) , Zc), mod(y π(1) -x π(1) , Zc), …, mod(y π(L) -x π(L) , Zc)}, 0≤i≤L, π(i) is an integer in the range of 0 to L, and π(i) is different for different i, the set Q2 is obtained by arranging the elements in the set Q3{mod(y0-x0, Zc), mod(y1-x1, Zc), …, mod(y L -x L , Zc)} in ascending order,

[0009] Feature 1: the set Q1 contains k non-empty sub-sets C1, …, Ck, k the union of the k non-empty sub-sets is the set Q1, the sub-set Cjcontains n j elements, 1≤j≤k, n j .j less than or equal to x, the subset C j includes the first elements of the set Q1, k is greater than or equal to 2,

[0010] the second feature is that the difference between max{C j} and min{C j} in the subset C j} is less than or equal to y, max{C j} and min{C j} are the maximum value and the minimum value in the subset C j , respectively,

[0011] the third feature is that when 1≤j≤z-1, min{C j}≥max{C j+1}, when z≤j≤k-1, max{C j}≤min{C j+1}, 2≤z≤k-1;

[0012] According to the LDPC matrix, the information bit sequence is encoded to obtain a code word sequence.

[0013] The technical solution can ensure that the girth corresponding to the submatrix A is at least 8. Compared with the case that the submatrix A corresponds to the same girth in the existing LDPC code construction scheme, the minimum lifting value required by the application is smaller, and therefore the application can be applied to a communication scenario with a high requirement for low latency. In addition, the scheme provided in the application can give an explicit LDPC code construction scheme for different column numbers (i.e., for different (L+1) columns) and different lifting values, so that the key parameters such as code rate and code length can be flexibly adjusted according to different transmission requirements, to better adapt to various complex communication environments and meet diversified applications.

[0014] In a second aspect, a communication method is provided, which can be executed by a receiving end device. In the absence of special description, the "receiving end device" in the present application can refer to the receiving end device itself (for example, a network device, a terminal device), a component (for example, a processor, a chip, or a chip system) in the receiving end device, or a logic module or software capable of realizing all or part of the functions of the receiving end device.

[0015] The method comprises: obtaining a symbol sequence; determining an LDPC matrix, the LDPC matrix being determined based on an exponent matrix of an LDPC base matrix and a lifting value Zc, wherein the exponent matrix of the base matrix comprises at least one submatrix A of 3 rows and (L+1) columns, L is an integer greater than or equal to 2, the value range of any element in the submatrix A is [0, Zc-1], and the submatrix A is:​

[0016] There exist positive integers k, x, y and z, such that the elements in the set Q1 {mod(z π(1) -x π(1) -z π(0) +x π(0) , Zc), mod(z π(2) -x π(2) -z π(0) +x π(0) , Zc), …, mod(z π(L) -x π(L) -z π(0) +x π(0) , Zc} satisfy at least one of Feature One, Feature Two and Feature Three, the set Q1 is determined based on the subscripts π(i) corresponding to the elements in the set Q2 {mod(y π(0) -x π(0) , Zc), mod(y π(1) -x π(1) , Zc), …, mod(y π(L) -x π(L) , Zc}, 0≤i≤L, π(i) is an integer from 0 to L, and i is different from π(i) is different, the set Q2 is obtained by arranging the elements of the set Q3 {mod(y0-x0, Zc), mod(y1-x1, Zc), …, mod(y L -x L , Zc} in ascending order,

[0017] Feature One is that the set Q1 includes k non-empty sub-sets C1, …, C k The union set of the k non-empty sub-sets is the set Q1, the sub-set C j includes n j elements, 1≤j≤k, n j is less than or equal to x, the sub-set C j includes the remaining elements in the first elements of the set Q1 except the first elements, and k is greater than or equal to 2,

[0018] Feature Two is that the difference between max{C j} and min{C j} in the sub-set C j is less than or equal to y, max{C j} and min{C j} are the maximum value and the minimum value in the sub-set C j ,

[0019] Feature Three is that when 1≤j≤z-1, min{Cj}≥max{C j+1}, when z≤j≤k-1,max{C j}≤min{C j+1}, 2≤z≤k-1;

[0020] Based on the LDPC matrix, the symbol sequence is decoded to obtain the information bit sequence.

[0021] For the beneficial effects of the second aspect, please refer to the description of the first aspect, which will not be repeated here.

[0022] In some implementations of the first or second aspect, the elements in the first row and first column of submatrix A are all 0, and submatrix A is:

[0023] In this submatrix A, the values ​​of elements a(n) in the second row and b(n) in the third row are both in the range [0, Zc-1], 1≤n≤L, and a(n) monotonically increases as n increases. The set Q4(b(1),b(2),…,b(L)) satisfies at least one of the following features: feature four, feature five, and feature six.

[0024] Feature four is that set Q4 includes k non-empty subsets C′1,…,C′ k The union of k non-empty subsets is set Q4, and subset C′ is... j Contains n j There are n elements, 1≤j≤k, n j Less than or equal to x, subset C′ j Includes the first set of Q4 Among the elements, excluding the first one The remaining elements after the first element, where k is greater than or equal to 2.

[0025] Feature five is: subset C′ j max{C′ j} min{C′ j The difference between} is less than or equal to y, max{C′ j} and min{C′ j} are subsets C′ j The maximum and minimum values ​​in the range.

[0026] Feature six is: when 1≤j≤z-1, min{C′ j}≥max{C′ j+1}, when z≤j≤k-1,max{C′ j}≤min{C′ j+1}

[0027] In some implementations of the first aspect or the second aspect, a(n) = n*d in the sub-matrix A, n and d are positive integers, 1≤n≤L, d≥2, the number of columns (L+1) of the sub-matrix A = 2*m*d+r, m is a positive integer, r is an integer, and 0≤r≤2*d-1, k, x, y and z are respectively:

[0028] When r≥1, k = 2*m+1, x = max{d, r}, y = d 2 , and z = m+1,

[0029] j = 1, C' j = {b(1), b(2), …, b(d-1)},

[0030] 2≤j≤m, C' j = {b((j-1)*d), b((j-1)*d+1), …, b(j*d-1)},

[0031] j = m+1, C' j = {b(m*d), b(m*d+1), …, b(m*d+r-1)},

[0032] m+2≤j≤2m+1, C' j = {b((j-2)d+r), b((j-2)d+r+1), …, b((j-2)*d+r+d-1)},

[0033] When r = 0, k = 2*m, x = d, y = d

[0034] j = 1, C' j = {b(1), b(2), …, b(d-1)},

[0035] 2≤j≤2m, C' j = {b((j-1)*d), b((j-1)*d+1), …, b(j*d-1)}.

[0036] The decoding performance of the LDPC code check matrix obtained based on a(n) and b(n) described in the above technical solutions is better than the decoding performance of the LDPC code check matrix obtained based on random search a(n) and b(n).

[0037] In some implementations of the first aspect or the second aspect, when r≥1, j = 1, C' j includes elements {Zc-1, Zc-2, …, Zc-(d-1)}, 2≤j≤m, C' j{Zc-(L+2)*(i-1)*d,Zc-1-(L+2)*(i-1)*d,Zc-2-(L+2)*(i-1)*d,…,Zc-(d-1)-(L+2)*(i-1)*d}, j = m+1, C' j {Zc-(L+2)*m*d,Zc-1-(L+2)*m*d,Zc-2-(L+2)*m*d,…,Zc-(r-1)-(L+2)*m*d}, m+2≤j≤2m+1, C' j Any element b(i) included in the above formula is b(i) = b(L-i)-(L-i+1)*d, where m*d+r≤i≤L.

[0038] In some implementations of the first aspect or the second aspect, a(n) = n in the sub-matrix A, n is a positive integer, and 1≤n≤L, and k, x, y and z are respectively: k = L, x = 1, y is any positive integer,

[0039] The decoding performance of the LDPC code check matrix based on a(n) and b(n) described in the above technical solutions is better than the decoding performance of the LDPC code check matrix based on randomly searched a(n) and b(n).

[0040] In some implementations of the first aspect or the second aspect, b(i) = Zc-(L+2)*i-c i , b(i) = Zc-(L+3)*(L-i)-1-c i where c i is greater than or equal to 0, and satisfies

[0041] In a third aspect, a communication apparatus is provided, which is configured to perform the method in any of the above aspects or implementations thereof. Specifically, the apparatus can include units and / or modules for performing the method in any of the above aspects or implementations thereof, such as a processing unit and / or a transceiving unit.

[0042] In an implementation, the apparatus is a transmitting device or a receiving device. When the apparatus is a transmitting device or a receiving device, the transceiving unit can be a transceiver, or an input / output interface, or a communication interface; and the processing unit can be at least one processor. Optionally, the transceiver is a transceiving circuit. Optionally, the input / output interface is an input / output circuit.

[0043] In another implementation, the apparatus is a chip, chip system or circuit for a transmitting end device or a receiving end device. When the apparatus is a chip, chip system or circuit for a transmitting end device or a receiving end device, the transceiving unit can be an input / output interface, interface circuit, output circuit, input circuit, pin or related circuit on the chip, chip system or circuit; and the processing unit can be at least one processor, processing circuit or logic circuit.

[0044] In a fourth aspect, a communication apparatus is provided, which comprises a memory configured to store a computer program or instructions; and at least one processor configured to execute the computer program or instructions stored in the memory to perform the method in any one of the aspects or the implementation manners thereof.

[0045] In an implementation, the apparatus is a transmitting end device or a receiving end device.

[0046] In another implementation, the apparatus is a chip, chip system or circuit for a transmitting end device or a receiving end device.

[0047] In a fifth aspect, a communication apparatus is provided, which comprises at least one processor and a communication interface, the at least one processor configured to acquire, through the communication interface, a computer program or instructions stored in a memory to perform the method in any one of the aspects or the implementation manners thereof. The communication interface can be implemented by hardware or software.

[0048] In an implementation, the apparatus further comprises the memory.

[0049] In a sixth aspect, a processor is provided, which is configured to perform the method in any one of the aspects.

[0050] For the transmitting and acquiring / receiving operations of the processor, if no special description is provided, or if it does not contradict with the actual role or inherent logic in the related description, it can be understood as the processor outputting and receiving, inputting and the like, or as the transmitting and receiving operations performed by the radio frequency circuit and the antenna, which are not limited in the present application.

[0051] In a seventh aspect, a computer readable storage medium is provided, which stores program codes for execution by an apparatus, and the program codes comprise codes for performing the method in any one of the aspects or the implementation manners thereof.

[0052] In an eighth aspect, a computer program product is provided, which comprises instructions, and when the computer program product is run on a computer, the computer is caused to perform the method in any one of the aspects or the implementation manners thereof.

[0053] In a ninth aspect, a chip is provided, which includes a processor and a communication interface. The processor reads instructions stored on a memory through the communication interface, and executes the method provided in any one of the aspects or the implementation manners thereof. The communication interface can be implemented by hardware or software.

[0054] Optionally, as an implementation manner, the chip further includes a memory, which stores a computer program or instructions. The processor is configured to execute the computer program or instructions stored on the memory, and when the computer program or instructions are executed, the processor is configured to execute the method provided in any one of the aspects or the implementation manners thereof.

[0055] In the method provided in the present application, the number of chips for implementing the method is not limited, for example, the method can be implemented by one chip, or two or more chips. When the number of chips for implementing the method is two or more, the chips can be from the same manufacturer or different manufacturers.

[0056] In a tenth aspect, a computer program is provided, which, when running on a computer, causes the method provided in any one of the aspects or the implementation manners thereof to be executed.

[0057] In an eleventh aspect, a communication system is provided, which includes at least one of the sending device or the receiving device described above. BRIEF DESCRIPTION OF DRAWINGS

[0058] FIG. 1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0059] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0060] FIG. 3 is a Tanner graph of a check matrix H of an LDPC.

[0061] FIG. 4 is a schematic diagram of a structure of a check matrix.

[0062] FIG. 5 is a schematic diagram of an information transmission process.

[0063] FIG. 6 is a schematic flowchart of a communication method 600 based on an LDPC code provided in the present application.

[0064] FIG. 7 is a simulation schematic diagram of an LDPC code constructed based on the method proposed in the present application and an LDPC code constructed based on random search of a shift value.

[0065] FIG. 8 is a schematic block diagram of a communication apparatus 1000 provided in an embodiment of the present application.

[0066] FIG. 9 is a schematic block diagram of a communication apparatus 1100 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] In order to understand the embodiments of the present application, the following will be introduced before the embodiments of the present application are introduced.

[0068] "Indicative of" or "indicate" can include both direct and indirect indication, or "indicative of" or "indicate" can explicitly and / or implicitly indicate. The first, second, etc. various numerical designations are only for the convenience of description and do not limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc. "Predefined" can be achieved by pre-storing corresponding codes, tables or other means for indicating relevant information in the device, and the specific implementation manner is not limited in the present application. The "protocol" referred to can refer to a standard protocol in the communication field, which can include a long term evolution (LTE) protocol, a new radio (NR) protocol and a related protocol applied in a future communication system, and the present application is not limited thereto. The words "example", "for example", "exemplary", "as an example", etc. are used to indicate an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized. "At least one" refers to one or more, and "multiple" refers to two or more. "At most one" refers to one or 0. "And / or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple. The description related to the sending of messages, information or data by network element A to network element B and the receiving of messages, information or data from network element A by network element B is intended to indicate which network element the message, information or data is intended for, and does not limit whether they are directly sent or indirectly sent via other network elements. "When", "in the case of", "if" and "if" and other descriptions all refer to the objective situation in which the device will make corresponding processing, and are not limited by time, and do not require the device to have a judgment action when implemented, nor does it mean that there are other limitations. "Corresponding to", "correspondingly" and equivalent expressions mean that the two have a corresponding relationship, which can include indirect correspondence. For example, corresponding to a certain objective situation, the device will directly or indirectly make corresponding processing, and it is not required that the corresponding processing must follow the occurrence of the objective situation.

[0069] In addition, the network architecture and service scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, with the evolution of network architecture and the appearance of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0070] The communication system to which the embodiments of the present application can be applied will be described below.

[0071] The embodiments of the present application can be applied to various communication systems, including but not limited to: a 5th generation (5G) system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as a 6th generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), an internet of things (IoT) communication system, a narrow band-internet of things (NB-IoT) system, or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, etc., without limitation.

[0072] The communication system applicable to the embodiments of the present application can include one or more transmitting end devices and one or more receiving end devices. Optionally, one of the transmitting end device and the receiving end device can be a terminal device, and the other can be a network device. Optionally, both the transmitting end device and the receiving end device can be terminal devices. Optionally, both the transmitting end device and the receiving end device can be network devices.

[0073] FIG. 1 is a schematic diagram of a network architecture applicable to the embodiments of the present application. As shown in FIG. 1, the embodiments of the present application can be applicable to both uplink data transmission and downlink data transmission. In FIG. 1, only uplink data transmission or downlink data transmission between one network device and two terminal devices (e.g., terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting end device herein is a terminal device, and the receiving end device is a network device; conversely, in downlink data transmission, the transmitting end device is a network device, and the receiving end device is a terminal device. In addition, the embodiments of the present application are not limited in their applicability in other communication scenarios, for example, they can also be applied to sidelink communication.

[0074] The terminal device of the present application can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a drone, a wireless communication device, a user agent or a user apparatus, etc. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to users, and can be used to connect people, things and machines, such as handheld devices with wireless connection function, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.

[0075] The network device of the present application can be a device with wireless transceiving function, which can be a device providing wireless communication function service, usually located at the network side, including but not limited to next generation base station (gNodeB, gNB) in 5G system, base station in sixth generation mobile communication system, base station in future mobile communication system, or access node in wireless fidelity (WiFi) system, evolved node B (eNB) in long term evolution (LTE) system, radio network controller (RNC), node B (NB), base station controller (BSC), home base station (such as home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellite, unmanned aerial vehicle, etc. In one network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or be a RAN device including CU node and DU node, or be a RAN device including control plane CU node and user plane CU node, and DU node, or the network device can also be a wireless controller in cloud radio access network (CRAN) scenario, relay station, vehicle-mounted device, wearable device, etc. In addition, the base station can be a macro base station, micro base station, relay node, donor node or combination thereof. The base station can also refer to a communication module, modem or chip for setting in the foregoing device or apparatus. The base station can also be a mobile switching center, and a device assuming base station function in D2D, V2X, M2M communication, network side device in future communication network, device assuming base station function in future communication system, etc. The base station can support networks of the same or different access technologies, without limitation.

[0076] Unless otherwise defined, the apparatuses used in the embodiments of the present application to realize the functions of the terminal device or the network device can refer to the terminal device or the network device itself, or can refer to an apparatus capable of supporting the terminal device or the network device to realize the functions, such as a chip system or a chip, specifically, a system on a chip (SoC) or a Modem. The apparatus can be installed in the terminal device or the network device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0077] It should also be noted that some embodiments in the present document take the 5G system as an example to introduce specific scheme details. It can be understood that when the scheme is used in other communication systems, for example, the LTE system, or future communication systems, the messages, channels or information in the scheme can be replaced by messages, channels or information capable of realizing corresponding functions in other communication systems, and the present application does not limit this.

[0078] In addition, the embodiments of the present application can be applied to various application scenarios, such as a high throughput scenario, a high reliability scenario, a low latency scenario, a high reliability low latency scenario, or a low power consumption scenario. Among them, the high throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, and the high reliability low latency scenario can be, for example, an ultra reliable low latency communication (URLLC) scenario.

[0079] In order to facilitate understanding of the embodiments of the present application, several concepts or terms related to the embodiments of the present application are briefly described. The concepts or terms described below are based on the concepts or terms defined in the protocol, but do not mean that the embodiments of the present application can only be applied to the existing system, and the concepts or terms related to the embodiments of the present application can be applied to future systems. And the specific name of the concept or term (for example, the concept or term related to the functional description) can be adjusted with the development of future systems.

[0080] 1、LDPC code

[0081] LDPC code is a kind of linear block code. Linear block code is to divide the information sequence to be coded into groups in units of q bits, and then linearly operate the q information bits by the encoder to obtain m check bits, and then combine the q information bits and the m check bits to obtain a code word with length n=q+m. The mapping relationship from the q-bit information bits to the n-bit code word is usually represented by a corresponding check matrix H. According to the check matrix H, the code word sequence can be generated to complete the encoding process. After the code word sequence is transmitted through the channel, the receiving end device decodes the received signal to determine the original information bits.

[0082] The check matrix H of LDPC is a sparse matrix. The number of zero elements in the check matrix H is much larger than the number of non-zero elements, or in other words, the row weight (or column weight) of the check matrix is much smaller than the number of elements in each row (or each column) of the LDPC matrix. The LDPC code with the information bit sequence length equal to q and the code length equal to n can be uniquely determined by its check matrix H.

[0083] Tanner represented the check matrix H in the form of a graph in 1981. This graph is now called a Tanner graph, and the Tanner graph and the check matrix correspond one-to-one. The Tanner graph is composed of two types of vertices. One type of vertex represents a code word bit, which is called a variable node. The other type of vertex is a check node, which represents a check constraint relationship. Each check node represents a check constraint relationship. The following will be described in conjunction with FIG. 2 and FIG. 3.

[0084] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0085] In FIG. 2, {V i} represents a variable node (VN) set, and {C i} represents a check node (CN) set. Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. In FIG. 2, there are 8 variable nodes and 4 check nodes. If a code word bit is included in the corresponding check equation, a connecting line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0086] FIG. 3 is a Tanner graph of a check matrix H of an LDPC.

[0087] As shown in FIG. 3, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the check matrix H, and the m check nodes correspond to the m rows of the check matrix H. A cycle in the Tanner graph is a closed loop of vertices connected to each other, with one vertex in the loop serving as both the start and end point, and passing through each node only once. More specifically, a cycle refers to a closed loop formed by variable nodes, check nodes and edges. The length of the cycle is defined as the number of edges it contains, and the girth of the graph can also be referred to as the perimeter of the graph, which is defined as the minimum cycle length in the graph. As shown in FIG. 3, the girth is 4, as indicated by the black edges. The variable nodes in the Tanner graph correspond to each column of the check matrix H, i.e., each code bit of the LDPC. The check nodes in the Tanner graph correspond to each row of the check matrix H, i.e., each check bit of the LDPC. The connection between the two types of nodes corresponds to the values of the elements in the H matrix. If there is a connection between the i th check node and the j th variable node, it means that the value of the element (i, j) in the H matrix is 1, and if there is no connection, the corresponding element is 0. The connection between the variable nodes and the check nodes can also be referred to as an edge. The connection between the check nodes and the variable nodes can also be described as: the check nodes and the variable nodes have a connection or an edge. The edge relationship between the check nodes and the variable nodes can include the existence of an edge or the non-existence of an edge.

[0088] 2. QC-LDPC code

[0089] The QC-LDPC code is a type of structured LDPC code. Due to the unique structure of the check matrix, it can be implemented using a simple feedback shift register during encoding, reducing the encoding complexity of the LDPC code. The QC-LDPC code used in practice is represented using a base graph (BG). The elements in the BG are 0 or 1. The 1s and 0s in the BG are expanded, and after the expansion is completed, the check matrix H obtained can be used for encoding or decoding. In the embodiments of the present application, the BG can be written in matrix form, which can be referred to as the base matrix H BG in the present application. The elements in the base matrix H BG are 0, indicating that there is no edge in the base graph, and are 1, indicating that there is an edge in the base graph (or indicating that the corresponding check is associated with the corresponding variable). The NR LDPC code involves multiple base graph selection. Currently, two base graphs BG1 and BG2 are stored in the standard. When the information length is less than or equal to 292, or the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or the code rate is less than or equal to 0.25, BG2 is used, otherwise BG1 is used. The expansion process of the base matrix is described below.

[0090] Based on the base matrix and the lifting size Zc, the base matrix can be expanded into a complete check matrix for encoding or decoding. In this application, Z c It can also be called expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process is to lift all elements in the base matrix into a Zc*Zc square matrix, wherein 0 is lifted into a Zc*Zc zero matrix, 1 is lifted into a unit matrix and the unit matrix is cyclically shifted based on the corresponding shifting value (SV) of 1. The cyclic shift can be to the left or to the right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 unit matrix as an example, if the shifting values are 0, 1 and 3 respectively, the cyclic shift matrix after right cyclic shift is as shown in the following table:

[0091] (1) When the shifting value is 0 (i.e. remains unchanged), the corresponding cyclic shift matrix after cyclic shift is

[0092] (2) When the shifting value is 1, the corresponding cyclic shift matrix after cyclic shift is

[0093] (3) When the shifting value is 3, the corresponding cyclic shift matrix after cyclic shift is

[0094] It can also be understood that the complete check matrix H can be represented by an exponential matrix H b , wherein each element in H b corresponds to a Zc*Zc submatrix, and each element identifies the number of times of cyclic shift of the corresponding submatrix from the Zc*Zc unit matrix. Thus, the required storage space of the complete check matrix H is greatly reduced. The elements in the exponential matrix H b can also be called QC blocks.

[0095] For example, the exponential matrix H b of QC-LDPC code is as follows:

[0096] It can be seen that the size of the exponential matrix H b is 4 rows and 24 columns, and each element i in the exponential matrix H b represents a Zc-order square matrix , wherein i represents the cyclic shifting value of the cyclic shift matrix, and i is an integer. In addition, "-1" in the exponential matrix H b represents a zero matrix, and "0" represents a unit matrix.

[0097] For example, As shown below:

[0098] Optionally, the zero elements in the exponent matrix H b may be represented in other forms in addition to "-1", such as using "-" or null to represent a full zero matrix.

[0099] It can be understood that the matrix corresponding to changing the positions greater than and equal to 0 in the above exponent matrix H b to 1 and the positions of -1 to 0 is a base matrix. The 1 in the base matrix is extended to a Zc-order cyclic shift matrix based on the elements in the corresponding position of the exponent matrix, and the 0 is extended to a Zc-order all-zero matrix. After the extension is completed, the check matrix H is obtained.

[0100] Then, the information bit sequence c can be encoded based on the check matrix H to obtain a codeword sequence, wherein the codeword sequence includes (N+2*Zc-K) check bits w, N is the length of the codeword sequence, K=Kb*Zc, Kb is the column number of the information column corresponding to the base graph, and Zc is the lifting value, which is described in detail in Term Explanation 3. Specifically, the check bits w are determined based on the information bit sequence c and the check matrix H, wherein the check bits are w=[w0,w1,w2,…,w N+2 * Zc-K-1 ] T , c=[c0,c1,c2,…,c N-1 ] T , and the encoding process is to solve the equation to obtain w.

[0101] 3. Lifting size Zc and shifting value

[0102] The storage content of the 5G LDPC code about the shifting value includes: (1) a lifting size list; and (2) a shifting value list corresponding to each row of the lifting size list.

[0103] For example, the lifting size list is shown in Table 1.

[0104] Table 1

[0105] The jth row of the lifting size list includes wherein a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}; the index of the lifting size corresponds to the column mark of the shifting value, that is, the lifting size index in each row of the lifting size list corresponds to a group of shifting values.

[0106] For example, the list of shift values is shown in Table 2.

[0107] Table 2

[0108] For fixed lifting value index, one non-zero position of the base matrix corresponds to one shift value. For example, H BG The shift value corresponding to the 0th row and 0th column in H BG The shift value corresponding to the 1st row and 6th column in H BG The shift value corresponding to the 2nd row and 9th column in H

[0109] It can be understood that when LDPC encoding is performed, the lifting value needs to be determined first, and then the corresponding shift value is determined based on the selected lifting value to construct the check matrix. For example, the determined lifting value is 40, and the lifting value index corresponding to 40 in Table 1 is 2, and then the check matrix can be constructed based on the shift values in the column corresponding to the lifting value index = 2 in Table 2.

[0110] 4. Structure of check matrix and base matrix

[0111] FIG. 4 is a schematic diagram of the structure of the check matrix.

[0112] As shown in (a) of FIG. 4, the check matrix can include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region can include the A part and the B part shown in (b) of FIG. 4, where the A part corresponds to information bits (or information symbols, system symbols, etc.), and the B part is a square matrix and corresponds to core check bits (or core check symbols), where the core check can be a check corresponding to the highest code rate, or can be a check with a degree greater than or equal to 2, or can be a check node corresponding to a row set with a maximum row weight (a row weight significantly / higher than other rows). The all-zero region can correspond to the C part of (b) of FIG. 4, which is an all-zero matrix. The incremental redundancy region can correspond to the D part of (b) of FIG. 4. The raptor-like region can correspond to the E part of (b) of FIG. 4, which can be a unit matrix and corresponds to check bits for low rate extension. The B part and the E part are both check parts, the B part is defined as a core check region, and the feature can be a non-lower triangular encoding part (i.e., a value above the diagonal is non-all 0), or an encoding part with a column weight greater than 1, and the E part is defined as an extension check region, and the feature can be a lower triangular encoding part (i.e., a value above the diagonal is all 0), or a diagonal matrix.

[0113] The check matrix of the LDPC code shown in FIG. 4 adopts a "raptor-like" structure, and can be gradually extended to a low code rate from a high code rate core matrix. In actual use, as shown in (a) of FIG. 4, the first X rows and the first Y columns of the check matrix can be intercepted, and as the code rate gradually decreases from high to low, X and Y gradually increase, and the area of the matrix used also gradually expands.

[0114] It should be noted that the check matrix can be represented by an LDPC base matrix, and therefore the structure of the LDPC base matrix is similar to that of the check matrix, which will not be described in detail here.

[0115] 5. Information length, code length, and code rate

[0116] The information length is the length (i.e., the number of bits) of the sequence of information bits to be sent, which can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits, which is not specifically limited in the present application.

[0117] The code length refers to the length of the sequence of bits to be sent, which can be a sequence of transmission bits corresponding to modulated symbols.

[0118] Code rate refers to the ratio of the length of the information bit sequence to be sent to the code length.

[0119] Optionally, the above three values can be pre-configured by high layer signaling, medium access control (MAC) layer or downlink physical layer signal, and can also be obtained or calculated directly by the transceiver. For example, the code length can be determined by the frame structure, number of layers and modulation scheme of the encoding and information bit sequence to be sent; the code rate can be indicated in the above manner, or given in the modulation and coding scheme (MCS).

[0120] 6. Information transmission process

[0121] FIG. 5 is a schematic diagram of an information transmission process suitable for the present application. As shown in FIG. 5, information is sent from a source, processed by source encoding, channel encoding, modulation, air interface transmission, demodulation, channel decoding, source recovery, and so on, and reaches a sink, completing the transmission of information from the source to the sink. Among them, the processing shown in the upper layer of FIG. 5 (including source encoding, channel encoding and modulation, etc.) is performed at the sending end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. Embodiments of the present application mainly relate to source encoding, channel encoding, channel decoding and source recovery shown in FIG. 5.

[0122] Based on the description in the background art, the present application proposes a communication method based on LDPC code, which can effectively solve the above technical problems. The method proposed in the present application is described in detail below.

[0123] FIG. 6 is a schematic flowchart of a communication method 600 based on LDPC code provided by the present application. The method includes the following steps.

[0124] It can be understood that the method 600 can be executed by a sending end device and a receiving end device, and unless otherwise specified, the "sending end device" or "receiving end device" can refer to the sending end device or receiving end device itself, or can refer to a device capable of supporting the sending end device or receiving end device to implement the function. For the convenience of description, the sending end device and the receiving end device are used to describe below. Among them, the sending end device can be a terminal device or a network device, and the receiving end device can be a terminal device or a network device.

[0125] S610, the sending end device obtains an information bit sequence.

[0126] It can be understood that if the sending end device needs to communicate with the receiving end device, i.e., the sending end device needs to send a signal to the receiving end device, the sending end device needs to first obtain a sequence of information bits corresponding to the signal to be sent to the receiving end device.

[0127] Wherein, the sending end device obtaining the sequence of information bits can refer to that the sending end device source encodes the source symbols to generate the sequence of information bits, or the sending end device obtaining the sequence of information bits can also refer to that the sending end device receives the sequence of information bits from other communication devices, and the application does not limit the way of obtaining the sequence of information bits.

[0128] S620, the sending end device determines the LDPC matrix. Wherein, the LDPC matrix is determined based on the exponent matrix of the LDPC base matrix (hereinafter referred to as the base matrix) and the lifting value Zc.

[0129] For example, the base matrix is BG1 or BG2 of NR.

[0130] The exponent matrix of the base matrix at least has a 3-row (L+1)-column submatrix A, L is an integer greater than or equal to 2, the value range of any element in the submatrix A is [0, Zc-1], and the submatrix A is:

[0131] It can be understood that the elements in the exponent matrix that are not equal to -1 are the corresponding positions about the exponent matrix corresponding to the base matrix, which is described in the foregoing b , and will not be repeated here.

[0132] For the submatrix A, there are positive integers k, x, y and z, such that the elements in the set Q1{mod(z π(1) -x π(1) -z π(0) +x π(0) , Zc), mod(z π(2) -x π(2) -z π(0) +x π(0) , Zc), …, mod(z π(L) -x π(L) -z π(0) +x π(0) , Zc)} satisfy at least one of the characteristics one, the characteristics two and the characteristics three, and mod represents the modulo operation. First, the process of obtaining the set Q1 is described, and then the characteristics satisfied by the set Q1 are described.

[0133] The process of obtaining the set Q1 is as follows:

[0134] First, the set Q3{mod(y0-x0,Zc), mod(y1-x1,Zc), …, mod(y L -xL The elements in Q2 are rearranged in ascending order, and a set Q2{mod(y π(0) -x π(0) The elements in Q2 are rearranged in ascending order, and a set Q2{mod(y π(1) -x π(1) The elements in Q2 are rearranged in ascending order, and a set Q2{mod(y π(L) -x π(L) The elements in Q2 are rearranged in ascending order, and a set Q2{mod(y

[0135] The characteristics of set Q1 are as follows:

[0136] Characteristic one: k≥2, set Q1 includes k non-empty subsets C1,…,C k The union of the k non-empty subsets is set Q1, and subset C j contains n j elements, 1≤j≤k, n j is less than or equal to x, and subset C j includes the remaining elements in the first n elements of set Q1 except the first n elements.

[0137] Characteristic two: for all j∈{1,2,…,k}, the difference between max{C j} and min{C j} in subset C j is less than or equal to y, where max{C j} and min{C j} are the maximum and minimum values in subset C j , respectively.

[0138] Characteristic three: 2≤z≤k-1, when 1≤j≤z-1, min{C j}≥max{C j+1}, when z≤j≤k-1, max{C j}≤min{C j+1}, that is, the subsets first increase and then decrease.

[0139] The technical solution can ensure that the girth corresponding to the sub-matrix A is at least 8, compared with the case that the sub-matrix A corresponds to the same girth in the existing LDPC code construction scheme, the minimum lifting value required by the application is relatively small, and therefore the application can be applied to a communication scene with high low-latency requirement. In addition, the scheme provided in the application can give a clear LDPC code construction scheme for different column numbers (i.e., for different (L+1) columns) and different lifting values, so that the key parameters such as code rate and code length can be flexibly adjusted according to different transmission requirements, to better adapt to various complex communication environments and meet diversified applications.

[0140] In a possible implementation, the sub-matrix A is determined based on the matrix A', where the matrix A' is:

[0141] Correspondingly, the sub-matrix A can be converted into the matrix A' through the following operations, specifically:

[0142] (1) subtracting the corresponding x from all elements in each column i of the sub-matrix A respectively, to obtain: i

[0143] (2) subtracting (y0-x0) from all elements in the second row of the matrix obtained in (1), and subtracting (z0-x0) from all elements in the third row, to obtain:

[0144] (3) taking all elements in the matrix obtained in (2) modulo Zc, to obtain a first matrix, and the first matrix is as follows:

[0145] (4) the matrix obtained by permuting the elements in the second row of the first matrix in ascending order is the matrix A'.

[0146] It can be understood that the values of the elements (a(1), a(2), …, a(L)) in the second row of the matrix A' are all in the range of [0, Zc-1], and the elements in the second row are monotonically increasing from left to right.

[0147] It can also be understood that the above description is the process of converting the sub-matrix A into the matrix A', and if the matrix A' is known, the sub-matrix A can also be determined through the inverse operation of the above operation.

[0148] For example, Zc=9, the first matrix is and the matrix A' is

[0149] ​It can be understood that, since the sub-matrix A and the matrix A' can be converted to each other, for the sub-matrix A, there are positive integers k, x, y and z, such that the elements in the set Q1 satisfy the characteristics one, the characteristics two and the characteristics three, then equivalently, for the matrix A', there are the same positive integers k, x, y and z, such that the set Q4(b(1), b(2), …, b(L)) (the set Q4 is the elements in the third row of the matrix A') satisfies the characteristics four, the characteristics five and the characteristics six, wherein the characteristics one corresponds to the characteristics four, the characteristics two corresponds to the characteristics five, and the characteristics three corresponds to the characteristics six.

[0150] The characteristics four is that k≥2, the set Q4 includes k non-empty sub-sets C'1, …, C'k, the union set of the k non-empty sub-sets is the set Q4, the sub-set C'j includes n k elements, 1≤j≤k, n j is less than or equal to x, the sub-set C'j includes the remaining elements in the first x elements of the set Q4 except the first x elements. j j j

[0151] The characteristics five is that the difference between max{C'j} and min{C'j} in the sub-set C'j is less than or equal to y, max{C'j} and min{C'j} are the maximum value and the minimum value in the sub-set C'j respectively. j j j j j j

[0152] The characteristics six is that 2≤z≤k-1, when 1≤j≤z-1, min{C'j}≥max{C'j}, when z≤j≤k-1, max{C'j}≤min{C'j}. j j+1 j j+1

[0153] The matrix A' is exemplified. In the example, L=5, Zc=25, (0, a(1), a(2), a(3), a(4), a(5))=(0, 1, 3, 5, 6, 8), k=3, x=2, y=16, ​​​​​​​​​​​​​​​where k = 3 and x = 2 represent that (b(1), b(2), b(3), b(4), b(5)) is divided into 3 sub-sets, the number of elements in each sub-set is less than or equal to 2, z = 2 represents that the sub-set C'1 to the sub-set C'2 decreases, the sub-set C'2 to the sub-set C'3 increases, and y = 16 represents that the difference between the maximum value and the minimum value in each sub-set does not exceed 16. Then, a specific example of (b(1), b(2), b(3), b(4), b(5)) satisfying the above setting corresponding features is C'1 = (b(1), b(2)) = (12, 18), C'2 = (b(3)) = (10), and C'3 = (b(4), b(5)) = (9, 24). The girth corresponding to the matrix A' created based on this example is 8.

[0154] In another possible implementation, the elements in the first row and the first column of the sub-matrix A are all 0, and the sub-matrix A can be represented as:

[0155] where the values of the elements a(n) in the second row and the elements b(n) in the third row of the sub-matrix A are in the range of [0, Zc-1], 1≤n≤L, and a(n) monotonically increases with the increase of n, and the set Q4(b(1), b(2), …, b(L)) satisfies at least one of feature four, feature five and feature six. Here, no longer elaborated.

[0156] FIG. 7 is a simulation diagram of the LDPC code constructed based on the above example and the LDPC code constructed based on the random search shift value. Wherein, the horizontal axis is the signal to noise ratio (SNR), and the vertical axis is the block error rate (BLER), curve #1 is the decoding performance curve of the check matrix based on the above example, and curve #2 is the decoding performance curve of the check matrix obtained by randomly searching (a(1), a(2), a(3), a(4), a(5)) and (b(1), b(2), b(3), b(4), b(5)) under the same lifting value and base matrix condition as the above example. It can be seen that, under the same error rate, curve #1 has obvious improvement in performance compared with curve #2, that is, the QC-LDPC code construction scheme proposed in the present application performs better in performance compared with the randomly generated QC-LDPC code.

[0157] The following gives several possible specific implementation modes of constructing the matrix A'.

[0158] Implementation mode one

[0159] (1) Set a(n) in the matrix A' = n*d, that is, a(n) constitutes an arithmetic sequence with a tolerance of d, and d is an integer greater than or equal to 2.

[0160] Specifically, a(l) = d, a(2) = 2*d, and so on, a(L) = L*d.

[0161] (2) Set the number of columns (L+1) of the matrix A' = 2*m*d+r, m is a positive integer, r is an integer and 0≤r≤2*d-1.

[0162] (3) Set k and x.

[0163] ① When r≥1, let k = 2*m+1, x = max{d, r}, that is, divide {b(l), b(2), …, b(L)} into (2m+1) sub-sets C' j , the number of elements in each sub-set C' j does not exceed max{d, r}. The elements contained in each sub-set are exemplarily given as follows.

[0164] When j = 1, C' j = {b(l), b(2), …, b(d-1)};

[0165] When 2≤j≤m, C' j = {b((j-1)*d), b((j-1)*d+1), …, b(j*d-1)};

[0166] When j = m+1, C' j = {b(m*d), b(m*d+1), …, b(m*d+r-1)}; m+2≤j≤2m+1, C' j = {b((j-2)d+r), b((j-2)d+r+1), …, b((j-2)*d+r+d-1)}.

[0167] ② When r = 0, let k = 2*m, x = d, that is, divide {b(l), b(2), …, b(L)} into (2*m) sub-sets C' j , the number of elements in each sub-set C' j does not exceed d. The elements contained in each sub-set are exemplarily given as follows.

[0168] When j = 1, C' j = {b(l), b(2), …, b(d-1)};

[0169] When 2≤j≤2*m, C' j = {b((j-1)*d), b((j-1)*d+1), …, b(j*d-1)}.

[0170] (3) Set y and z.

[0171] Let y = d2 i.e. each C' j The difference between the maximum and minimum values in C' 2 .

[0172] Let z = m + 1, i.e. all elements in C'1are greater than all values in C'2, all elements in C'2are greater than all values in C'3, and so on, up to C m all elements in C m+1 are greater than all elements in C m+1 and so on, up to C 2m+1 are gradually increasing.

[0173] As an example, a construction scheme that satisfies the description of implementation mode one when r = 0 is given below.

[0174] When j = 1, C' j includes elements {Zc-1, Zc-2,..., Zc-(d-1)}.

[0175] When 2≤j≤m, C' j includes elements {Zc-(L+2)*(j-1)*d, Zc-1-(L+2)*(j-1)*d, Zc-2-(L+2)*(j-1)*d,..., Zc-(d-1)-(L+2)*(j-1)*d}.

[0176] When m+1≤j≤2m, C' j includes any element b(i) = b(L-i)-(L-i+1)*d, where m*d≤i≤L.

[0177] As an example, a construction scheme that satisfies the description of implementation mode one when r≥1 is given below.

[0178] When j = 1, C' j includes elements {Zc-1, Zc-2,..., Zc-(d-1)}.

[0179] It can be understood that the partitioning characteristics of the elements in each sub-set C' j in the present application can only satisfy the description of characteristic four, and the present application does not limit the order of the elements in the sub-set C' j For example, C'1b(1) = Zc-1, b(2) = Zc-2 and b(2) = Zc-1, b(1) = Zc-2 are all feasible schemes.

[0180] When 2≤j≤m, C' j{Zc-(L+2)*(j-1)*d,Zc-1-(L+2)*(j-1)*d,Zc-2-(L+2)*(j-1)*d,...,Zc-(d-1)-(L+2)*(j-1)*d}.

[0181] When j = m + 1, C' j {Zc-(L+2)*m*d,Zc-1-(L+2)*m*d,Zc-2-(L+2)*m*d,...,Zc-(r-1)-(L+2)*m*d}.

[0182] When m + 2≤j≤2m+1, C' j Any element b(i) included in the matrix A' satisfies b(i) = b(L-i)-(L-i+1)*d, where m*d+r≤i≤L.

[0183] Based on the above construction method, an example is given in combination with specific numerical values. For example, d = 3, L = 6, m = 1, r = 1, then based on the description in the first implementation manner, k = 3, x = 3, y = 9, z = 2. Then, (a(1), a(2), a(3), a(4), a(5), a(6)) = (3, 6, 9, 12, 15, 18), if Zc = 43, C'1 = (b(1), b(2)) = (42, 41), C'2 = (b(3)) = (19), C'3 = (b(4), b(5), b(6)) = (32, 36, 40). The girth corresponding to the matrix A' constructed based on the example is 8.

[0184] Second implementation manner

[0185] (1) Set a(n) in the matrix A' = n*d, d is equal to 1, that is, a(n) constitutes an arithmetic sequence with a common difference of 1.

[0186] Specifically, a(1) = 1, a(2) = 2,..., and so on, a(L) = L.

[0187] (2) Set k and x.

[0188] Let k = L, x = 1, that is, divide {b(1), b(2),..., b(L)} into L subsets C' j , each subset C' j contains one element.

[0189] Specifically, C'1 = {b(1)}, C'2 = {b(2)},..., and so on, C' L = {b(L)}.

[0190] (3) Set y and z.

[0191] The value of y is not limited in this implementation.

[0192] Let That is, {b(1), b(2), …, b(z)} is monotonically decreasing, and {b(z), b(z+1), …, b(L)} is monotonically decreasing, represents the floor.

[0193] A construction scheme of b(i) conforming to (3) is given below.

[0194] When , b(i) = Zc-(L+2)*i-c i ; when , b(i) = Zc-(L+3)*(L-i)-1-c i , where c o is greater than or equal to 0 and satisfies In the example, is less than and is different from by 1.

[0195] In the example, {c1, c2, …, c L} are randomly selected from all natural numbers, and the above inequalities are maintained. It can be understood that many other constructions can be obtained by adjusting the value range of {c0, c1, c2, …, c L}, which also conforms to the description in (3).

[0196] Based on the above b(i) construction method, specific numerical values are used for illustration. In the example, L = 8, then (a(1), a(2), a(3), a(4), a(5), a(6), a(7), a(8)) = (1, 2, 3, 4, 5, 6, 7, 8), if the promotion value Zc = 55, (b(1), b(2), b(3), b(4)) = (45, 31, 21, 9), (b(5), b(6), b(7), b(8)) = (17, 28, 41, 54). (c1, c2, c3, c4, c5, c6, c7, c8) = (0, 4, 4, 6, 4, 4, 2, 0) The girth corresponding to the matrix A′ constructed based on this example is 8.

[0197] The translation value construction method proposed in the above implementation mode one and implementation mode two is determined, so that the complexity of random search can be reduced. In addition, the minimum lifting value required by the scheme proposed in the application is small, and for all other lifting values greater than the minimum lifting value, the corresponding QC-LDPC code can be constructed, the lifting value application range is large, and fine-grained code length can be achieved, which is better than the current random search method. In addition, through simulation comparison, the LDPC code construction scheme proposed in the application has obvious improvement in performance compared with the random search LDPC code construction scheme.

[0198] In S630, the sending end device encodes the information bit sequence according to the LDPC matrix, and outputs a codeword sequence.

[0199] In the application, the LDPC matrix can also be referred to as an LDPC encoding matrix. For example, the LDPC matrix can be an LDPC check matrix, or an LDPC generator matrix. The LDPC check matrix or the LDPC generator matrix is a matrix obtained by lifting and shifting the elements in all regions of the base matrix, and the LDPC generator matrix and the LDPC check matrix correspond to each other.

[0200] Here, the LDPC matrix is taken as an LDPC check matrix H as an example to simply describe this step. The information bit sequence c is encoded based on the LDPC check matrix H to obtain a codeword sequence, wherein the codeword sequence includes (N+2*Zc-K) check bits w, N is the length of the codeword sequence, K=Kb*Zc, and Kb is the column number of the information column corresponding to the base graph. Specifically, the check bits w are determined based on the information bit sequence c and the check matrix H, wherein the check bits are w=[w0,w1,w2,…,w N+2 * Zc-K-1 T , c=[c0,c1,c2,…,c K-1 ] T , the encoding process is to solve the equation to obtain w.

[0201] In S640, the sending end device determines a symbol sequence based on the codeword sequence.

[0202] It can be understood that the symbol sequence can be a sequence after rate matching and modulation. For example, the sending end device performs rate matching on the codeword sequence, then modulates the sequence after rate matching to obtain a symbol sequence, and then maps the modulated symbol sequence to a physical resource for transmission.

[0203] In S650, the sending end device sends the symbol sequence to the receiving end device. Correspondingly, the receiving end device receives the symbol sequence from the sending end device.

[0204] ​It can be understood that, due to the channel noise signal introduced in the transmission process of the symbol sequence, the symbol sequence #1 sent by the sending device and the symbol sequence #2 received by the receiving device can be different.

[0205] At S660, the receiving device decodes the symbol sequence according to the LDPC matrix to obtain the information bit sequence.

[0206] The LDCP matrix according to which the receiving device decodes is the same as the LDPC matrix according to which the sending device encodes, and the specific manner in which the receiving device determines the LDPC matrix can refer to the description on the sending device side, which will not be described in detail here.

[0207] It can be understood that the steps in the above figures are only exemplary and are not strictly limited. In addition, the size of the serial number of the above processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. It can also be understood that some optional features in the embodiments of the present application can not depend on other features in some scenarios, or can be combined with other features in some scenarios, without limitation. It can also be understood that the methods and operations implemented by the device (sending device or receiving device) in the above method embodiments can also be implemented by the components (such as chips or circuits) of the device, without limitation.

[0208] The method embodiments provided by the present application are described in detail above in combination with FIGS. 1 to 7, and the device embodiments of the present application will be described below in combination with FIGS. 8 and 9. It can be understood that, in order to realize the functions in the above embodiments, the devices in FIGS. 8 and 9 include corresponding hardware structures and / or software modules for executing various functions. Those skilled in the art should easily realize that, in combination with the units and method steps of the examples described in the embodiments disclosed in the present application, the present application can be realized in the form of hardware or a combination of hardware and computer software. It can be understood that the technical features described in the above method embodiments are also applicable to the following device embodiments.

[0209] FIGS. 8 and 9 are structural schematic diagrams of possible devices provided by the embodiments of the present application. These devices can be used to realize the functions of the sending device or the receiving device in the above method embodiments, and thus can also realize the beneficial effects possessed by the above method embodiments.

[0210] FIG. 8 is a schematic block diagram of a communication device 1000 provided by the embodiments of the present application. As shown in FIG. 8, the device 1000 can include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside, and the processing unit 1020 is used for data processing. The communication unit 1010 can also be referred to as a communication interface or a transceiver unit.

[0211] In one possible design, the apparatus 1000 can implement steps or procedures corresponding to those performed by a transmitting device in the above-described method embodiments, where the processing unit 1020 is configured to perform processing-related operations of the transmitting device in the above-described method embodiments, and the communication unit 1010 is configured to perform transmitting-related operations of the transmitting device in the above-described method embodiments.

[0212] In another possible design, the apparatus 1000 can implement steps or procedures corresponding to those performed by a receiving device in the above-described method embodiments, where the communication unit 1010 is configured to perform receiving-related operations of the receiving device in the above-described method embodiments, and the processing unit 1020 is configured to perform processing-related operations of the receiving device in the above-described method embodiments.

[0213] It is to be understood that the apparatus 1000 here is in the form of functional units. The expression "unit" herein can refer to, among other things, an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, or other suitable components that provide the described functionality. In one example, it is to be understood that the apparatus 1000 can be specifically a transmitting device in the above-described embodiments, and can be configured to perform the procedures and / or steps corresponding to the transmitting device in the above-described method embodiments, or the apparatus 1000 can be specifically a receiving device in the above-described embodiments, and can be configured to perform the procedures and / or steps corresponding to the receiving device in the above-described method embodiments. To avoid redundancy, details are not repeated here.

[0214] The apparatus 1000 of each of the above-described solutions has the functionality to implement the corresponding steps performed by the transmitting device in the above-described methods, or the apparatus 1000 of each of the above-described solutions has the functionality to implement the corresponding steps performed by the receiving device in the above-described methods. The functionality can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functionality; for example, the communication unit can be replaced by a transceiver (e.g., a transmitting unit in the communication unit can be replaced by a transmitter, and a receiving unit in the communication unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor, which performs the corresponding transmitting and receiving operations and related processing operations in the above-described method embodiments.

[0215] In addition, the communication unit can also be a transceiver (e.g., can include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In embodiments of the present application, the apparatus in FIG. 8 can be a receiving end device or a transmitting end device in the foregoing embodiments, or can be a chip or a chip system, for example, a system on chip (SoC). Wherein, the communication unit can be an input / output circuit, a communication interface; and the processing unit is a processor or a microprocessor integrated on the chip or an integrated circuit. Herein, no limitation is made.

[0216] FIG. 9 is a schematic block diagram of a communication apparatus 1100 provided by embodiments of the present application. The apparatus 1100 includes a processor 1110 and a transceiver 1120. Wherein, the processor 1110 and the transceiver 1120 communicate with each other through an internal connection path, and the processor 1110 is configured to execute instructions to control the transceiver 1120 to transmit and / or receive signals.

[0217] Optionally, the apparatus 1100 can further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 through an internal connection path. The memory 1130 is configured to store instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In a possible implementation manner, the apparatus 1100 is configured to implement each process and step corresponding to the transmitting end device in the method embodiments. In another possible implementation manner, the apparatus 1100 is configured to implement each process and step corresponding to the receiving end device in the method embodiments.

[0218] Optionally, the memory 1130 can be integrated in the processor 1110.

[0219] In a possible scenario, the apparatus 1100 includes at least one processor integrated with a memory, and other memories in addition to the memory integrated on the processor.

[0220] It can be understood that the apparatus 1100 can be specifically the transmitting end device or the receiving end device in the foregoing embodiments, or can be a chip or a chip system. Correspondingly, the transceiver 1120 can be a transceiver circuit of the chip, and no limitation is made herein. Specifically, the apparatus 1100 can be configured to execute each step and / or process corresponding to the transmitting end device or the receiving end device in the method embodiments.

[0221] Optionally, the memory 1130 can include read-only memory and random access memory, and provide instructions and data to the processor. The memory can include non-volatile random access memory. For example, the memory can also store device type information. The processor 1110 can be used to execute the instructions stored in the memory, and when the processor 1110 executes the instructions stored in the memory, the processor 1110 is used to perform the steps and / or processes of the above-mentioned method embodiments corresponding to the sending end device or the receiving end device.

[0222] In the implementation process, the steps of the above method can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as hardware processor execution completion, or executed by a combination of hardware and software modules in the processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, and other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0223] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capability. In the implementation process, the steps of the above method embodiments can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The above processor can be a general processor, a digital signal processing (digital signal processing, DSP), an ASIC, a field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The processor in the embodiments of the present application can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as hardware decoding processor execution completion, or executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, and other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0224] It is to be appreciated that the memory in the embodiments of the application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Where the nonvolatile memory is, for example, read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. The volatile memory, which can be used as external cache, can be, for example, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), or direct rambus RAM (DR RAM). It is to be appreciated that the memory described herein is intended to include, among other things, these and any other memory suitable for storing or providing program code or instructions to a processor or other system.

[0225] Optionally, the memory (e.g., 1130) in the embodiments of the application can be integrated in the processor (e.g., 1110).

[0226] In addition, the application also provides a computer readable storage medium, the computer readable storage medium stores computer instructions, when the computer instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0227] The application also provides a computer program product, the computer program product includes computer program code or instructions, when the computer program code or instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0228] Further, the application provides a chip including a processor. A memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the sending device or the receiving device in any one of the method embodiments are performed.

[0229] Further, the chip can further include a communication interface. The communication interface can be an input / output interface, an interface circuit, or the like. Further, the chip can further include a memory.

[0230] Further, the application provides a communication system including the sending device and the receiving device in the embodiments of the application.

[0231] It should be further noted that the memory described herein is intended to include, but not limited to, these and any other suitable types of memory.

[0232] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other form. The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., they can be located in one place, or distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment. In addition, each functional unit in each embodiment of the application can be integrated into a processing unit, or each unit can be physically present separately, or two or more units can be integrated into one unit.

[0233] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0234] It can be understood that the "embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0235] It can also be understood that in the present application, "when", "if" and "when" all refer to the case that the network element will make corresponding processing under certain objective circumstances, not the time limit, and it is not required that the network element must have a judgment action when it is implemented, nor does it mean that there are other limitations.

[0236] It can also be understood that in the embodiments of the present application, "A corresponding B" means that B is associated with A and B can be determined according to A. However, it can also be understood that determining B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

Claims

1. A communication method based on a low-density parity-check (LDPC) code, characterized by, The method comprises: obtaining an information bit sequence; determining an LDPC matrix, the LDPC matrix being based on an exponent matrix of an LDPC base matrix and a lifting value Zc, wherein, At least one 3-row (L+1)-column sub-matrix A exists in the exponent matrix of the base matrix, L is an integer greater than or equal to 2, the value range of any element in the sub-matrix A is [0, Zc-1], and the sub-matrix A is: There are positive integers k, x, y and z, so that the elements in the set Q1{mod(z π(1) -x π(1) -z π(0) +x π(0) , Zc), mod(z π(2) -x π(2) -z π(0) +x π(0) , Zc), …, mod(z π(L) -x π(L) -z π(0) +x π(0) , Zc)} satisfy at least one of the characteristics one, characteristics two and characteristics three, the set Q1 is determined based on the subscript π(i) corresponding to the elements in the set Q2{mod(y π(0) -x π(0) , Zc), mod(y π(1) -x π(1) , Zc), …, mod(y π(L) -x π(L) , Zc)}, 0≤i≤L, the π(i) is an integer from 0 to L, and i is different, π(i) is not the same, the set Q2 is obtained by arranging the elements of the set Q3{mod(y0-x0, Zc), mod(y1-x1, Zc), …, mod(y L -x L , Zc)} in ascending order, The features are: the k is greater than or equal to 2, the set Q1 includes k non-empty sub-sets C1,..., Ck k , the union of the k non-empty sub-sets is the set Q1, the sub-set Cj j includes n j elements, 1≤j≤k, the n j is less than or equal to x, the sub-set Cj j includes the first Among the elements, excluding the first one elements remaining outside the elements, The second feature is that the subset C j The difference between max{C j} and min{C j} is less than or equal to the y, where max{C j} and min{C j} are the maximum and minimum values, respectively, in the subset C j ​ The third feature is: 2≤z≤k-1, when 1≤j≤z-1, min{C j}≥max{C j+1}, when z≤j≤k-1, max{C j}≤min{C j+1}; encoding the information bit sequence according to the LDPC matrix to obtain a codeword sequence.

2. A communication method based on a low-density parity-check (LDPC) code, comprising: obtaining a symbol sequence; determining an LDPC matrix, the LDPC matrix being based on an exponent matrix of an LDPC base matrix and a lifting value Zc, wherein, At least one 3-row (L+1)-column sub-matrix A exists in the exponent matrix of the base matrix, L is an integer greater than or equal to 2, the value range of any element in the sub-matrix A is [0, Zc-1], and the sub-matrix A is: There exist positive integers k, x, y and z, such that the elements in the set Q1 {mod(z π(1) -x π(1) -z π(0) +x π(0) , Zc), mod(z π(2) -x π(2) -z π(0) +x π(0) , Zc), mod(z π(L) -x π(L) -z π(0) +x π(0) , Zc)} satisfy at least one of the following characteristics: characteristic one, characteristic two and characteristic three, the set Q1 is determined based on the subscript π(i) corresponding to the elements in the set Q2 {mod(y π(0) -x π(0) , Zc), mod(y π(1) -x π(1) , Zc), mod(y π(L) -x π(L) , Zc)}, 0≤i≤L, the π(i) is an integer from 0 to L, and i is different, the π(i) is different, the set Q2 is obtained by arranging the elements in the set Q3 {mod(y0-x0, Zc), mod(y1-x1, Zc), mod(y L -x L , Zc)} in ascending order, The features are: the k is greater than or equal to 2, the set Q1 includes k non-empty sub-sets C1, …, Ck k , the union of the k non-empty sub-sets is the set Q1, the sub-set Cj j includes n j elements, 1≤j≤k, the n j is less than or equal to x, the sub-set C j includes the first Among the elements, excluding the first one elements remaining outside the elements, The second feature is that the subset C j max{C j} - min{C j} is less than or equal to the y, where max{C j} and min{C j} are the maximum and minimum values, respectively, in the subset C j ​ The third feature is: 2≤z≤k-1, when 1≤j≤z-1, min{C j}≥max{C j+1}, when z≤j≤k-1, max{C j}≤min{C j+1}; decoding the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

3. The method according to claim 1 or 2, characterized in that, The elements in the first row and the first column of the sub-matrix A are all 0, and the sub-matrix A is: wherein the elements a(n) in the second row and the elements b(n) in the third row of the sub-matrix A have a value range of [0, Zc-1], 1≤n≤L, and a(n) monotonically increases with n, and the set Q4(b(1), b(2), …, b(L)) satisfies at least one of the following characteristics four, five and six, The fourth feature is that the set Q4 includes k non-empty subsets C'1,..., C'k k , the union of which is the set Q4, and each subset C'j j contains n j elements, 1≤j≤k, and n j is less than or equal to x, and C'j j includes the first x Among the elements, excluding the first one elements remaining outside the elements, k>2, The fifth feature is that the subset C' j The difference between max{C' j} and min{C' j} is less than or equal to the y, where max{C' j} and min{C' j} are the maximum and minimum values, respectively, in the subset C' j ​ The sixth characteristic is: when 1≤j≤z-1, min{C′ j }≥max{C′ j+1 }, when z≤j≤k-1,max{C′ j }≤min{C′ j+1 } 4. The method of claim 3, wherein, in the sub-matrix A, a(n)=n*d, n and d are positive integers, 1≤n≤L, and d≥2, the number of columns (L+1) of the sub-matrix A=2*m*d+r, m is a positive integer, r is an integer, and 0≤r≤2*d-1, the k, x, y and z are respectively: when r≥1, k=2*m+1, x=max{d, r}, wherein, j = 1, C' j = {b(l), b(2),..., b(d - 1)}, 2≤j≤m, C j = {b((j-1)*d), b((j-1)*d+1),..., b(j*d-1)}, j = m + 1, C' = C j = {b(m*d), b(m*d+1),..., b(m*d+r-1)}, m+2≤j≤2m+1, C' j = {b((j-2)d+r), b((j-2)d+r+1),..., b((j-2)*d+r+d-1)}, when r=0, k=2*m, x=d, wherein, j = 1, C' j = {b(l), b(2),..., b(d - 1)}, 2≤j≤2m, C' j = {b((j-1)*d), b((j-1)*d+1),..., b(j*d-1)}, said y = d 2 , said z = m + 1.

5. The method of claim 4, wherein, when r≥1, j = 1, the C' j includes the elements {Zc_1, Zc_2,..., Zc_(d-1)}, 2≤j≤m, the C' j includes the elements {Zc-(L+2)*(j-1)*d, Zc-1-(L+2)*(j-1)*d, Zc-2-(L+2)*(j-1)*d,..., Zc-(d-1)-(L+2)*(j-1)*d}, j = m + 1, the C' of said C j comprising the elements {Zc-(L+2)*m*d, Zc-1-(L+2)*m*d, Zc-2-(L+2)*m*d,..., Zc-(r-1)-(L+2)*m*d}, m+2≤j≤2m+1, said C' j any element b(i) = b(L-i) - (L-i+1)*d included in the set B, where m*d+r≤i≤L.

6. The method of claim 3, wherein, in the sub-matrix A, a(n)=n, n is a positive integer, and 1≤n≤L, the k, x, y and z are respectively: said k = L, said x = 1, said y is any positive integer, said 7. The method of claim 6, wherein, b(i) = Zc-(L+2)*i-c i , b(i) = Zc-(L+3)*(L-i)-1-c i , wherein c i greater than or equal to 0 and satisfying 8. A communications device, characterized by comprising at least one processor and an interface circuit, the interface circuit being configured to receive a signal from another communication device outside the communication device and transmit the signal to the processor or send a signal from the processor to the other communication device outside the communication device, the processor being configured to implement the method of any one of claims 1, 3 to 7 by logic circuit or executing code instructions, or to implement the method of any one of claims 2 to 7.

9. The communication apparatus according to claim 8, wherein The communication device is a chip or a chip system.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, when the computer program or instructions are executed, the method of any one of claims 1, 3 to 7 is implemented, or the method of any one of claims 2 to 7 is implemented.

11. A computer program product, characterised in that, comprising a computer program, when the computer program is executed, the method of any one of claims 1, 3 to 7 is implemented, or the method of any one of claims 2 to 7 is implemented.

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