Issue pipe sharing for reservation stations

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for issue pipe sharing. One of the methods includes concurrently issuing a plurality of instructions to different execution units using selection logic to select which source data elements to obtain from the N read ports into the PRF by a process that includes a physical register file (PRF), a plurality of execution units, and a reservation station (RSV) that includes a plurality of issue pipes.

Description

Attorney Docket No. 56113-0782WO1ISSUE PIPE SHARING FOR RESERVATION STATIONSBACKGROUND

[0001] This specification relates to devices that include one or more reservation stations (RS Vs) that can assist with out-of-order (OoO) instruction execution on computing devices. Reservation stations (RSVs) are components in OoO processors that hold instructions until they are ready to be issued for execution by one of multiple execution units. Commonly, an instruction stored by an RSV becomes ready for execution when data needed to execute the instruction becomes available, e.g., arguments to an ADD instruction or an address of a LOAD instruction. Data can become available when the processor stores required input data in a physical register file (PRF), e.g.. which can occur due to execution of a prior instruction. High performing OoO processors have multiple read ports into the PRF in order to read source data to support simultaneous execution of operations in multiple execution units.

[0002] The number of available read ports into the PRF is often a performance bottleneck. This is because increasing the number of read ports into the PRF, with the intention of allowing more simultaneous execution of instructions, is often not feasible due to frequency limitations, timing pressure, and other backend complications. These issues can be caused by a combination of (i) the need of a PRF to provide data for multiple execution units within a single clock cycle, and (ii) the fact that increasing the number of read ports can delay signals, e.g., due to capacitance of closely packed wires. Adding additional read ports to the PRF can also lead to a larger physical size for the PRF, higher power consumption, and more heat generation.SUMMARY

[0003] This specification describes technologies for improved OoO processing.These technologies generally involve an issue pipe that can issue multiple instructions in parallel by sharing read ports into the physical register file or by obtaining source data from a bypass network. A bypass network can include a data path architecture that allows skipping or bypassing of one or more processing stages or operations. In this specification, an issue pipeline, or for brevity, an issue pipe, is circuitry of a processor that retrieves source data for instructions that are ready to be executed and issues the ready instructions to one or more execution units.Attorney Docket No. 56113-0782WO1

[0004] A single read of the issue pipe into a register of a physical register file (PRF) can be alternatively used to read source data for a first, or second, instruction of the at least two different instructions. Whether the single read is used for the first or second instruction depends on selection logic, e.g., whether or not either the first or second instruction require the use of the read or whether or not the first or second instruction is of higher priority than the other.

[0005] In existing systems, each instruction in OoO processing uses a separate issue pipe to perform operations such as obtaining source data from a PRF. This specification describes improvements where a single issue pipe is used for multiple different instructions, thereby reducing issues, such as processing delays caused by many wires connected to a PRF to provide read ports for each issue pipe of a system.

[0006] A shared issue pipe can be configured with one or more shared read ports into a PRF. The shared issue pipe can provide source data for multiple different instructions using the shared read ports. The reads into the PRF can provide source data which is processed by the instructions to generate output data. If a total number of reads for the multiple instructions exceed the number of read ports of the shared issue pipe, a system can either (i) prioritize one instruction over the other by canceling at least one of the multiple instructions and using the shared read ports for the non-canceled instructions or (ii) obtain source data from a non-PRF source, such as a bypass network. A bypass value, e.g., stored in an RSV, can be used by the system to determine whether or not source data can be obtained from a bypass network. If an instruction is canceled more than a threshold number of compute cycles, another instruction can be canceled for the next compute cycle to allow the canceled instruction to execute.

[0007] The technology described in this specification can be implemented so as to realize one or more of the following advantages. For example, techniques can optimize the use of read ports into a PRF. In general, more read ports into a PRF can lead to timing pressure, energy usage increases, or thermal increases. However, more read ports into the PRF can help to increase a number of instructions that can be performed in parallel. For example, to process a set of N instructions in parallel where each instruction requires access to two sources from the PRF, the PRF would need to support 2N read ports, which is often infeasible. In contrast, the techniques described in this specification allow for increasing the number of instructions to be performed in parallel without increasing the number of read ports into the PRF. For example, the system could allowAttorney Docket No. 56113-0782WO1 more than N instructions to be processed in parallel without increasing the number read ports ordinarily required by N instructions by sharing the available read ports between the instructions. In addition, the techniques described in this specification reduce the number of cycles in which read ports into the PRF are unused.

[0008] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below.Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is an overv iew of logical stages of an example OoO processor system.

[0010] FIG. 2 shows an example system for selecting read ports for one or more instructions.

[0011] FIG. 3 shows an example system for obtaining source data for concurrently- issued instructions from a PRF and bypass network.

[0012] FIG. 4 shows a system that combines elements of FIG. 2 and FIG. 3.

[0013] FIG. 5 shows an overview of obtaining source data and executing instructions.

[0014] FIG. 6 is a detailed view of an issue pipe and a process of obtaining source data.

[0015] FIG. 7 is a flowchart of an example process for sharing an issue pipe.

[0016] FIG. 8 is a flowchart of an example process 800 for using a bypass network to increase instances of sharing an issue pipe.

[0017] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0018] FIG. 1 is an overv iew of logical stages of an example OoO processor system. The system is an example of a system that can implement OoO execution and can generally execute instructions through six main stages: a fetch stage 102, a decode stage 104, a dispatch stage 106, an issue stage 108, an execution stage 112, and a commit stage 114. Each of these stages can be implemented using digital logic circuitry of any appropriate device, e.g., an integrated circuit device. Each stage can be performed by oneAttorney Docket No. 56113-0782WO1 or more functional modules of the device. In some implementations, each stage is implemented by a distinct functional module. The various modules as mentioned above may be implemented using various logic circuitry components, to include AND, OR, NOT, NAND, or XOR gates. Other implementations may employ other circuitry components or data processing apparatus.

[0019] The fetch stage 102 is generally responsible for retrieving each subsequent block of instructions for execution. The instructions can be fetched from an instruction cache if they have been previously executed or from the main memory if the instruction address is not found in the instruction cache. The fetch stage 102 can also be preceded by a branch prediction stage that can use various branch prediction techniques to predict which block of instructions will be executed next. For example, the branch prediction stage can make a prediction of whether a branch will be taken before the conditional information that determines whether the branch will be taken becomes available.

[0020] The decode stage 104 can analyze the incoming instructions and convert them into data that can be understood and executed by the execution units. As part of this process, the decode stage 104 can determine which processor resources are needed to effectuate the results of each instruction.

[0021] The dispatch stage 106 prepares processor resources that are required in order to execute the instructions. For example, the processor can perform a register renaming process that can allocate a physical register from the physical register file for each logical register to which the instruction will write data. To do so, the processor can query a freelist, which is a microarchitectural structure that maintains information about the availability of physical registers to be allocated for program execution. When a batch of N instructions is fetched, the processor can query the freelist in order to allocate N physical registers that are available to store the results of executing the instructions.

[0022] The dispatch stage 106 can also store a representation of the instructions in a reorder buffer (ROB). The ROB is a microarchitectural structure that maintains information about each instruction in flight as well as the program order of the instructions. For example, the ROB can store for each instruction its logical register name (LRN) to physical register name (PRN) mapping as well as information about whether the instruction is a speculative instruction or not. In order to maintain the instructions in the ROB in program order, in some implementations the ROB can beAttorney Docket No. 56113-0782WO1 implemented as a circular buffer that operates with new instructions being inserted at the tail of the ROB and the head of the ROB indicating the oldest uncommitted instruction.

[0023] The dispatch stage 106 can then send each instruction represented in the ROB to a reservation station (RSV) 110, where the instructions wait to be issued. A reservation station is a microarchitectural structure that maintains a queue of instructions that are waiting to be executed. Commonly an instruction becomes ready for execution when its source data becomes available. For example, an ADD instruction becomes ready to be executed when its two operands become available by being written into the physical register file.

[0024] During the issue stage 108. the RSV 110 generally repeatedly selects the oldest ready instruction and sends the instruction to an appropriate execution unit. In more detail, the RSV 110 can send the instruction to one or more of issue pipes 122a-d. The issue pipes 122a-d are configured to obtain source data for the instruction to process. The issue pipes 122a-d can obtain source data from a PRF 130, a bypass network 140, or a combination of both the PRF 130 and the bypass network 140. The PRF 130 can store output data from one or more instruction executions. Such output data can be obtained by the issue pipes 122a-d as source data. The bypass network 140 can access intermediate stages in an execution pipeline. The bypass network 140 can provide such data as source data to the issue pipes 122a-d. Data obtained by the issue pipes 122a-d as source data can be generated after the commit stage 114. In some cases, the bypass network 140 processes data obtained from the commit stage 114 and provides such data to one or more of the issue pipes 122a-d, the PRF 130, or both the issue pipes 122a-d and the PRF 130.

[0025] The issue pipes 122a-d can select one or more execution units to process obtained source data according to the issued instructions — e.g., adding first source data with second source data for a corresponding ADD instruction. The issue pipe 122d can select one or more execution units to process obtained source data from at least one of the PRF 130 or the bypass network 140. The issue pipe 122d can select an execution pipe 124, an execution unit 126, or both. The execution units can be configured to execute an instruction, e.g., by using one or more execution pipelines. The operations of the issue pipes and execution units are described in more detail with respect to figures 2 through 8.

[0026] The RSV 110 can maintain a single instruction queue, or the RSV 110 can be partially or fully distributed by maintaining multiple queues that are each dedicated to aAttorney Docket No. 56113-0782WO1 set of one or more execution units. For example, store instructions and floating point instructions can be maintained in separate queues of the RSV.

[0027] During the execution stage 112, multiple execution units process issued instructions in parallel. The processor can be implemented with multiple different types of execution units for a variety of types of instructions. For example, the processor can have some execution units for integer arithmetic, some execution units for floating point arithmetic, some execution units for loads and stores, or some execution units for multicycle instructions, to name just a few examples.

[0028] Notably, the execution stage 112 can execute instructions out of program order because of the way the RSV 110 keeps track of instructions that are ready to be issued. For example, an ADD instruction that reads from the physical register fde can be executed before a preceding load instruction that reads from memory, assuming there is no data dependency between them.

[0029] During the commit stage 114, the results of the execution units are written back to one or more structures in the processor. Importantly, the instructions are committed in program order, which has been preserved in the ROB. In some implementations, the results are first written back to each instruction’s entry in the ROB, and then fully committed when the instruction reads the head of the ROB. The head of the ROB represents the oldest instruction that has not yet been committed. For instructions that are speculative, the result can be maintained in the ROB until the corresponding condition is resolved. For instructions that are not speculative, their results can be written to the physical register file in program order.

[0030] The processor can use a number of other structures that relate to maintaining the correct state of the program being executed. As one example, the processor can maintain an architected map table (AMT) that stores a mapping between LRNs and allocated PRNs that represents a permanent state of the program that is not subject to being flushed or re-executed due to a mispredicted branch. When a new instruction writes to a logical register maintained in the AMT, this frees up the corresponding physical register, and the processor can return its PRN to the freelist.

[0031] For speculative instructions, or instructions that have not yet been committed, the processor can maintain a rename map table (RMT) that stores a speculative state of renamed registers. Thus, the RMT can store the LRN to PRN mapping of the speculativeAttorney Docket No. 56113-0782WO1 state of the processor. When a mispredicted branch occurs, the processor can perform a flush recovery process that rolls back effects of speculative instructions and recovers a previous state of the RMT by walking a portion of the ROB and re-executing instructions.

[0032] FIG. 2 shows an example system 200 for selecting read ports for one or more instructions. The example of system 200 considers two instructions, instruction A and instruction B, which can be any type of instruction. Instruction A includes three sources, source RA 202, source RB 204, and source RC 206. Instruction B includes two sources, source RD 208 and source RE 210. In general, instructions with any arbitrary number of sources can be used according to the techniques described in reference to FIG. 2. For simplicity of illustration, two instructions with three and two sources, respectively, are considered.

[0033] The instructions A and B can be instructions that were stored in an RSV, such as the RSV 110 of FIG. 1, and are being issued by an issue pipe 201 prior to execution by execution units 230 and 240. The issue pipe 201 can be similar to the issue pipe 122d of FIG. 1 but instead of obtaining source data from both a PRF and bypass network, the issue pipe 201 of the system 200 obtains source data from just the PRF 220. FIG. 2 focuses discussion on the selection logic performed by an issue pipe whereas later figures focus discussion on obtaining source data from different elements, e.g.. both a PRF and bypass network.

[0034] The issue pipe 201 uses selection logic to select which source data elements to obtain from the read ports of the issue pipe 201 into the PRF 220. The selection logic includes a first multiplexor (MUX) 212 and a second MUX 214. The first MUX 212 is used to select between the source RB 204 of instruction A and the source RD 208 of instruction B. The second MUX 214 is used to select between the source RC 206 and the source RE 210. The issue pipe 201 uses the selection of MUXs 212 and 214 to determine which source data elements to obtain from the PRF 220.

[0035] In some cases, the MUXs 212 and 214 can be configured to select whichever source is valid for a given instruction. For example, the MUX 212 can select the source RB 204 if the MUX 212 receives a valid signal corresponding to the source RB 204. The MUX 212 can select the source RD 208 if the MUX 212 receives a valid signal corresponding to the source RD 208. A valid signal can indicate that a correspondingAttorney Docket No. 56113-0782WO1 instruction requires a given source, e.g., a valid signal for the source RB 204 can indicate that the instruction A requires at least two sources.

[0036] In some cases, if both valid signals are received corresponding to both sources, a MUX can make a default selection. A default selection can select a valid source for a higher priority instruction. In some cases, if the instruction A corresponds to a multicycle (MX) operation and the instruction B corresponds to a store data (STD) operation, the MUX 212 can select the source for the MX operation as a default selection.

[0037] In some cases, the issue pipe 201 cancels an instruction based on a threshold number of available PRF reads. For example, if the MUX 212 receives valid data signals corresponding to the source RB 204 and RD 208, the issue pipe 201 can cancel the instruction B. The instruction B can return to, or remain, in an RSV, such as the RSV 110. Instructions can be canceled when simultaneously issued instructions require more sources than available read ports on a given issue pipe. For example, if the combined number of source reads required for the instruction A and the instruction B is greater than three, the issue pipe 201 can cancel at least one of the instructions, such as the instruction B, because the issue pipe 201 only has three read ports into the PRF 220 and therefore cannot simultaneously issue the instructions in this instance. However, if the combined sources of the instruction A and B do not exceed the available read ports of the issue pipe 201, such as if the instruction A requires two sources and the instruction B requires one source, the issue pipe 201 can proceed with simultaneous issuing of both instructions because the source data for both instructions can be obtained with the limited set of read ports available to the issue pipe 201. An issue pipe with more read ports can support additional instructions and vice versa. One or more thresholds can be used as part of selection logic to select a read of an instruction, such as the instruction A or the instruction B. In some cases, selection logic can be configured to select a read of a first instruction when a count of the first instruction PRF reads satisfies a threshold. The selection logic can include selecting a read of either the instruction A or the instruction B, e.g., based on a combined number of source reads required for the instruction A, the instruction B, or a combination of these satisfying one or more threshold values.

[0038] If an instruction is canceled a threshold number of times in a row, one or more different instructions, e.g., of a different type of operation, can be blocked in a subsequent compute cycle to allow' the canceled instruction to make forward progress. For example, if the instruction B is canceled more than three times in three consecutive compute cycles,Attorney Docket No. 56113-0782WO1 the issue pipe 201 can block the instruction A in a fourth cycle and issue the waiting instruction B instead.

[0039] FIG. 3 shows an example system 300 for obtaining source data for concurrently issued instructions from a PRF and bypass network. The system 300 again shows an instruction A and instruction B. Instead of the selection logic show n in FIG. 2, the system 300 obtains source data from both a PRF 320 and a bypass network 330. The PRF 320 can be similar to the PRF 130. The bypass network 330 can be similar to the bypass network 140. One instruction can be assigned to one or more PRF reads and another instruction can be assigned to one or more bypass networks. In the example of FIG. 3, the instruction A, and corresponding sources RA 302, RB 304, and RC 306, are assigned to three available read ports from the issue pipe 301 into the PRF 320. In some cases, the issue pipe 301 only has three reads into the PRF 320. In some cases, the issue pipe 301 has other numbers of reads into the PRF 320. The instruction B, and corresponding sources RD 308 and RE 310 are assigned to obtain data using one or more bypass netw orks, such as the bypass network 330. The approach of assigning sources to PRF or bypass networks beforehand helps to avoid selection logic and avoid instances of canceling, e.g.. where required sources for instructions outnumber available read ports of an issue pipe into a PRF. Source data obtained by the issue pipe 301 from the PRF 320 and the bypass network 330 can be provided to the execution units 340 and 350 to process the instruction A and instruction B, respectively.

[0040] FIG. 4 show s a system 400 that combines elements of FIG. 2 and FIG. 3. In particular, the system 400 combines selection logic for selecting read ports for one or more instructions with multiple options for obtaining source data for instructions. Similar to previous examples, an issue pipe 401 is issuing two instructions, instructions A and B, simultaneously or at least concurrently. These instructions can require up to three and two sources, respectively. Optional sources for the instruction A are represented by sources RA 402, RB 404, and RC 406. Optional sources for the instruction B are represented by sources RD 408 and RE 410.

[0041] Considering a case where the instruction A requires each of the sources RA 402, RB 404, and RC 406 and the instruction B requires at least one of sources RD 408 and RE 410, as described in regard to FIG. 2, the required sources would outnumber the available read ports into the PRF 420, e.g., the required sources being at least four and the available read ports being shown as three in this example. With the system 200, one ofAttorney Docket No. 56113-0782WO1 the instructions A or B could be canceled by the issue pipe in response to detecting the number of sources outnumbering the available read ports. The system 400. however, reduces the likelihood of canceling instructions by optionally obtaining source data from the bypass network 430. Because the source RD 408 is available in the bypass network 430, the issue pipe 401 can obtain the source data for the source RD 408 from the bypass network 430 and obtain source data for all required sources of the instruction A. If the source RD 408 is the only required source of the instruction B, or any other sources can also be obtained in a bypass network, the issue pipe 401 can continue to issue both the instruction A and the instruction B simultaneously. The issue pipe 401 can provide the obtained source data for the instruction A and the instruction B to an execution unit 440 and 450, respectively.

[0042] FIG. 5 shows an overview of obtaining source data and executing instructions. For example, an issue pipe 502 is shared by a first instruction 504 and a second instruction 506. The issue pipe 502 is shown receiving the source data 508 from the PRF 510. In some cases, the issue pipe 502 receives at least a portion of the source data 508 from a by pass network 512. For example, issue pipe 502 can either read source data from the PRF 510 or bypass the PRF 510 by reading intermediate processing data from the bypass network 512. The bypass networks can allow source data to be read from one or more processing stages in an execution pipeline, e.g., prior to the pipeline writing output data to the PRF 510 or other PRF. Additional aspects of obtaining source data are described in more detail with reference to FIG. 6. The issue pipe 502 can select one or more execution units to execute instructions for which the issue pipe 502 has obtained source data. For example, the issue pipe 502 can select the execution units 520 and 530. The execution units 520 and 530 can use the obtained source data to generate output data according to the first instruction 504 and the second instruction 506. The instructions can each use at least a portion of the source data 508 to generate the output data. For example, the execution unit 520 can process the source data 522 for the first instruction 504 and generate output data 526 and the execution unit 530 can process the source data 534 for the second instruction 532 and generate output data 536.

[0043] FIG. 6 is a detailed view of the issue pipe 502 and the process of obtaining source data. In this example, the source data includes data from both a PRF and by pass network, e.g., the PRF 510 and the bypass network 512. The issue pipe 502 is used to obtain the PRF source data 602 and, optionally, the bypass source data 614, from the PRFAttorney Docket No. 56113-0782WO1510 and the bypass network 512, respectively. Again, the first instruction 504 and the second instruction 506 are shown. The first instruction 504 and the second instruction 506 can be issued by the system 100 using the issue pipe 502.

[0044] The instructions can simultaneously issue as long as one or more conditions are met. The one or more conditions can include a sum of source reads for the first instruction 504 and source reads for the second instruction 506 not exceeding the number of issue pipe read ports 606. In general, the number of read ports can vary depending on implementation and can include any number of read ports. In the example of FIG. 6. the issue pipe read ports 606 include three read ports. If the sum of source reads for the first instruction 504 and source reads for the second instruction 506 exceed three, the issue pipe 502 can cancel the issuing of one of the instructions, such as the second instruction 506.

[0045] The issue pipe 502 can determine source reads and cancel instructions in a number of different ways. For example. MUXs 610 and 612 can be used to determine source reads or cancel instructions, similar to the MUXs discussed in reference to FIG. 2 and FIG. 4. If the MUX 610 receives data from both the first instruction 504 and the second instruction 506 indicating that both instructions require access to a given read port, the MUX 610 can provide a signal configured to cancel the second instruction 506.

[0046] The issue pipe 502 can be used to determine source reads or cancel instructions, e.g.. by reading data corresponding to one or more instructions in an RSV, such as the RSV 110. For example, the issue pipe 502 can obtain one or more parameters from the RSV, such as the RSV 110. The one or more parameters can include data that identifies one or more instructions. The issue pipe 502 can obtain data from the RSV when issuing instructions. The data that identifies one or more instructions can indicate a number of reads required by one or more instructions. Based on obtained parameters, the issue pipe 502 can cancel or proceed to obtain source data for the one or more issued instructions.

[0047] In general, if the first instruction 504 only needs one source read, it can use read port 606a. If the first instruction 504 needs two reads, it can use read ports 606a and 606b. If the first instruction 504 needs three reads, it can use read ports 606a, 606b, and 606c. In the last case, the second instruction 506 can be canceled, e.g.. via a signal provided by the MUX 610 or the MUX 612. If the second instruction 506 only needs oneAttorney Docket No. 56113-0782WO1 source read, it can use read port 606c. If the second instruction 506 needs two reads, it can use read ports 606c and 606b. The first instruction 504 and the second instruction 506 can provide signals to the MUXs 610 and 612 indicating whether or not the instruction requires data from a give read port, e.g., indicating how many source reads each instruction requires. The instructions can provide signals configured to obtain data from one or more registers of the PRF.

[0048] In some cases, the issue pipe 502 is configured to be used with a specific set of one or more types of operations. For example, the issue pipe 502 can be configured to be used with a multicycle (MX) operation and a store data (STD) operation. The first instruction 504 can be an MX operation and the second instruction 506 can be a STD operation. An MX operation can have a maximum of three sources while a STD operation can have a maximum of two sources. The STD operation can read source data, e.g., from the PRF. and send the data to a load store unit to write to memory. The STD operation may not require any ALU logic and hence it can be issued simultaneously along with another operation on the same pipe, such as an MX operation. The MX operation can be any operation that requires one or more compute cycles to complete.

[0049] The RSV 110 can select the oldest ready operations for the issue pipe 502 corresponding to the specific set of operations the issue pipe 502 is configured to be used with. For example, if the issue pipe 502 is configured to be used with instructions representing a MX and STD operation, the RSV 110 can select the oldest instructions with matching operations every cycle. The issue pipe 502 can be used to issue the matching instructions. If the total number of sources across both the issued instructions exceed three, then the STD operation’s issue can be canceled, e.g., unless one or more sources can be obtained from a non-PRF source such as the bypass network 512.

[0050] If an instruction is canceled a threshold number of times in a row. one or more different instructions, e.g., of a different type of operation, can be blocked in a subsequent compute cycle to allow the canceled instruction to make forward progress. For example, if an instruction including the STD operation is canceled more than three times in three consecutive compute cycles, the issue pipe 502 can block the MX operation instruction in a fourth cycle and issue the waiting STD operation instruction instead.

[0051] The bypass network 512 can be used to limit the cases of canceling an instruction. For example, a sum of reads required for instructions that share the issue pipeAttorney Docket No. 56113-0782WO1502 may exceed a number of PRF reads supported by the issue pipe 502. But if at least one of the instructions can obtain source data from a non-PRF source, the instructions can still be issued simultaneously because obtaining source data from non-PRF sources may not count against the limit of PRF reads supported by the issue pipe 502. When using bypass networks, the issue pipe 502 can determine whether or not the number of reads of the instructions minus the number of reads available in bypass network 512 exceeds the number of read ports supported by the issue pipe 502. Based on this determination, the issue pipe 502 can cancel an instruction if the number of reads required from the PRF, and not including reads that can be obtained from the bypass network 512, exceeds the number of read ports supported by the issue pipe 502.

[0052] In some cases, a system can check an RSV to determine whether or not an instruction sharing the issue pipe 502 can obtain data from a bypass network. In some cases, the system only checks in cases where the reads of instructions sharing the issue pipe 502 exceed the maximum supported reads. In some cases, the system checks at every issue time and, e.g., uses bypass networks over using PRF reads when bypass data is available.

[0053] Information indicating whether or not source data can be obtained from the bypass network 512 can be stored in an RSV, such as the RSV 110. Information can be stored as a bit vector in the RSV. When a producer instruction wakes up a dependent instruction, the system 100 can initialize a bypass control bit vector whose width is equal to the number of cycles supported in the bypass network 512. The bit vector can be shifted one bit every cycle. When a corresponding operation issues, if a system determines that the vector has a bit set, it means data for the operation is available in the bypass network 512 and can be obtained from the specified cycle. The issue pipe 502 can compare a maximum available number of the issue pipe read ports 606 with a value indicating the number of reads required by the first instruction 504 and the second instruction 506 but not counting reads that can be obtained from the bypass network 512. Thus, the issue pipe 502 can determine the maximum available number of the issue pipe read ports 606, values indicating the number of reads required by instructions sharing the issue pipe 502, values indicating the number of PRF reads required by the instructions, or values indicating the number of reads available in the bypass network 512 for the instructions. Using data from the bypass network 512 can improve the chances of instructions sharing the issue pipe 502.Attorney Docket No. 56113-0782WO1

[0054] For example, the system 100, e.g., via the issue pipe 502, can check if an RSV storing the first instruction 504 and the second instruction 506 includes a bypass value for either the first instruction 504 or the second instruction 506. The bypass value can be used by the system 100 to obtain bypass source data 614, e.g., from one or more intermediate stages in an execution pipeline. The bypass value can identify a particular bypass stage within an execution pipeline of a producer instruction. The bypass value can include a bit vector whose width is equal to a number of possible bypass stages of a given producer execution pipeline. The bit vector can be shifted each compute cycle such that the system 100 can determine whether a produced source value is available in an intermediate stage or not. By using the bypass network 512, the improvements provided by the sharing of the issue pipe 502 can be enhanced because the bypass network 512 allows the first instruction 504 and the second instruction 506 to more likely be issued simultaneously.

[0055] When data is not available in the bypass network 512, or is partially available in the bypass network 512, the issue pipe 502 can obtain source data from the PRF 510. In cases where there is no bypass network 512, all source data can be obtained from the PRF 510.

[0056] The PRF source data 602 is obtained using issue pipe read ports 606 and PRF read ports 608. Each of the issue pipe read ports 606 are assigned to obtain source data from one or more of the PRF read ports 608 according to the data required by the first instruction 504 and the second instruction 506. The MUXs 610 and 612 perform selection logic to provide read access into the PRF 510 for either the first instruction 504 or the second instruction 506 for at least one of the issue pipe read ports 606. The selection logic can include determining whether or not an instruction requires a source read or not. The read port 606a can be a dedicated port for the first instruction 504. In some cases, no dedicated ports are used but all ports have a MUX to select one or another instruction. The read ports 606b and 606c can be shared between the first instruction 504 and the second instruction 506. Where existing techniques would require five read ports into the PRF 510, the described techniques reduce this number to three by sharing two read ports.

[0057] In general, any type of instruction or number of sources can share an issue pipe in accordance with the techniques described in this specification. In the example of FIG. 6, the issue pipe 502 includes three ports in the issue pipe read ports 606. In someAttorney Docket No. 56113-0782WO1 cases, other numbers of read ports are used, such as five, ten, or other numbers. Although two instructions are shown, in some cases, additional instructions can share an issue pipe, such as the issue pipe 502. An issue pipe can include any number of read ports for sharing. If at least one of the instructions sharing the issue pipe use less than a maximum number of read ports, the issue pipe can obtain data for the instructions simultaneously.

[0058] FIG. 7 is a flowchart of an example process 700 for sharing an issue pipe. For convenience, the process 700 will be described as being performed by a system of one or more computers, located in one or more locations, and programmed appropriately in accordance with this specification. For example, a system described in this specification, such as the system 100, 200, 300, or 400, appropriately programmed, can perform the process 700.

[0059] In some cases, the process 700 is performed by a processor that includes a physical register file (PRF) comprising a plurality of registers; a plurality of execution units; and a reservation station (RSV) comprising a plurality of issue pipes, wherein each issue pipe comprises circuitry configured to obtain one or more source data elements for an instruction and to issue the instruction to a respective execution unit of the plurality of execution units using the obtained one or more source data elements, wherein an issue pipe of the plurality’ of issue pipes has N read ports into the physical register file.

[0060] The process 700 includes concurrently issuing a plurality of instructions to different execution units using selection logic to select which source data elements to obtain from N read ports into a physical register file (702). For example, as shown in FIG. 2, FIG. 4, and FIG. 6, selection logic can be used to select which source data elements to obtain from a PRF, such as the PRF 510. Selection logic can include one or more MUXs. An issue pipe can concurrently issuing instructions by providing source data to one or more execution units, e.g., the execution units 230 and 240.

[0061] In some cases, the process 700 includes determining (i) a number of PRF reads of a first instruction and (ii) a number of PRF reads of a second instruction (704). For example, an issue pipe, such as the issue pipe 502 can determine a number of PRF reads for the first instruction 504 and the second instruction 506. The issue pipe can use an RSV or obtain data from the instructions. Such as signals from instructions indicate one or more Boolean values, indicating whether or not a source read is required, or a valueAttorney Docket No. 56113-0782WO1 indicating where in a PRF data is to be read, such as a value indicating a specific register of the PRF 510 to read source data from.

[0062] In some cases, the process 700 includes obtaining source data for the first instruction, or a combination of the first instruction and the second instruction, based on the determination (706). For example, an issue pipe can obtain data from a source data element, such as the PRF 510, the bypass network 512, or both the PRF 510 and the bypass network 512.

[0063] FIG. 8 is a flowchart of an example process 800 for using a bypass network to increase instances of sharing an issue pipe. For convenience, the process 800 will be described as being performed by a system of one or more computers, located in one or more locations, and programmed appropriately in accordance with this specification. For example, a system described in this specification, such as the system 100, 200, 300, or 400, appropriately programmed, can perform the process 700.

[0064] In some cases, the process 800 is performed by a processor comprising a PRF comprising a plurality of physical registers; a plurality of execution units; and an RSV comprising a plurality of issue pipes, wherein each issue pipe comprises circuitry configured to obtain source data for an instruction and to issue the instruction to a respective execution unit of the plurality of execution units using the obtained source data, and wherein a first issue pipe of the plurality of issue pipes has N read ports into the PRF.

[0065] The process 800 includes concurrently issuing a plurality of instructions having more than N total sources to different respective execution units by obtaining one or more source data elements from a PRF and one or more source data elements from a bypass network (802). For example, as shown in FIG. 3, the issue pipe 301 issues instruction A and B concurrently using the execution units 340 and 350.

[0066] In some cases, the process 800 includes determining (i) a number of PRF reads of a first instruction and a second instruction and (ii) an availability of source data for the first instruction or the second instruction in the bypass network (804). For example, the issue pipe 502 can determine the number of PRF reads required by the first instruction 504 and the second instruction 506. The issue pipe 502 can determine if the first instruction 504, the second instruction 506, or both the first instruction 504 and the second instruction 506 require source data that will be available in a bypass network, suchAttorney Docket No. 56113-0782WO1 as the bypass network 512. The issue pipe 502 can determine if source data is available in the bypass network 512. e g., by checking the RSV 110 for a bypass value indicating whether or not source data for a given instruction is available. The bypass value can indicate which execution stage, of one or more execution stages, the source data can be obtained from. In some cases, a bit vector is used and the issue pipe 502 can determine, based on determining whether or not a bit vector is set or not, an availability of source data for one or more instructions.

[0067] In some cases, the process 800 includes obtaining source data for the first instruction, or a combination of the first instruction and the second instruction, based on the determination (806). For example, the issue pipe 502 can obtain the bypass source data 614 from the bypass network 512. The issue pipe 502 can obtain the bypass source data 614, e.g., if the issue pipe 502 determines that an RSV storing the first instruction 504 and the second instruction 506 includes a bypass value indicating that source data for one or more of the instructions is available in the bypass network 512. The issue pipe 502 can obtain at least some other elements of source data from a PRF, such as the PRF 510, or it can exclusively obtain source data from the bypass network 512.

[0068] The subject matter and the actions and operations described in this specification can be implemented in digital electronic circuitry, in tangibly -embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The subject matter and the actions and operations described in this specification can be implemented as or in one or more computer programs, e g., one or more modules of computer program instructions, encoded on a computer program earner, for execution by, or to control the operation of, data processing apparatus. The carrier can be a tangible non-transitory computer storage medium. Alternatively or in addition, the carrier can be an artificially-generated propagated signal, e g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be or be part of a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. A computer storage medium is not a propagated signal.Attorney Docket No. 56113-0782WO1

[0069] The term “data processing apparatus” encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. Data processing apparatus can include special-purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit) , or a GPU (graphics processing unit). The apparatus can also include, in addition to hardware, code that creates an execution environment for computer programs, e.g.. code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0070] A computer program can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and it can be deployed in any form, including as a stand-alone program, e.g., as an app. or as a module, component, engine, subroutine, or other unit suitable for executing in a computing environment, which environment may include one or more computers interconnected by a data communication network in one or more locations.

[0071] A computer program may, but need not, correspond to a file in a file system. A computer program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub-programs, or portions of code.

[0072] The processes and logic flows described in this specification can be performed by one or more computers executing one or more computer programs to perform operations by operating on input data and generating output. The processes and logic flows can also be performed by special-purpose logic circuitry, e.g., an FPGA, an ASIC, or a GPU, or by a combination of special-purpose logic circuitry and one or more programmed computers.

[0073] Computers suitable for the execution of a computer program can be based on general or special-purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a central processing unit for executing instructions and one or moreAttorney Docket No. 56113-0782WO1 memory devices for storing instructions and data. The central processing unit and the memory can be supplemented by, or incorporated in, special-purpose logic circuitry.

[0074] Generally, a computer will also include, or be operatively coupled to, one or more mass storage devices, and be configured to receive data from or transfer data to the mass storage devices. The mass storage devices can be, for example, magnetic, magneto-optical, or optical disks, or solid state drives. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

[0075] To provide for interaction with a user, the subject matter described in this specification can be implemented on one or more computers having, or configured to communicate with, a display device, e g., a LCD (liquid crystal display) monitor, or a virtual-reality (VR) or augmented-reality (AR) display, for displaying information to the user, and an input device by which the user can provide input to the computer, e.g., a keyboard and a pointing device, e.g., a mouse, a trackball or touchpad. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback and responses provided to the user can be any form of sensory feedback, e.g., visual, auditory, speech, or tactile feedback or responses; and input from the user can be received in any form, including acoustic, speech, tactile, or eye tracking input, including touch motion or gestures, or kinetic motion or gestures or orientation motion or gestures. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user’s device in response to requests received from the web browser, or by interacting with an app running on a user device, e.g., a smartphone or electronic tablet. Also, a computer can interact with a user by sending text messages or other forms of message to a personal device, e.g., a smartphone that is running a messaging application, and receiving responsive messages from the user in return.

[0076] This specification uses the term "‘configured to” in connection with systems, apparatus, and computer program components. That a system of one or more computers is configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. That one or more computerAttorney Docket No. 56113-0782WO1 programs is configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by data processing apparatus, cause the apparatus to perform the operations or actions. That special-purpose logic circuitry is configured to perform particular operations or actions means that the circuitry has electronic logic that performs the operations or actions.

[0077] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what is being claimed, which is defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claim may be directed to a subcombination or variation of a subcombination.

[0078] Similarly, while operations are depicted in the drawings and recited in the claims in a particular order, this by itself should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0079] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.Attorney Docket No. 56113-0782WO1Aspects and embodiments of the disclosed subject matter may be as set out in the following numbered examples. The following examples may be combined in any suitable way. For example, while examples 1 to 11 relate to a processor, the features of examples 1 to 11 may be included in method examples 12 to 16. Furthermore, the features of examples 1 to 11 may be combined with the features of examples 17 to 20.Example 1. A processor comprising: a physical register file (PRF) comprising a plurality of registers; a plurality of execution units; and a reservation station (RSV) comprising a plurality of issue pipes, wherein each issue pipe comprises circuitry configured to obtain one or more source data elements for an instruction and to issue the instruction to a respective execution unit of the plurality7of execution units using the obtained one or more source data elements, wherein an issue pipe of the plurality of issue pipes has N read ports into the PRF and is configured to concurrently issue a plurality of instructions to different respective execution units by using selection logic to select which source data elements to obtain from the N read ports into the PRF.Example 2. The processor of example 1, wherein concurrently issuing the plurality of instructions comprises concurrently issuing the plurality7of instructions if and only if a total number of sources for the plurality of instructions is equal to or less than N.Example 3. The processor of any one of examples 1-2, wherein one of the read ports is dedicated to a first instruction type.Example 4. The processor of any one of examples 1-3, wherein one or more other read ports are shared between the first instruction type and a second instruction type.Example 5. The processor of any one of examples 1-4, wherein the issue pipe is configured to: determine (i) a number of PRF reads of a first instruction and (ii) a number of PRF reads of a second instruction; and obtain source data for the first instruction, or a combination of the first instruction and the second instruction, based on the determination.Attorney Docket No. 56113-0782WO1Example 6. The processor of any one of examples 1-5, wherein the selection logic is configured to select a read of a first instruction when a count of the first instruction PRF reads satisfies a threshold.Example 7. The processor of any one of examples 1-6. wherein the selection logic is configured to select a read of a second instruction when a count of the first instruction PRF reads satisfies a first threshold and a count of a second instruction PRF reads satisfies a second threshold.Example 8. The processor of any one of examples 1-7, wherein the issue pipe is configured to: determine (i) a number of PRF reads of a first instruction and (ii) a number of PRF reads of a second instruction, wherein determining (i) the number of PRF reads of the first instruction and (ii) the number of PRF reads of the second instruction comprises: obtaining one or more parameters of the first instruction and the second instruction stored in the RSV, wherein the RSV stores a set of one or more parameters for the first instruction and a set of one or more parameters for the second instruction.Example 9. The processor of any one of examples 1-8, wherein the issue pipe is configured to: issue a first instruction and cancel a second instruction; obtain source data elements for the first instruction in a first compute cycle; and obtain source data elements for the second instruction in a second compute cycle subsequent to the first compute cycle.Example 10. The processor of any one of examples 1-9, wherein the N read ports into the PRF number three.Example 11. The processor of any one of examples 1-10, wherein the plurality of instructions includes a multicycle (MX) operation and a store data (STD) operation.Example 12. A method performed by a processor comprising: a physical register file (PRF) comprising a plurality of registers; a plurality of execution units; andAttorney Docket No. 56113-0782WO1 a reservation station (RSV) comprising a plurality of issue pipes, wherein each issue pipe comprises circuitry configured to obtain one or more source data elements for an instruction and to issue the instruction to a respective execution unit of the plurality of execution units using the obtained one or more source data elements, wherein an issue pipe of the plurality' of issue pipes has N read ports into the PRF, the method comprising: concurrently issuing a plurality of instructions to different execution units using selection logic to select which source data elements to obtain from the N read ports into the PRF.Example 13. The method of example 12, further comprising: determining (i) a number of PRF reads of a first instruction and (ii) a number of PRF reads of a second instruction; and obtaining source data for the first instruction, or a combination of the first instruction and the second instruction, based on the determination.Example 14. The method of any one of examples 12-13, wherein determining (i) the number of PRF reads of the first instruction and (ii) the number of PRF reads of the second instruction comprises: obtaining one or more parameters of the first instruction and the second instruction stored in the RSV, wherein the RSV stores a set of one or more parameters for the first instruction and a set of one or more parameters for the second instruction.Example 15. The method of any one of examples 12-14, wherein determining (i) the number of PRF reads of the first instruction and (ii) the number of PRF reads of the second instruction comprises: obtaining signals from the first instruction and the second instruction; and determining, using the signals, (i) the number of PRF reads of the first instruction and (ii) the number of PRF reads of the second instruction.Example 16. The method of any one of examples 12-15, wherein the plurality of instructions includes a multicycle (MX) operation and a store data (STD) operation.Example 17. A processor comprising: a physical register file (PRF) comprising a plurality of physical registers;Attorney Docket No. 56113-0782WO1 a plurality of execution units; and a reservation station (RSV) comprising a plurality7of issue pipes, wherein each issue pipe comprises circuitry configured to obtain source data for an instruction and to issue the instruction to a respective execution unit of the plurality of execution units using the obtained source data, wherein a first issue pipe of the plurality of issue pipes has N read ports into the PRF and is configured to concurrently issue a plurality of instructions having more than N total sources to different respective execution units by obtaining one or more source data elements from the PRF and one or more source data elements from a bypass network.Example 18. The processor of example 17, wherein obtaining the one or more source data elements from the bypass network comprises obtaining the one or more source data elements after the one or more source data elements are produced by one or more of the plurality of execution units and before the one or more source data elements are written back to the PRF.Example 19. The processor of any one of examples 17-18, wherein the first issue pipe is configured to concurrently issue the plurality7of instructions by using selection logic to select which source data elements to obtain from the N read ports into the PRF.Example 20. The processor of any one of examples 17-19, wherein the selection logic is configured to select a read of a first instruction when a count of the first instruction PRF reads satisfies a threshold.

[0080] What is claimed is:

Claims

Attorney Docket No. 56113-0782WO1CLAIMS1. A processor comprising: a physical register file (PRF) comprising a plurality of registers; a plurality of execution units; and a reservation station (RSV) comprising a plurality of issue pipes, wherein each issue pipe comprises circuitry configured to obtain one or more source data elements for an instruction and to issue the instruction to a respective execution unit of the plurality of execution units using the obtained one or more source data elements, wherein an issue pipe of the plurality of issue pipes has N read ports into the PRF and is configured to concurrently issue a plurality of instructions to different respective execution units by using selection logic to select which source data elements to obtain from the N read ports into the PRF.

2. The processor of claim 1. wherein concurrently issuing the plurality of instructions comprises concurrently issuing the plurality of instructions if and only if a total number of sources for the plurality of instructions is equal to or less than N.

3. The processor of any one of claims 1-2, wherein one of the read ports is dedicated to a first instruction type.

4. The processor of any one of claims 1-3, wherein one or more other read ports are shared between the first instruction type and a second instruction type.

5. The processor of any one of claims 1-4, wherein the issue pipe is configured to: determine (i) a number of PRF reads of a first instruction and (ii) a number of PRF reads of a second instruction; and obtain source data for the first instruction, or a combination of the first instruction and the second instruction, based on the determination.

6. The processor of any one of claims 1-5, wherein the selection logic is configured to select a read of a first instruction when a count of the first instruction PRF reads satisfies a threshold.Atorney Docket No. 56113-0782WO17. The processor of any one of claims 1-6, wherein the selection logic is configured to select a read of a second instruction when a count of the first instruction PRF reads satisfies a first threshold and a count of a second instruction PRF reads satisfies a second threshold.

8. The processor of any one of claims 1-7, wherein the issue pipe is configured to: determine (i) a number of PRF reads of a first instruction and (ii) a number of PRF reads of a second instruction, wherein determining (i) the number of PRF reads of the first instruction and (ii) the number of PRF reads of the second instruction comprises: obtaining one or more parameters of the first instruction and the second instruction stored in the RSV, wherein the RSV stores a set of one or more parameters for the first instruction and a set of one or more parameters for the second instruction.

9. The processor of any one of claims 1-8, wherein the issue pipe is configured to: issue a first instruction and cancel a second instruction; obtain source data elements for the first instruction in a first compute cycle: and obtain source data elements for the second instruction in a second compute cycle subsequent to the first compute cycle.

10. The processor of any one of claims 1-9, wherein the N read ports into the PRF number three.

11. The processor of any one of claims 1-10, wherein the plurality of instructions includes a multicycle (MX) operation and a store data (STD) operation.

12. A method performed by a processor comprising: a physical register file (PRF) comprising a plurality of registers: a plurality of execution units; and a reservation station (RSV) comprising a plurality of issue pipes, wherein each issue pipe comprises circuitry configured to obtain one or more source data elements for an instruction and to issue the instruction to a respective execution unit of the plurality ofAttorney Docket No. 56113-0782WO1 execution units using the obtained one or more source data elements, wherein an issue pipe of the plurality of issue pipes has N read ports into the PRF, the method comprising: concurrently issuing a plurality of instructions to different execution units using selection logic to select which source data elements to obtain from the N read ports into the PRF.

13. The method of claim 12, further comprising: determining (i) a number of PRF reads of a first instruction and (ii) a number of PRF reads of a second instruction; and obtaining source data for the first instruction, or a combination of the first instruction and the second instruction, based on the determination.

14. The method of any one of claims 12-13, wherein determining (i) the number of PRF reads of the first instruction and (ii) the number of PRF reads of the second instruction comprises: obtaining one or more parameters of the first instruction and the second instruction stored in the RSV, wherein the RSV stores a set of one or more parameters for the first instruction and a set of one or more parameters for the second instruction.

15. The method of any one of claims 12-14, wherein determining (i) the number of PRF reads of the first instruction and (ii) the number of PRF reads of the second instruction comprises: obtaining signals from the first instruction and the second instruction; and determining, using the signals, (i) the number of PRF reads of the first instruction and (ii) the number of PRF reads of the second instruction.

16. The method of any one of claims 12-15, wherein the plurality of instructions includes a multicycle (MX) operation and a store data (STD) operation.

17. A processor comprising: a physical register file (PRF) comprising a plurality of physical registers; a plurality of execution units; andAttorney Docket No. 56113-0782WO1 a reservation station (RSV) comprising a plurality of issue pipes, wherein each issue pipe comprises circuitry configured to obtain source data for an instruction and to issue the instruction to a respective execution unit of the plurality of execution units using the obtained source data, wherein a first issue pipe of the plurality of issue pipes has N read ports into the PRF and is configured to concurrently issue a plurality of instructions having more than N total sources to different respective execution units by obtaining one or more source data elements from the PRF and one or more source data elements from a bypass network.

18. The processor of claim 17, wherein obtaining the one or more source data elements from the bypass network comprises obtaining the one or more source data elements after the one or more source data elements are produced by one or more of the plurality of execution units and before the one or more source data elements are written back to the PRF.

19. The processor of any one of claims 17-18. wherein the first issue pipe is configured to concurrently issue the plurality of instructions by using selection logic to select which source data elements to obtain from the N read ports into the PRF.

20. The processor of any one of claims 17-19, wherein the selection logic is configured to select a read of a first instruction when a count of the first instruction PRF reads satisfies a threshold.

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