Display device, active matrix substrate, and production method for display device

Abstract

A display device (1) includes a display area (DA) that includes a plurality of pixel electrodes, a non-display area (NDA) that is outside the display area (DA), a terminal area (TER) that is in the non-display area (NDA) and includes a plurality of first terminals (TE1–TE7), and one or more types of a first semiconductor layer (4, 24) that are in at least one of the display area (DA) and the non-display area (NDA) outside the terminal area (TER). The terminal area (TER) includes a second semiconductor layer (34) that is formed from the same material as at least one of the types of the first semiconductor layer (4, 24). The first semiconductor layer (4, 24) and the second semiconductor layer (34) are formed as the same layer.

Description

Display device, active matrix substrate, and method for manufacturing a display device

[0001] The present disclosure relates to a display device, an active matrix substrate, and a method for manufacturing a display device.

[0002] In the field of display devices such as liquid crystal display devices and display devices equipped with, for example, an OLED (Organic Light Emitting Diode) or a QLED (Quantum dot Light Emitting Diode) as a light-emitting element, when a defect occurs after the completion of the display device, analysis is often performed using the display device to investigate the cause of the defect.

[0003] For example, Patent Document 1 describes providing an analysis element for inspecting the deterioration of a light-emitting layer in a frame area, which is a non-display area of a display device.

[0004] International Publication WO2020 / 161774 A1

[0005] However, Patent Document 1 only describes providing an analysis element for inspecting the deterioration of a light-emitting layer in the frame area of a display device, and does not describe providing an analysis element for inspecting the deterioration of a light-emitting layer by utilizing a terminal area provided in the frame area of the display device, for example, where a plurality of terminals are formed. Therefore, in the case of a display device provided with the analysis element described in Patent Document 1, it is necessary to separately secure a space for providing the analysis element in the non-display area, and there is a problem that it is impossible to realize a narrow frame with a narrower non-display area.

[0006] An aspect of the present disclosure aims to provide a display device, an active matrix substrate, and a method for manufacturing a display device that can more efficiently and accurately perform analysis for investigating the cause of a defect and suppress an increase in the non-display area.

[0007] To solve the aforementioned problems, the display device of this disclosure includes: a display area provided with a plurality of pixel electrodes; a non-display area provided outside the display area; a terminal area provided with a plurality of first terminals in the non-display area; and one or more first semiconductor layers provided in at least one of the non-display area other than the terminal area and the display area, wherein the terminal area is provided with a second semiconductor layer made of the same material as at least one of the first semiconductor layers, and the first semiconductor layer and the second semiconductor layer are formed as the same layer.

[0008] To solve the above-mentioned problems, the present disclosure provides a method for manufacturing a display device, comprising: a display area provided with a plurality of pixel electrodes; a non-display area provided outside the display area; and a terminal area in the non-display area provided with a plurality of terminals, the method comprising forming a first semiconductor layer provided in at least one of the non-display area other than the terminal area and the display area, and a second semiconductor layer provided in the terminal area, using the same material and the same process.

[0009] To solve the above problems, the active matrix substrate of the present disclosure includes: a first region provided with a plurality of electrodes; a second region provided outside the first region; a terminal region in the second region provided with a plurality of first terminals; and one or more first semiconductor layers provided in at least one of the second region and the first region other than the terminal region, wherein the terminal region is provided with a second semiconductor layer made of the same material as at least one of the first semiconductor layers, and the first semiconductor layer and the second semiconductor layer are formed as the same layer.

[0010] According to one aspect of this disclosure, it is possible to provide a display device, an active matrix substrate, and a method for manufacturing a display device that enable more efficient and accurate analysis for investigating the cause of malfunctions, while suppressing an increase in the non-display area.

[0011] Figure 1 is a plan view showing the schematic configuration of the display device of Embodiment 1. Figure 1 is a cross-sectional view showing the schematic configuration of the display area of ​​the display device shown in Figure 1. Figure 1 is a cross-sectional view showing the schematic configuration of the drive circuit formation area of ​​the display device shown in Figure 1. Figure 1 is a cross-sectional view showing the schematic configuration of the terminal area of ​​the display device shown in Figure 1. Figure 1 is a diagram showing an example of the process of forming a first terminal provided in the terminal area of ​​the display device shown in Figure 1. Figure 1 is a diagram showing an example of the process of forming another first terminal that can be provided in the terminal area of ​​the display device shown in Figure 1. Figure 1 is a diagram showing the case where the second semiconductor layer is exposed at the first terminal shown in Figure 4 provided in the terminal area of ​​the display device shown in Figure 1. Figure 1 is a diagram showing the case where a circuit board is mounted on the display device shown in Figure 1. Figure 1 is a diagram showing a part of the manufacturing process of the display device shown in Figure 1. Figure 1 is a diagram showing the remaining part of the manufacturing process of the display device shown in Figure 1. Figure 1 is a diagram showing an example of the process of exposing the second semiconductor layer at the first terminal provided in the terminal area of ​​the display device shown in Figure 1. Figure 1 is a diagram showing the case where a circuit board is mounted on the display device of Embodiment 2. Figure 12 is a cross-sectional view showing the schematic configuration of the display area of ​​the display device shown in Figure 12.

[0012] The embodiments of this disclosure will be described below with reference to Figures 1 to 13. For the sake of convenience, in the following, components having the same function as those described in a particular embodiment will be denoted by the same reference numerals, and their descriptions may be omitted.

[0013] [Embodiment 1] Figure 1 is a plan view showing the schematic configuration of the display device 1 of Embodiment 1. Figure 2 is a cross-sectional view showing the schematic configuration of the display area DA of the display device 1 shown in Figure 1. Figure 3 is a cross-sectional view showing the schematic configuration of the drive circuit formation area DRU2 of the display device 1 shown in Figure 1. Figure 4 is a cross-sectional view showing the schematic configuration of the terminal area TER of the display device 1 shown in Figure 1.

[0014] As shown in Figure 1, the display device 1 includes a display area DA with a plurality of pixel electrodes, a non-display area NDA located outside the display area DA, and a terminal area TER in the non-display area NDA with a plurality of first terminals TE1 to TE7. The display area DA has a plurality of pixels PIX arranged in a row that contribute to the display of an image. The non-display area NDA is the area surrounding the display area DA. Each of the plurality of pixels PIX includes, for example, a red subpixel RSP that emits red light, a green subpixel GSP that emits green light, and a blue subpixel BSP that emits blue light. Pixel electrodes are provided for each color subpixel. Furthermore, alignment marks ALM1 and ALM2 may be provided in the non-display area NDA other than the terminal area TER.

[0015] Figure 2 shows a cross-sectional view of a red subpixel RSP that emits red light within the display area DA. Although not shown, the cross-sectional views of the green subpixel GSP that emits green light and the blue subpixel BSP that emits blue light are similar to the cross-sectional view of the red subpixel RSP that emits red light shown in Figure 2. In this embodiment, as shown in Figure 2, a first semiconductor layer 4 is provided in the display area DA of the display device 1, and as shown in Figure 3, a first semiconductor layer 24 is provided in the non-display area NDA other than the terminal area TER of the display device 1, for example, the drive circuit formation area DRU2, and as shown in Figure 4, a second semiconductor layer 34 is provided in the terminal area TER of the display device 1.

[0016] The first semiconductor layer 4 shown in Figure 2 has three types of first semiconductor layers, as it has high-concentration doped regions 4H1 and 4H2, low-concentration doped regions 4L1 and 4L2, and an undoped region 4O. The first semiconductor layer 24 shown in Figure 3 has three types of first semiconductor layers, as it has high-concentration doped regions 24H1 and 24H2, low-concentration doped regions 24L1 and 24L2, and an undoped region 24O. The second semiconductor layer 34 shown in Figure 4 has three types of second semiconductor layers, as it has high-concentration doped regions 34H1 and 34H2, low-concentration doped regions 34L1, 34L2, 34L3, and 34L4, and undoped regions 34O1, 34O2, and 34O3. The first semiconductor layer refers to a semiconductor layer provided in the non-display area NDA or display area DA other than the terminal area TER, and the second semiconductor layer refers to a semiconductor layer provided in the terminal area TER.

[0017] The highly doped regions 4H1 and 4H2 of the first semiconductor layer 4 shown in Figure 2, the highly doped regions 24H1 and 24H2 of the first semiconductor layer 24 shown in Figure 3, and the highly doped regions 34H1 and 34H2 of the second semiconductor layer 34 shown in Figure 4 are all made of the same material. Furthermore, the low-doped regions 4L1 and 4L2 of the first semiconductor layer 4 shown in Figure 2, the low-doped regions 24L1 and 24L2 of the first semiconductor layer 24 shown in Figure 3, and the low-doped regions 34L1, 34L2, 34L3, and 34L4 of the second semiconductor layer 34 shown in Figure 4 are all made of the same material. In addition, the undoped region 4O of the first semiconductor layer 4 shown in Figure 2, the undoped region 24O of the first semiconductor layer 24 shown in Figure 3, and the undoped region 34O of the second semiconductor layer 34 shown in Figure 4 are all made of the same material.

[0018] In this embodiment, the display device 1 is provided with three types of first semiconductor layers in the non-display area NDA and display area DA other than the terminal area TER, and the terminal area TER is provided with three types of second semiconductor layers made of the same material as each of the three types of first semiconductor layers. However, the embodiment is not limited to this. For example, the terminal area TER may be provided with second semiconductor layers made of the same material as some of the three types of first semiconductor layers. Alternatively, the terminal area TER of the display device 1 may be provided with second semiconductor layers made of the same material as one or more types of first semiconductor layers provided in at least one of the non-display area NDA and display area DA other than the terminal area TER. Furthermore, the terminal area TER of the display device 1 may be provided with second semiconductor layers made of the same material as one or more types of first semiconductor layers provided in the display area DA. Note that the first semiconductor layers 4 and 24 and the second semiconductor layer 34 are formed using the same material and the same process, as will be described later, and are therefore formed as the same layer.

[0019] As shown in Figures 2 and 3, the first semiconductor layer 4 and the first semiconductor layer 24 are each provided on a barrier layer 3 provided on the substrate 2. A second deflection plate 20b is provided on the side of the substrate 2 opposite to the side on which the barrier layer 3 is provided.

[0020] As shown in Figure 2, a laminated film is formed on the first semiconductor layer 4, in which a first insulating film 5, a first metal layer 6a, a second insulating film 8, second metal layers 9a and 9b, a planarization film 10, a first passivation film 11, a second passivation film 13, a conductive layer 14, a third passivation film 15, a conductive layer 16a, an alignment film 17, a liquid crystal layer 18, a color filter substrate 19, a first deflection plate 20a, a transparent adhesive 21, and a functional film 22 are stacked in this order. The first transistor TR1 includes a first semiconductor layer 4. The second metal layer 9a, which is the source electrode, is in contact with the highly doped region 4H1 of the first semiconductor layer 4 via a first contact hole CO1 formed in the first insulating film 5 and the second insulating film 8. The second metal layer 9b, which is the drain electrode, is in contact with the highly doped region 4H2 of the first semiconductor layer 4 via a second contact hole CO2 formed in the first insulating film 5 and the second insulating film 8. The first metal layer 6a is the gate electrode. The second metal layer 9c is electrically connected to the second metal layer 9b, and the conductive layer 14 is electrically connected to the conductive layer 16a. The conductive layer 16a is in contact with the second metal layer 9c via a third contact hole CO3 formed in the planarization film 10, the first passivation film 11, the second passivation film 13, and the third passivation film 15. The conductive layer 14 and the conductive layer 16a constitute the pixel electrode. The third metal layer 12a forms an auxiliary capacitance with the conductive layer 14.

[0021] As shown in Figure 3, a laminated film is formed on the first semiconductor layer 24, in which a first insulating film 5, a first metal layer 6b, a second insulating film 8, second metal layers 9d and 9e, a planarization film 10, a first passivation film 11, a second passivation film 13, a third passivation film 15, a liquid crystal layer 18, a color filter substrate 19, a first deflection plate 20a, a transparent adhesive 21, and a functional film 22 are stacked in this order. The second transistor TR2 includes a first semiconductor layer 24. The second metal layer 9d, which is the source electrode, is in contact with the highly doped region 24H1 of the first semiconductor layer 24 via a fourth contact hole CO4 formed in the first insulating film 5 and the second insulating film 8. The second metal layer 9e, which is the drain electrode, is in contact with the highly doped region 24H2 of the first semiconductor layer 24 via a fifth contact hole CO5 formed in the first insulating film 5 and the second insulating film 8. The first metal layer 6b is the gate electrode. The third metal layer 12b is wiring.

[0022] As shown in Figure 4, the second semiconductor layer 34 is provided on a barrier layer 3 provided on the substrate 2. A laminated film is formed on the second semiconductor layer 34 in which the first insulating film 5, the first metal layers 6c, 6d, and 6e, the second metal layer 9f, and the conductive layer 16b are stacked in this order.

[0023] At least one of the first terminals TE1 to TE7 of the display device 1, in this embodiment, as shown in Figure 4, for example, the first terminal TE7 is constructed by stacking a second semiconductor layer 34, a first insulating film 5, first metal layers 6c, 6d, and 6e, a second metal layer 9f, and a conductive layer 16b in this order.

[0024] As described above, the number of films constituting the second multilayer film, which is formed on the second semiconductor layer 34, is less than the number of films constituting the first multilayer film, which is formed on the first semiconductor layer 4 and the first semiconductor layer 24, respectively.

[0025] As shown in Figures 1 and 4, before mounting the circuit board 43 shown in Figure 8 onto the display device 1, the surfaces of the multiple first terminals TE1 to TE7 of the terminal region TER are exposed.

[0026] As shown in Figure 4, when performing an analysis to investigate the cause of a malfunction using the second semiconductor layer 34 provided in the terminal region TER, the process of removing the upper layer can be significantly reduced compared to when performing an analysis to investigate the cause of a malfunction using the first semiconductor layer 4 provided in the display region DA or the first semiconductor layer 24 provided in the non-display region NDA other than the terminal region TER. This shortens the upper layer removal time and avoids the risk of damage or loss of the analysis area due to the peeling process, thus enabling a more efficient and accurate analysis to investigate the cause of a malfunction. Furthermore, since the second semiconductor layer 34 is formed utilizing the terminal region TER of the non-display region NDA, it is possible to suppress the enlargement of the non-display region NDA.

[0027] As shown in Figure 4, the second semiconductor layer 34 has, in a plan view, a first region which is undoped regions 34O1, 34O2, and 34O3 that overlap with the first metal layers 6c, 6d, and 6e, and a second region which is not overlapped with the first metal layers 6c, 6d, and 6e, which is highly doped regions 34H1, 34H2 and low-doped regions 34L1, 34L2, 34L3, and 34L4. The impurity concentrations differ between the first and second regions, and in this embodiment, the impurity concentration is higher in the second region than in the first region. As described above, by providing the second semiconductor layer 34 which has regions with different impurity concentrations, even when the first semiconductor layer 4 provided in the display region DA and the first semiconductor layer 24 provided in the non-display region NDA other than the terminal region TER have regions with different impurity concentrations, analysis for investigating the cause of malfunction can be performed using the second semiconductor layer 34.

[0028] Furthermore, as shown in Figure 4, the second semiconductor layer 34 may include an undoped region 34O2 as the central region as the first region, and highly doped regions 34H1 and 34H2 as the source and drain regions as the second region, with a low-concentration doped region 34L2 between the undoped region 34O2 and the highly doped region 34H1, and a low-concentration doped region 34L3 between the undoped region 34O2 and the highly doped region 34H2. By providing such a second semiconductor layer 34, it is possible to use the second semiconductor layer 34 to analyze the cause of malfunctions in the undoped region, the highly doped region (source and drain regions), and even the low-concentration doped region of the first semiconductor layer 24 provided in the display region DA and the non-display region NDA other than the terminal region TER.

[0029] As shown in Figure 2, the display area DA of the display device 1 includes a first transistor TR1 having a first semiconductor layer 4, a scanning signal line (not shown) electrically connected to a first metal layer 6a which is the gate electrode of the first transistor TR1, and a data signal line (not shown) electrically connected to a second metal layer 9a which is the source electrode of the first transistor TR1. The first metal layer 6a is made of the same material as the scanning signal line, and the second metal layer 9a is made of the same material as the data signal line.

[0030] For example, some of the first terminals TE1 to TE7 shown in Figure 1, specifically some first terminals TE7, may be dummy terminals that are not connected to the wiring route from the display area DA to the terminal area TER, and the second semiconductor layer 34 may be provided only on these dummy terminals.

[0031] The first semiconductor layer 4, the first semiconductor layer 24, and the second semiconductor layer 34 provided in the display device 1 may be oxide semiconductor layers or silicon semiconductor layers. The first semiconductor layer 4, the first semiconductor layer 24, and the second semiconductor layer 34 provided in the display device 1 may include two or more types of semiconductor layers with different constituent materials. For example, one of the two or more types of semiconductor layers may be an oxide semiconductor layer, and the other of the two or more types of semiconductor layers may be a silicon semiconductor layer. Furthermore, the silicon semiconductor layer may be a crystalline silicon semiconductor layer or an amorphous silicon semiconductor layer.

[0032] Figure 5 shows an example of the process for forming the first terminals TE1 to TE7 provided in the terminal area TER of the display device 1 shown in Figure 1. Figure 6 shows an example of the process for forming other first terminals that can be provided in the terminal area TER of the display device 1 shown in Figure 1.

[0033] In this embodiment, the first terminals TE1 to TE6 provided in the terminal area TER of the display device 1 shown in Figure 1 will be described as having the same configuration as the first terminal TE7 shown in Figure 4.

[0034] As shown in Figure 5, the process of forming the first terminals TE1 to TE7 includes: step S1 of forming an island-shaped second semiconductor layer 34 for each of the first terminals TE1 to TE7; and step S2 of patterning and forming first metal layers 6c', 6d', and 6e' for each of the first terminals TE1 to TE7 on a first insulating film 5 (not shown), and using the first metal layers 6c', 6d', and 6e' as a mask to form high-concentration doped regions 34H1 and 34H2. The process includes: step S3 to form first metal layers 6c, 6d, and 6e by further patterning the first metal layers 6c', 6d, and 6e, and to form low-concentration doped regions 34L1, 34L2, 34L3, and 34L4 using the first metal layers 6c, 6d, and 6e as a mask; step S4 to form island-shaped second metal layers 9f for each of the first terminals TE1 to TE7; and step S5 to form island-shaped conductive layers 16b for each of the first terminals TE1 to TE7.

[0035] In this embodiment, in step S2 shown in Figure 5, the first metal layers 6c', 6d', and 6e' were patterned for each of the first terminals TE1 to TE7 with a plurality of linear patterns having openings in between when viewed from above. Then, in step S3 shown in Figure 5, the first metal layers 6c', 6d', and 6e' were further patterned to form first metal layers 6c, 6d, and 6e with wider openings between the linear patterns. In this embodiment, as shown in Figure 5, the case in which the first metal layers 6c', 6d', 6e' and the first metal layers 6c, 6d, 6e extend in the vertical direction in the figure has been described as an example, but the invention is not limited to this. In step S2 shown in Figure 5, as shown in Figure 6, the first metal layers 6f', 6g', 6h', 6i', 6j' extending in the left-right direction in the figure are patterned and formed, and in the subsequent step S3, the first metal layers 6f', 6g', 6h', 6i', 6j' are further patterned to widen the openings between the linear patterns. Furthermore, in step S2 shown in Figure 5, as shown in Figure 6, the first metal layers 6k', 6l' having a grid-like pattern with openings are patterned and formed, and in the subsequent step S3, the first metal layers 6k', 6l' are further patterned to widen the openings in the grid-like pattern.

[0036] Figure 7 shows the case where the second semiconductor layer 34 is exposed at the first terminal TE7 shown in Figure 4, which is provided in the terminal region TER of the display device 1 shown in Figure 1.

[0037] As shown in Figure 7, the first terminal TE7a with the second semiconductor layer 34 exposed can be obtained by removing the first insulating film 5, the first metal layers 6c, 6d, and 6e, the second metal layer 9f, and the conductive layer 16b provided on the first terminal TE7 shown in Figure 4. Compared to the case where analysis for investigating the cause of a malfunction is performed using the first semiconductor layer 4 provided in the display area DA or the first semiconductor layer 24 provided in the non-display area NDA other than the terminal area TER, as described above, the process of removing the upper layers can be greatly reduced, shortening the upper layer removal time and avoiding the risk of damage or loss of the analysis area due to the peeling process. Therefore, analysis for investigating the cause of a malfunction can be performed more efficiently and accurately.

[0038] As an example of investigating the cause of a defect that may occur using the second semiconductor layer 34, one can analyze whether the patterning positions of the low-concentration doped regions 34L1, 34L2, 34L3, and 34L4 are in predetermined positions. The low-concentration doped regions 34L1, 34L2, 34L3, and 34L4 formed on the second semiconductor layer 34 of the terminal region TER shown in Figure 4 are formed in the same process as the low-concentration doped regions 4L1 and 4L2 formed on the first semiconductor layer 4 provided on the red subpixel RSP shown in Figure 2. Therefore, by analyzing whether the patterning positions of the low-concentration doped regions 34L1, 34L2, 34L3, and 34L4 formed on the second semiconductor layer 34 are in predetermined positions, it is possible to estimate whether the patterning positions of the low-concentration doped regions 4L1 and 4L2 formed on the first semiconductor layer 4 provided on the red subpixel RSP shown in Figure 2 are in predetermined positions.

[0039] Figure 8 shows the case where the circuit board 43 is mounted on the display device 1 shown in Figure 1.

[0040] As shown in Figure 8, a flexible printed circuit board (FPC) is mounted on the display device 1 shown in Figure 1 as a circuit board 43 including the second terminal TE1'. In this embodiment, the drive circuit including the second transistor TR2 provided in the drive circuit formation regions DRU1 and DRU2 is formed in the process of forming the first transistor TR1 provided in the display region DA, and the drive circuit provided in the drive circuit formation region DRU3 is provided externally.

[0041] As shown in Figure 8, the display device 1 comprises a first substrate 41, which is a laminate below the liquid crystal layer 18 shown in Figures 2 and 3, and is provided with a display area DA and a non-display area NDA, and a second substrate 42 facing the surface of the first substrate 41 on which the display area DA and non-display area NDA are provided. In a plan view, the terminal area TER of the non-display area NDA does not overlap with the second substrate 42. The first terminals TE1 to TE7 provided in the terminal area TER of the non-display area NDA are connected to the second terminal TE1' of the circuit board 43 by an anisotropic conductive material, so that each of the multiple first terminals TE1 to TE7 overlaps with each of the multiple second terminals TE1' of the circuit board 43 in a plan view. Thus, even when a circuit board 43 including a second terminal TE1' is provided on the first terminals TE1 to TE7 provided in the terminal region TER of the non-display region NDA, the process of removing the upper layer can be significantly reduced compared to when analysis for investigating the cause of a malfunction is performed using the first semiconductor layer 4 provided in the display region DA or the first semiconductor layer 24 provided in the non-display region NDA other than the terminal region TER. This shortens the upper layer removal time and avoids the risk of damage or loss of the analysis area due to the peeling process, thus enabling more efficient and accurate analysis for investigating the cause of a malfunction.

[0042] Figure 9 shows a part of the manufacturing process of the display device 1 shown in Figure 1. Figure 10 shows the remaining part of the manufacturing process of the display device 1 shown in Figure 1. Figure 11 shows an example of the process of exposing the second semiconductor layer 34 at the first terminals TE1 to TE7 provided in the terminal region TER of the display device 1 shown in Figure 1.

[0043] In this embodiment, the case in which the first semiconductor layer 4, the first semiconductor layer 24, and the second semiconductor layer 34 provided in the display device 1 are crystalline silicon semiconductor layers will be described as an example, but the embodiment is not limited to this.

[0044] In step S11 shown in FIG. 9, the first semiconductor layer 4O' provided in the display area DA, the first semiconductor layer provided in the drive circuit formation areas DRU1 and DRU2 which are non-display areas NDA other than the terminal area TER not shown in the figure, and the second semiconductor layer 34O' provided in the terminal area TER were formed in the same process using an amorphous silicon semiconductor material which is the same material. In step S12 shown in FIG. 9 after that, laser annealing treatment was performed on the first semiconductor layer 4O' provided in the display area DA, the first semiconductor layer provided in the drive circuit formation areas DRU1 and DRU2 not shown in the figure, and the second semiconductor layer 34O' provided in the terminal area TER, and the amorphous silicon semiconductor layer was converted into a crystalline silicon semiconductor layer.

[0045] In step S13 shown in FIG. 9 after that, the first semiconductor layer 4O provided in the display area DA, the first semiconductor layer provided in the drive circuit formation areas DRU1 and DRU2 not shown in the figure, and the second semiconductor layer 34O provided in the terminal area TER were patterned into a predetermined shape. In step S14 shown in FIG. 9 after that, the first insulating film 5 was formed and then the first metal layer 6 was formed. In step S15 shown in FIG. 9 after that, the first metal layer 6 was patterned into the first metal layers 6a' to 6e' of a predetermined shape. Then, using the first metal layers 6a' to 6e' of a predetermined shape as a mask, high-concentration impurity implantation was performed to form the high-concentration doped regions 4H1 and 4H2 of the first semiconductor layer 4, the high-concentration doped regions 34H1 and 34H2 of the second semiconductor layer 34, and the high-concentration doped regions 24H1 and 24H2 of the first semiconductor layer 24 not shown in the figure.

[0046] In step S1 in FIG. 10 after that, the first metal layers 6a' to 6e' of a predetermined shape were further patterned to obtain the first metal layers 6a to 6e of a predetermined shape. Then, using the first metal layers 6a to 6e of a predetermined shape as a mask, low-concentration impurity implantation was performed to form the low-concentration doped regions 4L1 and 4L2 of the first semiconductor layer 4, the low-concentration doped regions 34L1, 34L2, 34L3, and 34L4 of the second semiconductor layer 34, and the low-concentration doped regions 24L1 and 24L2 of the first semiconductor layer 24 not shown in the figure.

[0047] In the subsequent step S17 shown in FIG. 10, after forming the second metal layer and patterning it, the second metal layer 9f is formed in the terminal region TER, the second metal layers 9a, 9b, and 9c are formed in the display region DA, and the second metal layers 9d and 9e are formed in the drive circuit formation regions DRU1 and DRU2 (not shown), respectively. In the subsequent step S18 shown in FIG. 10, after forming the conductive layer and patterning it, the conductive layer 16b is formed in the terminal region TER and the conductive layer 16a is formed in the display region DA, respectively. In the subsequent step S19 shown in FIG. 10, after bonding the color filter substrate 19, the liquid crystal layer 18 is injected. Then, after providing the first deflection plate 20a and the second deflection plate 20b, a functional film 22, which is a film having at least one of an optical compensation function, a touch sensor function, and a protection function, is provided on the first deflection plate 20a via a transparent adhesive 21.

[0048] As described above, the manufacturing method of the display device 1 includes a step of forming, in the same process using the same material, a first semiconductor layer provided in at least one of the non-display region NDA other than the terminal region TER and the display region DA and a second semiconductor layer provided in the terminal region TER.

[0049] In the present embodiment, the case where the display device 1 is rectangular has been described as an example, but the present invention is not limited thereto, and the display device 1 may have a different shape such as a circular shape, an elliptical shape, a triangular shape, a polygon having five or more sides, a trapezoidal shape, etc.

[0050] Currently, in display devices used in vehicle-mounted applications, etc., low-temperature poly-silicon TFTs are often applied because reliability is highly regarded. Even in this case, from the perspective of reliability, it is common to adopt an LDD structure, which is a low-concentration doped region, as a countermeasure against hot carrier degradation for peripheral driver TFTs, in which TFT characteristic shift is likely to occur due to the influence of a high applied voltage. However, when forming this LDD, which is a low-concentration doped region, using a resist mask, the influence of the photo alignment accuracy is large, and even a slight deviation will have a great impact on the reliability in terms of characteristics.

[0051] Furthermore, when performing LDD verification of the TFT after panel completion, it is necessary to peel off multiple layers of different materials formed on the semiconductor layer (Si film), which is the measurement layer, one layer at a time from the top layer in order to expose the Si film. However, repeated removal of upper layers can cause the area around the Si film of the measurement layer to be dug down, resulting in a more uneven surface shape, and the Si layer itself may have a thinner or even disappearing pattern.

[0052] Therefore, by providing the second semiconductor layer, which is an analytical semiconductor layer, in the terminal region TER, it becomes possible to form the Si layer over a larger area than the pixel TFT. Furthermore, since there is no opposing substrate or planarization film in the terminal region TER, the number of times the upper layer of the Si layer is peeled off can be reduced. As a result, the risk of Si layer loss is avoided, and analysis of the Si film using a scanning capacitance microscope can be performed accurately and quickly. In addition to analysis using a scanning capacitance microscope, analysis using electron backscattered diffraction patterns, which evaluates the crystallinity of the Si film that affects the electrical properties of the TFT, can also be performed over a wider area, allowing for the reliable acquisition of more accurate data.

[0053] [Embodiment 2] Figure 12 shows the case where a circuit board 43 is mounted on the display device 1a of Embodiment 2. Figure 13 is a cross-sectional view showing the schematic configuration of the display area DA of the display device 1a shown in Figure 12.

[0054] As shown in Figure 12, the display device 1a comprises a first substrate 51 provided with a display area DA and a non-display area NDA, and a sealing layer 65 that seals the display area DA, and the terminal area TER does not overlap with the sealing layer 65 in a plan view.

[0055] As shown in Figure 12, the display device 1a comprises a first substrate 51 provided with a display area DA and a non-display area NDA, and a circuit board 43 equipped with a plurality of second terminals TE1', where each of the plurality of first terminals TE1 to TE7 is superimposed on each of the plurality of second terminals TE1' of the circuit board 43 in a plan view.

[0056] Thus, even when a circuit board 43 including a second terminal TE1' is provided on the first terminals TE1 to TE7 provided in the terminal area TER of the non-display area NDA, the process of removing the upper layer can be significantly reduced compared to when analysis for investigating the cause of a malfunction is performed using the first semiconductor layer provided in the display area DA or the first semiconductor layer provided in the non-display area NDA other than the terminal area TER. This shortens the upper layer removal time and avoids the risk of damage or loss of the analysis area due to the peeling process, thus enabling more efficient and accurate analysis for investigating the cause of a malfunction.

[0057] As shown in Figure 13, in the display area DA of the display device 1a, the substrate 2 is provided with, in this order from the substrate 2 side, a barrier layer 3, a thin-film transistor layer including a first transistor TR1' having a first semiconductor layer 84 including highly doped regions 84H1 and 84H2 and an undoped region 84O, a red light-emitting element 59R, a green light-emitting element 59G, a blue light-emitting element 59B and a bank 60, a sealing layer 65, and a functional film 22. The thin-film transistor layer including the first transistor TR1' is a layer that includes a first semiconductor layer 84, an inorganic insulating film 52, a gate electrode G, an inorganic insulating film 53, an inorganic insulating film 54, a source electrode S and a drain electrode D, and a planarization film 55.

[0058] The red subpixel RSP provided in the display area DA of the display device 1a includes a red light-emitting element 59R, the green subpixel GSP provided in the display area DA of the display device 1a includes a green light-emitting element 59G, and the blue subpixel BSP provided in the display area DA of the display device 1a includes a blue light-emitting element 59B. The red light-emitting element 59R included in the red subpixel RSP includes an anode 56 which is a pixel electrode, a functional layer 57R which includes a red light-emitting layer, and a cathode 58. The green light-emitting element 59G included in the green subpixel GSP includes an anode 56 which is a pixel electrode, a functional layer 57G which includes a green light-emitting layer, and a cathode 58. The blue light-emitting element 59B included in the blue subpixel BSP includes an anode 56 which is a pixel electrode, a functional layer 57B which includes a blue light-emitting layer, and a cathode 58.

[0059] The sealing layer 65 is a light-transmitting film and can be composed of, for example, an inorganic sealing film 70 covering the cathode 58, an organic film 71 above the inorganic sealing film 70, and an inorganic sealing film 72 above the organic film 71. The sealing layer 65 prevents foreign substances such as water and oxygen from penetrating the red light-emitting element 59R, the green light-emitting element 59G, and the blue light-emitting element 59B.

[0060] Furthermore, the red light-emitting layer provided in the red light-emitting element 59R, the green light-emitting layer provided in the green light-emitting element 59G, and the blue light-emitting layer provided in the blue light-emitting element 59B may be light-emitting layers containing quantum dots, or they may be light-emitting layers containing organic light-emitting materials.

[0061] As described above, the first substrate 41 shown in Figure 8 and the first substrate 51 shown in Figure 12, on which the terminal region TER is formed, have been described as, for example, an active matrix substrate with TFTs used in a display device, but are not limited to this. For example, the first substrate on which the terminal region TER is formed is not limited to an active matrix substrate for a display device, but may be an active matrix substrate with TFTs used in a non-display device such as a sensor. In the case of such an active matrix substrate, it includes a first region on which a plurality of electrodes are provided, a second region provided outside the first region, a terminal region in the second region on which a plurality of first terminals are provided, and one or more first semiconductor layers provided in at least one of the second region and the first region other than the terminal region, and the terminal region is provided with a second semiconductor layer made of the same material as at least one of the first semiconductor layers, and the first semiconductor layer and the second semiconductor layer are formed as the same layer.

[0062] [Additional Notes] This disclosure is not limited to the embodiments described above, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of this disclosure. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

[0063] This disclosure can be used for display devices, active matrix substrates, and methods for manufacturing display devices.

[0064] 1, 1a Display device 2 Substrate 3 Barrier layer 4 First semiconductor layer 4H1, 4H2 High-concentration doped region 4L1, 4L2 Low-concentration doped region 4O Undoped region 5 First insulating film 6, 6a-6e First metal layer 8 Second insulating film 9a-9f Second metal layer 10 Planarization film 11 First passivation film 12a, 12b Third metal layer 13 Second passivation film 14, 16a, 16b Conductive layer 15 Third passivation film 17 Alignment film 18 Liquid crystal layer 19 Color filter substrate 20a First deflection plate 20b Second deflection plate 21 Transparent adhesive 22 Functional film 24 First semiconductor layer 24H1, 24H2 High-concentration doped region 24L1, 24L2 Low-concentration doped region 24O 34 Undoped region Second semiconductor layer 34H1, 34H2 High-concentration doped region 34L1 to 34L4 Low-concentration doped region 34O1 to 34O3 Undoped region 41, 51 First substrate 42 Second substrate 43 Circuit board 56 Lower electrodes 57R, 57G, 57B Functional layer 58 Upper electrode 59R Red light-emitting element 59G Green light-emitting element 59B Blue light-emitting element 65 Encapsulation layer 84 First semiconductor layer 84H1, 44H2 High-concentration doped region 84O Undoped region DA Display region NDA Non-display region TE1 to TE7 First terminal TE7a First terminal where the second semiconductor layer is exposed TE1' Second terminalTER Terminal area ALM1, ALM2 Alignment marks DRU1-DRU3 Drive circuit formation area CO1-CO5 Contact holes TR1, TR1' First transistor TR2 Second transistor S Source electrode D Drain electrode G Gate electrode RSP Red subpixel GSP Green subpixel BSP Blue subpixel PIX Pixel

Claims

1. A display device comprising: a display area provided with a plurality of pixel electrodes; a non-display area provided outside the display area; a terminal area provided with a plurality of first terminals in the non-display area; and one or more first semiconductor layers provided in at least one of the non-display area and the display area other than the terminal area, wherein the terminal area is provided with a second semiconductor layer made of the same material as at least one of the first semiconductor layers, and the first semiconductor layer and the second semiconductor layer are formed as the same layer.

2. The display device according to claim 1, wherein the first semiconductor layer is provided in the display area.

3. The display device according to claim 1 or 2, wherein a first multilayer film is formed on the first semiconductor layer, a second multilayer film is formed on the second semiconductor layer, and the number of films constituting the second multilayer film is less than the number of films constituting the first multilayer film.

4. A display device according to any one of claims 1 to 3, comprising: a first substrate on which the display area and the non-display area are provided; and a second substrate facing the surface of the first substrate on which the display area and the non-display area are provided, wherein the terminal area does not overlap with the second substrate in a plan view.

5. A display device according to any one of claims 1 to 3, comprising: a first substrate provided with the display area and the non-display area; and a sealing layer that seals the display area, wherein the terminal area does not overlap with the sealing layer in a plan view.

6. The display device according to any one of claims 1 to 5, wherein the plurality of first terminals in the terminal region have exposed surfaces.

7. A display device according to any one of claims 1 to 5, comprising: a first substrate on which the display area and the non-display area are provided; and a circuit board which is a substrate different from the first substrate and has a plurality of second terminals, wherein each of the plurality of first terminals is superimposed on each of the plurality of second terminals of the circuit board in a plan view.

8. The display device according to any one of claims 1 to 7, wherein at least one of the plurality of first terminals has the second semiconductor layer, the first insulating film, the first metal layer, the second metal layer, and the conductive layer stacked in this order.

9. The display device according to claim 8, wherein the second semiconductor layer includes a first region superimposed on the first metal layer in a plan view and a second region not superimposed on the first metal layer in a plan view, and the impurity concentrations differ between the first region and the second region.

10. The display device according to claim 9, wherein the second semiconductor layer has a central region as a first region and a source region and a drain region as a second region.

11. The display device according to any one of claims 8 to 10, wherein the first metal layer is formed in plan view of a plurality of linear patterns having openings in between or a grid-like pattern having openings.

12. The display device according to any one of claims 8 to 11, wherein the display area includes a transistor having the first semiconductor layer, a scanning signal line electrically connected to the gate electrode of the transistor, and a data signal line electrically connected to the source electrode of the transistor, the first metal layer being made of the same material as the scanning signal line, and the second metal layer being made of the same material as the data signal line.

13. A display device according to any one of claims 1 to 12, wherein some of the plurality of first terminals are dummy terminals that are not connected to the wiring routed from the display area to the terminal area, and the second semiconductor layer is provided on the dummy terminals.

14. The display device according to any one of claims 1 to 13, wherein the second semiconductor layer is an oxide semiconductor layer.

15. The display device according to any one of claims 1 to 13, wherein the second semiconductor layer is a silicon semiconductor layer.

16. The display device according to any one of claims 1 to 13, wherein the second semiconductor layer comprises two or more semiconductor layers made of different constituent materials.

17. The display device according to claim 16, wherein one of the two or more semiconductor layers is an oxide semiconductor layer, and the other of the two or more semiconductor layers is a silicon semiconductor layer.

18. The display device according to claim 15 or 17, wherein the silicon semiconductor layer is a crystalline silicon semiconductor layer.

19. The display device according to claim 15 or 17, wherein the silicon semiconductor layer is an amorphous silicon semiconductor layer.

20. A method for manufacturing a display device, comprising: a display area provided with a plurality of pixel electrodes; a non-display area provided outside the display area; and a terminal area in the non-display area provided with a plurality of terminals, the method comprising forming a first semiconductor layer provided in at least one of the non-display area other than the terminal area and the display area, and a second semiconductor layer provided in the terminal area, using the same material and the same process.

21. An active matrix substrate comprising: a first region provided with a plurality of electrodes; a second region provided outside the first region; a terminal region provided with a plurality of first terminals in the second region; and one or more first semiconductor layers provided in at least one of the second region and the first region other than the terminal region, wherein the terminal region is provided with a second semiconductor layer made of the same material as at least one of the first semiconductor layers, and the first semiconductor layer and the second semiconductor layer are formed as the same layer.

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