Multi-temperature operation of photonic integrated circuits

Abstract

A photonic integrated circuit (PIC) includes a. first area having first components configured to operate at a first cryogenic temperature. The first cryogenic temperature is determined by circulation of a first cryogenic coolant. In addition, the PIC includes a second area having second components configured to operate at a second cryogenic temperature. The second cryogenic temperature is determined by circulation of a second cryogenic coolant and the second cryogenic temperature is colder than the first cryogenic temperature. Further, the second area is separated from the first area by a trench etched through a substrate of the PIC, and. is connected to the first area, with a signal bridge comprising components that carry electrical and photonic signals. The second area is further connected, to the first area by a mechanical support structure that extends through the trench.

Description

MULTI-TEMPERATURE OPERATIONOF PHOTONIC INTEGRATED CIRCUITSCLAIM OF PRIORITY

[0001] This application claims the benefit of priority to U.S. Patent Application Serial No. 63 / 631,584, filed on April 9, 2024, which is incorporated by reference herein in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to integrated devices operated at cryogenic temperatures and more particularly to photonic sources operating at a first temperature and photonic detectors operating at a second temperature.BACKGROUND

[0003] Photonic computations use complex photonic integrated circuits (PICs) that have light sources, light propagation / manipulation, and light detection. Different portions of the computation can use photonic elements that have different temperature requirements. Cooling an entire PIC to a cryogenic temperature, based on a temperature requirement for one type of photonic element, can limit the scalability of a photonic computation across multiple PICs.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The following description includes discussion of figures having illustrations given by way of example of implementations of embodiments of the disclosure. The drawings should be understood by way of example, and not by way of limitation. As used herein, references to one or more "embodiments" are to be understood as describing a particular feature, structure, or characteristic included in at least one implementation of the subject matter. Thus, phrases such as "in one embodiment" or "in an alternate embodiment" appearing herein describe various embodiments and implementations of the subject matter, and do not necessarily all refer to thesame embodiment. However, they are also not necessarily mutually exclusive. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure ("FIG.") number in which that element or act is first introduced.

[0005] FIG. 1 illustrates an example photonic integrated circuit (PIC) having a. first component, array and second component array thermally isolated from the PIC, in accordance with some embodiments.

[0006] FIG. 2 A illustrates a second example PIC having a first component array and second component array thermally isolated from the PIC, in accordance with some embodiments.

[0007] FIG. 2B illustrates a detailed view of the optical and electrical connections between the first area and the second area of the PIC of FIG.2A, in accordance with some embodiments.

[0008] FIG. 3 illustrates a flow diagram of a method for fabricating a PIC having a thermally isolated area, in accordance with some embodiments.

[0009] FIG. 4 A illustrates a system diagram of a PIC configured and fabricated for multi -temperature operation in accordance with some embodiments.

[0010] FIG. 4B illustrates another system diagram of a PIC configured and. fabricated for multi -temperature operation in accordance with some embodiments.

[0011] FIG. 5 A and FIG. 5B illustrate a. flow diagram for packaging a PIC having a thermally isolated area in accordance with some embodiments.

[0012] FIG. 6 illustrates a flow diagram of a method for operating a PIC at two temperatures, in accordance with some embodiments.

[0013] FIG. 7 illustrates a PIC layout having a first area, second area, and third area, that are each thermally isolated in accordance with some embodiments.

[0014] FIG. 8A and FIG. 8B illustrate an example of a PIC comprising multiple suspended regions that are each thermally isolated in accordance with some embodiments.

[0015] FIG 9 illustrates a system diagram for multi-temperature operation of a PIC in accordance with some embodiments.

[0016] FIG. 10 illustrates an example cryogenic chamber comprising two cryogenic coolants in accordance with some embodiments.

[0017] Descriptions of certain details and implementations follow, including a description of the figures, which may depict, some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the disclosure is provided below, followed by a more detailed description with reference to the drawings.DETAILED DESCRIPTION

[0018] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide an understanding of various embodiments of the inventive subject matter. It will be evident, however, to those skilled in the art, that embodiments of the inventive subject matter may be practiced without these specific details. In general, well-known instruction instances, structures, and techniques are not necessarily shown in detail.

[0019] Photonic integrated circuits (PICs) can be used for photonic computation using a combination of linear optical elements, and quantum optical elements (e.g., with single photons). Such PICs can include fabricated elements including: light sources (LEDs, lasers, single-photon generation from quantum dots, from spontaneous parametric downconversion, etc.), waveguides, light manipulation elements (modulators, phase shifters, multi -pl exers, etc.), and light, detectors (thermopiles, photodiodes, avalanche diodes, single photon detectors, number-resolving photon detectors).10020] Within a PIC, certain photonic elements can have temperature dependence on the operation and / or performance of the photonic element. For example, thermal phase shifters can be implemented in an on-chip Mach-Zender Interferometer, where one arm of the interferometer contains a thermal controller (e.g., thermometer and heater) that can locally heat the waveguide segment of the interferometer arm. When the waveguide segmentis heated, thermo-optic effects can impart a phase shift to light propagating along the length of that waveguide segment. Such photonic elements can have optimal temperature ranges for operating based on the material properties of the waveguide segment(s) and / or thermal control! er(s). Another example is superconducting nanowire single photon detectors (SSPD) that require a cryogenic temperature around 2 Kelvin in order for the superconducting junctions to operate as intended. Oftentimes, a single type of photonic element can set a temperature requirement that is much stricter than remaining photonic elements, such as detectors requiring 2 K for operation when the remaining on-chip elements are able to operate at 77 K and / or up to room temperature (approximately 290 K).

[0021] One conventional solution to a. photonic computation using elements with multiple temperature requirements is to distribute the photonic components among specialized PICs. For example, a 2 K cryostat can house a chip containing only the detectors, and a room -temperature chip can operate the remaining photonic elements. However, this requires fiber optic patch cables that run between multiple chips, which introduces large elements of light loss at each fiber optic coupling junction, and can significantly impact the overall efficiency of the photonic computation.

[0022] Another conventional solution is to cool the entire PIC to the lowest temperature required. Cooling a single PIC to 2 K can be achieved with conventional cryogenic equipment, however, scaling a conventional cryogenic PIC configuration to multiple PICs for larger photonic computations can be expensive and inefficient. Much of the cooling power that is used to cool the whole chip can be considered wasted, and could instead be distributed to just the photonic elements which have specific temperature requirements.

[0023] Aspects of the present disclosure address deficiencies of conventional solutions by operating a PIC at multiple temperatures, enabling photonic computations to be performed in a compact PIC while each photonic element is operated at an optimal temperature for that photonic element. In particular, the present disclosure thermally de-couples thedetector section of a PIC while still allowing electrical and photonic signals to be sent and received between the detector(s) and the rest of the PIC.

[0024] Thermal isolation can be achieved for a specific region within the photonic circuit through suspending the specific region, that is, removing bulk material so there is minimal heat transfer between regions of the photonic circuit. Mechanical support is provided so that the detector section remains connected to the PIC in a compact manner. A PIC that is manufactured in accordance with the present disclosure can be cryogenically operated using two separate cold areas: a first cold area at a first cryogenic temperature (e.g., 77 K, 30 K) run by a. first cryogenic system and a second cold area at a second cryogenic temperature (e.g., 4 K, 2 K) run by a second cryogenic system.

[0025] In some examples, the different cold areas of the PIC are housed in the same vacuum cryostat such that different portions of the single PIC can operate at drastically different temperatures. In some examples, a photonic computing system can comprise several instances of multi -temperature PICs. In some examples, the multi -temperature PICs are all housed in the same vacuum cryostat. In some example embodiments, different multi-temperature PICs can be housed in different vacuum cryostats and interconnected with one another (e.g., via optical fiber coupling, free space optics, etc.). In some example embodiments, one or more multi -temperature PICs are coupled to one or more single temperature PICs (e.g., a single PIC maintained at 77 K) to implement photonic tasks. In some example embodiments, the assorted vacuum cryostats that house multi-temperature PICs can be operated by a single first cryogenic coolant, system (e.g., first cryoplant, nitrogen cryogenic supply system) and a single second cryogenic coolant system (e.g., second cryoplant, helium cryogenic supply system), where the first and second cryogenic coolant systems are components in a larger cryoplant setting.

[0026] In some examples, a. photonic integrated circuit (PIC) comprises a. first area having first components configured to operate at a first cryogenic temperature, that is determined by circulation of a first cryogenic coolant; a second area having second components configured to operate at a secondcryogenic temperature, that is determined by circulation of a. second cryogenic coolant, the second cryogenic temperature being colder than the first cryogenic temperature; a trench formed within a substrate of the PIC, the trench separating the second area from the first area; a signal bridge connecting the second area, and the first area, the signal bridge comprising components that each carry at least one of electrical signals and photonic signals; and at least one mechanical support structure that extends through the trench and which mechanically connects the second area and the first area.

[0027] In some examples, the trench etched through the substrate thermally isolates the second area from the first area. In some examples, the at least one mechanical support structure comprises circular traces of substrate material that remain within the trench after the trench is etched through the substrate. In some examples, the at least one mechanical support structure additionally comprises a continuous film covering a first portion of the first area, and a second portion of the second area. The continuous film is formed from thermally insulating material.

[0028] In some examples, the first components comprise a photonic element selected from one of a light source and a. waveguide. In some examples, the second components comprise a superconducting detector element, such as a superconducting nanowire detector array. In some examples, the signal bridge further comprises electrical connections to at least one element in the detector array.

[0029] In some examples, the first cryogenic coolant is liquid nitrogen and the second cryogenic coolant is liquid helium. In some examples, the first cryogenic coolant is liquid helium and the second cryogenic coolant is a mixture of helium isotopes.

[0030] In some examples, the PIC additionally comprises a third area having third components configured to operate at a third cryogenic temperature, that is determined by circulation of a third cryogenic coolant, the third cryogenic temperature being colder than the second cryogenic temperature, a second signal bridge connecting the third area and the second area, the second signal bridge comprising components that each carry at leastone of electrical signals and photonic signals; and at least one mechanical support structure that extends through the trench and which mechanically connects the third area, and the second area. The trench etched through the substrate additionally thermally isolates the third area from the second area. In some examples, the first cryogenic coolant is liquid nitrogen, the second cryogenic coolant is liquid helium, and the third cryogenic coolant is a mixture of helium isotopes. In some examples, the second cryogenic coolant is liquid nitrogen, and the third cryogenic coolant is liquid helium.

[0031] In some examples, the PIC additionally comprises a third area having third components configured to operate at a third temperature that is warmer than the first cryogenic temperature, a second signal bridge connecting the third area and the first area, the second signal bridge comprising components that cany at least one of electrical and photonic signals; and at least one mechanical support structure that, extends through the trench and which mechanically connects the third area and the first area. The trench etched through the substrate additionally thermally isolates the third area, from the first area.

[0032] In some examples, a method, for operating a photonic integrated circuit, having a. first area, and a second area, that is thermally isolated from the first area through a trench, the method comprises packaging the photonic integrated circuit on a first chip holder, that mechanically connects to the first area and is mechanically unconnected to the second area; securing a cold finger to the second area; attaching the first chip holder to a first cold plate that is configured to operate in a first cryogenic system; attaching the cold finger to a second cold plate that is configured to operate in a second cryogenic system; assembling a vacuum chamber that houses the first cold plate and the second cold plate; operating a first photonic component at a first cryogenic temperature determined by operation of the first cryogenic system that is located within the first area of the photonic integrated circuit; and operating a. second photonic component, at a. second cryogenic temperature determined by operation of the second cryogenic system that is located within the second area of the photonic integrated circuit.

[0033] In some examples, the method further comprises receiving a first signal at the second component that is from the first component. The first signal is routed through a signal connection that spans the trench. Consistent with these examples, the method further comprises receiving a second signal at a third component that is located in at least one of the first area and the first chip holder. The second signal is from the second component and is generated while the second component is operated at the second cryogenic temperature. The second signal is routed through the signal connection that spans the trench.

[0034] FIG. 1 shows a system diagram of a photonic integrated circuit (PIC) 100 incorporating a first component array 110 and a second component array 120. In some examples, PIC 100 can additionally include a first area 101, a second area 102, trench 114, mechanical supports 116, and mechanical stability layer 118. Additionally, PIC 100 can include photonic connections 112 and 122 and electrical connections 124 in some examples. In some example embodiments, the photonic connections 112 comprise fibers that are edge coupled to waveguides in the PIC 100. In some example embodiments, the fibers can be fused or attached with adhesive to the PIC 100. An advantage of the multi -temperature cooling approach of the PIC 100 includes maintaining photonic and electrical connections to the PIC 100 at a stable or warmer temperature (e.g., 77 K, above 10 K, 300 K) to avoid physical issues at the edge couple interface (e.g., cracking) while allowing portions of the PIC 100 to be cooled to colder cryogenic temperature (e.g., 2 K).

[0035] In some examples, first component array 110 can be located in the first area 101 of the PIC 100. In some examples, second component array 120 can be located in the second area 102 of the PIC 100.

[0036] In some examples, first component array 110 and second component array 120 can include any suitable quantity of photonic elements. In some examples, any of the photonic elements in first component array 1 10 and / or second component array 120 can include suitable photonic element(s), such as: light source (e.g., light emitting diode, laser, single photon source, etc.), waveguide, interferometer, ring resonator, modulator, phase-shifter,amplifier, filter, splitter, multiplexing unit, de-multiplexing unit, photodiode, and / or single or number-resolving photon detector (e.g., avalanche photodiode, SSPD, etc,), and / or any other suitable photonic element.. In some examples, elements in first component array 110 can be all the same photonic elernent(s) or can be a combination of different photonic elements. Similarly, in some examples, elements in second component array 120 can be all the same photonic element(s) or can be a combination of different photonic elements.

[0037] In some examples, photonic elements in first component array 110 can have an operating temperature within any suitable temperature range. For example, first component array 110 can include a light source (e.g., laser, single-photon source). In another example, first, component array 1 10 can include a phase shifter as part of an interferometer, which can use thermo-optic effects to impart a phase shift to light propagating along an arm of the interferometer. In some examples, the operating temperature range can be 300 K to 77 K, and can require the use of a cryogenic refrigerant such as liquid oxygen, liquid helium, and / or any other suitable refrigerant, to achieve the required operating temperature of the photonic component.

[0038] Similarly, in some examples, photonic elements in second component array 120 can have an operating temperature within any suitable temperature range. For example, second component array 120 can include a superconducting detector element such as a superconducting nanowire single-photon detector (SSPD) that can detect single photons when the SSPD is operated at a cryogenic temperature. As a particular example, a superconducting material layer in the SSPD can determine an operating temperature, such as 4 Kelvin (K) for a sputtered niobium nitride (NbN) superconducting layer. In some examples, a detector in the second, component, array 120 can have an operating temperature that is in a range of 2 K to 77 K, and can require the use of a cryogenic refrigerant such as liquid helium to achieve the required operating temperature of the photonic component. In some examples, a detector in the second component array 120 can have an operating temperature that is below 2 K, and / or sub-K (e.g., milli-Kelvin), and can require the use of a cryogenic system such as adilution refrigerator operating with a mixture of helium-3 and helium-4 isotopes.

[0039] In some examples, first component array 110 and / or second component array 120 can include photonic elements designed for operation in any suitable wavelength band. Similarly, in some examples, first component array 1 10 and / or second component array 120 can include (partially or wholly) electronic elements (e.g., voltage source(s), wires, resistors, inductors, capacitors, transistors, diodes, etc.) that can operate at any suitable voltage level and / or RF frequency and / or with any suitable qubit, technology.

[0040] As shown in FIG. 1, and in some examples, second area 102 can be a suspended region of the PIC device layer. In particular, photonic elements of second component array 120 cart be thermally isolated from first area 101 through suspension over trench 114, and use of mechanical supports 116 and mechanical stability layer 1 18. Fabrication of trench 114, mechanical supports 116, and mechanical stability layer 118 can follow any suitable fabrication process to remove bulk substrate material, such as that described in connection with FIG. 3. In some examples, second area 102 can be supported by mechanical supports 116, which can have any suitable design and / or dimension(s). For example, as shown in FIG. 1, the spiral design of mechanical supports 116 can minimize the amount of material remaining between first area 101 and second area 102, thus minimizing heat leaks between the suspended second area 102 and the main first, area 101. Other design considerations for mechanical supports 116 include ensuring adequate support, for the mass contained in second area 102, and mechanical stability during packaging and operation of the PIC.

[0041] In some examples, first component array 110 and second component array 120 can include photonic connections 1 12 and 122 and / or electrical connections 124. In some examples, photonic connections 112 and / or 122 can include waveguides, modulators, mirrors, gratings, and / or any other suitable photonic elements. In some examples, photonic connections 112 can be located in first area 101 and can be used to transport photonic signals on and off PIC 100. As a particular example, photonic connections 112 can beused to bring light from a light source (e.g., laser) external to PIC 100 onto the first area 101. for example to a single-photon source. In another particular example, photonic connections 112 can be used to send light from a photonic element (e.g., interferometer) to another PIC (not shown).

[0042] In some examples, as shown in FIG. 1, photonic connections 122 can carry photonic signals to and / or from first area 101 to second area 102. In some examples, photonic connections 122 can cany photonic signals to and / or from a source external to PIC 100 to second area 102 (not shown). In some examples, electrical connections 124 can carry electrical signals to and / or from second area. 102 and can connect to an electrical component in first area 101 (not shown) and / or external to first area 101 as shown in FIG.1 (e.g., wire bond pads on a. PCB or other packaging substrate of PIC 100). In some examples, electrical connections 124 can be wire traces made of any suitable electrically conductive material. In some examples, electrical connections 124 can perform any suitable opto-electronic function for photonic elements in first, component array 1 10 and / or second component, array 120. For example, electrical connections 124 can be used to modulate a reflection and / or transmission coefficient of a waveguide, to drive a light source and / or single photon source, detect, photons, and / or carry' electrical pulses corresponding to photo-converted electrons (e.g., pulse output at a SSPD in second component array 120).

[0043] In some examples, photonic connections 122 and / or electrical connections 124 can extend between first area. 101 and the suspended second area 102, i.e., across trench 114. This can be achieved, for example, by including photonic connections 112 and / or electrical connections 124 in patterning and fabrication of PIC 100, as described below' at block 304 of flow diagram 300 in connection with FIG. 3. Then, as further described below' at block 310, when the bulk micromachining process removes material from the handle wafer, the photonic connections 112 and / or electrical connections 124 form a. signal bridge between the first area. 101 and second area 102.

[0044] In some examples, any suitable additional mechanical stability layers 118 can be included in the fabrication of PICs 100. For example, asshown in FIG 1 , the mechanical stability layers 118 can include a thermally insulating layer (e.g., 100 nm of fused silica) fabricated over the suspended second area 102, mechanical supports 1 16, photonic connections 112, electrical connections 124, and a portion of first area 101. In some examples, mechanical stability layer 118 can be a final aspect of any wafer processing performed in order to arrive at PIC 100, as described below at block 306 of flow diagram 300 in connection with FIG. 3.

[0045] FIG 2A shows an example of a PIC layout 200 comprising a first area 201, a second area 202, a photonic array 210, a trench 214, mechanical supports 216, and a photonic array 220. In some examples, PIC layout 200 can be designed and fabricated for multi-temperature operation.

[0046] In some examples, second area 202 can be thermally isolated from first area 201 through removal of bulk material and subsequent suspension, consistent with the description of second area 102 and first area 101. In some examples, photonic array 210 can be positioned within PIC layout 200 according to thermal requirements of specific photonic elements in photonic array 210. As shown in FIG. 2 A, photonic array 210 can be fabricated in first area 201.

[0047] Similarly, in some examples, photonic array 220 can be positioned within PIC layout 200 according to thermal requirements of specific photonic elements in photonic array 220. As shown in FIG. 2B, photonic array 220 can be fabricated in second area 202.

[0048] FIG. 2B shows second view of PIC layout 200, specifically region 230.

[0049] In some examples, second area 202 can be thermally isolated from first area 201 through fabrication of trench 214 and mechanical supports 216. In some examples, thermal isolation can be achieved through removal of bulk material and subsequent suspension of second area 202. In some examples, trench 214 and mechanical supports 216 can be designed and fabricated using any suitable process to remove bulk substrate material, such as that described in connection with FIG. 3. In some examples, trench 214 can be substantially similar to trench 114 described above. In someexamples, mechanical supports 216 can be substantially similar to mechanical supports 116 described above.

[0050] In some examples, as shown, photonic connections 222 and electrical connections 224 can bridge trench 214 and / or mechanical supports 216. In some examples, photonic connections 222 and electrical connections 224 can have a first terminal end in first area 201 at a. photonic element and / or electrical element (as appropriate to the type of connection). In some examples, photonic connections 222 and electrical connections 224 can have a second terminal end in second area 202 at a photonic and / or electrical element. For example, as shown, photonic connections 222 can direct light to elements in photonic array 220, where the photonic connections 222 couple to photonic array 220 using any suitable coupling mechanism. In this example, photonic array 220 comprises SSPD and can output electrical signals, which can be carried through electrical connections 224 that connect to photonic array 220.

[0051] FIG. 3 shows an example flow diagram 300 of a method for fabrication of a PIC having a thermally isolated area in accordance with some embodiments, such as PIC 100 as described, above in connection with FIG. 1 through FIG. 2B. Although the example flow diagram 300 depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the flow diagram 300. In other examples, different components of an example device or system that implements the flow diagram 300 may perform functions at substantially the same time or in a specific sequence.

[0052] According to some examples, the method includes preparing a handle wafer at block 302. In some examples, the handle wafer can be a silicon wafer, a III-V semiconductor wafer, and / or any other suitable material. In some examples, preparing the handle wafer comprises performing any suitable wafer processing to the bulk wafer, including suitable surface treatments, growing any additional material layers (e.g., dielectric stacks, insulation layers, doped semiconductor layers, etc.), and / oretching undesired material layers. In some examples, a. first side of the handle wafer can be prepared using a first set of processing techniques. In some examples, a second side of the handle wafer can be prepared using a second set of processing techniques. In some examples, the second side of the handle wafer can be an opposing side (e.g., "back side”) to the first side of the handle wafer. In some examples, the first side and the second side can be determined based on a crystalline structure of the material comprising the handle wafer.

[0053] According to some examples, the method includes fabricating PIC components at block 304 (e.g., waveguides, couplers). In some examples, the first side of the handle wafer can be used to fabricate PIC components. In some examples, the second side of the handle wafer can be used to fabricate PIC components. In some examples, both the first side of the handle wafer and the second side of the handle wafer can be used to fabricate PIC components.

[0054] In some examples, any suitable fabrication techniques can be used at block 304, such as photoresist coating, lithographic patterning, dry etching and / or wet etching, ion implantation, metallization, material deposition using any suitable technique (e.g., sputtering, thermal deposition, atomic layer deposition, plasma deposition, etc.), and / or any other fabrication techniques. In some examples, the same technique(s) or sequence of techniques can be used iteratively to build up photonic components, electrical components, connections between electrical and / or photonic components, etc. In some examples, any suitable photonic components can be fabricated at block 304 using any suitable sequence of fabrication techniques.

[0055] In some examples, a. single area, of the handle wafer can be fabricated at block 304. In some examples, at block 304 the handle wafer can be processed to fabricate an array of individual chips having the same or different PIC component(s) and / or circuit layouts.

[0056] According to some examples, the method includes fabricating thermal insulating layer at block 306. In some examples, the thermal insulating layer can correspond to mechanical stability layer 118 as described above in connection with FIG. 1 . In some examples, the thermalinsulating layer can be fabricated at a later or a final stage of fabrication of the PIC components. In some examples, the thermal insulating layer can be fabricated over an area of the PIC that contains a. particular type of photonic element, e.g., such as second area 102 / 202 as described above in connection with FIG 1 through FIG. 2B. In some examples, the thermal insulating layer can be any suitable material, such as silicon dioxide (e.g., continuous film of silicon dioxide). In some examples, the thermal insulating layer can have any suitable thickness, such as 50 nanometers (nm), 100 nm, 1000 nm, etc. In some embodiments, the mechanical stability layer (film) is omitted, and the mechanical supports 116 are rigid enough (e.g., thick enough) to support the second area 102 / 202. For example, in some embodiments, the photonic connections 222 are waveguides that traverse the trench over the top of the mechanical supports 116 without the continuous film acting as a mechanical stability layer.

[0057] According to some examples, the method includes patterning regions for mechanical supports at block 308. In some examples, the mechanical supports can correspond to mechanical supports 116 / 216 as described above in connection with FIG. 1 through FIG. 2B. In some examples, patterning such regions can include fabrication techniques mentioned above at block 304, such as photoresist coating and / or lithography. In some examples, at block 308, a. side of the handle wafer that is opposite the side used for fabrication at block 304 can be patterned. In some examples, the side of the handle patterned at block 308 can correspond to a side containing bulk material of the handle wafer (i.e., region where minimal or no additional layers of processing have been performed).

[0058] According to some examples, the method includes etching away handle wafer to fabricate mechanical supports at block 310. In some examples, the bulk material of the handle wafer can be selectively removed in the patterned areas using any suitable removal method, such as wet etching, dry etching (e.g., plasma etching with or without reactive ion etching, deep reactive ion etching, etc.), and / or any other suitable bulk micromachining techniques. In some examples, etching can include forming a particular sidewall profile to the remaining bulk material, such as undercut sidewalls. In some examples, sidewall profiles can be controlled by etchanisotropy (or isotropy), agitation, alignment of the crystalline surface orientation (e.g., <100> surface vs. <110> surface on silicon), and / or any other suitable sidewall profiling technique.

[0059] In some examples, at block 310, any suitable amount of material can be removed. For example, a handle wafer can have a bulk thickness of several hundred microns (e.g., 725 microns), and a device layer (e.g., formed on the handle wafer) can have a thickness of several microns (e.g., 5 microns). In this example, at block 310, several hundred microns of bulk material can be removed, leaving only the device layer suspended in the regions indicated by the pattern used at block 308. In a similar example, at block 310, several hundred microns of bulk material can be removed while leaving several microns of bulk material. For example, 10 microns of material (e.g., 5 microns of bulk material and 5 microns of device layer) can be suspended in the regions indicated by the pattern used at block 308. In some examples, the amount of bulk material removed can be determined based on a desired amount of thermal leakage between a first area, of the circuit (e.g., first area. 101 / 201) and a. second area of the circuit (e.g., second area 102 / 202).

[0060] In some examples, multiple iterations of block 308 (patterning) and block 310 (bulk etching) can be performed, with slightly different patterning and removal amounts between each iteration, to create a. three-dimensionally etched structure in the bulk region of the handle wafer. In some examples, the second area can be partially supported by the bulk material, depending on the etch profiles and desired three-dimensional shape of the bulk region. In some examples, the etched areas can be re-filled with any suitable material, such as a thermally insulating material of any suitable thickness. In this particular example, the second area can be fully supported by a new material that thermally insulates the device layer from the bulk material present beneath the first area.

[0061] In some examples, at the conclusion of the method shown in flow7diagram 300, the PIC can comprise a first area having first photonic components and a second area having second photonic components, wherethe second area can be suspended by mechanical supports comprising either bulk material and / or device layers.

[0062] FIG. 4A shows a system diagram 400 of a. PIC configured and fabricated for multi-temperature operation. In some examples, system diagram 400 comprises a first area 401, a second area 402, a trench 403, mechanical supports 404, a. mechanical stability layer 405, a first thermal contact 410, and. a second thermal contact 420.

[0063] In some examples, system diagram 400 comprises a. PIC that includes a first photonic element, such as a thermal phase shifter, in the first area. 401. The first photonic element can have any suitable photonic input and / or outputs, and can in some examples have opto-electronic features, such as imparting a phase change to incoming light due to a voltage pulse applied to the photonic element that can change a refractive index of the photonic element while the voltage pulse is applied. In some examples, the first photonic element can be operable within any suitable temperature range, and can additionally have an optimal temperature range where any desired operating characteristics that linked to thermally dependent, material properties (e.g., refractive index, modulation depth, bandwidth, etc.) are optimized.

[0064] In some examples, the PIC comprises a second area with second photonic elements, such as one or more SSPD, in the second area 402. In some examples, the second photonic element can be operable at any suitable temperature and / or temperature range. As a particular example, an SSPD can be operable at 2 K. In a particular example, the second photonic element can be operable in a temperature range that is different than that of the first photonic elements. In some examples, the layout and design of the PIC can group the second photonic elements into the second area 402. In some examples, the PIC can be fabricated (using any suitable mechanism, such as flow diagram 300 described above in connection with FIG. 3) to thermally isolate the second area 402, as shown and described above in connection with FIG. 2A and FIG. 2B. In some examples, thermal isolation can be achieved using trench 403, mechanical supports 404 and mechanical stability layer 405, similar to the corresponding trench, mechanical support, andmechanical stability layers described above in connection with FIG. 1 through FIG. 2B. As shown in FIG. 4A, any suitable photonic and / or electrical connections can be made through the trench 403 and mechanical supports 404, such as connecting the second photonic element to an electronic integrated circuit (EIC). As a particular example, electrical traces can connect an output of an SSPD to an EIC for analog-to-digital conversion.

[0065] As shown in system diagram 400, operation of the PIC comprises using first thermal contact 410 and second thermal contact 420. In some examples, first thermal contact 410 can be cooled to a. range of cryogenic temperatures that can include 77 K. In some examples, second thermal contact 420 can be cooled to a range of cryogenic temperatures that can include 2 K. In some examples, as shown in FIG. 4A, second thermal contact 420 can make thermal contact to second area 402 by contacting a surface of the PIC that is opposite to where first thermal contact 410 contacts first area 401. In this particular example, second thermal contact 420 can contact the mechanical stability layer 405 on a top surface w'hen first thermal contact 410 is made on a. bottom surface. In this particular example, trench 40.3 can be continuous across second area 402 when viewed in a cross-section, such that second area 402 remains thermally isolated from first thermal contact 410.

[0066] FIG. 4B show's another system diagram 450 of a PIC configured and fabricated for multi -temperature operation. In some examples, system diagram 450 comprises a first area 451, a second area 452, a trench 453, mechanical supports 454, a. mechanical stability layer 455, a first thermal contact 460, and a second thermal contact 470.

[0067] In some examples, system diagram 450 can include a PIC that includes a. first photonic element, such as a thermal phase shifter, in the first area 451. The first photonic element can have any suitable photonic input and / or outputs, and can in some examples have opto-electronic features, such as phase control due to a voltage pulse applied to the photonic element. In some examples, the first photonic element can be operable within any suitable temperature range, and can additionally have an optimal temperaturerange w'here any desired operating characteristics (e.g., reflection / transmission coefficients, modulation depth, bandwidth, etc.) are optimized.

[0068] In some examples, the PIC comprises a second area with second photonic elements, such as one or more SSPD, in the second area 452. In some examples, the second photonic element can be operable at any suitable temperature and / or temperature range. As a particular example, an SSPD can be operable at 2 K. In a particular example, the second photonic element can be operable in a temperature range that is different than that of the first photonic elements. In some examples, the layout and design of the PIC can arrange the second photonic elements into the second area 452. In some examples, the PIC can be fabricated (using any suitable mechanism, such as flow7diagram 300 described above in connection with FIG. 3) to thermally isolate the second area. 452, as shown and described above in connection with FIG. 2 A and FIG. 2B. In some examples, thermal isolation can be achieved using trench 45.3, mechanical supports 454 and mechanical stability layer 455, similar to the corresponding trench, mechanical support, and mechanical stability layers described above in connection with FIG. 1 through FIG. 2B. As shown in FIG. 4B, any suitable photonic and / or electrical connections can be made through the trench 453 and mechanical supports 454, such as connecting the second photonic element to an EIC. As a particular example, electrical traces can connect an output of an SSPD to an EIC for analog-to-digital conversion.

[0069] As shown in system diagram 450, operation of the PIC comprises using first, thermal contact 460 and second thermal contact. 470. In some examples, first thermal contact 460 can be cooled to a range of cryogenic temperatures that can include 77 K. In some examples, second thermal contact. 470 can be cooled to a range of cryogenic temperatures that can include 2 K. In some examples, as shown in FIG. 4B, second thermal contact 470 can make thermal contact to second area 452 by contacting a surface of the PIC that is adjacent to where first thermal contact 460 contacts first area 451. In this particular example, second thermal contact 470 can contact a bottom surface of a remaining portion of a substrate of the PIC when first thermal contact 460 is made on a bottom surface. In this particular example,trench 453 comprises areas of substrate and device material that are removed during patterning and fabrication of mechanical supports 454.

[0070] FIG. 5 A and FIG. 5B show a flow diagram 500 of a method for packaging a PIC having a thermally isolated area in accordance with some embodiments, such as PIC 100 as described above in connection with FIG. 1 through FIG. 2B. / XI though the example routine depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present, disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the routine. In other examples, different components of an example device or system that implements the routine may perform functions at. substantially the same time or in a specific sequence.

[0071] According to some examples, the method includes fabricating the PIC at block 502, substantially similar to block 308 of flow diagram 300 as described above in connection with FIG 3.

[0072] According to some examples, the method, includes etching away handle wafer to fabricate mechanical supports at block 504, substantially similar to block 310 of flow diagram 300 as described above in connection with FIG 3.

[0073] According to some examples, the method includes securing first area of the PIC 100 to a chip package at block 506. In some examples, block 506 can include performing any suitable chip packaging functions, such as adding re-distribution layers to facilitation wire bonding to a PCB and performing wire bonding within the chip and / or to a PCB or other electronic circuitry' off of the chip.

[0074] According to some examples, the method includes aligning a supporting jig to the thermally isolated area of the PIC (i.e., second area 102) at block 508. In some examples, the chip package used at block 506 can have a void where the thermally isolated area of the PIC is located. In order to facilitate additional packaging operations performed on or near the thermally isolated area, any suitable mechanical supports and / or support jig(s) can be positioned, on or near the second area. In some examples, the supporting jig(s) can be positioned on the same side of the PIC as the chippackage used at block 506, as shown in the pictorial diagram accompanying block 508. In some examples, the supporting jig(s) positioned on an opposing side of the PIC as the chip package used at block 506. In some examples, the positioning of supporting jigs can be determined by the design of the cold finger and support structures, as discussed below' in FIG. 5B.

[0075] According to some examples, the method includes adding cold contact to the thermally isolated area (i.e., second area 102) at block 510. In some examples, the cold contact can be any suitable material, chosen for material properties and. behaviors at a range of temperatures. Examples of relevant material properties include thermal stability, thermal expansion coefficients, and / or thermal conductivity at cryogenic temperatures.

[0076] According to some examples, the method includes aligning a cold finger to second area at block 512. In some examples, the cold finger can be any suitable mechanical object, such as a. screw, a bundle of wires, a. small section of metal stock, etc. In some examples, the cold finger can be aligned on the same side of the PIC as the chip package used at block 506. In some examples, the cold finger can be aligned on an opposing side of the PIC as the chip package used at block 506, as shown in the pictorial diagram accompanying block 510.

[0077] According to some examples, the method includes securing second cold finger to second area, and remove support at block 514.

[0078] In some examples, any of the above blocks can be repeated when the PIC has multiple thermally isolated areas, such as PIC 700 having third area. 703 thermally isolated from second area 702. The second area 702 can itself be thermally isolated from first area 701. In some examples, each thermally isolated area can use a selection of materials with thermal properties and behaviors suitable for a desired operating temperature range. As a particular example, second area 702 can be designed to operate in a temperature range that includes 2 K, and a first set of materials can be used to contact a. first cold finger that, has adequate cooling power to cool second area 702 to 2 K. Continuing this particular example, third area 703 can be designed to operate in a temperature range from 2 K-0.5 K, and a second set. of materials (which can comprise the first set of materials) can be used tocontact a second cold finger that has adequate cooling power to cool third area 703 to 0.5 K. In some examples, multiple thermally isolated areas can operate at any combination of cryogenic temperatures.

[0079] According to some examples, the method includes continuing further assembly to first cold plate and. second cold plate at block 516.

[0080] FIG 6 shows an example flow diagram 600 of a. method for operating a PIC at two temperatures, in accordance with some embodiments. Although the example flow diagram 600 depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the flow diagram 600. In other examples, different components of an example device or system that implements the flow diagram 600 may perform functions at substantially the same time or in a specific sequence.

[0081] According to some examples, at block 602, the method includes packaging PIC on chip holder comprising a. void where the second area, of PIC can be located. In some examples, the PIC can have a first area and a second area, as described above by PIC 100, first area 101, and second area. 102 in connection with FIG. I . In some examples, packaging the PIC on a chip holder can use any suitable materials and / or methods, such as by following flow diagram 500 described above in connection with FIG. 5 A and FIG. 5B.

[0082] In some examples, at block 602, packaging the PIC on a. chip holder comprises mechanically securing the chip to the holder using any suitable adhesive materials and / or epoxies. In particular, an adhesive material can be chosen based on temperature characteristics of the adhesive material, such that the PIC can remain securely attached to the chip holder at a. range of temperatures including cryogenic temperatures reached by a first cryogenic system.

[0083] In some examples, at block 602, packaging the PIC on a. chip holder comprises making photonic and / or electronic connections to external components (e.g., wire bonding to circuit traces on a printed circuit board(PCB), coupling a fiber to a. light source, etc.). In some examples, any external components can be included on the chip holder and / or assembly including the chip holder where the PIC is packaged.

[0084] According to some examples, at block 604, the method includes securing a cold finger to the second area. In some examples, the cold finger can comprise any suitable mechanical object. In some examples, any suitable method(s) can be used to secure the component of the cold finger that contacts the second area, such as block 508 through block 514 as described in flow diagram 500 above in connection with FIG. 5 A and. FIG. 5B.

[0085] According to some examples, at block 606, the method includes completing the assembly of cold finger and packaged PIC to a second cold plate. In addition to making mechanical and thermal contact, to the second area of the PIC, the cold finger can comprise connections to additional sub assemblies that can result, in mounting the cold finger to a cold plate.

[0086] According to some examples, at block 608, the method includes attaching a first cold plate to assembly of cold finger and packaged PIC.

[0087] According to some examples, at block 610, the method includes assembling a vacuum chamber that houses the first cold plate and the second cold plate. In some examples, assembly of the vacuum chamber can include any additional components such as heaters, thermometers, additional electrical wiring, valves, inlet and / or outlet plumbing for cryogenic coolants, etc.

[0088] According to some examples, at block 612, the method includes operating a. first cryogenic system that cools the first cold plate and a. second cryogenic system that cools the second cold plate. For example, FIG. 9 shows system diagram 900 comprising dual-temperature operation of a PIC such as PIC 100.

[0089] According to some examples, the method includes using a first photonic component on the first area of the PIC at a first temperature (e.g., 77 K) determined by the first cryogenic system at block 614. In some example embodiments, components in the first area can include one or more of phase shifters, pumped ring photon sources, filters, MZIs, waveguide tapers, and / or electronics to interface with photonic components.

[0090] According to some examples, the method includes using a second photonic component on the second area of the PIC at a second temperature (e.g., below 4 K) determined by the second cryogenic system at block 616. In some example embodiments, components in the second area can include light detectors (e.g., single photon detectors) and / or control electronics to interface with detectors and electrical traces.

[0091] Note that although flow diagram 600 is an overview of operation of two regions of a PIC at two different cry ogenic temperatures, flow diagram 600 can be adapted to operate a PIC at multiple (e.g., three or more) temperatures, with a. corresponding quantity of areas of the PIC being held at the multiple temperatures. For example, as shown in FIG. 7, a PIC 700 layout can incorporate a first area 701, second area. 702, and third area. 703. .As shown in PIC 700, in some examples, first component array 710 can be located in the first area. 701, second component array 720 can be located in second area 702, and third component array 730 can be located in third area 70.3.

[0092] Similar to PIC 100, second area 702 of PIC 700, and in particular, elements of second component array 720 can be thermally isolated from first area. 701 by trench 714, mechanical connections 716, and mechanical stability layer 718. Additionally, third area 703, and in particular, any elements of third component array 730 can be thermally isolated from second area 702 and from first area 701 by trench 724, mechanical connections 726, and mechanical stability layer 718.

[0093] In some examples, first component array 710 can be substantially similar to first component array 110 in that first component array 710 can have any suitable quantity of photonic elements, can include any suitable photonic elements and / or combination of electro-optic elements, and can have an operating temperature within any suitable range. In some examples, first component array 110 can have any suitable quantity of photonic connections 712 that can send and / or receive photonic signals on and / or off of the PIC. In some examples, photonic connections 712 can additionally or alternatively include electronic connections.

[0094] In some examples, second component array 720 can be substantially similar to first component array 120 in that second component array 720 can have any suitable quantity of photonic elements, can include any suitable photonic elements and / or combination of photonic elements, and can have an operating temperature within any suitable range. In particular, an operating temperature range for second component array 720 can, in some examples, be colder than an operating temperature range for first component array 710. As a particular example, first component array 710 can operate in a temperature range of 300 K to 77 K, and second component array 720 can operate in a temperature range of 77 K to 2 K. In some examples, second component array 720 can have any suitable quantity of photonic connections 722 that can send and / or receive photonic signals to any of an area off of the PIC, first component array 710, and / or third component array 730. In some examples, photonic connections 722 can additionally or alternatively include electronic connections.

[0095] In some examples, third component array 730 can include any suitable quantity of photonic elements. In some examples, any of the photonic elements in third component array 730 can include any suitable photonic elements, such as: light source (e.g., light emitting diode, laser, single photon source, etc.), waveguide, interferometer, ring resonator, modulator, phase-shifter, amplifier, filter, splitter, multiplexing unit, demultiplexing unit, photodiode, and / or single or number-resolving photon detector (e.g., avalanche photodiode, SSPD, etc.), and / or any other suitable photonic element(s). In some examples, elements in third component array 730 can be all the same photonic element(s) or can be a combination of different photonic elements. In some examples, third component array 730 can have any suitable quantity of electronic connections 728 and / or photonic connections 732 that can send and / or receive electronic and / or photonic signals to any other electronic and / or photonic component, such as second component array 720, bond pads to off-chip circuitry, etc.

[0096] In some examples, elements of first component array 710, second component array 720, and / or third component array 730 can additionally or alternatively include any suitable electrical elements that are operative in any suitable temperature range.

[0097] For example, any of first component array 710, second component array 720, and / or third component array 730 can include superconducting qubits and associated electrical circuitry to perform state preparation, evolution, and / or readout of the superconducting qubits. The superconducting qubits can be any suitable qubit incorporating a Josephson junction, such as a phase qubit, flux qubit, charge qubit (e.g., transmon), coupled qubits, etc. The associated electrical circuitry can include any suitable radio frequency and / or microwave circuitry, such as a bias current line, readout resonators, transmission lines, busses, magnetometers, electrometers, etc. The superconducting qubits can have a. different operating temperature than portions of the associated electrical circuitry, where the superconducting qubit(s) can be operative at 1 K or sub-Kelvin, and the associated electrical circuitry' can be operative at or above 2 K.

[0098] As another example, any of first component array 710, second component array 720, and / or third component array 730 can include spin qubits and associated electrical circuitry- to perform state preparation, evolution, and / or readout of the spin qubits. The spin qubits can be any suitable qubit based on controlling a spin (or coupled spins) of a charge carrier (e.g., electron, hole, etc.) in a semiconductor device, such as lateral quantum dots formed by using electrostatic gates to confine particles in a 2- dimensional electron gas, self-assembled quantum dots which confine neutral and / or charged excitons, and / or any other suitable physical implementation of a spin qubit. The associated electrical circuitry can include any suitable radio frequency and / or microwave circuitry such as charge sensors, radio frequency reflectometry, gate sensors, cryogenic amplifiers (e.g., using Josephson junctions), transmission lines, etc.

[0099] In some examples, as shown in FIG. 7, fabrication of trench 714 and / or trench 724, mechanical connections 716 and / or 726, and mechanical stability layer 718 can follow any suitable fabrication process to remove bulk substrate material, such as that described in connection with FIG 3. In some examples, second area 702 and third area 703 can be supported by mechanical connections 716 and mechanical connections 726 respectively, which can have any suitable design, as described above in connection with mechanical supports 116 shown in FIG. 1.

[0100] In particular, mechanical connections 716 can be designed minimize thermal leakage between first area 701 and. second area 702 while providing adequate support to the mass contained in second area 702 and third area.703. Similarly, mechanical connections 726 can be designed minimize thermal leakage between second area 702 and third area 703 while providing adequate support to the mass contained in third area 703. In some examples, mechanical connections 716 and mechanical connections 726 can have a. substantially similar design, dimensions, and fabrication techniques. In some examples, mechanical connections 716 and mechanical connections 726 can have different designs, dimensions, and / or fabrication techniques.

[0101] FIG. 8 A shows an example PIC 800 comprising multiple suspended regions that are each thermally isolated from the others. In some examples, PIC 800 can include photonic and / or electrical elements that can be operated in three distinct (i.e., not overlapping) temperature ranges.

[0102] FIG 8B shows another view of PIC 800, which comprises a. first area 810, mechanical supports 815, a second area 820, mechanical supports 825, and a third area 830. In some examples, second area 820 and third area 830 are each thermally isolated from first area 810 through the removal of bulk substrate material, as described above in connection with FIG. 3. In some examples, second area 820 and. third area 830 are each thermally isolated from each other. In some examples, second area 820 and third area. 830 can each be suspended. In some examples, mechanical supports 815 can connect second area 820 to first area. 810. In some examples, mechanical supports 825 can connect third area 830 to second area 820. In some examples, although not shown in FIG. 8A and FIG. 8B, any additional features described above in connection with dual-temperature operation of a PIC (e.g., photonic and / or electronic connections) can be made to any- corresponding regions of PICs 800.

[0103] FIG. 9 shows a system diagram 900 for dual-temperature operation of a. PIC such as PIC 100. In some examples, the system can include vacuum chamber 902, first cryogenic system 904, first cold plate 906, second cryogenic system 908, second cold plate 910, and PIC 912 having cold island 914.

[0104] In some examples, first cryogenic system 904 and / or second cryogenic system 908 can be any suitable cryogenic system, and can comprise any suitable number of cryogenic sub-systems. Cryogenic systems can comprise a liquefied gas held in a vacuum flask such as helium-3, helium-4, hydrogen, neon, nitrogen, fluorine, argon, oxygen, and / or methane. Cryogenic liquid systems can additionally comprise recovery lines for capturing gaseous forms of the cryogenic coolant as the coolant boils off into the gas phase. Cryogenic systems can be a mechanical cryocooler such as Gifford-McMahon, pulse tube, and / or Stirling cryocooler. Cryogem c systems can additionally or alternatively be based on the magnetocaloric effect ("magnetic refrigeration").

[0105] In some examples, first cold plate 906 can be mounted within vacuum chamber 902 and can be cooled by first cryogenic system 904. In some examples, first cold plate 906 can contact at least a portion of PIC 912 and can provide cooling power of any suitable amount to the heat load generated by PIC 912. That is, in some examples, PIC can be cooled via first cold plate 906 to any suitable temperature related to the use of first cryogenic system 904. As a particular example, when first cryogenic system 904 uses liquid nitrogen as a coolant, then PIC 912 can be held within temperature range that includes 77 K due to contact with first cold plate 906.

[0106] In some examples, second cryogenic system 908 can provide more cooling power (e.g., to reach a lower temperature) than first cryogenic system 904. In some examples, second cryogenic system 908 can use first cryogenic system 904 as a part of the sub-systems of second cryogenic system 908 (and vice-versa). In some examples, second cold plate 910 can be mounted within vacuum chamber 902 and can be cooled by second cryogenic system 908. In some examples, second, cold plate 910 can contact at least a portion of PIC 912, such as cold island 914, and can provide cooling power of any suitable amount to the heat load generated by the portion of PIC 912 contacting second cold plate 910 (e.g., cold island 914). In some example embodiments, the first cold plate 906 is attached to a first movable mount or arm (not depicted) and the PIC 912 rests on the first cold plate 906 and the first movable mount. In some embodiments, the second cold plate 910 is attached to a second movable mount or arm that positions(e.g., suspends) the second cold plate over the PIC 912 such that components of the cold plate 910 are thermally coupled to the PIC 912 (e.g., the cold island 914).

[0107] In some examples, cold island 914 can be any suitable portion of PIC 912. For example, as described above in connection with FIG. 1, cold island 914 can correspond to second area 102 and can be a. region of PIC 100 that has components that operate at a cryogenic temperature regulated by the second cryogenic system 908. As another particular example, when second cryogenic system 908 uses liquid helium as a coolant, then cold island. 914 can be held within a temperature range that includes 2 K due to contact with second cold plate 910, where contact to cold island 914 can be made as described above in connection with FIG. 4A through FIG. 5B, and PIC 912 can be operated according to flow diagram 600 as described above in connection with FIG. 6.

[0108] FIG 10 shows an example cryogenic chamber comprising two cryogenic coolants. A cryogenic chamber can be coupled to one or more fluid conduits 1031 for the cryo-coolants. In the illustrated example, the cryogenic chamber system diagram 1040 has a liquid helium-4 vessel 1045 (e.g., tank) and a liquid nitrogen-cooled thermal shield 1050, where the thermal shield 1050 is cooled by a liquid nitrogen vessel 1052 (e.g., tank, LN2 vessel, one or more LN2 tubes), all housed under vacuum (e.g., 10'6millibar) for thermal isolation and convection mitigation. The liquid helium and liquid nitrogen are supplied from a cryoplant in some examples. The helium outlet 1030, liquid helium inlet 1032, liquid nitrogen inlet 1034, and liquid nitrogen outlet 1036 can couple the cryo-fluids into and out. of the cryogenic chamber system diagram 1040.

[0109] A helium valve 1061 (e.g., liquid helium valve) and. second helium valve 1063 (e.g., helium gas valve) may further be implemented to couple the helium into and out of the cabinet. The helium outlet 1030 is connected to a helium-4 recovery system. A Jouie-Thompson (JI’) heat exchanger 1054 and IT valve 1056 are implemented to bring the liquid helium saturation temperature to sub 4 K (e.g., enable liquid helium working at subatmosphere region, where saturation temperature is below- 4 K). In someexamples, a. cryogenic payload, such as a. metal cold head (e.g., cold plate, cold finger, etc.) is thermally connected, (e.g., thermally slagged) to a channel that circulates the liquid helium from outlet 1057 for cryogenic cooling below74 K, where the cooling the payload, the coolant returned via inlet 1059.

[0110] Example 1 is a photonic integrated circuit (PIC) comprising: a first area having first components configured to operate at a first cryogenic temperature, the first cryogenic temperature being determined by circulation of a first cryogenic coolant; a second area having second components configured to operate at a second cryogenic temperature, the second cryogenic temperature being determined by circulation of a second cryogenic coolant, the second cryogenic temperature being colder than the first cryogenic temperature; a trench formed within a substrate of the PIC, the trench separating the second area from the first area; a. signal bridge connecting the second area and the first area, the signal bridge comprising components that each cany at least, one of electrical signals and photonic signals, and at least one mechanical support structure that extends through the trench, the at least one mechanical support, structure mechanically connecting the second area and the first area.

[0111] In Example 2, the subject matter of Example 1 includes, wherein the trench formed within the substrate thermally isolates the second area, from the first area.

[0112] In Example 3, the subject matter of Examples 1-2 includes, wherein the at least one mechanical support structure comprises circular traces of substrate material that remain within the trench after the trench is etched through the substrate.

[0113] In Example 4, the subject matter of Examples 2 ---3 includes, wherein the at least one mechanical support structure additionally comprises a continuous film covering a first portion of the first area and a second portion of the second area, wherein the continuous film is formed from thermally insulating material.

[0114] In Example 5, the subject matter of Examples 1-4 includes, wherein the first components comprise a photonic element selected, from one of a light source and a waveguide.

[0115] In Example 6, the subject matter of Examples 1-5 includes, wherein the second components comprise a superconducting detector element.

[0116] In Example 7, the subject matter of Example 6 includes, wherein the signal bridge further comprises electrical connections to at least one element in the superconducting detector element.

[0117] In Example 8, the subject matter of Examples 1-7 includes, wherein the first cryogenic coolant comprises liquid nitrogen, and wherein the second cryogenic coolant comprises liquid helium.

[0118] In Example 9, the subject matter of Examples 1-8 includes, wherein the first cryogenic coolant comprises liquid helium; and wherein the second cryogenic coolant comprises a mixture of helium isotopes.

[0119] In Example 10, the subject matter of Examples 2-9 includes, a third area having third components configured to operate at a third cryogenic temperature, wherein the third cryogenic temperature is determined bycirculation of a third cryogenic coolant, the third cryogenic temperature being colder than the second cryogenic temperature; a second signal bridge connecting the third area and the second area, the second signal bridge comprising components that each carry at least one of electrical signals and photonic signals; and at least one mechanical support structure that extends through the trench, the at least one mechanical support mechanically connecting the third area and the second area, wherein the trench etched through the substrate additionally thermally isolates the third area from the second area.

[0120] In Example 11 , the subject matter of Example 10 includes, wherein the first cryogenic coolant comprises liquid nitrogen; and wherein the second cryogenic coolant comprises liquid helium; wherein the third cryogenic coolant comprises a mixture of helium isotopes.

[0121] In Example 12, the subject matter of Examples 10-11 includes, wherein the second cryogenic coolant comprises liquid nitrogen; wherein the third cryogenic coolant comprises liquid helium.

[0122] In Example 13, the subject matter of Examples 2-12 includes, a third area having third, components configured to operate at a third temperature that is warmer than the first, cryogenic temperature, a second signal bridge connecting the third area and the first area, the second signal bridge comprising components that carry at least, one of electrical and photonic signals; and at least one mechanical support structure that extends through the trench, the at least one mechanical support structure mechanically connecting the third area and the first area, wherein the trench formed within the substrate separates and thermally isolates the third area from the first area.

[0123] Example 14 is a method for operating a photonic integrated circuit (PIC) having a first, area and a second area that is thermally isolated from the first area through a trench, the method comprising: packaging the PIC on a first chip holder, the first chip holder mechanically connecting to the first area and being mechanically unconnected to the second area; securing a cold finger to the second area; attaching the first chip holder to a first cold plate that is configured to operate in a vacuum chamber with a first, cryogenic system; attaching the cold finger to a second cold plate that is configured to operate in the vacuum chamber with a second cryogenic system; assembling the vacuum chamber that houses the first cold plate and. the second cold plate; operating a first component at a first cryogenic temperature determined by operation of the first cryogenic system, the first component being located within the first area of the PIC; and operating a second component at a second cryogenic temperature determined by operation of the second cryogenic system, the second component being located within the second area of the PIC.

[0124] In Example 15, the subject matter of Example 14 includes, wherein operating the second component, at the second cryogenic temperature determined by operation of the second, cryogenic system further comprises: receiving a first, signal at. the second component, that is from the first, component, wherein the first signal is routed through a signal connection that spans the trench; and receiving a second signal at a third component that is located within at least one of the first area and the first chip holder, wherein the second signal is from the second component and is generatedwhile the second component is operated at the second cryogenic temperature, wherein the second signal is routed through the signal connection that spans the trench.

[0125] In Example 16, the subject matter of Examples 14—15 includes, packaging a second PIC having the first area and the second area that is thermally isolated from the first area, through the trench on a third chip holder, wherein the third, chip holder mechanically connects to the first area and is mechanically unconnected to the second area, wherein the second PIC is distinct from the PIC on the first chip holder; securing a second cold finger to the second area of the second PIC; attaching the third chip holder to a third cold plate that is configured to operate in a second vacuum chamber with the first cryogenic system; attaching the second cold finger to a. fourth cold plate that is configured to operate in the second vacuum chamber with the second cryogenic system; assembling the second vacuum chamber that, houses the third cold plate and the fourth cold plate; operating a third component at the first cryogenic temperature determined by operation of the first cryogenic system, wherein the third component, is located within the first area of the second PIC, and operating a fourth component at the second cryogenic temperature determined by operation of the second cryogenic system, wherein the fourth component is located within the second area of the second PIC

[0126] Example 17 is a method of manufacturing a photonic integrated circuit (PIC) having a first area and a second area that is thermally isolated from the first area, the method comprising: preparing a substrate; fabricating a device layer using the substrate, the device layer comprising a first array of components in a first area of the PIC and a second array of components in a second, area of the PIC; fabricating a thermally insulating layer over the second area of the PIC; patterning a side of the substrate opposite to the device layer; and forming a trench by performing at least one bulk micromachining technique to remove substrate material, after forming the trench, the second area of the PIC being separated and thermally insulated from the first area of the PIC.

[0127] In Example 18, the subject matter of Example 17 includes, the second area is suspended by mechanical supports within the trench, wherein the mechanical supports comprise at least one of the device layer and the substrate material, wherein the mechanical supports are defined by patterning the side of the substrate opposite to the device layer.

[0128] In Example 19, the subject matter of Examples 17 -18 includes, wherein the thermally insulating layer over the second area of the PIC extends across the trench and covers a portion of the first area.

[0129] In Example 20, the subject matter of Examples 17—19 includes, wherein at least one component in the second array of components is connected to at least one component in the first array of components by a signal element fabricated in the device layer, wherein the signal element spans the trench.

[0130] Example 21 is an apparatus comprising means to implement of any of Examples 1-20.

[0131] Example 22 is a system to implement of any of Examples 1-20.

[0132] Example 23 is a method to implement of any of Examples 1-20.

[0133] As used herein, a computer-readable storage medium refers, for example, to both machine-storage media and transmission media. Thus, the terms include both storage devices / media and carrier waves / modulated data signals. The terms "machine-readable medium," "computer-readable medium” and "device-readable medium" mean the same thing and may be used interchangeably in this disclosure.

[0134] As used herein, a machine storage medium refers, for example, to a single or multiple storage devices and media (e.g., a centralized or distributed, database, and associated caches and servers) that store executable instructions, routines and data. The term shall accordingly be taken to include, but not be limited to, solid-state memories, and. optical and magnetic media, including memory internal or external to processors. Specific examples of machine-storage media, computer- storage media and. devicestorage media include non-volatile memory, including by way of example semiconductor memory devices, e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory(EEPROM), FPGA, and flash memory devices, magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD- ROM and DVD-ROM disks. The terms "machine-storage medium,” “devicestorage medium," "computer-storage medium" mean the same thing and may be used interchangeably in this disclosure. The terms "machine-storage media," "computer-storage media," and "device-storage media" specifically exclude carrier waves, modulated data signals, and other such media.

[0135] As used herein, a non-transitory computer-readable storage medium refers, for example, to a tangible medium that is capable of storing, encoding, or carrying the instructions for execution by a machine.

[0136] It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first cold plate could be termed a second cold plate, and, similarly, a second cold plate could be termed a first cold plate, without departing from the scope of the various described embodiments. The first cold plate and the second cold plate are both cold plates, but they are not the same cold plate.

[0137] The terminology used in the description of the various described embodiments herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used in the description of the vari ous described embodiments and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0138] As used herein, the term "if" is, optionally, construed to mean "when" or "upon" or "in response to determining" or "in response todetecting" or "in accordance with a determination that," depending on the context.

[0139] The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen in order to best explain the principles underlying the claims and their practical applications, to thereby enable others skilled, in the art to best use the embodiments with various modifications as are suited to the particular uses contemplated.

Claims

CLAIMSWhat is claimed is:

1. A photonic integrated circuit (PIC) comprising: a first area having first components configured to operate at a first cryogenic temperature, the first cryogenic temperature being determined by circulation of a first cryogenic coolant; a second area having second components configured to operate at a second cryogenic temperature, the second cryogenic temperature being determined by circulation of a second cryogenic coolant, the second, cryogenic temperature being colder than the first cryogenic temperature; a trench formed within a substrate of the PIC, the trench separating the second area from the first area; a signal bridge connecting the second area and the first area, the signal bridge comprising components that each carry at least one of electrical signals and photonic signals; and at least one mechanical support, structure that extends through the trench, the at least one mechanical support structure mechanically connecting the second area and the first area.

2. The PIC of claim 1, wherein the trench formed within the substrate thermally isolates the second area from the first area.

3. The PIC of claim 1, wherein the at least one mechanical support structure comprises circular traces of substrate material that remain within the trench after the trench is etched through the substrate.

4. The PIC of claim 2, wherein the at least one mechanical support, structure additionally comprises a continuous film covering a first portion of the first area and a second portion of the second area, wherein the continuous film is formed from thermally insulating material.

5. The PIC of claim 1, wherein the first components comprise a photonic element selected from one of a light source and a waveguide.

6. The PIC of claim 1, wherein the second components comprise a superconducting detector element.

7. The PIC of claim 6, wherein the signal bridge further comprises electrical connections to at least one element in the superconducting detector element.

8. The PIC of claim 1, wherein the first cryogenic coolant comprises liquid nitrogen; and wherein the second cryogenic coolant comprises liquid helium.

9. The PIC of claim 1, wherein the first cryogenic coolant comprises liquid helium; and wherein the second cryogenic coolant comprises a mixture of helium isotopes.

10. The PIC of claim 2, further comprising: a third area having third components configured to operate at a third, cryogenic temperature, wherein the third cryogenic temperature is determined by circulation of a third cryogenic coolant, the third cryogenic temperature being colder than the second cryogenic temperature; a second signal bridge connecting the third area and the second area, the second signal bridge comprising components that each carry at least one of electrical signals and photonic signals; and at least one mechanical support structure that extends through the trench, the at least one mechanical support mechanically connecting the third area, and the second area, wherein the trench etched through the substrate additionally thermally isolates the third area from the second area.11 . The PIC of claim 10, wherein the first cryogenic coolant comprises liquid, nitrogen; and wherein the second cryogemc coolant comprises liquid helium; wherein the third cryogenic coolant comprises a mixture of helium isotopes.

12. The PIC of claim 10, wherein the second cryogenic coolant comprises liquid nitrogen; wherein the third cryogenic coolant comprises liquid helium.

13. The PIC of claim 2, further comprising: a third area having third components configured to operate at a third temperature that is warmer than the first cryogenic temperature, a second signal bridge connecting the third area and the first area, the second signal bridge comprising components that carry at least one of electrical and photonic signals; and at least one mechanical support structure that extends through the trench, the at least, one mechanical support, structure mechanically connecting the third area and the first area, wherein the trench formed, within the substrate separates and thermally isolates the third area from the first area.

14. A method for operating a photonic integrated circuit (PIC) having a first area, and a second area, that is thermally isolated from the first, area through a trench, the method comprising: packaging the PIC on a first chip holder, the first chip holder mechanically connecting to the first area and being mechanically unconnected to the second area; securing a cold finger to the second area; attaching the first chip holder to a first cold plate that is configured to operate in a vacuum chamber with a first cryogenic system; attaching the cold finger to a second cold plate that is configured to operate in the vacuum chamber with a. second cryogenic system; assembling the vacuum chamber that houses the first cold plate and the second cold plate; operating a first component at a first cryogenic temperature determined by operation of the first cryogenic system, the first component being located within the first area of the PIC; and operating a second component at a second cryogenic temperature determined by operation of the second cryogenic system, the second component being located within the second area of the PIC.

15. The method of claim 14, wherein operating the second component at the second cryogenic temperature determined by operation of the second cryogenic system further comprises: receiving a first signal at the second component that is from the first component, wherein the first signal is routed through a signal connection that spans the trench; and receiving a second signal at a third component that is located within at least one of the first area and the first chip holder, wherein the second signal is from the second component and is generated while the second component is operated at the second cryogenic temperature, wherein the second signal is routed through the signal connection that spans the trench.

16. The method of claim 14, further comprising: packaging a second PIC having the first area and the second area that is thermally isolated from the first area through the trench on a third chip holder, wherein the third chip holder mechanically connects to the first area, and is mechanically unconnected to the second area, wherein the second PIC is distinct from the PIC on the first chip holder; securing a second cold finger to the second area of the second PIC; attaching the third chip holder to a third cold plate that is configured to operate in a second vacuum chamber with the first cryogenic system; attaching the second cold finger to a fourth cold plate that is configured to operate in the second vacuum chamber with the second cryogenic system; assembling the second vacuum chamber that houses the third cold plate and the fourth cold plate; operating a third component at the first cryogenic temperature determined by operation of the first cryogenic system, wherein the third component is located within the first area, of the second PIC, and operating a fourth component at the second cryogenic temperature determined by operation of the second cryogenic system, wherein the fourth component is located within the second area of the second PIC.

17. A method of manufacturing a photonic integrated circuit (PIC) having a first area and a second area that is thermally isolated from the first area, the method comprising: preparing a substrate; fabricating a. device layer using the substrate, the device layer comprising a first array of components in a first area of the PIC and a second array of components in a second area of the PIC; fabricating a thermally insulating layer over the second area of thePIC; patterning a. side of the substrate opposite to the device layer; and forming a trench by performing at least one bulk micromachining technique to remove substrate material, after forming the trench, the second area of the PIC being separated and thermally insulated from the first area of the PIC.

18. The method of claim 17, the second area is suspended by mechanical supports within the trench, wherein the mechanical supports comprise at least one of the device layer and the substrate material, wherein the mechanical supports are defined by patterning the side of the substrate opposite to the device layer.

19. The method of claim 17, wherein the thermally insulating layer over the second area of the PIC extends across the trench and covers a. portion of the first area.

20. The method of claim 17, wherein at least one component in the second array of components is connected, to at least one component in the first array of components by a signal element fabricated in the device layer, wherein the signal element spans the trench.

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