Touch display panel and touch display apparatus

Abstract

A touch display panel and a touch display apparatus. The touch display panel comprises a driving backplane, light-emitting devices, an encapsulation layer and a touch layer. The driving backplane comprises a plurality of pixel circuits, a plurality of data lines and a plurality of power lines, wherein the pixel circuits are distributed in a first direction and a second direction; the data lines and the power lines extend in the second direction and are distributed in the first direction; one data line is connected to at least one column of pixel circuits, and the data line is used for writing a data signal to the pixel circuits connected thereto; one power line is connected to at least one column of pixel circuits, and the power line is used for transmitting a first power signal to the pixel circuits connected thereto; the light-emitting devices are arranged on one side of the driving backplane, and each comprise a first electrode, a light-emitting layer, and a second electrode which are distributed in a direction away from the driving backplane; one first electrode is connected to one pixel circuit, and one data line overlaps with at least one first electrode; the encapsulation layer covers each light-emitting device; and the touch layer is arranged on the side of the encapsulation layer away from the driving backplane.

Description

Touch display panel and touch display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a touch display panel and a touch display device. Background Technology

[0002] Touch display panels can display images and enable human-computer interaction, and are therefore widely used. However, when displaying images, sometimes scrolling stripes similar to water ripples appear, especially in dimly lit environments such as indoors, where the stripes are more noticeable and affect the display effect.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0004] Summary of the Invention

[0005] This disclosure provides a touch display panel and a touch display device.

[0006] According to one aspect of this disclosure, a touch display panel is provided, comprising:

[0007] A driving backplane includes multiple pixel circuits, multiple data lines, and multiple power lines. The pixel circuits are distributed along a first direction and a second direction. Each of the data lines and the power lines extends along the second direction and is distributed along the first direction. One data line is connected to at least one column of the pixel circuits and is used to write data signals to the pixel circuits connected to it. One power line is connected to at least one column of the pixel circuits and is used to transmit a first power signal to the pixel circuits connected to it.

[0008] Multiple light-emitting devices are disposed on one side of the driving backplate, and each light-emitting device includes a first electrode, a light-emitting layer, and a second electrode distributed in a direction away from the driving backplate; a first electrode is connected to a pixel circuit, and a data line overlaps with at least one first electrode;

[0009] An encapsulation layer covers each of the light-emitting devices;

[0010] The touch layer is located on the side of the encapsulation layer away from the drive backplane.

[0011] In one exemplary embodiment of this disclosure, the touch display panel further includes:

[0012] Multiple shielding structures are disposed between the second electrode and the data line, and overlap with at least a portion of the data line.

[0013] In one exemplary embodiment of this disclosure, the power lines and the data lines are alternately distributed along the first direction; the shielding structure is disposed at intervals in the same layer as the first electrode; at least one of the shielding structures overlaps with the power lines and data lines connected to the same column of the pixel circuits, and the shielding structure is connected to the power lines it overlaps with.

[0014] In one exemplary embodiment of this disclosure, the shielding structure is disposed in the same layer as the first electrode, and the shielding structure is connected to the first electrode.

[0015] In one exemplary embodiment of this disclosure, the shielding structure extends along the second direction, and one of the shielding structures overlaps with one of the data lines; the boundary of one of the shielding structures in the first direction is at least partially located outside the boundary of the data line it overlaps with.

[0016] In one exemplary embodiment of this disclosure, at least one of the following is not less than 2 μm: the spacing between two adjacent shielding structures, the spacing between the shielding structure and the nearest first electrode, and the spacing between two adjacent first electrodes.

[0017] In one exemplary embodiment of this disclosure, in the first direction, the distance between the center of a data line and the center of the first electrode that overlaps with it is less than the distance to the boundary of the first electrode.

[0018] In one exemplary embodiment of this disclosure, each of the light-emitting devices shares the same second electrode, and the second electrode is provided with a plurality of hollowed-out gaps that overlap with the data line.

[0019] In one exemplary embodiment of this disclosure, the perforated slits extend along the second direction, and one of the data lines overlaps with a plurality of perforated slits spaced apart along the second direction.

[0020] In one exemplary embodiment of this disclosure, the region of the second electrode located between two adjacent perforated slots in the second direction overlaps with the first electrode.

[0021] In one exemplary embodiment of this disclosure, the second electrode is a mesh structure connected by a plurality of electrode portions and connecting portions, and any two adjacent electrode portions are connected by the connecting portions; one electrode portion overlaps with one first electrode.

[0022] In one exemplary embodiment of this disclosure, the orthographic projection of the electrode portion on the drive backplate is at least partially located outside the orthographic projection of the first electrode overlapping with it on the drive backplate.

[0023] In one exemplary embodiment of this disclosure, the pixel circuit includes a plurality of transistors; a first electrode overlaps with at least one of the transistors.

[0024] In one exemplary embodiment of this disclosure, the power cord includes a cord body and a protrusion, the cord body extending along the second direction, the protrusion being distributed along the first direction and connected to the cord body; one of the protrusions overlaps with at least one of the first electrodes.

[0025] In one exemplary embodiment of this disclosure, the drive backplane includes:

[0026] A photosensitive element is disposed on the side of the power line away from the light-emitting device;

[0027] At least one of the protrusions is provided with a light-transmitting hole, and the light-transmitting hole does not overlap with any of the transistors.

[0028] In one exemplary embodiment of this disclosure, the pixel circuit includes a plurality of transistors; at least one first electrode includes an electrode body and a connecting portion extending outward from the electrode body, the connecting portion being connected to the pixel circuit; at least a portion of the first electrode further includes an extension portion extending outward from the electrode body, at least one of the extension portions overlapping at least one of the transistors.

[0029] In one exemplary embodiment of this disclosure, at least one extension overlaps with the data line.

[0030] In one exemplary embodiment of this disclosure, the drive backplane includes:

[0031] Substrate;

[0032] A transistor layer is disposed on one side of the substrate and includes each transistor of the pixel circuit;

[0033] A first source / drain layer is disposed on the side of the transistor layer away from the substrate and is connected to at least a portion of the transistors;

[0034] The second source / drain layer is disposed on the side of the first source / drain layer away from the substrate, and includes the power line and the data line.

[0035] According to one aspect of this disclosure, a touch display panel is provided, comprising:

[0036] A driving backplane includes multiple pixel circuits, multiple data lines, and multiple power lines. The pixel circuits are distributed along a first direction and a second direction. Each of the data lines and the power lines extends along the second direction and is distributed along the first direction. One data line is connected to at least one column of the pixel circuits and is used to write data signals to the pixel circuits connected to it. One power line is connected to at least one column of the pixel circuits and is used to transmit a first power signal to the pixel circuits connected to it.

[0037] Multiple light-emitting devices are disposed on one side of the driving backplate, and each light-emitting device includes a first electrode, a light-emitting layer, and a second electrode distributed in a direction away from the driving backplate; a first electrode is connected to a pixel circuit.

[0038] Multiple shielding structures are disposed between the second electrode and the data line, and overlap with at least a portion of the data line;

[0039] An encapsulation layer covers each of the light-emitting devices;

[0040] The touch layer is located on the side of the encapsulation layer away from the drive backplane.

[0041] In one exemplary embodiment of this disclosure, the power lines and the data lines are alternately distributed along the first direction; the shielding structure is disposed at intervals in the same layer as the first electrode; at least one of the shielding structures overlaps with the power lines and data lines connected to the same column of the pixel circuits, and the shielding structure is connected to the power lines it overlaps with.

[0042] In one exemplary embodiment of this disclosure, the shielding structure is disposed in the same layer as the first electrode, and the shielding structure is connected to the first electrode.

[0043] In one exemplary embodiment of this disclosure, the shielding structure extends along the second direction, and one of the shielding structures overlaps with one of the data lines; the boundary of one of the shielding structures in the first direction is at least partially located outside the boundary of the data line it overlaps with.

[0044] According to one aspect of this disclosure, a touch display panel is provided, comprising:

[0045] A driving backplane includes multiple pixel circuits, multiple data lines, and multiple power lines. The pixel circuits are distributed along a first direction and a second direction. Each of the data lines and the power lines extends along the second direction and is distributed along the first direction. One data line is connected to at least one column of the pixel circuits and is used to write data signals to the pixel circuits connected to it. One power line is connected to at least one column of the pixel circuits and is used to transmit a first power signal to the pixel circuits connected to it.

[0046] Multiple light-emitting devices are disposed on one side of the driving backplate, and each light-emitting device includes a first electrode, a light-emitting layer, and a second electrode distributed in a direction away from the driving backplate; a first electrode is connected to a pixel circuit; each light-emitting device shares the same second electrode, and the second electrode has multiple hollow areas that overlap with the data line;

[0047] An encapsulation layer covers each of the light-emitting devices;

[0048] The touch layer is located on the side of the encapsulation layer away from the drive backplane.

[0049] In one exemplary embodiment of this disclosure, the cutout area is a slit extending along the second direction, and one of the data lines overlaps with a plurality of cutout areas spaced apart along the second direction; the region of the second electrode located between two adjacent cutout areas in the second direction overlaps with the first electrode.

[0050] In one exemplary embodiment of this disclosure, the second electrode is a mesh structure connected by multiple electrode portions and connecting portions, and a hollow area is surrounded by multiple electrode portions and connecting portions; any two adjacent electrode portions are connected by the connecting portions; an electrode portion overlaps with a first electrode.

[0051] According to one aspect of this disclosure, a touch display device is provided, comprising the touch display panel described in any one of the preceding claims.

[0052] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0053] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0054] Figure 1 is a schematic diagram of one embodiment of the touch display panel of this disclosure.

[0055] Figure 2 is a partial cross-sectional view of one embodiment of the touch display panel of this disclosure.

[0056] Figure 3 is a schematic diagram of the pixel circuit in one embodiment of the touch display panel of this disclosure.

[0057] Figure 4 is a first partial top view of one embodiment of the touch display panel of this disclosure.

[0058] Figure 5 is a partial top view of the light-shielding layer and semiconductor layer in Figure 4.

[0059] Figure 6 is a partial top view of the light-shielding layer to the first gate layer in Figure 4.

[0060] Figure 7 is a partial top view of the light-shielding layer to the second gate layer in Figure 4.

[0061] Figure 8 is a partial top view of the light-shielding layer to the first source / drain layer in Figure 4.

[0062] Figure 9 is a partial top view of the light-shielding layer to the second source / drain layer in Figure 4.

[0063] Figures 10-15 are top views of each single layer of the film in Figure 4.

[0064] Figure 16 is a second partial top view of one embodiment of the touch display panel of this disclosure.

[0065] Figure 17 is a partial top view of the light-shielding layer to the first gate layer in Figure 16.

[0066] Figure 18 is a partial top view of the light-shielding layer to the second gate layer in Figure 16.

[0067] Figure 19 is a partial top view of the light-shielding layer to the first source / drain layer in Figure 16.

[0068] Figure 20 is a partial top view of the light-shielding layer to the second source / drain layer in Figure 16.

[0069] Figure 21 is a partial top view of the second source / drain layer and the first electrode in Figure 16.

[0070] Figures 22-27 are single-layer top views of each film layer in Figure 16.

[0071] Figure 28 is a partial top view of the first electrode in Figure 16.

[0072] Figure 29 is a schematic diagram of a first type of embodiment of the touch display panel of this disclosure.

[0073] Figure 30 is a schematic diagram of another embodiment of the first type of touch display panel of this disclosure.

[0074] Figure 31 is a schematic diagram of a second type of embodiment of the touch display panel of this disclosure.

[0075] Figure 32 is a top view of the first electrode in Figure 31.

[0076] Figure 33 is a schematic diagram of another embodiment of the second type of touch display panel of this disclosure.

[0077] Figure 34 is a top view of the first electrode in Figure 33.

[0078] Figure 35 is a schematic diagram of another embodiment of the second type of touch display panel disclosed herein.

[0079] Figure 36 is a top view of the first electrode in Figure 35.

[0080] Figure 37 is a schematic diagram of a third type of embodiment of the touch display panel of this disclosure.

[0081] Figure 38 is a top view of the second electrode in Figure 37.

[0082] Figure 39 is a schematic diagram of the fourth type of embodiment of the touch display panel of this disclosure.

[0083] Figure 40 is a top view of the first electrode in Figure 39.

[0084] Figure 41 is a partial top view of the pixel openings and touch layer in one embodiment of the touch display panel of this disclosure. Detailed Implementation

[0085] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0086] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0087] In this document, the first direction X and the second direction Y are two intersecting directions. They can be perpendicular to each other or form an angle that is not a right angle. In the accompanying drawings of this disclosure, the first direction X is horizontal and the second direction Y is vertical, but this is not a limitation. Those skilled in the art will know that if the touch display panel is rotated, the actual orientation of the first direction X and the second direction Y may change accordingly.

[0088] In this article, the "overlap" of features A and B means that the orthographic projections of feature A and feature B onto a plane at least partially coincide. Orthographic projection refers to projection onto the plane along a direction perpendicular to the plane. This plane can be any surface of the touch display panel perpendicular to the light emission direction, such as the surface of a substrate, driving backplate, etc.

[0089] In this article, "same layer setting" means that A and B belong to different regions that are continuous or discontinuous within the same film layer, and each region can be formed simultaneously; "different layers" means that A and B belong to different film layers, and different film layers refer to film layers that are formed at different times.

[0090] The transistor described in this article includes a gate, a first terminal, and a second terminal. The conduction and cutoff between the first and second terminals can be achieved by controlling the voltage of the gate. The first terminal can be the source, and the second terminal can be the drain; of course, the first terminal can also be the drain, and the second terminal can also be the source. Specifically, if the input signal is from the first terminal, then the first terminal is the source, and the second terminal is the drain; if the input signal is from the second terminal, then the second terminal is the source, and the first terminal is the drain. In other words, the source and drain can be interchanged depending on the change in the input signal.

[0091] For a P-type transistor, when the gate receives a high level, both the first and second terminals are turned off; when the gate receives a low level, both the first and second terminals are turned on. For an N-type transistor, when the gate receives a high level, both the first and second terminals are turned on; when the gate receives a low level, both the first and second terminals are turned off.

[0092] This disclosure provides a touch display panel, as shown in FIG1, which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA, or it may be a discontinuous area surrounding the display area AA, for example, the peripheral area WA may be distributed on both sides of the display area AA. The display area AA may be used to emit light to display images, while the peripheral area WA may not emit light.

[0093] As shown in Figure 2, the touch display panel may include a driving backplane BP, a light-emitting device LD, an encapsulation layer TFE, and a touch layer TL. The light-emitting device LD is located on one side of the driving backplane BP and emits light under the drive of the driving backplane BP. The encapsulation layer TFE covers the light-emitting device LD to protect it from external water, oxygen, and other impurities. The touch layer TL is located on the side of the encapsulation layer TFE away from the driving backplane BP and is used to sense touch operations to realize human-computer interaction. The following is a detailed description of each part:

[0094] The driving backplane (BP) has a driving circuit that drives the light-emitting diode (LD) to emit light to display an image. In some embodiments of this disclosure, the driving backplane (BP) may include a substrate (SU) and a circuit layer located on one side of the substrate (SU). The substrate (SU) may be a flat plate structure, and its material may be a rigid material such as glass or a flexible material such as polyimide. Furthermore, the substrate (SU) may be a single-layer or multi-layer structure.

[0095] The circuit layer includes the aforementioned driving circuitry. For example, the driving circuitry may include pixel circuitry located in the display area AA and peripheral circuitry located in the peripheral area WA. The pixel circuitry can be of structures such as 3T1C, 7T1C, or 8T1C, as long as it can drive the light-emitting diodes (LDs) to emit light. No special limitations are placed on its structure here. Here, nTmC indicates that one pixel circuit includes n thin-film transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). The number of pixel circuits can be the same as the number of light-emitting diodes (LDs), and they are connected one-to-one with each LD. Of course, multiple LDs can be connected to the same pixel circuit; no special limitations are placed here.

[0096] The peripheral circuit is connected to the pixel circuit and is used to input driving signals to the pixel circuit in order to control the light-emitting device (LD) to emit light. The peripheral circuit may include a gate driving circuit and a light-emitting control circuit, and of course, it may also include other circuits. The specific structure of the peripheral circuit is not specifically limited here.

[0097] The following explanation uses a pixel circuit with a 7T1C structure as an example:

[0098] As shown in Figure 3, the pixel circuit has 7 transistors and 1 storage capacitor, namely, the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the storage capacitor Cst.

[0099] As shown in Figure 3, the first terminal of the first reset transistor T1 is connected to the first reset signal line VIL1 to receive the first reset signal Vinit1, and the second terminal is connected to the gate of the driving transistor T3 and the first plate of the storage capacitor Cst, for example, connected to the N node; the first reset signal Vinit1 can be transmitted to the gate of the driving transistor T3 and the first plate of the storage capacitor through the first reset transistor T1.

[0100] The first terminal of the write transistor T4 is connected to the data line DAL to receive the data signal DA, and the second terminal is connected to the first terminal of the drive transistor T3, for example, at node N2. In other words, the pixel circuit is connected to the data line DAL through the first terminal of the write transistor T4.

[0101] The first terminal of the compensation transistor T2 is connected to the second terminal of the driving transistor T3, for example, at node N3. The second terminal of the compensation transistor T2 is connected to the gate of the driving transistor T3. The gate and the second terminal of the driving transistor T3 can be connected through the compensation transistor T2.

[0102] The first terminal of the first light-emitting control transistor T5 and the second terminal of the storage capacitor Cst are connected to the power line VDL to receive the first power signal VDD. The second terminal is connected to the first terminal of the driving transistor T3, for example, at node N2, so that the power line VDL is connected to the first terminal of the driving transistor T3 through the first light-emitting control transistor T5.

[0103] The first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the first electrode ANO of a light-emitting device LD, for example, at node N4, thereby connecting the second electrode of the driving transistor T3 and the light-emitting device LD through the second light-emitting control transistor T6.

[0104] The first electrode of the second reset transistor T7 is connected to the second reset signal line VIL2 to receive the second reset signal Vinit2. Its second electrode is connected to the first electrode ANO of the light-emitting device LD and the second electrode of the light-emitting control transistor T6, for example, at node N4. The second electrode CAT of the light-emitting device LD can receive the second power supply signal VSS.

[0105] Simultaneously, to control the on / off state of each transistor, the gate of the first reset transistor T1 is connected to the first reset control line REL1 to input the first reset control signal RE1; the gate of the second reset transistor T7 is connected to the second reset control line REL2 to input the second reset control signal RE2. The gates of the compensation transistor T2 and the write transistor T4 are connected to the scan line GL to input the scan signal GA; the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control line EML to input the light-emitting control signal EM. This pixel circuit PC can be used to drive the connected light-emitting device LD to emit light in response to the signals provided by the connected signal lines.

[0106] The working principle of the pixel circuit PC described below is explained using the example of P-type low-temperature polysilicon transistors:

[0107] During the reset phase: The first reset control signal RE1 is low, turning on the first reset transistor T1. The gate of the driving transistor T3 and the first plate of the storage capacitor Cst are written with the reset signal Vinit1, resetting node N1 and eliminating the influence of the previous frame. Simultaneously, the second reset control signal RE2 is low, turning on the second reset transistor T7. The first electrode ANO of the light-emitting device LD and the second electrode of the light-emitting control transistor T6 are written with the second reset signal Vinit2, resetting node N4 and initializing it, eliminating the influence of the data from the previous frame.

[0108] In some embodiments of this disclosure, node N1 of the nth row pixel circuit is connected to the nth first reset control line REL1 and receives the first reset control signal RE1 output by the nth first reset control line REL1; node N4 of the nth row pixel circuit is connected to the (n+1)th first reset control line REL1 and receives the first reset control signal RE1 output by the (n+1)th first reset control line REL1, so that the reset of node N1 of the nth row pixel circuit and the reset of node N4 of the (n+1)th row pixel circuit are performed simultaneously.

[0109] During the write phase: the scan signal GA is low, which turns on the write transistor T4 and the compensation transistor T2, writing the data signal DA to the gate of the driving transistor T3 and the first plate Cst1 of the storage capacitor Cst. That is, the data signal DA is written to node N1 through nodes N2 and N3 until the potential of node N1 reaches Vdata + Vth. Here, Vdata is the voltage of the data signal DA, and Vth is the threshold voltage of the driving transistor T3. The scan signal GA for the write transistor T4 and the compensation transistor T2 can be the same signal.

[0110] During the light-emitting stage: the light-emitting control signal EM is low, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the driving transistor T3 is turned on under the action of the voltage Vdata+Vth stored in the storage capacitor Cst and the first power supply signal VDD. At this time, the light-emitting device LD emits light. It should be noted that resetting the N4 node can also be performed during the writing stage, as long as it is before the light-emitting stage.

[0111] The output current of the driving transistor T3 satisfies the following formula: I=(μWCox / 2L)(Vgs-Vth) 2

[0112] Where I is the output current of driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the channel of driving transistor T3; L is the channel length of driving transistor T3; Vgs is the gate-source voltage difference of driving transistor T3 (the voltage difference between the gate and the source (first electrode)); and Vth is the threshold voltage of driving transistor T3.

[0113] Based on the formula for the output current of the driving transistor T3, substituting the gate voltage Vdata+Vth and the source voltage (voltage of the first power supply signal) VDD of the driving transistor T3 in the pixel circuit of this disclosure into the formula, we can obtain: the output current of the driving transistor T3 I=(μWCox / 2L)(Vdata+Vth-VDD-Vth) 2 It can be seen that the output current of this pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thus eliminating the influence of the threshold voltage of the driving transistor T3 on its output current. The output current can be controlled solely by the voltage Vdata of the data signal DA, so as to control the brightness of the light-emitting device LD.

[0114] Furthermore, each transistor in the pixel circuit in the above embodiments may be a P-type transistor using a low-temperature polysilicon process. However, based on the description and teachings of this disclosure, those skilled in the art can easily conceive of using N-type transistors, i.e., using N-type transistors or a combination of N-type and P-type transistors, in the pixel circuit PC structure of the embodiments of this disclosure without any creative effort. Therefore, these implementations are also within the protection scope of the embodiments of this disclosure.

[0115] The aforementioned driving circuit may include multiple thin-film transistors (TFTs) and capacitors. The TFTs may be top-gate or bottom-gate type TFTs. Each TFT may include an overlapping active layer and a gate, with the active layers of each TFT disposed on the same semiconductor layer; alternatively, they may be disposed on multiple semiconductor layers, with the active layers of each TFT distributed on different semiconductor layers. The material of the semiconductor layer may be polycrystalline silicon or metal oxide, without special limitation.

[0116] The following section, in conjunction with the 7T1C pixel circuit described above, provides a detailed explanation of the film structure for driving the backplane BP:

[0117] As shown in Figure 2, the transistors in the pixel circuit PC are top-gate type low-temperature polysilicon transistors. The driving backplane BP may include a substrate SU and, along a direction away from the substrate SU, a light-shielding layer BSM, a semiconductor layer SE, a first gate layer GAT1, a second gate layer GAT2, a first source / drain layer SD1, and a second source / drain layer SD2, which are sequentially distributed, wherein:

[0118] As shown in Figures 5, 6, 10, and 22, the light-shielding layer BSM can be made of a light-shielding material, such as metal or metal oxide. The light-shielding layer BSM can block at least part of the transistor, preventing light from affecting the electrical performance of the driving transistor. For example, the light-shielding layer BSM can at least overlap with the channel portion of the driving transistor T3 to prevent light from affecting the electrical performance of the driving transistor T3. The light-shielding layer BSM can be made of metal, but other materials that can block light can also be used.

[0119] In some embodiments, the light-shielding layer BSM may include multiple first light-shielding portions BS1, second light-shielding portions BS2, and light-shielding connecting portions BS3. Each first light-shielding portion BS1 may be arrayed along a first direction X and a second direction. Two adjacent first light-shielding portions BS1 in the second direction Y are connected by second light-shielding portions BS2, and two adjacent first light-shielding portions BS1 in the first direction X are connected by light-shielding connecting portions BS3, thereby connecting the light-shielding layer BSM into a mesh-like whole; wherein:

[0120] The first light-shielding part BS1 can overlap with the channel of the driving transistor T3, and the orthogonal projection of the channel of the driving transistor T3 on the substrate SU can be located within the orthogonal projection of the first light-shielding part BS1 on the substrate SU.

[0121] The second light-shielding part BS2 can be connected to the first light-shielding part BS1 and overlap with the channels of the first reset transistor T1 and the compensation transistor T2, and the orthogonal projection of the channels of the first reset transistor T1 and the compensation transistor T2 on the substrate SU can be located within the orthogonal projection of the second light-shielding part BS2 on the substrate SU.

[0122] As shown in Figures 4-7, 11, 17 and 23, the semiconductor layer SE may include the channel portion of each transistor (T1-T7) of the pixel circuit and the doped portion connecting at least part of the channel portion, through which the connection of some transistors can be realized.

[0123] In some embodiments, the semiconductor layer SE can be made of polycrystalline silicon. When forming the semiconductor layer SE, an amorphous silicon layer can be formed first and patterned according to the desired pattern of the semiconductor layer SE. Then, the amorphous silicon layer is irradiated with a laser to achieve crystallization, resulting in polycrystalline silicon. A mask is then used to dope the area outside the channel portion to achieve conductivity, resulting in a doped portion. In the accompanying drawings of this application, the position of the channel portion is used to indicate the position of the transistor.

[0124] In some implementations, the semiconductor layer SE may include multiple semiconductor units. A semiconductor unit may include the channels of each transistor in a pixel circuit. For example, a semiconductor unit may include a first semiconductor part SE1, a second semiconductor part SE2, and a third semiconductor part SE3. The first semiconductor part SE1 and the third semiconductor part SE3 may be distributed along a first direction X. The second semiconductor part SE2 is located between the first semiconductor part SE1 and the third semiconductor part SE3 and connects the first semiconductor part SE1 and the third semiconductor part SE3.

[0125] The first reset transistor T1, the compensation transistor T2, the second light-emitting control transistor T6, and the second reset transistor T7 are located in the first semiconductor section SE1 and are distributed along the second direction Y.

[0126] The driving transistor T3 is located in the second semiconductor section SE2, and the writing transistor T4 and the first light-emitting control transistor T5 are located in the third semiconductor section SE3 and are distributed along the second direction Y.

[0127] As shown in Figures 4, 6, 7, 12, 16, 17, and 24, the first gate layer GAT1 may include the first plate Cst1 of the storage capacitor Cst, a scan line GL, a first reset control line REL1, a second reset control line REL2, and a light emission control line EML. The scan line GL extends along the first direction X, and the area where the scan line GL overlaps with the first semiconductor section SE1 is the gate of the write transistor T4 and the compensation transistor T2. The first reset control line REL1 extends along the first direction X, and the area where it overlaps with the first semiconductor section SE1 is the gate of the first reset transistor T1. The second reset control line REL2 extends along the first direction X, and the area where it overlaps with the first semiconductor section SE1 is the gate of the second reset transistor T7. The light emission control line EML extends along the first direction X, and the area where it overlaps with the first semiconductor section SE1 is the gate of the first light emission control transistor T5, and the area where it overlaps with the third semiconductor section SE3 is the gate of the second light emission control transistor T6. The area where the first electrode plate Cst1 overlaps with the second semiconductor section SE2 is the gate of the driving transistor T3, that is, the first electrode plate Cst1 is reused as the gate of the driving transistor T3.

[0128] The first reset control line REL1 and the scan line GL both have two overlapping regions that are interconnected with the first semiconductor part SE1, so that the first reset transistor T1 and the compensation transistor T2 both include two channels connected in series through the doped part, forming a dual-channel structure, which can reduce leakage current.

[0129] In addition, the second reset control line REL2 connected to the nth row pixel circuit PC can be reused as the first reset control line REL1 connected to the (n+1)th row pixel circuit PC, so that when the nth row pixel circuit PC is in the reset phase, the (n+1)th row pixel circuit PC can reset the light-emitting device LD, thereby improving working efficiency.

[0130] As shown in Figures 4, 7-9, 13, 16, 18, and 25, the second gate layer GAT2 may include a second electrode Cst2 of the storage capacitor Cst, a first reset signal line VIL1, and a second reset signal line VIL2. The first reset signal line VIL1 and the second reset signal line VIL2 extend along a first direction X and are distributed along a second direction Y. The second electrode Cst2 is located between the first reset signal line VIL1 and the second reset signal line VIL2. The second electrode Cst2 overlaps with the first electrode Cst1 and has an opening that exposes the first electrode Cst1. The orthogonal projection of the first electrode Cst1 onto the substrate SU can cover the orthogonal projection of the opening onto the substrate SU.

[0131] The second gate layer GAT2 may further include a first shielding block BL1, at least a portion of which overlaps with the doped portion between the two channels of the compensation transistor T2. Simultaneously, the first shielding block BL1 can be connected to the power supply line VDL, thereby connecting to a constant-voltage first power supply signal VDD. This serves two purposes: firstly, the first power supply signal VDD acts as a signal shield, preventing interference from other signals to the compensation transistor T2; secondly, it reduces the impedance of the power supply line VDL. Of course, the first shielding block BL1 may also be disconnected from the power supply line VDL and connected to other constant signals, as long as the signal stability of the compensation transistor T2 is ensured.

[0132] As shown in Figures 4, 8, 9, 14, 16, 19, and 26, taking a row pixel circuit as an example, the first source / drain layer SD1 may include multiple connection portions, which may include the first connection portion SL1 to the fifth connection portion SL5, wherein:

[0133] The first connection part SL1 can be connected to the first reset transistor T1 and the first reset signal line VIL1 through a via.

[0134] The second connection part SL2 can simultaneously connect the first reset transistor T1 and the compensation transistor T2 to the first plate Cst1 through a via, and the via connecting the first plate Cst1 passes through the opening of the second plate Cst2.

[0135] The third connection part SL3 can be connected to the second reset transistor T7 and the second reset signal line VIL2 via a via.

[0136] The fourth connection part SL4 can be connected to the doped part connected to the channel part of the write transistor T4 through a via, thereby connecting to the first electrode of the write transistor T4.

[0137] The fifth connection portion SL5 can be connected to the doped portion of the channel portion of the driving transistor T3 and the channel portion of the second reset transistor T7 via a via, thereby connecting to the second electrode of the driving transistor T3 and the second reset transistor T7. The fifth connection portion SL5 can also be connected to the first electrode ANO via a via.

[0138] As shown in Figures 4, 9, 15, 16, 20, 21, and 27, the second source / drain layer SD2 may include multiple data lines DAL and multiple power lines VDL. Both the data lines DAL and the power lines VDL can extend along the second direction Y and are distributed along the first direction X, wherein:

[0139] A pixel circuit can be connected to a data line DAL via its write transistor T4, thereby receiving the data signal DA through the data line DAL. Furthermore, the data line DAL can be connected to the fourth connection part SL4 via a via, thereby connecting to the first terminal of the write transistor T4 through the adapter of the fourth connection part SL4.

[0140] A pixel circuit can be connected to a power line VDL via the first terminal of its first light-emitting control transistor T5. Simultaneously, the power line VDL can also be connected to the second plate Cst2 of the storage capacitor Cst to receive the first power signal VDD. A column of pixel circuits can be connected to a single power line VDL.

[0141] The second source / drain layer SD2 may also include an electrode adapter S1, which can be connected to the fifth connection part SL5 through a via, and the first electrode ANO can be connected to the electrode adapter S1 through a via.

[0142] In some embodiments of this disclosure, as shown in Figures 7 and 12, to prevent the data signal on the data line DAL from interfering with the signal at the gate of the driving transistor T3, the second gate layer GAT2 may further include a second shielding block BL2, which is at least partially located between the data line DAL and the second connection portion SL2. That is, the orthographic projection of the second shielding block BL2 on the substrate SU is at least partially located between the orthographic projections of the data line DAL and the second connection portion SL2 on the substrate SU. Simultaneously, the second shielding block BL2 can be connected to the power line VDL, thereby shielding the data signal on the data line DAL by inputting a constant first power supply signal VDD to the second shielding block BL2, preventing it from interfering with the signal at the gate of the driving transistor T3.

[0143] Furthermore, the first shielding block BL1 and the second shielding block BL2 can be an integral structure, or they can be independent structures that are spaced apart from each other.

[0144] In some embodiments of this disclosure, as shown in Figures 8 and 9, in order to maintain the stability of the first power signal VDD and reduce the voltage drop, the first source / drain layer SD1 may further include sub-power lines VDLs extending along the second direction Y. The sub-power lines VDLs are overlapped with the power lines VDL in a one-to-one correspondence, and the overlapping sub-power lines VDLs are connected to the power lines VDL through vias. Simultaneously, the first electrode of the first light-emitting control transistor T5 and the second electrode plate Cst2 of the storage capacitor Cst are both connected to a sub-power line VDLs and connected to a power line VDL through the sub-power lines VDLs.

[0145] In addition, the power line VDL can be connected to the first shielding block BL1 and the second shielding block BL2 through the sub-power lines VDLs. Furthermore, the power line VDL can also be connected to the light-shielding layer BSM, thereby forming a network for transmitting the first power signal VDD in space, which helps to reduce resistance.

[0146] Furthermore, as shown in Figure 2, the drive backplane BP may also include a buffer layer BUF, a first gate insulating layer GI1, a second gate insulating layer GI2, a dielectric layer ILD, a first planarization layer PLN1, and a second planarization layer PLN2, wherein:

[0147] The light-shielding layer BSM is disposed on one side of the substrate SU, and the buffer layer BUF covers the light-shielding layer BSM. The buffer layer BUF can be made of inorganic insulating materials such as silicon nitride and silicon oxide. The thickness of the buffer layer BUF is less than that of the light-shielding layer BSM, and it protrudes in the area corresponding to the light-shielding layer BSM on the surface of the light-shielding layer BSM away from the substrate SU.

[0148] The first gate insulating layer GI1 covers the semiconductor layer SE, and the first gate insulating layer GI1 can be made of inorganic insulating materials such as silicon nitride and silicon oxide. The first gate layer GAT1 can be disposed on the surface of the first gate insulating layer GI1 away from the substrate SU.

[0149] The second gate insulating layer GI2 covers the first gate layer GAT1, and the second gate insulating layer GI2 can be made of inorganic insulating materials such as silicon nitride and silicon oxide. The second gate layer GAT2 can be disposed on the surface of the second gate insulating layer GI2 away from the substrate SU.

[0150] The dielectric layer ILD covers the second gate layer GAT2, and the dielectric layer ILD can be made of inorganic insulating materials such as silicon nitride and silicon oxide. The first source / drain layer SD1 can be disposed on the surface of the dielectric layer ILD away from the substrate SU.

[0151] The first planarization layer PLN1 may cover the first source / drain layer SD1, and the first planarization layer PLN1 may be made of organic materials such as resin. Of course, in some embodiments, the drive backplane BP may include a passivation layer that may cover the first source / drain layer SD1, and the first planarization layer PLN1 covers the passivation layer. The second source / drain layer SD2 may be disposed on the surface of the first planarization layer PLN1 away from the substrate SU.

[0152] The second planarization layer PLN2 can cover the second source / drain layer SD2 and the surfaces of the first planarization layer PLN1 that are not covered by the second source / drain layer SD. The second planarization layer PLN2 can be made of organic materials such as resin. The first electrode AN is disposed on the surface of the second planarization layer PLN2 away from the substrate SU.

[0153] Of course, in other embodiments of this disclosure, the circuit layer driving the backplane BP may be provided with only one source-drain layer, or with three or more source-drain layers. Correspondingly, the planarization layer may also be one, three or more.

[0154] As shown in Figure 2, the light-emitting device LD can be arrayed along the first direction X and the second direction Y. It can be an OLED (organic light-emitting diode) made of organic light-emitting materials; or an LED (light-emitting diode) made of inorganic light-emitting materials, such as Micro LED (micron light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); or a QLED (quantum dot diode) and other devices. No special limitation is made on the specific structure of the light-emitting device LD here.

[0155] Taking an OLED as an example, the light-emitting device (LD) can include a first electrode (ANO), a light-emitting layer (EL), and a second electrode (CAT) stacked sequentially along a direction away from the driving backplane (BP). Each first electrode (ANO) can be arranged in an array along the Y-axis and the second Y-axis. The LD is connected to the pixel circuit through the first electrode (ANO). For example, the first electrode (ANO) can be connected to the electrode adapter (S1) through a via. The first electrode (ANO) can serve as the anode, and the second electrode (CAT) can serve as the cathode. Both are made of conductive materials such as metals and metal oxides. The light-emitting layer (EL) can include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked sequentially along a direction away from the driving backplane (BP). Of course, other structures can also be used, as long as they can cooperate with the first electrode (ANO) and the second electrode (CAT) to emit light. The second electrode (CAT) can be a continuous, solid layer structure, allowing each LD to share the second electrode (CAT).

[0156] The light-emitting diode (LD) has at least three colors, such as red, green, and blue, and there are multiple LDs of each color. Each LD can be divided into multiple pixels, and a pixel can include at least three LDs of different colors. In some embodiments, the LDs can directly emit monochromatic light, with different colored LDs emitting different colors of light to achieve color display. For example, the light-emitting layers (EL) of each LD can be arrayed. In other embodiments, the EL of each LD can be a continuous, single-layer structure, meaning all LDs share the same EL, resulting in the same emitted color. In this case, color display can be achieved by cooperating with a color filter layer on the side of the LD furthest from the driving backplane (BP). The color filter layer has filter sections that overlap with each LD, and the colors of the different filter sections can be different. The color of the LD refers to the color of its own emission or the color of the overlapping filter sections.

[0157] As shown in Figure 2, in order to limit the range of the light-emitting device LD, a pixel definition layer PDL can be set on the driving back plate BP. The pixel definition layer PDL and the first electrode ANO are located on the same surface of the driving back plate BP, and the pixel definition layer PDL can have pixel openings PH that expose each first electrode ANO, so that the range of the light-emitting device LD can be limited through each pixel opening PH.

[0158] Furthermore, considering that the organic light-emitting materials of different colored light-emitting devices (LDs) have different lifespans, in order to improve the uniformity of lifespan, the sizes of different colored light-emitting devices (LDs) can be made different. The size can be reflected by the size of the area of ​​the orthogonal projection of the pixel opening PH onto the driving backplate BP. For example, as shown in Figure 21, the blue light-emitting device LD2 is larger than the red and green light-emitting devices LD3, and the red light-emitting device LD1 is larger than the green light-emitting device LD3.

[0159] As shown in Figure 21, in some embodiments of this disclosure, each light-emitting device (LD) can be divided into device columns distributed along a first direction X. A device column may include multiple light-emitting devices (LDs) distributed along a second direction Y. The position of the device column can be reflected by the position of the first electrode ANO or the position of the pixel opening PH. Simultaneously, each device column may include multiple first device columns and multiple second device columns distributed along the first direction X. The first device column may include two types of light-emitting devices (LDs) of different colors, while the second device columns contain light-emitting devices of the same color. For example, a red light-emitting device LD1 and a blue light-emitting device LD2 may be distributed in the first device column, and a green light-emitting device LD3 may be distributed in the second device column.

[0160] As shown in Figure 1, the touch display panel can have a source drive circuit DI set in the peripheral area WA, which can be integrated into a chip. The source drive circuit DI can output data signals DA to each data line DAL. When the write transistor T4 of the pixel circuit PC in the same row is turned on, it can output data signals to the pixel circuit PC in that row.

[0161] As shown in Figure 1, in some embodiments of this disclosure, the device array can be divided into multiple groups. Data signals can be transmitted to the data lines DAL in groups via a gating circuit MU, without simultaneously outputting data signals to each data line DAL. For example, the data line DAL connected to the pixel circuit connected to the light-emitting device LD of the first device array can be designated as the first data line DAL1, and the data line DAL connected to the pixel circuit connected to the light-emitting device LD of the second device array can be designated as the second data line DAL2. Simultaneously, the driving backplane BP also includes a gating circuit MU, which can be simultaneously connected to each data line DAL. Through the gating circuit MU, a data signal can be output to the first data line DAL1 at the first moment of the write phase, and a data signal can be output to the second data line DAL2 at the second moment of the write phase. The first device array can be an odd-numbered array, and the second device array can be an even-numbered array.

[0162] Furthermore, the selection circuit MU may include multiple switching circuits connected one-to-one with each data line DAL. If a switching circuit is turned on, the source drive circuit can transmit the data signal DA to the data line DAL connected to it through the switching circuit; if the switching circuit is turned off, the data line DAL connected to it cannot receive the data signal DA. The data signal DA can be output to the first data line DAL1 and the second data line DAL2 in batches by controlling the on and off states of the switching circuits. For example, at the first moment of the write phase, the switching circuit connected to the first data line DAL1 is turned on, and the switching circuit connected to the second data line DAL2 is turned off; at the second moment of the write phase, the switching circuit connected to the first data line DAL1 is turned off, and the switching circuit connected to the second data line DAL2 is turned on. In some embodiments of this disclosure, the switching circuit may include a transistor, and the on and off states of the switching circuit are realized by controlling the on and off states of the transistor.

[0163] Of course, in other embodiments of this disclosure, the data line DAL may also include more groups such as a third device column, and the data line DAL connected to each group of device columns can receive data signals simultaneously.

[0164] As shown in Figure 2, the encapsulation layer TFE can cover each light-emitting device (LD) to block external moisture and oxygen, preventing the LD from being corroded. In some embodiments of this disclosure, the encapsulation layer TFE can be a thin-film encapsulation method, which may include a first inorganic layer CVD1, an organic layer IJP, and a second inorganic layer CVD2, wherein:

[0165] The first inorganic layer CVD1 can cover each light-emitting device (LD), that is, the first inorganic layer CVD1 can cover the surface of the second electrode CAT away from the driving backplane BP. The material of the first inorganic layer CVD1 can include inorganic insulating materials such as silicon nitride and silicon oxide. The first inorganic layer CVD1 can be a monolithic structure, which can extend to the peripheral region WA and the transition region CA.

[0166] The organic layer IJP can be disposed on the surface of the first inorganic layer CVD1 away from the driving backplate BP. The boundary of the orthogonal projection of the organic layer IJP on the driving backplate BP can be located in the peripheral area WA, ensuring that the organic layer IJP can cover each light-emitting device LD.

[0167] The second inorganic layer CVD2 can cover the organic layer IJP and the first inorganic layer CVD1, which is not covered by the organic layer IJP. The second inorganic layer CVD2 can block the intrusion of water and oxygen, and planarization is achieved by the organic layer IJP, which is fluid before curing. The material of the second inorganic layer CVD2 can include inorganic insulating materials such as silicon nitride and silicon oxide.

[0168] In addition, in order to limit the position of the organic layer IJP and prevent it from contacting the outside world, an outer barrier dam located in the outer perimeter area WA can be set on the drive back plate BP. The outer barrier dam is a ring structure set around the display area AA. The organic layer IJP can be limited within the range surrounded by the outer barrier dam. The second inorganic layer CVD2 and the first inorganic layer CVD1 can cover the organic layer IJP to prevent it from contacting the outside world, which is beneficial to prevent water and oxygen erosion.

[0169] As shown in Figure 2, the touch layer TL can be disposed on the surface of the encapsulation layer TFE away from the driving backplane BP. The touch layer TL may include at least one electrode layer, which may include touch electrodes for transmitting touch signals. The touch electrodes are located within the display area AA, and touch operations can be sensed through the touch electrodes to realize human-computer interaction. The touch layer TL may adopt a capacitive touch structure, which can be a mutual capacitance structure or a self-capacitive structure. Of course, the embodiments of this disclosure do not exclude the use of resistive touch structures or other touch structures, which will not be listed here.

[0170] As shown in Figure 2, taking a mutual capacitance touch structure as an example, the touch layer TL may include a touch buffer layer TBL, a first electrode layer TMA, an insulating isolation layer TLD, a second electrode layer TMB, and a touch planarization layer TOC covering the second electrode layer TMB; wherein:

[0171] The touch buffer layer (TBL) can cover the encapsulation layer (TFE), which can be made of inorganic insulating materials such as silicon nitride and silicon oxide, or organic insulating materials. The touch buffer layer (TBL) can be a single-layer structure.

[0172] The first electrode layer TMA can be located on the surface of the touch buffer layer TBL away from the driving backplane BP. Its material can be conductive materials such as metal or metal oxide. The specific pattern is not specifically limited here.

[0173] The insulating isolation layer TLD can cover the first electrode layer TMA. It can be made of inorganic insulating materials such as silicon nitride and silicon oxide, or it can be made of organic insulating materials. The insulating isolation layer TLD can be a whole layer structure.

[0174] The second electrode layer TMB can be located on the surface of the insulating isolation layer TLD away from the driving backplane BP. The material can be conductive materials such as metals and metal oxides, and the specific pattern is not specifically limited here.

[0175] The touch planarization layer TOC can cover the second electrode layer TMB, which can be made of organic insulating materials such as resin, and the touch planarization layer TOC can be a whole layer structure.

[0176] The touch electrode may include a first touch electrode and a second touch electrode that intersect each other, and each touch electrode includes multiple electrode blocks connected in series. The electrode blocks of the first touch electrode are connected in series through a bridging portion located in the first electrode layer TMA; the electrode blocks of the first touch electrode and the second touch electrode are located in the second electrode layer TMB, the first touch electrode and the second touch electrode intersect at the bridging portion and are separated by an insulating isolation layer, maintaining mutual insulation while intersecting; the touch planarization layer TOC covers the second electrode layer TMB.

[0177] As shown in Figure 41, the second electrode layer TMB can be a mesh structure with multiple mesh holes TH. One mesh hole TH can overlap with one pixel opening PH, reducing the shading of the light-emitting device LD. Furthermore, the boundary of the orthogonal projection of a mesh hole TH on the substrate SU surrounds the orthogonal projection of the pixel opening PH that overlaps with it on the substrate SU.

[0178] The inventors discovered that when displaying images, touch display panels sometimes exhibit stripes with brightness inconsistent with the surrounding area. Furthermore, as different display frames switch, these stripes scroll in the second direction (Y) or the first direction (X), resembling ripples on water, thus affecting the display quality. Further observation revealed that these stripes typically occur during touch operations and are more pronounced in touch display panels equipped with the aforementioned gating circuit.

[0179] After analysis, the inventors concluded that the stripes were caused by the capacitance between the touch electrode of the touch layer TL and the second electrode CAT of the light-emitting device LD. The second electrode CAT overlaps with the data line DAL, and therefore also has capacitance. This causes changes in the touch signal on the touch electrode to be coupled to the data line DAL through the capacitance, interfering with the data signal DA. In other words, there is noise coupled into the data signal, which leads to abnormalities in the data signal DA output to the pixel circuit, resulting in the stripes. The stripe problem is particularly serious for touch display panels that use an active pen for main control.

[0180] Meanwhile, for touch display panels with the aforementioned gating circuit, the noise voltage of the data signals received by pixel circuits in different rows may be different, which visually results in a water ripple effect. Furthermore, for pixel circuits in the same row, the data signals of the data line DAL are written in batches, but the light-emitting stage is activated simultaneously. Therefore, during the writing stage, some pixel circuits have already written data signals but have not yet started the light-emitting stage, while some pixel circuits have not yet written data signals but have not yet started the light-emitting stage. The data signals that have already been written are affected by the interference of the touch signal, causing display abnormalities.

[0181] To address the aforementioned issues, the inventors have provided several solutions to reduce interference from touch signals to data signals, which are detailed below:

[0182] First type of solution

[0183] A data line DAL can overlap with the first electrode ANO of at least one light-emitting device LD. Since the pixel circuit will reset the voltage of the first electrode ANO to eliminate the influence of the previous frame image, the first electrode ANO is located between the second electrode CAT and the data line DAL. The coupling effect of the first electrode ANO can be used to shield the touch signal to a certain extent, reducing interference to the data signal.

[0184] As shown in Figure 29, in some embodiments of the first type of scheme, the overlapping area of ​​the data line DAL and the first electrode ANO can be made as large as possible. For example, the distance between the two intersection points of the straight line passing through the center of the orthographic projection of the first electrode ANO on the drive backplane BP and the orthographic projection is the maximum length of the first electrode ANO in the second direction Y. Therefore, the center of the data line DAL and the first electrode ANO that overlaps with it in the first direction X can be made as close as possible, and the overlapping area of ​​the data line DAL and the first electrode ANO can be made as large as possible, thereby improving the shielding effect. For example, in the first direction X, the distance between a data line DAL and the center of the first electrode ANO that overlaps with it is less than the distance to the boundary of the first electrode ANO, and this distance can be 0.

[0185] Furthermore, any data line DAL can overlap with the first electrode ANO of the light-emitting device LD of the first device column. This allows the first electrode ANO of the first device column LD to simultaneously shield the data line DAL from interference. Since the first device column includes two light-emitting devices of different colors, the interference of the touch signal on the data signal is more noticeable on the screen. Therefore, the first electrode ANO of the first device column can be used to shield the data line DAL, improving display abnormalities. Simultaneously, the light-emitting devices LD of the second device column are of the same color, allowing any power line VDL to overlap with the first electrode ANO of at least one light-emitting device LD of the second device column.

[0186] As shown in Figure 30, in some other embodiments of the first type of scheme, a column of first electrodes ANO can also overlap with two or more data lines DAL, thereby simultaneously shielding multiple data lines DAL from interference of touch signals. For example, each data line DAL can be divided into multiple line groups, each line group has two data lines DAL, each line group is distributed along the first direction X, and the power line VDL is distributed between adjacent line groups, and the power line VDL between two adjacent line groups can be an integral structure; the two data lines DAL of a line group overlap with the same column of first electrodes ANO, and the two data lines DAL can be symmetrically arranged about the center of the first electrode ANO. The first electrode ANO that overlaps with a line group belongs to the first device column with light-emitting devices LD of different colors, while the second device column can overlap with the power line VDL.

[0187] Furthermore, for the pixel circuit of the 7T1C structure mentioned above, it can adopt the LTPO (low-temperature polycrystalline silicon oxide) scheme. Its compensation transistor and first reset transistor can be N-type metal oxide transistors, and other transistors are P-type polycrystalline silicon transistors. The compensation transistor and the first reset transistor are located on the side of the other transistors away from the substrate SU.

[0188] It should be noted that although the signal of the first electrode ANO itself will also change, because the first electrodes ANO are distributed in an array at intervals, and one data line DAL needs to provide data signals to the pixel circuits connected to multiple first electrodes ANO (for example, one data line DAL can be connected to the pixel circuits connected to 2000 first electrodes ANO), the voltage of the signal of the data line DAL is much greater than the voltage of a single first electrode ANO. This makes the signal fluctuation on the first electrode ANO much smaller than the voltage of the signal of the data line DAL. Therefore, the first electrodes ANO can play a certain shielding role.

[0189] Second type of scheme

[0190] Multiple shielding structures DL can be set between the second electrode CAT and the data line DAL. Specifically, the shielding structure DL is located on the side of the data line DAL closest to the second electrode CAT, and vice versa. Simultaneously, the shielding structure DL can overlap with the data line DAL and can accept signals with fluctuations smaller than the data signal, reducing interference from the touch signal to the data signal caused by coupling through the second electrode CAT.

[0191] As shown in Figures 31 and 32, in some embodiments of the second type of scheme, the shielding structure DL can be disposed on the same layer as the first electrode ANO so that they can be formed simultaneously through the same process; at least one shielding structure DL overlaps with the power line VDL and data line DAL connecting the same column of pixel circuits, and the shielding structure DL and the overlapping power line VDL are connected through vias, so that a constant voltage first power signal can be supplied to the shielding structure DL. At this time, the interference of touch signal can be shielded by the shielding structure DL, reducing abnormal fluctuations in the data signal. At the same time, the shielding structure DL and the first electrode ANO can be spaced apart, that is, the two are not connected.

[0192] The size and shape of the shielding structure DL are limited by the space between the first electrodes ANO. In some embodiments, the spacing between two adjacent shielding structures DL and the spacing between a shielding structure DL and the nearest first electrode is not less than 2 μm to prevent adhesion between the shielding structures DL and between the shielding structure DL and the first electrode. The shape of the orthographic projection of the shielding structure DL on the drive backplate BP may have two sides, which are parallel to the sides of the orthographic projection of the first electrode ANO adjacent to the shielding structure DL on the drive backplate BP.

[0193] As shown in Figures 33-36, in some other embodiments of the second type of scheme, the shielding structure DL and the first electrode ANO are arranged in the same layer, and one shielding structure DL is connected to one first electrode ANO, that is, the shielding structure DL and the first electrode ANO are an integral structure. The signal of the first electrode ANO is input to the shielding structure DL to play a shielding role. The principle that the signal of the first electrode ANO can play a shielding role has been explained in the first type of scheme above, and will not be described in detail here.

[0194] For a first electrode ANO and its connected shielding structure DL, the shielding structure DL can extend along the second direction Y, and a shielding structure DL can overlap with a data line. The same data line can overlap with multiple shielding structures DL distributed along the second direction Y, and multiple shielding structures DL overlapping with the same data line can be regarded as a shield line divided into multiple segments, which overlaps with the data line. Different shielding structures DL can be connected to different first electrodes ANO, so that the signals of different shielding structures DL can be different. Of course, the same first electrode ANO can be connected to one or more shielding structures DL.

[0195] Furthermore, the boundary of the shielding structure DL in the first direction X can be located at least partially outside the boundary of the data line it overlaps with, ensuring that the data line DAL can be shielded. However, the distance between the shielding structure DL and the first electrode that is adjacent to it but not connected is not less than 2 μm, and the distance between shielding structures DL that overlap with the same data line and are distributed at intervals is not less than 2 μm.

[0196] As shown in Figures 33 and 34, in some embodiments, a shielding structure DL overlapping with the first data line DAL1 connected to the first device array can be provided, while the second data line DAL2 has no shielding structure DL overlapping with it, and only the first data line DAL1 is shielded. This helps to simplify the pattern of the film layer where the first electrode ANO is located. Since the data signals of the first data line DAL1 and the second data line DAL2 are written in batches, and the light-emitting phase of the pixel circuits connected to them is turned on simultaneously, after the pixel circuit connected to the first data line DAL1 writes its data signal, it needs to wait for the pixel circuit connected to the second data line DAL2 to write its data signal. During this period, the already written data signal may be affected by touch signals and change. Therefore, the risk of interference to the signal of the first data line DAL1 is greater than that of the second data line DAL2. Thus, only the first data line DAL1 can be shielded.

[0197] Of course, as shown in Figures 35 and 36, in other embodiments, a shielding structure DL overlapping with each data line can also be provided to shield each data line.

[0198] Third type of scheme

[0199] As shown in Figures 37 and 38, the second electrode CAT can be a single-layer structure, and all light-emitting devices share the same second electrode CAT. This allows the second electrode CAT to be hollowed out in the area corresponding to the data line DAL, avoiding capacitance between it and the data line DAL, thereby reducing interference of touch signals on data signals. Specifically, multiple hollowed-out areas CH overlapping with the data line DAL can be formed on the second electrode CAT. By reducing the capacitance between the data line DAL and the second electrode CAT at the hollowed-out areas CH, the interference of touch signals on data signals can be improved.

[0200] In some embodiments of the third type of scheme, the cutout area CH can be a slit extending along the second direction Y, that is, extending in the same direction as the data line DAL. The size of the slit in the second direction Y is smaller than its size in the first direction X. A data line DAL overlaps with multiple cutout areas CH distributed at intervals along the second direction Y, while the second electrode CAT remains continuous between adjacent cutout areas CH to avoid being interrupted by the cutout areas CH along the second direction Y and affecting the transmission of the first power signal. For example, the area of ​​the second electrode CAT located between two adjacent cutout areas CH in the second direction Y can overlap with the first electrode ANO. Since the first electrode ANO has a certain shielding effect, the area overlapping with the first electrode ANO is continuous, and no cutout area CH is set. In addition, the width of the cutout area CH in the first direction X can be not less than the width of the data line DAL that overlaps with it.

[0201] Fourth type of scheme

[0202] As shown in Figures 39 and 40, the second electrode CAT can be a single-layer structure, and all light-emitting devices share the same second electrode CAT. The second electrode CAT can be meshed to form a mesh structure, with the mesh openings being hollow areas CH. These hollow areas CH overlap with the data lines DAL, thereby reducing the overlapping area with the data lines DAL and thus minimizing the impact of coupling capacitance. For example, the second electrode CAT can adopt a mesh structure connected by multiple electrode sections CA1 and connecting sections CA2. The hollow areas CH can be formed by multiple electrode sections CA1 and connecting sections CA2. One electrode section CA1 can overlap with one first electrode ANO. The orthogonal projection of the first electrode ANO on the driving backplate BP is at least partially located within the overlapping electrode section CA1, preventing them from being misaligned and reducing the light-emitting range of the light-emitting device LD. Simultaneously, any two adjacent electrode sections CA1 can be connected through connecting sections CA2, and the electrode section CA1 and the connecting section CA2 can form through-holes in the mesh structure.

[0203] As shown in Figures 4, 16, and 28, to reduce the impact of light on the transistor, the first electrode ANO can overlap with at least one transistor to shield the transistor. In some embodiments of this disclosure, at least a portion of the first electrode ANO may include an electrode body AN1 and at least one extension AN2. The electrode body AN1 may be exposed by the pixel opening PH, while the extension AN2 may extend outward from the electrode body AN1 and be covered by the pixel definition layer PDL. At least one extension AN2 may overlap with a transistor, i.e., overlap with the channel of the transistor, thereby shielding the transistor. This transistor may be at least one of the first reset transistor T1 and the compensation transistor T2 of the pixel circuit. The pixel circuit whose extension AN2 overlaps with the first electrode ANO and the pixel circuit connected to the first electrode ANO are adjacent in the first direction X, but are not the same pixel circuit. Furthermore, the electrode body AN1 may also overlap with the driving transistor T3 of the pixel circuit.

[0204] For example, as shown in Figures 21 and 28, the first electrode ANO of the red light-emitting device LD1 has two extensions AN2, the first electrode ANO of the blue light-emitting device LD2 has one extension AN2, and the first electrode ANO of the green light-emitting device LD3 does not have an extension AN2. The extension AN2 of the first electrode ANO of the blue light-emitting device can overlap with the first reset transistor T1 of a pixel circuit; one extension AN2 of the first electrode ANO of the red light-emitting device can overlap with the compensation transistor T2 of a pixel circuit, and the other extension AN2 can overlap with a data line DAL, thus shielding touch signal interference.

[0205] Furthermore, based on the third type of scheme mentioned above, the boundary of the orthographic projection of an electrode part CA1 on the driving back plate BP surrounds the boundary of the orthographic projection of the electrode body AN1 that overlaps with it on the driving back plate BP, thereby maximizing the range of light emission that the light-emitting device LD can emit.

[0206] In addition, each first electrode ANO may also include a transition portion AN3, which may extend outward from the electrode body AN1 and be covered by the pixel definition layer PDL. The transition portion AN3 may be connected to the second reset transistor T7 and the second light-emitting control transistor T6 of the pixel circuit.

[0207] As shown in Figures 4, 9, 15 and 27, in some embodiments of this disclosure, the power line VDL may include a line body VD1 and a protrusion VD2. The line body VD1 extends along the second direction Y, and the protrusion VD2 is distributed along the first direction X with the line body VD1 and is connected to the line body VD1. The power line VDL can be locally widened by the protrusion VD2, which is beneficial to reduce the impedance of the power line VDL.

[0208] As shown in Figures 4, 9, 15, and 27, the driving backplate BP may also include a photosensitive element, which can be located on the side of the power line VDL away from the light-emitting device LD. The photosensitive element can detect ambient light; the specific structure of the photosensitive element is not specifically limited here. Simultaneously, a protrusion VD2 overlaps with at least one first electrode ANO. Since the first electrode ANO is a light-shielding structure, placing the protrusion VD2 within the area blocked by the first electrode ANO will not affect the transmittance of the touch display panel within the area of ​​the first electrode ANO, allowing the photosensitive element to receive ambient light. Furthermore, at least one protrusion VD2 may have a light-transmitting hole Ho, and the light-transmitting hole does not overlap with any transistor, further improving transmittance.

[0209] This disclosure also provides a touch display device, which may include the touch display panel of any of the above embodiments. The specific structure and beneficial effects of the touch display panel can be referred to the above embodiments of the touch display panel, and will not be described in detail here.

[0210] The touch display device disclosed herein can be a tablet computer, a laptop computer, or a mobile phone, or other electronic devices with touch display functions, which will not be listed here.

[0211] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A touch display panel, comprising: A driving backplane includes multiple pixel circuits, multiple data lines, and multiple power lines. The pixel circuits are distributed along a first direction and a second direction. Each of the data lines and the power lines extends along the second direction and is distributed along the first direction. One data line is connected to at least one column of the pixel circuits and is used to write data signals to the pixel circuits connected to it. One power line is connected to at least one column of the pixel circuits and is used to transmit a first power signal to the pixel circuits connected to it. Multiple light-emitting devices are disposed on one side of the driving backplate, and each light-emitting device includes a first electrode, a light-emitting layer, and a second electrode distributed in a direction away from the driving backplate; a first electrode is connected to a pixel circuit, and a data line overlaps with at least one first electrode; An encapsulation layer covers each of the light-emitting devices; The touch layer is located on the side of the encapsulation layer away from the drive backplane. 2.The touch display panel of claim 1, wherein, The touch display panel also includes: Multiple shielding structures are disposed between the second electrode and the data line, and overlap with at least a portion of the data line. 3.The touch display panel of claim 2, wherein, The power lines and data lines are alternately distributed along the first direction; the shielding structure is disposed at intervals in the same layer as the first electrode; at least one of the shielding structures overlaps with the power lines and data lines connected to the same column of the pixel circuits, and the shielding structure is connected to the power lines it overlaps with. 4.The touch display panel of claim 2, wherein, The shielding structure is disposed in the same layer as the first electrode, and the shielding structure is connected to the first electrode. 5.The touch display panel of claim 4, wherein, The shielding structure extends along the second direction, and one of the shielding structures overlaps with one of the data lines; the boundary of one of the shielding structures in the first direction is at least partially located outside the boundary of the data line it overlaps with. 6.The touch display panel of claim 2, wherein, At least one of the following is not less than 2 μm: the spacing between two adjacent shielding structures, the spacing between the shielding structure and the nearest first electrode, and the spacing between two adjacent first electrodes. 7.The touch display panel of claim 1, wherein, In the first direction, the distance between the center of the data line and the center of the first electrode that overlaps with it is less than the distance to the boundary of the first electrode. 8.The touch display panel of claim 1, wherein, Each of the light-emitting devices shares the same second electrode, and the second electrode has multiple hollow areas that overlap with the data line. 9.The touch display panel of claim 8, wherein, The hollow area is a slit structure extending along the second direction, and one of the data lines overlaps with a plurality of hollow areas that are spaced apart along the second direction. 10.The touch display panel of claim 9, wherein, The region of the second electrode located between two adjacent hollowed-out areas in the second direction overlaps with the first electrode. 11.The touch display panel of claim 8, wherein, The second electrode is a mesh structure consisting of multiple electrode portions and connecting portions connected together. A hollow area is formed by multiple electrode portions and connecting portions. Any two adjacent electrode portions are connected by the connecting portions. An electrode portion overlaps with a first electrode. 12.The touch display panel of claim 11, wherein, The orthographic projection of the electrode portion on the drive backplate is at least partially located outside the orthographic projection of the first electrode overlapping with it on the drive backplate. 13.The touch display panel of claim 1, wherein, The pixel circuit includes a plurality of transistors; a first electrode overlaps with at least one of the transistors. 14.The touch display panel of claim 13, wherein, The power cord includes a cord body and a protrusion. The cord body extends along the second direction, and the protrusion is distributed along the first direction and connected to the cord body. One of the protrusions overlaps with at least one of the first electrodes. 15.The touch display panel of claim 14, wherein, The drive backplate includes: A photosensitive element is disposed on the side of the power line away from the light-emitting device; At least one of the protrusions is provided with a light-transmitting hole, and the light-transmitting hole does not overlap with any of the transistors. 16.The touch display panel of claim 13, wherein, The pixel circuit includes a plurality of transistors; at least one first electrode includes an electrode body and a connecting portion extending outward from the electrode body, the connecting portion being connected to the pixel circuit; at least a portion of the first electrode also includes an extension portion extending outward from the electrode body, at least one of the extension portions overlapping with at least one of the transistors. 17.The touch display panel of claim 16, wherein, At least one extension overlaps with the data line. 18.The touch display panel of claim 1, wherein, The drive backplate includes: Substrate; A transistor layer is disposed on one side of the substrate and includes transistors of the pixel circuit; A first source / drain layer is disposed on the side of the transistor layer away from the substrate and is connected to at least a portion of the transistors; The second source / drain layer is disposed on the side of the first source / drain layer away from the substrate, and includes the power line and the data line.

19. A touch display panel, comprising: A driving backplane includes multiple pixel circuits, multiple data lines, and multiple power lines. The pixel circuits are distributed along a first direction and a second direction. Each of the data lines and the power lines extends along the second direction and is distributed along the first direction. One data line is connected to at least one column of the pixel circuits and is used to write data signals to the pixel circuits connected to it. One power line is connected to at least one column of the pixel circuits and is used to transmit a first power signal to the pixel circuits connected to it. Multiple light-emitting devices are disposed on one side of the driving backplate, and each light-emitting device includes a first electrode, a light-emitting layer, and a second electrode distributed in a direction away from the driving backplate; a first electrode is connected to a pixel circuit. Multiple shielding structures are disposed between the second electrode and the data line, and overlap with at least a portion of the data line; An encapsulation layer covers each of the light-emitting devices; The touch layer is located on the side of the encapsulation layer away from the drive backplane. 20.The touch display panel of claim 19, wherein, The power lines and data lines are alternately distributed along the first direction; the shielding structure is disposed at intervals in the same layer as the first electrode; at least one of the shielding structures overlaps with the power lines and data lines connected to the same column of the pixel circuits, and the shielding structure is connected to the power lines it overlaps with. 21.The touch display panel of claim 19, wherein, The shielding structure is disposed in the same layer as the first electrode, and the shielding structure is connected to the first electrode. 22.The touch display panel of claim 21, wherein, The shielding structure extends along the second direction, and one of the shielding structures overlaps with one of the data lines; the boundary of one of the shielding structures in the first direction is at least partially located outside the boundary of the data line it overlaps with.

23. A touch display panel, comprising: A driving backplane includes multiple pixel circuits, multiple data lines, and multiple power lines. The pixel circuits are distributed along a first direction and a second direction. Each of the data lines and the power lines extends along the second direction and is distributed along the first direction. One data line is connected to at least one column of the pixel circuits and is used to write data signals to the pixel circuits connected to it. One power line is connected to at least one column of the pixel circuits and is used to transmit a first power signal to the pixel circuits connected to it. Multiple light-emitting devices are disposed on one side of the driving backplate, and each light-emitting device includes a first electrode, a light-emitting layer, and a second electrode distributed in a direction away from the driving backplate; a first electrode is connected to a pixel circuit; each light-emitting device shares the same second electrode, and the second electrode has multiple hollow areas that overlap with the data line; An encapsulation layer covers each of the light-emitting devices; The touch layer is located on the side of the encapsulation layer away from the drive backplane. 24.The touch display panel of claim 23, wherein, The cutout area is a slit extending along the second direction, and one of the data lines overlaps with a plurality of cutout areas spaced apart along the second direction; the region of the second electrode located between two adjacent cutout areas in the second direction overlaps with the first electrode.

25. The touch display panel of claim 23, wherein, The second electrode is a mesh structure consisting of multiple electrode portions and connecting portions connected together. A hollow area is formed by multiple electrode portions and connecting portions. Any two adjacent electrode portions are connected by the connecting portions. An electrode portion overlaps with a first electrode.

26. A touch display device comprising the touch display panel as described in any one of claims 1-25.

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