Semiconductor epitaxial structure and LED chip

Abstract

The present invention relates to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor epitaxial structure, which comprises a first semiconductor layer, an active layer and a second semiconductor layer, which are sequentially stacked from bottom to top, wherein the first semiconductor layer comprises a gate elimination layer; the semiconductor epitaxial structure is provided with a V-shaped defect, which extends from the gate elimination layer to the active layer; the first semiconductor layer is an N-type doped layer and is doped with a carbon impurity; and the doping concentration of an N-type dopant in the gate elimination layer is greater than the doping concentration of the carbon impurity in the gate elimination layer. In the present invention, a gate elimination layer is added while retaining a V-shaped defect in a semiconductor epitaxial structure, and by means of controlling growth process conditions, the doping concentration of an N-type dopant in the gate elimination layer is greater than the doping concentration of a carbon impurity therein, and thus the thyristor effect caused by the growth of the V-shaped defect is avoided; moreover, it is ensured that holes are injected via sidewalls of the V-shaped defect, and thus the difficulty of hole injection is reduced and the efficiency of hole injection is improved, thereby significantly enhancing the light-emission efficiency of an LED.

Description

A semiconductor epitaxial structure and an LED chip Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor epitaxial structure and an LED chip. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor electronic component that emits light. LEDs offer advantages such as high efficiency, long lifespan, small size, and low power consumption, making them suitable for indoor and outdoor white light lighting, screen displays, and backlighting. In the development of the LED industry, gallium nitride (GaN)-based materials are a typical representative of V-III compound semiconductors, and improving the photoelectric performance of GaN-based LEDs has become crucial for the semiconductor lighting industry.

[0003] Epitaxial wafers are the initial finished products in the LED manufacturing process. Existing GaN-based LED epitaxial wafers include a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer. The substrate provides the growth surface for the epitaxial material, the N-type semiconductor layer provides electrons for recombination and light emission, the P-type semiconductor layer provides holes for recombination and light emission, and the active layer is used for radiative recombination of electrons and holes to produce light emission.

[0004] In traditional LEDs, V-shaped defects are created in the active layer to improve luminous efficiency. This is typically achieved through cooled growth or accelerated growth; however, this method leads to a significant increase in the carbon impurity doping concentration, resulting in thyratron effects. Therefore, how to avoid thyratron effects while retaining the V-shaped defects has become a pressing problem. Technical solutions

[0005] The present invention provides a semiconductor epitaxial structure, comprising: a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially from bottom to top; the first semiconductor layer includes a gate-clearing layer, the semiconductor epitaxial structure is provided with a V-type defect, the V-type defect extends from the gate-clearing layer to the active layer, the first semiconductor layer is an N-type doped layer, and the first semiconductor layer is doped with carbon impurities, the doping concentration of the N-type dopant in the gate-clearing layer is greater than the doping concentration of the carbon impurities in the gate-clearing layer.

[0006] The present invention provides an LED chip, comprising: a substrate; a semiconductor epitaxial structure disposed on the upper surface of the substrate, the semiconductor epitaxial structure being as described above; a first electrode forming an ohmic contact with a first semiconductor layer; and a second electrode forming an ohmic contact with a second semiconductor layer.

[0007] Compared with the prior art, the present invention provides a semiconductor epitaxial structure that retains the V-type defect while adding a gate-free layer. By controlling the growth process conditions, the doping concentration of N-type dopant in the gate-free layer is greater than that of carbon impurities, thus avoiding the gate-free effect caused by growing the V-type defect. At the same time, it ensures that holes are injected through the sidewalls of the V-type defect, reducing the difficulty of hole injection, improving the efficiency of hole injection, and thus significantly improving the luminous efficiency of the LED. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 is a schematic diagram of a semiconductor epitaxial structure provided in an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of another semiconductor epitaxial structure provided in an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of the structure of a V-shaped defect provided in an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of the structure of an LED chip provided in an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram showing the variation of the doping concentration of N-type dopant and the doping concentration of carbon impurities in the gate-clearing layer provided in an embodiment of the present invention with thickness.

[0014] Figure 6 is another schematic diagram showing the variation of the doping concentration of N-type dopant and the doping concentration of carbon impurities in the gate-clearing layer provided by an embodiment of the present invention with thickness.

[0015] Figure label:

[0016] 10. Substrate 30, First semiconductor layer 301, N-type GaN layer 302, U-type GaN layer 40, Gate clearing layer 41, V-type defect 50, Stress relief layer 60, Active layer 70, Electron blocking layer 80, Second semiconductor layer 31, First electrode 81, Second electrode Embodiments of the present invention

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In the description of this invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] The present invention provides a semiconductor epitaxial structure, comprising: a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially from bottom to top; the first semiconductor layer includes a gate-clearing layer, the semiconductor epitaxial structure is provided with a V-type defect, the V-type defect extends from the gate-clearing layer to the active layer, the first semiconductor layer is an N-type doped layer, and the first semiconductor layer is doped with carbon impurities, the doping concentration of the N-type dopant in the gate-clearing layer is greater than the doping concentration of the carbon impurities in the gate-clearing layer.

[0020] By adopting the above technical solution, the V-type defect is preserved, thus improving the luminous efficiency of the LED. At the same time, by setting the doping concentration of N-type dopant to be greater than that of carbon impurities in the gate-clearing layer, the gate-clearing effect caused by excessively high carbon impurity doping concentration during the growth of the V-type defect can be avoided.

[0021] In one embodiment, the ratio of the carbon impurity doping concentration to the N-type dopant concentration in the gate-clearing layer is no greater than 0.7. By employing the above technical solution, the generation of gate-clearing effects can be further effectively avoided.

[0022] In one embodiment, the material of the gate-clearing layer is Al. e In f Ga (1-e-f) N, where 0≤e≤1, 0≤f≤1.

[0023] In one embodiment, the thickness of the gate-clearing layer is 3-200 nm. By adopting the above technical solution and adjusting the thickness of the gate-clearing layer to a suitable range, the size of the V-shaped defect can be effectively controlled, ensuring that the V-shaped defect meets the performance requirements for LED use.

[0024] In one embodiment, the doping concentration of the N-type dopant in the gate-clearing layer ranges from 5E16 atoms / cm². 3 ~5E19 atoms / cm 3 By adopting the above technical solution, controlling the doping concentration range of N-type dopant in the gate-clearing layer can prevent leakage current problems in semiconductor epitaxial structures caused by excessive N-type doping content, and avoid gate-clearing effects caused by excessively low N-type doping concentration.

[0025] In one embodiment, the doping concentration of carbon impurities in the gate-clearing layer ranges from 1E16 atoms / cm². 3 ~5E19 atoms / cm 3 By employing the above technical solution, controlling the doping concentration range of carbon impurities in the gate-clearing layer can effectively avoid the generation of gate fluid effects.

[0026] In one embodiment, the doping concentration of N-type dopants in the first semiconductor layer is greater than the doping concentration of carbon impurities in the first semiconductor layer. By employing the above technical solution, when the doping concentration of N-type dopants in the first semiconductor layer is greater than the doping concentration of carbon impurities in the first semiconductor layer, it is possible to more effectively ensure that no thyristor effect occurs throughout the entire region of the first semiconductor layer, thereby improving the overall luminous quality of the light-emitting diode.

[0027] In one embodiment, the ratio of the carbon impurity doping concentration to the N-type doping concentration in the first semiconductor layer is no greater than 0.7. By employing the above technical solution, the generation of thyristor effect in the first semiconductor layer region can be further effectively avoided, thereby further improving the overall luminous quality of the light-emitting diode.

[0028] In one embodiment, the N-type dopant is silicon atoms.

[0029] In one embodiment, the second semiconductor layer is a P-type doped layer, and carbon impurities are doped in the second semiconductor layer, with the doping concentration of the P-type dopant being greater than the doping concentration of the carbon impurities. By simultaneously controlling the doping concentration of both the N-type and P-type dopant in the epitaxial structure to be greater than the carbon impurity concentration, the generation of thyristor effects can be minimized, further improving the overall luminous performance of the light-emitting diode.

[0030] In one embodiment, the ratio of the carbon impurity doping concentration to the P-type doping concentration in the second semiconductor layer is no greater than 0.7. By employing the above technical solution, the generation of thyristor effect in the epitaxial structure can be further effectively avoided, thereby further improving the overall luminous performance of the light-emitting diode.

[0031] In one embodiment, the P-type dopant is a magnesium atom.

[0032] In one embodiment, the first semiconductor layer further includes an N-type GaN layer; or, the first semiconductor layer further includes a U-type GaN layer and an N-type GaN layer; the second semiconductor layer includes a P-type GaN layer.

[0033] In one embodiment, the semiconductor epitaxial structure may further include a stress relief layer located between the gate-off layer and the active layer. The stress relief layer has a superlattice structure, with V-shaped defects penetrating through it. Using the above technical solution, the stress relief layer can effectively alleviate the stress problem between the gate-off layer and the active layer.

[0034] In one embodiment, an electron blocking layer may be further included between the second semiconductor layer and the active layer, with the V-shaped defect extending into the electron blocking layer. Using the above technical solution, the electron blocking layer can be used to prevent electron leakage from the active layer, further improving luminous efficiency.

[0035] In one embodiment, the width of the top opening of the V-shaped defect is defined as W, the depth of the V-shaped defect is defined as H, and the ratio of W to H ranges from 1 to 2.

[0036] In one embodiment, the depth H of the V-shaped defect ranges from 20 to 800 nm.

[0037] In one embodiment, the width W of the top opening of the V-shaped defect ranges from 25 to 1500 nm.

[0038] In one embodiment, the included angle θ at the bottom of the V-shaped defect ranges from 50° to 70°.

[0039] In one embodiment, the longitudinal cross-section of the V-shaped defect is triangular or triangular-like.

[0040] The above-mentioned technical solution for V-shaped defects can ensure the injection space of holes in the V-shaped defects, thereby increasing the number of holes injected through the V-shaped defects and preventing the LED's brightness from decreasing under high current conditions due to the increase in the LED's driving voltage.

[0041] The present invention provides an LED chip, comprising: a substrate; a semiconductor epitaxial structure disposed on the upper surface of the substrate, the semiconductor epitaxial structure being as described above; a first electrode forming an ohmic contact with a first semiconductor layer; and a second electrode forming an ohmic contact with a second semiconductor layer.

[0042] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention and through various specific implementation methods.

[0043] As shown in Figure 1, the present invention provides a semiconductor epitaxial structure comprising a first semiconductor layer 30, an active layer 60, and a second semiconductor layer 80 stacked sequentially from bottom to top.

[0044] The first semiconductor layer 30 is an N-type doped layer, and carbon impurities are doped in the first semiconductor layer 30.

[0045] Specifically, the first semiconductor layer 30 can provide electrons to the active layer 60 under the influence of a power source. In some embodiments, the N-type doped layer includes a nitride layer containing N-type dopants, such as an N-type GaN layer 301. The N-type dopants may include one or a combination of Si, Ge, and Sn.

[0046] In one embodiment, as shown in FIG2, the first semiconductor layer 30 further includes a U-shaped GaN layer 302. Specifically, the U-shaped GaN layer 302 is disposed between the N-shaped GaN layer 301 and the substrate 10. If the substrate 10 is a patterned substrate 10, the U-shaped GaN layer 302 can fill the patterned substrate 10, and at the same time, the U-shaped GaN layer 302 can be used as a buffer layer between the substrate 10 and the N-shaped GaN layer 301 to control crystal defects, improve the subsequent growth of the N-shaped GaN layer 301, and alleviate the stress problems caused by lattice mismatch and thermal mismatch between the N-shaped GaN layer 301 and the substrate 10.

[0047] The first semiconductor layer 30 also includes a gate-off layer 40. The semiconductor epitaxial structure has V-type defects 41 extending from the gate-off layer 40 towards the active layer 60. That is, the gate-off layer 40 is the growth starting point for the V-type defects 41, which originate from the gate-off layer 40 and extend to the active layer 60 or to the lower boundary of the second semiconductor layer 80. The doping concentration of N-type dopant in the gate-off layer 40 is greater than the doping concentration of carbon impurities in the gate-off layer 40.

[0048] Specifically, the luminous efficiency of an LED can be improved by incorporating V-type defects 41 in the active layer 60. However, the growth process of V-type defects 41 typically requires cooling, which leads to a significant increase in the doping concentration of carbon impurities in the semiconductor layer, resulting in a gate-closing effect. Therefore, by increasing the gate-closing layer 40 to have a higher doping concentration of N-type dopant than carbon impurity doping concentration, the gate-closing effect caused by the growth of V-type defects 41 is overcome while retaining the V-type defects 41.

[0049] In one embodiment, the material of the gate-clearing layer 40 is Al. e In f Ga (1-e-f)N, where 0≤e≤1, 0≤f≤1. For example, the material of the gate-clearing layer can be AlInGaN, InGaN, AlGaN, AlInN, GaN, AlN, InN, etc. Preferably, in this embodiment of the invention, the material of the gate-clearing layer 40 is GaN.

[0050] In one embodiment, the thickness of the gate-clearing layer 40 is 3-200 nm. Specifically, the size of the V-shaped defect 41 is controlled by the thickness of the gate-clearing layer 40. When the thickness of the gate-clearing layer 40 is less than 3 nm, the overall V-shaped defect 41 from the gate-clearing layer 40 to the active layer 60 is too small, which will result in insufficient injection space for the V-shaped defect 41 and will also increase the driving voltage of the light-emitting diode, causing the overall brightness of the light-emitting diode to be low under high current, thus affecting the luminous efficiency of the LED. When the thickness of the gate-clearing layer 40 is greater than 200 nm, the overall V-shaped defect 41 from the gate-clearing layer 40 to the active layer 60 will extend too much, which can easily cause leakage current in the semiconductor epitaxial structure, thereby reducing the luminous efficiency of the LED under low current.

[0051] In some embodiments of the present invention, the ratio of the carbon impurity doping concentration in the gate-free layer 40 to the N-type doping concentration in the gate-free layer 40 is not greater than 1. As shown in Figure 5, Figure 5 is a schematic diagram of the doping concentration of N-type dopant and the carbon impurity doping concentration as a function of thickness, where the ratio of the carbon impurity doping concentration in the gate-free layer 40 to the N-type doping concentration in the gate-free layer 40 is not greater than 1. The area within the solid line box represents the location of the gate-free layer 40. Typically, in order to create V-type defects, it is inevitable that the carbon impurity doping concentration will increase. By adding a gate-free layer 40 at this location and controlling the growth process conditions to ensure that the ratio of the carbon impurity doping concentration in the gate-free layer 40 to the N-type doping concentration in the gate-free layer 40 is not greater than 1, the gate-free effect is avoided. Furthermore, in some preferred embodiments, the ratio of the carbon impurity doping concentration in the gate-free layer 40 to the N-type doping concentration in the gate-free layer 40 is not greater than 0.7. As shown in Figure 6, Figure 6 is a schematic diagram showing the variation of the doping concentration of N-type dopant and carbon impurities in the degate layer 40 with thickness, where the ratio of the carbon impurity doping concentration to the N-type dopant doping concentration in the degate layer 40 is no greater than 0.7. The solid line area represents the location of the degate layer 40. In this area, by adjusting the growth process conditions, the difference between the doping concentration of N-type dopant and carbon impurity in the degate layer 40 is further widened, so that the ratio of the carbon impurity doping concentration to the N-type dopant doping concentration in the degate layer 40 is no greater than 0.7, thereby further effectively avoiding the generation of throttling effect.

[0052] In one embodiment, the doping concentration of the N-type dopant in the gate-clearing layer 40 ranges from 5E16 atoms / cm². 3 ~5E19 atoms / cm3 In a preferred embodiment, the doping concentration of the N-type dopant in the gate-clearing layer 40 ranges from 1E17 atoms / cm². 3 ~5E19 atoms / cm 3 In a more preferred embodiment, the doping concentration of the N-type dopant in the gate-clearing layer 40 ranges from 5E17 atoms / cm². 3 ~5E19 atoms / cm 3 N-type dopants can include one or a combination of Si, Ge, Sn, Se, and Te. Preferably, the N-type dopant is silicon atoms. Specifically, when the doping concentration of N-type dopants such as silicon atoms is too low, it is impossible to achieve a carbon impurity doping concentration lower than the N-type dopant concentration, making the thyristor effect in the LED unavoidable, and the LED still suffers from delayed lighting due to the thyristor effect. When the doping concentration of N-type dopants such as silicon atoms is too high, leakage current problems will occur in the LED epitaxial structure, resulting in a decrease in the quality of the LED epitaxial structure. Furthermore, higher costs are required to control the production process to increase the N-type doping concentration, resulting in disadvantages in both production cost and epitaxial structure quality. Therefore, the doping concentration of N-type dopants needs to be controlled to be greater than or equal to 5E16 atoms / cm². 3 Less than or equal to 5E19 atoms / cm 3 When the doping concentration of N-type dopant is within this range, it can suppress the generation of thyristor effect, ensure the quality of LED epitaxial structure, and keep production cost within a reasonable range.

[0053] In one embodiment, the doping concentration of carbon impurities in the gate-clearing layer 40 ranges from 1E16 atoms / cm². 3 ~5E19 atoms / cm 3 In a preferred embodiment, the carbon impurity doping concentration in the gate-clearing layer 40 ranges from 1E16 atoms / cm². 3 ~1E18atoms / cm 3 In a more preferred embodiment, the doping concentration of carbon impurities in the gate-clearing layer 40 ranges from 1E16 atoms / cm². 3 ~5E17 atoms / cm 3 If the doping concentration of carbon impurities in the gate-clearing layer 40 is greater than 5E19 atoms / cm 3 If the doping concentration of N-type dopant in the gate-free layer 40 is greater than that of carbon impurities, the generation of gate-free fluid effect cannot be avoided.

[0054] Furthermore, in one embodiment, the doping concentration of the N-type dopant in the first semiconductor layer 30 is greater than the doping concentration of the carbon impurities in the first semiconductor layer 30. By adopting the above technical solution, and by controlling the doping concentration of the N-type dopant in the first semiconductor layer 30 to be greater than the doping concentration of the carbon impurities in the first semiconductor layer 30, it is possible to more effectively ensure that no thyristor effect is generated in the entire area of ​​the first semiconductor layer 30, thereby improving the overall luminous quality of the light-emitting diode.

[0055] Furthermore, in one embodiment, the ratio of the carbon impurity doping concentration to the N-type doping concentration in the first semiconductor layer 30 is not greater than 0.7. This further avoids the generation of thyristor effects across the entire first semiconductor layer 30.

[0056] In one embodiment, as shown in FIG3, the width of the top opening of the V-shaped defect 41 is defined as W, the depth of the V-shaped defect 41 is defined as H, and the ratio of W to H is in the range of 1 to 2.

[0057] In one embodiment, the depth H of the V-shaped defect 41 ranges from 20 to 800 nm.

[0058] In one embodiment, the width W of the top opening of the V-shaped defect 41 ranges from 25 to 1500 nm.

[0059] In one embodiment, the included angle θ at the bottom of the V-shaped defect 41 ranges from 50° to 70°.

[0060] In one embodiment, the longitudinal cross-section of the V-shaped defect 41 is triangular or triangular-like. Considering practical process conditions in real-world applications, such as the fact that the inclined sidewalls are not perfectly smooth interfaces, the longitudinal cross-section of the V-shaped defect 41 of the present invention is not limited to a triangle, but can be a near-triangular or triangular-like shape. Specifically, the sidewalls of the V-shaped defect 41 can be straight, or they can be convex or concave arcs with curvature. The longitudinal cross-section of the V-shaped defect 41 corresponding to the sidewalls of a straight V-shaped defect 41 is triangular; the longitudinal cross-section of the V-shaped defect 41 with sidewalls that are convex or concave arcs with curvature is triangular-like.

[0061] Preferably, by employing the above-mentioned technology, the V-shaped defect 41 can ensure the injection space of holes in the V-shaped defect 41, thereby increasing the number of holes injected through the V-shaped defect 41 and preventing the LED's brightness from decreasing under high current conditions due to the increase in the LED's driving voltage.

[0062] In one embodiment, as shown in FIG2, the semiconductor epitaxial structure further includes a stress relief layer 50 located between the gate-off layer 40 and the active layer 60. The stress relief layer 50 is a superlattice structure, and a V-shaped defect 41 penetrates the stress relief layer 50. Specifically, the V-shaped defect 41 originates from the gate-off layer 40, passes upward through the stress relief layer 50, and extends to the active layer 60 or to the lower boundary of the second semiconductor layer 80. The stress relief layer 50 can be used as a buffer layer between the gate-off layer 40 and the active layer 60 to control crystal defects and alleviate stress problems between the gate-off layer 40 and the active layer 60.

[0063] In one embodiment, the second semiconductor layer 80 is a P-type doped layer, and carbon impurities are doped in the second semiconductor layer 80. The doping concentration of the P-type dopant in the second semiconductor layer 80 is greater than the doping concentration of the carbon impurities in the second semiconductor layer 80.

[0064] Specifically, a P-type doped layer is located on the active layer 60, comprising a P-type GaN layer. The P-type doped layer includes a P-type dopant and a carbon impurity, and the P-type dopant may include one or a combination of Mg, Zn, and Be. The P-type doped layer can be a single-layer structure or a multi-layer structure with different compositions.

[0065] Furthermore, in some embodiments, the ratio of the doping concentration of carbon impurities in the second semiconductor layer 80 to the doping concentration of P-type dopants in the second semiconductor layer 80 is not greater than 0.7.

[0066] By adopting the above technical solution, and simultaneously adjusting the doping concentration of N-type dopant to be greater than that of carbon impurities and the doping concentration of P-type dopant to be greater than that of carbon impurities in the epitaxial structure, the generation of thyristor effect can be avoided to a greater extent, thereby further improving the overall light-emitting performance of the light-emitting diode.

[0067] In one embodiment, as shown in FIG2, an electron blocking layer 70 is further included between the second semiconductor layer 80 and the active layer 60, and a V-shaped defect 41 extends to the electron blocking layer 70. When the upper surface of the existing active layer 60 is a planar structure, hole injection is difficult in the planar structure. However, by setting the V-shaped defect 41, holes are injected through the sidewalls of the V-shaped defect 41. Compared with the active layer 60 with a planar upper surface, the active layer 60 with the V-shaped defect 41 can perform hole injection better.

[0068] In one embodiment, the active layer 60 can be a quantum well (QW) structure. In some embodiments, the active layer 60 can also be a multiple quantum well (MQW) structure, wherein the multiple quantum well structure includes multiple quantum well layers (Wells) and multiple quantum barrier layers arranged alternately in a repeating manner, such as a GaN / AlGaN, InAlGaN / InAlGaN, or InGaN / AlGaN multi-quantum well structure. Furthermore, the composition and thickness of the well layers within the active layer 60 determine the wavelength of the generated light. To improve the luminescence efficiency of the active layer 60, this can be achieved by changing the depth of the quantum wells, the number of paired quantum wells and quantum barriers, the thickness, and / or other characteristics within the active layer 60.

[0069] The present invention also provides an LED chip, as shown in FIG4, comprising: a substrate 10, and a semiconductor epitaxial structure disposed on the upper surface of the substrate 10; the semiconductor epitaxial structure is the semiconductor epitaxial structure provided in any of the foregoing embodiments. It also includes a first electrode 31 and a second electrode 81, the first electrode 31 forming an ohmic contact with the first semiconductor layer 30, and the second electrode 81 forming an ohmic contact with the second semiconductor layer 80.

[0070] Although this document frequently uses terms such as substrate, U-shaped GaN layer, first semiconductor layer, first electrode, gate-clearing layer, V-type defect, stress-relieving layer, active layer, electron-blocking layer, second semiconductor layer, and second electrode, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor epitaxial structure, characterized by, include: The first semiconductor layer, the active layer, and the second semiconductor layer are stacked sequentially from bottom to top. The first semiconductor layer includes a gate-clearing layer. The semiconductor epitaxial structure is provided with a V-type defect. The V-type defect extends from the gate-clearing layer to the active layer. The first semiconductor layer is an N-type doped layer and is doped with carbon impurities. The doping concentration of the N-type dopant in the gate-clearing layer is greater than the doping concentration of the carbon impurities in the gate-clearing layer.

2. The semiconductor epitaxial structure of claim 1, wherein: The ratio of the doping concentration of the carbon impurity in the gate-clearing layer to the doping concentration of the N-type dopant in the gate-clearing layer is no greater than 0.

7.

3. The semiconductor epitaxial structure of claim 1, wherein: The material of the gate-off layer is Al e In f Ga (1-e-f) N, wherein 0≤e≤1, 0≤f≤1.

4. The semiconductor epitaxial structure of claim 1, wherein: The thickness of the gate-clearing layer is 3-200 nm.

5. The semiconductor epitaxial structure of claim 1, wherein: The doping concentration of the N-type dopant in the gate-off layer ranges from 5E16 atoms / cm 3 ~ 5E19 atoms / cm 3 .

6. The semiconductor epitaxial structure of claim 1, wherein: The doping concentration of the carbon impurities in the gate-off layer ranges from 1E16 atoms / cm 3 ~ 5E19 atoms / cm 3 .

7. The semiconductor epitaxial structure of claim 1, wherein: The doping concentration of the N-type dopant in the first semiconductor layer is greater than the doping concentration of the carbon impurity in the first semiconductor layer.

8. The semiconductor epitaxial structure of claim 7, wherein: The ratio of the doping concentration of the carbon impurity in the first semiconductor layer to the doping concentration of the N-type dopant in the first semiconductor layer is not greater than 0.

7.

9. The semiconductor epitaxial structure according to any one of claims 1 to 8, wherein: The N-type dopant is silicon atoms.

10. The semiconductor epitaxial structure of claim 1, wherein: The second semiconductor layer is a P-type doped layer, and carbon impurities are doped in the second semiconductor layer. The doping concentration of the P-type dopant in the second semiconductor layer is greater than the doping concentration of the carbon impurities in the second semiconductor layer.

11. The semiconductor epitaxial structure of claim 10, wherein: The ratio of the doping concentration of the carbon impurity in the second semiconductor layer to the doping concentration of the P-type dopant in the second semiconductor layer is not greater than 0.

7.

12. The semiconductor epitaxial structure of claim 10 or 11, wherein: The P-type dopant is magnesium atoms.

13. The semiconductor epitaxial structure of claim 1, wherein: The first semiconductor layer further includes an N-type GaN layer; or, the first semiconductor layer further includes a U-type GaN layer and an N-type GaN layer; the second semiconductor layer includes a P-type GaN layer.

14. The semiconductor epitaxial structure of claim 1, wherein: It also includes a stress relief layer located between the gate-clearing layer and the active layer. The stress relief layer has a superlattice structure, and the V-shaped defect penetrates the stress relief layer.

15. The semiconductor epitaxial structure of claim 1, wherein: An electron blocking layer is also included between the second semiconductor layer and the active layer, and the V-shaped defect extends into the electron blocking layer.

16. The semiconductor epitaxial structure of claim 1, wherein: The width of the top opening of the V-shaped defect is defined as W, the depth of the V-shaped defect is defined as H, and the ratio of W to H is in the range of 1 to 2.

17. The semiconductor epitaxial structure of claim 16, wherein: The depth H of the V-shaped defect ranges from 20 to 800 nm, and the width W of the top opening of the V-shaped defect ranges from 25 to 1500 nm.

18. The semiconductor epitaxial structure of claim 1, wherein: The included angle θ at the bottom of the V-shaped defect ranges from 50° to 70°.

19. The semiconductor epitaxial structure of claim 1, wherein: The longitudinal section of the V-shaped defect is triangular or triangular in shape.

20. An LED chip, characterized by include: Substrate; A semiconductor epitaxial structure disposed on the upper surface of the substrate, wherein the semiconductor epitaxial structure is the semiconductor epitaxial structure according to any one of claims 1-19; The first electrode forms an ohmic contact with the first semiconductor layer; The second electrode forms an ohmic contact with the second semiconductor layer.

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