Encoding method and apparatus, and decoding method and apparatus

Abstract

An encoding method and apparatus, and a decoding method and apparatus, which can be applied to the technical field of communications. An encoding apparatus acquires a sequence to be encoded (i.e., a first bit sequence), then encodes the first bit sequence on the basis of a first base matrix of LDPC codes, so as to obtain a second bit sequence, and outputs the second bit sequence, wherein the second bit sequence may be subjected to other processing and then transmitted via a channel; and after receiving a signal transmitted via the channel, a decoding apparatus processes the signal to obtain a sequence to be decoded (i.e., the second bit sequence), and then decodes the second bit sequence on the basis of the first base matrix, so as to obtain the first bit sequence, wherein the first base matrix may comprise a first sub-matrix, and elements in the first sub-matrix are taken from a Galois field GF(2m). With the first base matrix of the structure, the performance of LDPC codes can be improved.

Description

Encoding methods, decoding methods and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202411466674.0, filed on October 18, 2024, with the Chinese National Intellectual Property Administration, entitled “Encoding Method, Decoding Method and Apparatus”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, and an apparatus. Background Technology

[0003] Channel coding is one of the core technologies in wireless communication. The complete channel coding process includes, but is not limited to, adding cyclic redundancy check (CRC) codes, code block segmentation, error correction coding, rate adaptation, code block concatenation, data interleaving, and data scrambling. Among these, error correction coding is the most critical part. The purpose of error correction coding is to ensure that the receiver can automatically correct errors that occur during data transmission with as little redundancy overhead as possible. At the same bit error rate, the smaller the required redundancy overhead, the higher the coding efficiency.

[0004] Fifth-generation (5G) communication presents richer service application scenarios and new requirements for channel coding. For example, massive machine-type communication (mMTC) scenarios require smaller file packets to be transmitted, while ultra-reliable low-latency communications (URLLC) scenarios have very high requirements for encoding and decoding latency and low bit error rate. Therefore, based on the key requirements of channel coding for the three major 5G application scenarios, the 5G standard ultimately adopted low-density parity-check (LDPC) codes and polar codes. Compared with traditional linear block codes and convolutional codes, these two codes have superior performance, approaching the limits of Shannon theory very closely. At the same time, they have their own characteristics in terms of applicable scenarios and codec complexity.

[0005] However, in some application scenarios, the performance of LDPC codes cannot meet the requirements. Therefore, how to improve the performance of LDPC codes is an urgent problem to be solved. Summary of the Invention

[0006] This application provides an encoding method, a decoding method, and an apparatus that can help improve the performance of LDPC codes.

[0007] In a first aspect, embodiments of this application provide an encoding method. The method is applied to an encoding device, which can be applied to a terminal side, such as a terminal or an encoding module within a terminal, or a circuit or chip in the terminal responsible for encoding functions (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip or system-in-package (SIP) chip containing a modem core, etc.); or, the encoding device can be applied to a network side, such as a network device or an encoding module within a network device, or a circuit or chip in the network device responsible for encoding functions (such as a modem chip, also known as a baseband chip, or an SoC chip or SIP chip containing a modem core, etc.). The method includes:

[0008] Obtain the first bit sequence; encode the first bit sequence based on the first basis matrix of the LDPC code to obtain the second bit sequence; the first basis matrix includes a first submatrix, and the values ​​of the elements in the first submatrix are taken from the Galois field (GF)(2 m ), where m is a positive integer greater than 1; output the second bit sequence.

[0009] In this embodiment, the first basis matrix can also be called a multi-element basis matrix or a non-binary basis matrix. The values ​​of the elements in the first submatrix are taken from GF(2). m That is, the value of an element in the first submatrix is ​​less than or equal to 2. m -1. When constructing the multivariate basis matrix, the range of values ​​for the elements in the first submatrix is ​​extended to GF(2). m The first submatrix contains more bits, which helps improve the performance of LDPC codes, such as reducing the block error rate (BLER).

[0010] For example, the first basis matrix has a Laptor-like structure. For instance, the first basis matrix may include a core matrix and an extended matrix. The core matrix can be used for higher bitrate scenarios, and the extended matrix can be obtained by expanding the core matrix to achieve multi-bitrate encoding. The aforementioned first sub-matrix may include the core matrix from the first basis matrix.

[0011] In conjunction with the first aspect, in one possible implementation, the first basis matrix based on the LDPC code encodes the first bit sequence to obtain the second bit sequence, including:

[0012] Determine one or more expansion factors; the one or more expansion factors include the expansion factor z corresponding to the first submatrix; expand the elements of the first base matrix according to the one or more expansion factors to obtain a parity check matrix; the elements in the first submatrix include a first element, the first element corresponding to a z×z matrix in the parity check matrix; wherein, z is a positive integer; encode the first bit sequence based on the parity check matrix to obtain the second bit sequence;

[0013] Wherein, the z×z matrix is ​​either the following matrix or a cyclic shift matrix of the following matrix:

[0014] Wherein, k represents the value of the first element.

[0015] In this embodiment of the application, the elements in the first submatrix can be expanded using the expansion factor z, wherein any element in the first submatrix can be expanded into a z×z matrix.

[0016] For example, when the encoding device determines multiple expansion factors, these multiple expansion factors correspond to different parts of the first base matrix. For instance, the first base matrix also includes a second submatrix, and the expansion factors corresponding to the first submatrix and the second submatrix are different. The multiple expansion factors include the expansion factor z corresponding to the first submatrix and the expansion factor y corresponding to the second submatrix. In this way, using different expansion factors for different parts of the first base matrix allows for more flexible expansion of the first base matrix.

[0017] For example, when the encoding device determines an expansion factor, the elements in the first base matrix are expanded using the same expansion factor, which is simple to implement.

[0018] In conjunction with the first aspect, in one possible implementation, the method further includes:

[0019] Obtain the third bit sequence; encode the third bit sequence based on the second basis matrix of the LDPC code to obtain the fourth bit sequence; wherein the value range of the elements in the second basis matrix is ​​{0,1}, and the positions of the non-zero elements in the first and second basis matrices are the same; output the fourth bit sequence.

[0020] In this embodiment, the second basis matrix can also be called a binary basis matrix. The encoding device can store the first and second basis matrices of the LDPC code. The positions of the non-zero elements in the first and second basis matrices are the same, that is, the first and second basis matrices have the same structure. In this way, the multi-based basis matrix can reuse the structure of the binary basis matrix, which is simple to implement and can unify the encoding and decoding methods of multi-based LDPC codes and binary LDPC codes.

[0021] Secondly, embodiments of this application provide a decoding method, which is applied to a decoding device. The decoding device can be applied to the terminal side, such as a terminal or a decoding module within a terminal, or a circuit or chip in the terminal responsible for decoding (e.g., a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip or system-in-package (SIP) chip containing a modem core, etc.); or, the decoding device can be applied to the network side, such as a network device or a decoding module within a network device, or a circuit or chip in the network device responsible for decoding (e.g., a modem chip, also known as a baseband chip, or an SoC chip or SIP chip containing a modem core, etc.). The method includes:

[0022] Obtain the second bit sequence; decode the second bit sequence based on the first basis matrix of the LDPC code to obtain the first bit sequence; the first basis matrix includes a first submatrix, and the values ​​of the elements in the first submatrix are taken from the Galois field GF(2). m ), where m is a positive integer greater than 1.

[0023] In conjunction with the second aspect, in one possible implementation, the first basis matrix based on the LDPC code decodes the second bit sequence to obtain the first bit sequence, including:

[0024] Determine one or more expansion factors; the one or more expansion factors include the expansion factor z corresponding to the first submatrix;

[0025] The elements of the first base matrix are expanded according to the one or more expansion factors to obtain the parity check matrix; the elements in the first submatrix include a first element, which corresponds to the z×z matrix in the parity check matrix; wherein z is a positive integer;

[0026] The second bit sequence is decoded based on the parity check matrix to obtain the first bit sequence;

[0027] Wherein, the z×z matrix is ​​either the following matrix or a cyclic shift matrix of the following matrix:

[0028] Wherein, k represents the value of the first element.

[0029] In conjunction with the second aspect, in one possible implementation, the method further includes:

[0030] Obtain the fourth bit sequence; decode the fourth bit sequence based on the second basis matrix of the LDPC code to obtain the third bit sequence; wherein the value range of the elements in the second basis matrix is ​​{0,1}, and the positions of the non-zero elements in the first and second basis matrices are the same.

[0031] In conjunction with the first or second aspect, in one possible implementation, the value of the element in the i-th row of the first submatrix is ​​determined by the elements in a first set of values, which is related to the number of non-zero elements in the i-th row; where i is a positive integer.

[0032] In this embodiment, the number of non-zero elements in the i-th row can also be called the row weight of the i-th row. Different row weights correspond to different first value sets. The first value set is a predefined set of values. For example, the first value set can be predefined by a standard or protocol. Alternatively, the first value set can be predefined by an encoding device and / or a decoding device. Determining the values ​​of non-zero elements in the i-th row using a predefined set of values ​​ensures the performance of the LDPC code.

[0033] In conjunction with the first or second aspect, in one possible implementation, the number of elements in the first value set is the same as the number of non-zero elements in the i-th row, and one element in the first value set corresponds to the value of one non-zero element in the i-th row.

[0034] In conjunction with the first or second aspect, in one possible implementation, the first base matrix further includes a second submatrix, in which the values ​​of the elements are in the range {0,1}.

[0035] In this embodiment, the first submatrix is ​​a multivariate matrix, and the second submatrix is ​​a binary submatrix. That is, the first basis matrix includes a binary matrix part (corresponding to the second submatrix) and a multivariate matrix part (corresponding to the first submatrix). This first basis matrix can also be called a hybrid basis matrix or a hybrid LDPC matrix. The first and second submatrixes correspond to different rows in the first basis matrix. It is understood that the decoding complexity of the multivariate matrix part is higher than that of the binary matrix part. Therefore, the encoding device can extend the values ​​of some elements in the first basis matrix to GF(2^3). m The first basis matrix is ​​used to reduce decoding complexity by keeping the values ​​of the other part of the matrix GF(2), which makes it suitable for different decoding complexity requirements.

[0036] In one possible implementation, combining the first or second aspect, the expansion factor corresponding to the first submatrix is ​​less than the expansion factor corresponding to the second submatrix.

[0037] In this embodiment, one element in the first submatrix corresponds to m bits, and one element in the second submatrix corresponds to 1 bit. The expansion factor of the first submatrix is ​​smaller than that of the second submatrix, which can reduce the difference between the matrix dimensions after the expansion of the first and second submatrix, and can also help to make the parity check matrix obtained after expanding the first base matrix closer to a rectangular matrix.

[0038] In conjunction with either the first or second aspect, in one possible implementation, the expansion factor corresponding to the second submatrix is ​​y, and the expansion factor corresponding to the first submatrix is... or Where y is a positive integer, the This indicates rounding down, the... This indicates rounding up to the nearest integer.

[0039] In this embodiment, one element in the first submatrix corresponds to m bits, and one element in the second submatrix corresponds to 1 bit. Therefore, the expansion factor corresponding to the first submatrix can be y / m, which makes the parity check matrix obtained after expanding the first base matrix as rectangular as possible.

[0040] In conjunction with the first or second aspect, in one possible implementation, the expansion factor corresponding to the first submatrix is ​​z, and the expansion factor corresponding to the second submatrix is ​​m×z; wherein z is a positive integer.

[0041] In this embodiment, one element in the first submatrix corresponds to m bits, and one element in the second submatrix corresponds to 1 bit. Therefore, the expansion factor of the second submatrix is ​​m×z, which ensures that the parity check matrix obtained after expanding the first base matrix is ​​a standard rectangular matrix.

[0042] In conjunction with the first or second aspect, in one possible implementation, the number of columns of the second submatrix is ​​m times the number of columns of the first submatrix, and the expansion factor corresponding to the first submatrix is ​​the same as the expansion factor corresponding to the second submatrix.

[0043] In this embodiment, one element of the first submatrix corresponds to an m×m matrix, and the number of columns of the second submatrix is ​​m times the number of columns of the first submatrix. After expanding the first and second submatrixes using the same expansion factor, the expanded matrix can be a standard rectangular matrix.

[0044] In one possible implementation, in conjunction with the first or second aspect, the first submatrix includes the core matrix in the first base matrix, and the second submatrix includes the extended matrix in the first base matrix.

[0045] In this embodiment, the first basis matrix has a Laptler-like structure, comprising a core matrix and an extended matrix. The core matrix independently performs encoding and decoding as an LDPC code. Therefore, the range of values ​​for the elements in the core matrix can be extended to GF(2). m The elements in the extended matrix are kept in GF(2).

[0046] In one possible implementation, in conjunction with the first or second aspect, the first submatrix includes the core matrix and the extended matrix of the first basis matrix.

[0047] In this embodiment, the elements in both the core array and the extended array can be extended to GF(2). m This can improve the performance of LDPC codes.

[0048] Thirdly, embodiments of this application provide an encoding apparatus for performing the method in the first aspect or any possible implementation thereof. The encoding apparatus includes modules having functions for performing the method in the first aspect or any possible implementation thereof.

[0049] Fourthly, embodiments of this application provide a decoding apparatus for performing the methods in the second aspect or any possible implementation thereof. The decoding apparatus includes modules for performing the methods in the second aspect or any possible implementation thereof.

[0050] The modules in the third or fourth aspect can also be replaced with units or means, etc. The aforementioned modules can be implemented in software, hardware, or a combination of both.

[0051] Fifthly, embodiments of this application provide an encoding apparatus including a processing circuit for executing the method in the first aspect or any possible implementation of the first aspect. The processing circuit executes a program stored in a memory, and when the program is executed, the method described in the first aspect or any possible implementation of the first aspect is executed.

[0052] In one possible implementation, the memory is located outside the aforementioned encoding device.

[0053] In one possible implementation, the memory is located within the aforementioned encoding device.

[0054] In this embodiment, the processing circuit and memory can also be integrated into a single device; that is, the processing circuit and memory can be integrated together. For example, the encoding device can be a chip responsible for encoding functions, such as a baseband chip, or a SoC chip or SIP chip containing a modem module.

[0055] In one possible implementation, the encoding device further includes a transceiver circuit for receiving information (or input information) or sending information (or output information). For example, the encoding device may be a terminal device or a network device, etc.

[0056] In a sixth aspect, embodiments of this application provide a decoding apparatus, which includes a processing circuit for executing the methods of the second aspect or any possible implementation thereof. The processing circuit executes a program stored in a memory, and when the program is executed, the methods described in the second aspect or any possible implementation thereof are performed.

[0057] In one possible implementation, the memory is located outside the aforementioned decoding device.

[0058] In one possible implementation, the memory is located within the aforementioned decoding device.

[0059] In this embodiment, the processing circuit and memory can also be integrated into a single device; that is, the processing circuit and memory can be integrated together. For example, the decoding device can be a chip responsible for decoding functions, such as a baseband chip, a SoC chip containing a modulation / demodulation module, or a SIP chip, etc.

[0060] In one possible implementation, the decoding device further includes a transceiver circuit for receiving information (or input information) or sending information (or output information). For example, the decoding device may be a terminal device or a network device, etc.

[0061] In a seventh aspect, embodiments of this application provide an encoding device, which includes a processing circuit and a transceiver circuit. The processing circuit can be a logic circuit, and the transceiver circuit can be an interface circuit. The logic circuit and the interface are coupled. The interface circuit is used to input and / or output information, and the logic circuit is used to execute the method in the first aspect or any possible implementation of the first aspect.

[0062] Eighthly, embodiments of this application provide a decoding apparatus, which includes a processing circuit and a transceiver circuit. The processing circuit can be a logic circuit, and the transceiver circuit can be an interface circuit. The logic circuit and the interface are coupled. The interface circuit is used to input and / or output information, and the logic circuit is used to execute the method in the second aspect or any possible implementation of the second aspect.

[0063] Ninthly, embodiments of this application provide a computer-readable storage medium for storing a computer program that, when run on a computer, causes the methods shown in any of the first to second aspects or any possible implementation thereof to be executed.

[0064] In a tenth aspect, embodiments of this application provide a computer program product that, when run on a computer, causes the methods shown in any of the first to second aspects or any possible implementations described above to be executed.

[0065] The computer described in the ninth or tenth aspect may include, but is not limited to, terminal equipment or network equipment.

[0066] Eleventhly, embodiments of this application provide a communication system including an encoding device and a decoding device. The encoding device may be the device provided in the third, fifth, and seventh aspects, and the decoding device may be the device provided in the fourth, sixth, and eighth aspects. The encoding device may be used to perform the method shown in the first aspect or any possible implementation thereof, and the decoding device may be used to perform the method shown in the second aspect or any possible implementation thereof.

[0067] In a twelfth aspect, embodiments of this application provide a basis matrix for encoding and / or decoding, the basis matrix comprising a first submatrix, wherein the values ​​of the elements in the first submatrix are taken from the Galois domain GF(2). m ), where m is a positive integer greater than 1.

[0068] The parity check matrix obtained by expanding the base matrix as described above also falls within the protection scope of this application. Attached Figure Description

[0069] Figure 1 is a schematic diagram of the structure of the base matrix of an LDPC code provided in an embodiment of this application;

[0070] Figure 2A is a schematic diagram of the architecture of a communication system provided in an embodiment of this application;

[0071] Figure 2B is a schematic diagram of the architecture of the communication system provided in an embodiment of this application;

[0072] Figure 3 is an example of a communication chip system provided in an embodiment of this application;

[0073] Figure 4 is a schematic diagram of a tanner diagram provided in an embodiment of this application;

[0074] Figure 5 shows an example of selecting a base graph (BG) according to an embodiment of this application;

[0075] Figure 6 is a flowchart illustrating a communication method provided in an embodiment of this application;

[0076] Figure 7A is a schematic diagram of the structure of a first basis matrix provided in an embodiment of this application;

[0077] Figure 7B is a schematic diagram of the structure of a second basis matrix provided in an embodiment of this application;

[0078] Figure 8A shows an example of the performance of a first basis matrix and a binary basis matrix provided in an embodiment of this application;

[0079] Figure 8B shows an example of the performance of another first basis matrix and a binary basis matrix provided in the embodiments of this application;

[0080] Figure 9A is a schematic diagram of a hybrid LDPC matrix provided in an embodiment of this application;

[0081] Figure 9B is a schematic diagram of another hybrid LDPC matrix provided in an embodiment of this application;

[0082] Figure 10 is a schematic diagram of an encoding device provided in an embodiment of this application;

[0083] Figure 11 is a schematic diagram of a decoding device provided in an embodiment of this application;

[0084] Figure 12 is a schematic diagram of the structure of a device provided in an embodiment of this application;

[0085] Figure 13 is a schematic diagram of another device provided in an embodiment of this application;

[0086] Figure 14 is a schematic diagram of the structure of another device provided in an embodiment of this application. Detailed Implementation

[0087] To facilitate understanding of the technical solution of this application, the application will be further described below with reference to the accompanying drawings.

[0088] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used only to distinguish different objects and not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0089] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0090] In this application, "at least one (item)" refers to one or more, "more than one" refers to two or more, "at least two (items)" refers to two or three or more, and "and / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. "Or" indicates that there can be two relationships, such as only A exists and only B exists; when A and B are not mutually exclusive, it can also mean that there are three relationships, such as only A exists, only B exists, and both A and B exist simultaneously. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items. For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0091] In this application, "send" and "receive" indicate the direction of signal transmission. For example, "send information to XX" can be understood as the destination of the information being XX, which can include direct transmission via the air interface or indirect transmission via the air interface from other units or modules. "Receive information from YY" can be understood as the source of the information being YY, which can include direct reception from YY via the air interface or indirect reception from YY via the air interface from other units or modules. "Send" can also be understood as the "output" of a chip interface, and "receive" can also be understood as the "input" of a chip interface. In other words, sending and receiving can occur between devices, such as between network devices and terminal devices, or within a device, such as between components, modules, chips, software modules, or hardware modules within the device via buses, traces, or interfaces.

[0092] Channel coding is one of the core technologies in wireless communication. The complete channel coding process includes adding cyclic redundancy check (CRC) codes, code block segmentation, error correction coding, rate adaptation, code block concatenation, data interleaving, and data scrambling. Among these, error correction coding is the most critical part. The purpose of error correction coding is to ensure that the receiver can automatically correct errors that occur during data transmission with minimal redundancy overhead. At the same bit error rate, the smaller the overhead required, the higher the coding efficiency. Traditional channel coding and decoding generally include linear block codes (such as Hamming codes, Gray codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed-Solomon (RS) codes, etc.), convolutional codes, and concatenated codes. These codes have their own different characteristics and performance, and are suitable for different scenarios.

[0093] In the third generation (3 th -generation, 3G) and fourth generation (4G) th In 5G (5G-generation) mobile communication systems, Turbo codes, as a coding and decoding technique defined by the 3GPP standard, belong to convolutional codes and have excellent performance, approaching the limits of Shannon's theory very closely. th In the 5G era, data transmission rates are orders of magnitude higher than in 4G. For Turbo codes, their serial-processing-based decoders struggle to effectively support such high-speed data transmission. Simultaneously, the 5G era has brought about richer service application scenarios and new requirements for channel coding. For example, mMTC scenarios require smaller data packets, while URLLC scenarios have high requirements for encoding / decoding latency and low error rates. Therefore, based on the key channel coding requirements of the three major 5G application scenarios, 5G adopts quasi-cyclic (QC) low-density parity check (QC-LDPC) codes. In 5G, to adapt to the needs of different communication scenarios, LDPC codes can flexibly support different code lengths and rates. Furthermore, to improve communication reliability, LDPC codes can also support incremental redundancy (IR) hybrid automatic repeat request (IR-HARQ) characteristics.

[0094] Figure 1 is a schematic diagram of the structure of a basis matrix (or fundamental matrix) of an LDPC code provided in an embodiment of this application. As shown in Figure 1, the basis matrix of an LDPC code may include five components: A, B, C, D, and I. Matrix A and matrix B correspond to the core matrix (also called the core matrix, which can be represented by H) in the LDPC code. core Matrix A includes the information bits of the core matrix (i.e., this part corresponds to the information bits), and matrix B includes the parity bits of the core matrix (i.e., this part corresponds to the parity bits). Matrix B can have a double diagonal structure. Matrix C is an all-zero matrix. Matrix D and matrix I correspond to the extended matrices of the LDPC code (also called extended matrices, which can be represented by H). rex (Representation). Matrix D includes the information bits of the extended matrix. Matrix I includes the parity bits of the extended matrix. Matrix I can have a single diagonal structure; for example, matrix I can be an identity matrix.

[0095] The matrix shown in Figure 1 can also be called a raptor-like LDPC code. A raptor-like LDPC code can first design a high-rate parity check matrix (called the core matrix), and then generate parity bits incrementally by expanding the parity check matrix to achieve encoding at multiple rates. Retransmitting the expanded parity bits achieves support for IR-HARQ.

[0096] The core matrix of LDPC codes can be used in high code rate scenarios. This core matrix has a relatively low dimension, and good sparse matrices can be obtained through density evolution and computer-aided methods. The extended matrix of LDPC codes can be generated based on the core matrix; for each row added to the extended matrix, the basis matrix of the LDPC code gains a corresponding column.

[0097] The basis matrix of LDPC codes defined in current 5G protocols is a binary basis matrix, where the elements are either 0 or 1. However, in some application scenarios, the performance of LDPC codes encoded using binary basis matrices is limited, for example, by a high block error rate (BLER). This results in poor decoding performance of binary basis matrices in poor channel environments. Therefore, improving the performance of LDPC codes is an urgent problem to be solved.

[0098] In view of this, this application provides an encoding method, a decoding method, and an apparatus, and provides a structure for a low-density parity check (LDPC) code, which is beneficial to improving the performance of LDPC codes.

[0099] The LDPC codes or LDPC encodings used in this application are merely examples, and other names may be adopted as the standard progresses. This application does not limit the use of these names. Any code whose structure satisfies the basis matrix structure described below should fall within the protection scope of this application.

[0100] The following describes the communication system involved in the embodiments of this application.

[0101] The method provided in this application can be applied to various communication systems, such as Internet of Things (IoT) systems, narrowband Internet of Things (NB-IoT) systems, long term evolution (LTE) systems, 5th-generation (5G) communication systems, new radio (NR) systems, and new communication systems emerging in future communication development. IoT networks may include, but are not limited to, vehicle-to-everything (V2X) networks. Communication methods in V2X systems can be collectively referred to as vehicle-to-everything (V2X), where X can represent anything. For example, V2X can include: vehicle-to-vehicle (V2V) communication, vehicle-to-infrastructure (V2I) communication, vehicle-to-pedestrian (V2P) communication, or vehicle-to-network (V2N) communication, etc. In Figure 2A below, terminal devices (such as terminal device 3) can communicate with each other using device-to-device (D2D), machine-to-machine (M2M), or V2X technologies. The method provided in this application embodiment can also be applied to non-terrestrial network (NTN) communication (also known as non-land network communication).

[0102] The method provided in this application can be applied to wireless local area network (WLAN) systems, such as Wi-Fi. The method provided in this application can also be applied to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series protocols, such as the 802.11be protocol, the 802.11bn protocol, or next-generation protocols of the 802.11bn protocol, etc., and will not be listed individually.

[0103] The method provided in this application can be applied between two entities in a communication system, such as one entity sending information to or receiving information sent by the other entity. In a wireless communication system, communication devices are included, and these devices can communicate wirelessly using air interface resources. Air interface resources may include at least one of time-domain resources, frequency-domain resources, code resources, and spatial resources; this application does not limit this. For example, the aforementioned two entities may include a network device and a terminal device, or may include a chip that can be placed in a network device and a chip that can be placed in a terminal device, etc. Of course, as standards advance, other types of entities may emerge subsequently; this application does not limit this.

[0104] Figure 2A is a schematic diagram of the architecture of a communication system provided in an embodiment of this application. As shown in Figure 2A, the communication system may include at least one network device and at least one terminal device, such as terminal device 1 to terminal device 4 in Figure 2A. The terminal device and the network device can communicate via an air interface Uu link or via an NTN link, etc. For example, terminal device 3 and terminal device 4 can communicate via a D2D sidelink or other similar means. The form of the terminal device shown in Figure 2A is only an example. In a specific implementation, the terminal device may also include in-vehicle equipment or in-vehicle terminals in a vehicle network. This embodiment of the application does not limit the specific form of the terminal device when it is applied to a vehicle network or the Internet.

[0105] Figure 2B is a schematic diagram of the architecture of the communication system provided in an embodiment of this application. As shown in Figure 2B, the scenario of the communication system may include at least one of the following: point-to-point single connection between network devices and terminal devices, point-to-point dual connectivity (DC) between network devices and terminal devices, multi-hop single connection between network devices and terminal devices, or multi-hop dual connection between network devices and terminal devices.

[0106] Figure 2A exemplarily illustrates a network device and multiple terminal devices, while Figure 2B exemplarily illustrates single-connection and dual-connection. In specific implementations, the communication system may also include a greater number of network devices, and the coverage area of ​​each network device may include a greater or lesser number of terminal devices; this application embodiment does not limit this. The architectures shown in Figures 2A and 2B are merely examples and do not impose limitations on the network architecture applicable to this application. Any network architecture usable in this application is one where any network-side device in a cellular network communicates with or senses other devices.

[0107] The application scenarios of this application include, but are not limited to, signal transmission between any number of different devices, such as signal transmission between network devices and terminal devices, signal transmission between network devices and relay devices, signal transmission between relay base stations and terminal devices, signal transmission between multiple network devices and one terminal device, signal transmission between multiple network devices and multiple terminal devices, and signal transmission between one or more terminal devices.

[0108] The following provides a detailed description of terminal equipment and network equipment.

[0109] A terminal device is a device with wireless transceiver capabilities. It can communicate with access network equipment (or access devices, or network devices as described below) in a radio access network (RAN). Terminal devices can also be referred to as user equipment (UE), access terminal, terminal, subscriber unit, user station, mobile station, remote station, remote terminal, mobile device, user terminal, user agent, or user device, etc. In one possible implementation, the terminal device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; or it can be deployed on water, including ships; or it can be deployed in the air, such as on airplanes, balloons, or satellites. In another possible implementation, the terminal device can be a handheld device with wireless communication capabilities, vehicle-mounted device, wearable device, sensor, terminal in the Internet of Things (IoT), terminal in the Internet of Vehicles (IoV), drone, or any form of terminal device in a 5G network or future network; this application does not limit this. In another possible implementation, the terminal device can also be a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in autonomous driving, a wireless terminal in telemedicine, a wireless terminal in a smart grid, a wireless terminal in a smart city, or a wireless terminal in a smart home, etc.

[0110] In this application embodiment, the device for implementing the functions of the terminal device can be the terminal device itself; it can also be a device capable of supporting the terminal device in implementing the functions, such as a chip system. The device can be installed in the terminal device or used in conjunction with the terminal device. In this application embodiment, the chip system can be composed of chips or can include chips and other discrete devices. For ease of description, when examples are mentioned below, the technical solutions provided in this application embodiment are described using the UE as an example to illustrate the device for implementing the functions of the terminal device.

[0111] A network device can be a device deployed in a wireless access network to provide wireless communication services to terminal devices. This network device can also be called an access network device, access equipment, or RAN device, etc. For example, a network device can be a next-generation node B (gNB), a next-generation evolved node B (ng-eNB), or a network device in a future communication system. A network device can be any device with wireless transceiver capabilities, including but not limited to the base stations mentioned above (including base stations deployed on satellites). This network device can also be a device with base station functionality in a future communication system. As an example, this network device can be an access node, wireless relay node, or wireless backhaul node in a wireless-fidelity (Wi-Fi) system. As another example, this network device can be a wireless controller in a cloud radio access network (CRAN) scenario. As yet another example, this network device can be a wearable device or vehicle-mounted device capable of providing wireless communication services. As yet another example, this network device can also be a small cell, a transmission reception point (TRP) (or a transmission point), etc. In systems using different wireless access technologies, the names of devices with network equipment functions may vary, and these will not be listed one by one in the embodiments of this application.

[0112] Network devices can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile network device, and one or more cells can move according to the location of the mobile network device. In other examples, a helicopter or drone can be configured to be used as a device to communicate with another network device.

[0113] In some network device deployments, the network device may include centralized units (CUs) and distributed units (DUs). For example, some protocol layer functions of the network device may be centrally controlled by the CU, while the remaining part or all of the protocol layer functions may be distributed in the DU, which is centrally controlled by the CU. In other network device deployments, the CU may be divided into CU-control plane (CP) and CU-user plane (UP). In still other network device deployments, the network device may also be an open radio access network (ORAN) architecture. When the network device is an ORAN architecture, it may be a functional entity or module within the ORAN. For example, the network device may be one or more of CUs, DUs, or RUs. In an ORAN system, the CU may also be called an open (O)-CU, the DU may also be called an O-DU, the CU-CP may also be called an O-CU-CP, and the CU-UP may also be called an O-CU-UP, etc. The network device deployment methods listed here are merely examples. As standard technologies evolve, network devices may have other deployment forms, and this application does not limit these.

[0114] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing a portion of the access network's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a building baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0115] RAN nodes can support one or more types of fronthaul interfaces, each corresponding to a DU and RU with different functions. If the fronthaul interface between the DU and RU is a common public radio interface (CPRI), the DU is configured to implement one or more baseband functions, and the RU is configured to implement one or more radio frequency functions. If the fronthaul interface between the DU and RU is another type of interface, relative to CPRI, some downlink and / or uplink baseband functions, such as, for downlink, precoding, digital beamforming (BF), or one or more of inverse fast fourier transform (IFFT) / cyclic prefix addition (CP), are moved from the DU to the RU; and for uplink, digital beamforming (BF), or one or more of fast fourier transform (FFT) / cyclic prefix removal (CP), are moved from the DU to the RU. In one possible implementation, the interface can be an enhanced common public radio interface (eCPRI). Under the eCPRI architecture, the segmentation between DU and RU differs, corresponding to different categories (Cat) of eCPRI, such as eCPRI Cat A, B, C, D, E, F.

[0116] Taking eCPRI Cat A as an example, for downlink transmission, layer mapping is used as the dividing line. The DU is configured to implement one or more functions preceding layer mapping (i.e., coding, rate matching, scrambling, modulation, and layer mapping itself), while other functions following layer mapping (e.g., resource element (RE) mapping, digital beamforming (BF), or one or more functions of IFFT / CP addition) are implemented in the RU. For uplink transmission, de-RE mapping is used as the dividing line. The DU is configured to implement one or more functions preceding de-mapping (i.e., decoding, rate matching de-matching, descrambling, demodulation, inverse discrete Fourier transform (IDFT), channel equalization, and one or more functions of de-RE mapping), while other functions following de-mapping (e.g., digital BF or FFT / CP removal) are implemented in the RU. It is understood that descriptions of the functions of the DU and RU corresponding to various types of eCPRI can be found in the eCPRI protocol and will not be elaborated upon here.

[0117] In one possible design, the processing unit in the BBU used to implement baseband functions is called the baseband high (BBH) unit, and the processing unit in the RRU / AAU / RRH used to implement baseband functions is called the baseband low (BBL) unit.

[0118] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0119] Network devices and / or terminal devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and satellites. This application does not limit the scenario in which the network devices and terminal devices are located. Furthermore, terminal devices and network devices can be hardware devices, or software functions running on dedicated hardware or general-purpose hardware, such as virtualization functions instantiated on a platform (e.g., a cloud platform), or entities that include dedicated or general-purpose hardware devices and software functions. This application does not limit the specific form of the terminal devices and network devices.

[0120] In this application embodiment, the device for implementing the function of the network device can be the network device itself; it can also be a device capable of supporting the network device in implementing the function, such as a chip system. The device can be installed in the network device or used in conjunction with the network device. For ease of description, when specific examples are mentioned below, the technical solution provided in this application embodiment will be described using a base station as an example.

[0121] Figure 3 illustrates an example of a communication chip system provided in an embodiment of this application. As shown in Figure 3, the communication chip system includes at least one of two parts: encoding processing (or transmission processing) or decoding processing (or reception processing). The encoding processing part includes at least one of an encoding module, a modulation module, a layer mapping module, a precoding module, a framing module, an IFFT module, and an RF / IRF module. These modules encode, modulate, layer map, precode, frame, and IFFT the layer 2 (L2) data, and then process it into an over-the-air signal to be transmitted through the RF / IRF module. The decoding processing part includes at least one of an RF / IRF module, an FFT module, a deframing module, an equalization module, a de-mapping module, a demodulation module, and a decoding module. These modules process the received signal through RF / IRF to obtain baseband data, and complete physical layer signal processing through FFT, deframing, equalization, de-mapping, demodulation, and decoding to obtain L2 data. The encoding method provided in this application embodiment can be applied to the encoding module of the communication chip system, and the decoding method provided in this application embodiment can be applied to the decoding module of the communication chip system.

[0122] For example, the communication chip system described above may include a baseband chip, which implements the functions of the communication chip system. The communication chip system may not include an IRF module.

[0123] For example, the aforementioned communication chip system may include one or more chips to implement all or part of the functions of the communication chip system (such as encoding, modulation, layer mapping, precoding, framing, IFFT, etc.). Each of the one or more chips may include some modules of the aforementioned communication chip system. For instance, the communication chip system is applied to a base station. In this base station, some functions of the aforementioned communication chip system (e.g., encoding, i.e., the baseband chip of the BBU includes an encoding module) can be implemented by the baseband chip in the BBU, and other functions can be implemented by the baseband chip in the RRU.

[0124] The technical solutions provided in this application can be applied to channel coding / decoding, modulation, and demodulation between communication devices. Channel coding / decoding between communication devices can include: channel coding / decoding between network devices and terminal devices, channel coding / decoding between network devices, or channel coding / decoding between terminal devices. In this application, the term "channel coding / decoding" can also be abbreviated as "coding," and the term "coding" can also be described as "channel encoding / decoding," "network coding," "external code," or "source-channel joint encoding / decoding." The term "coding structure" can also be abbreviated as "coding," "code pattern," or "code design," and the term "coding structure" can also be described as "concatenated code," "layered code," "coupled code," "external code," "sliding window code," "product code," or "ladder code."

[0125] The following description uses encoding and decoding devices as examples to illustrate the method provided in this application. Alternatively, the encoding device can also be called a transmitting end, which can be a device for transmitting modulated signals, and the decoding device can also be called a receiving end, which can be a device for receiving the aforementioned signals. The specific names of the encoding and decoding devices are not limited in this application. As an example, the encoding device can be a terminal device or a chip or functional module of a terminal device, and the decoding device can be a network device or a chip or functional module of a network device. As another example, the encoding device can be a network device or a chip or functional module of a network device, and the decoding device can be a terminal device or a chip or functional module of a terminal device. As yet another example, the encoding and decoding devices can be different terminal devices, etc. Specific forms of the encoding and decoding devices will not be listed here.

[0126] To facilitate understanding of the embodiments of this application, the following is a brief explanation of several terms used in this document.

[0127] Channel coding: Encoding information transmitted through unreliable channels in digital communication to improve the reliability of information transmission. In channel coding, the transmitting end can adopt a certain coding type to convert the original information (such as information bits) into encoded data of a certain format and transmit it through the channel; the receiving end needs to decode the received data and restore the original information. The most critical part of channel coding is forward error correcting coding (FEC). The purpose of error correcting coding is to ensure that the receiving end can automatically correct errors that occur in data transmission with the least possible redundancy overhead. At the same bit error rate, the smaller the overhead required, the higher the coding efficiency. Traditional channel coding types generally include linear block codes (LBCs) (such as Hamming codes, Gray codes, BCH codes (Bose-Chaudhuri-Hocquenghem codes), RS codes (Reed-Solomon codes), etc.), convolutional codes, and concatenated codes. These codes have their own different characteristics and performance, and are suitable for different scenarios.

[0128] Code rate: The proportion of useful information to total information in the encoded data stream. In this application, the input information to be encoded, i.e., the useful information, is denoted as information bits, and the encoded data stream is denoted as encoded bits. Encoded bits include information bits and parity bits (or redundancy bits). For example, if there are K information bits and N encoded bits after channel coding, then the coding code rate is K / N. The number of encoded bits after channel coding can also be called the code length. It can be understood that high redundancy results in a low coding code rate and strong anti-interference capability, but low transmission efficiency; conversely, low redundancy results in a high coding code rate and weak anti-interference capability, but high transmission efficiency.

[0129] LDPC code: A type of linear block code. Because the parity-check matrix of this linear block code has a sparse property, with elements having a value of 1 accounting for a very small proportion, it is also called an LDPC code. For an LDPC code with K information bits and N code length, its parity-check matrix has a dimension of (N-K)×N, and the corresponding codeword can be defined by the parity-check matrix H:

[0130] Where c represents K information bits; w represents (N+D-K) check bits; [cw] T This represents a column vector of length (N+D) consisting of K information bits and (N+D-K) parity bits; D represents the number of puncture bits, which is an integer greater than or equal to 0. D = 0 indicates that no puncturing operation is performed on the codeword. For example, D = 2^Z. c Zc This represents the minimum value of z, where z is the lifting size. The value of z can be predefined and is an integer greater than or equal to 1.

[0131] The process of LDPC encoding based on the parity-check matrix H is to obtain the encoded output [cw] given the parity-check matrix H and the input c to be encoded. T The process; the process of LDPC decoding based on the parity-check matrix H, that is, given the parity-check matrix H and the input to be decoded [cw] T The process of recovering the input c to be encoded.

[0132] Parity-check matrix: Used for LDPC encoding or decoding. In this application, the parity-check matrix is ​​denoted as a matrix H of dimension M×N. Here, M is the number of parity bits, which satisfies: M = N - K. Therefore, the dimension of the parity-check matrix can also be denoted as (N - K)×N.

[0133] In this parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and (N-K) parity-check equations correspond to (N-K) parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and N symbols correspond to N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... p,q This indicates that the p-th check node and the q-th variable node are connected, where p can be an integer greater than or equal to 0 and less than or equal to (M-1), and q can be an integer greater than or equal to 0 and less than or equal to (N-1). The number of non-zero elements in each row of the check matrix H represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, and all variable nodes also have the same degree, the corresponding LDPC code is a regular code; otherwise, it is an irregular code.

[0134] For example, the parity-check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 is as follows:

[0135] In this verification matrix H, each row includes 10 variable nodes, and each column includes 5 verification nodes. If we use v0, v1, ..., v9 to represent the variable nodes and c0, c1, ..., c4 to represent the verification nodes, the verification matrix H can be represented using a graph model, such as a Tanner graph, factor graph, or tree graph. Figure 4 is a schematic diagram of a Tanner graph provided in an embodiment of this application. The Tanner graph representation of the above verification matrix H is shown in Figure 4. The degree of a node can be defined as the number of edges connected to it.

[0136] Quasi-cyclic low-density parity-check (QC-LDPC) codes: a subclass of LDPC. The parity check matrix of a QC-LDPC has quasi-cyclic properties, and its representation can be simplified based on the quasi-cyclic structure. For example, for an (N, K) QC-LDPC code, its parity check matrix H can be represented as:

[0137] Where M = m b ×z, N=n b ×z, P i,j Representing a z×z cyclic shift matrix (also called a cyclic shift square matrix or a cyclic shift submatrix) or a z×z all-zero matrix (also called an all-zero submatrix or an all-zero square matrix), a cyclic shift matrix can be represented by its corresponding cyclic shift coefficient V. i,j To simplify the representation, for example, the cyclic shift matrix can be defined as a cyclic right shift matrix of an identity matrix, where each element "1" in the identity matrix can be based on the cyclic shift coefficient V. i,j Perform a circular shift to the right. Where V i,j When P = -1, i,j V is a z×z matrix containing all zeros; i,j When P = 0, i,j Let V be a z×z identity matrix, which is obtained by cyclically shifting each "1" in the identity matrix to the right by 0 bits (or, in other words, without shifting); i,j ∈[-1, Z max When P = -1], i,j For each element "1" in a z×z identity matrix, cyclically shift V to the right. i,j The matrix obtained by Z max It is the maximum value of z, z≤Z max .

[0138] The element P in the verification matrix H i,j The process of converting a matrix into a cyclic shift matrix or a zero matrix can be achieved using the conversion function g(V). i,j Z) represents the following:

[0139] Where % represents the modulo operation; V i,j The value can be predefined, for example, through a protocol, such as in Tables 5.3.2-2 and 5.3.2-3 of the 3rd generation partnership project (3GPP) technical specification (TS) 38.212.

[0140] With Z=4, Zmax For example, if the value is 8, the element P in the check matrix... i,j The correspondence between these matrices and cyclic shift matrices or all-zero matrices is as follows:

[0141] The matrix corresponding to the element "-1" That is, an all-zero matrix; elements "0" to "7" correspond to a cyclic shift matrix, where elements "0" and "4" correspond to a matrix The matrix corresponding to elements "1" and "5" The matrix corresponding to elements "2" and "6" The matrix corresponding to elements "3" and "7"

[0142] Base graph and base matrix: In some implementations, the base graph can be simplified as a table, array, or sequence indicating the row and column positions of non-zero elements. In other implementations, the base graph can be identified by a base matrix.

[0143] A base graph can be represented as a graph of dimension m. b ×n b The basis matrix is ​​m. The basis matrix can be used to construct the parity-check matrix of a QC-LDPC code. b ×n b The corresponding check matrix has a dimension of (m) b ×z)×(n b As can be seen, each element in the basis matrix can be replaced with a matrix of dimension z×z, which can be called a submatrix of dimension z×z in the parity matrix.

[0144] It should be noted that the terms "z×z matrix" and "z×z submatrix" mentioned above refer to different objects. A single element in the base matrix can replace a z×z matrix, which is only a part of the parity check matrix and can therefore be called a submatrix of the parity check matrix.

[0145] A basis matrix can include zero elements and non-zero elements. Zero elements in a basis matrix can be replaced with a z×z matrix of all zeros; non-zero elements in a basis matrix can be a z×z cyclic parity check matrix P. i,j Let i and j represent the row and column positions of the non-zero elements in the basis matrix, respectively, and P i,j The specific cyclic shift matrix to be replaced can be determined by the transformation function g(V) mentioned above. i,j The determination is made using z, which will not be elaborated upon here.

[0146] In the basis matrix, zero elements can be represented by 0, and non-zero elements can be represented by 1. The number of bits for cyclic shift can be determined according to the conversion function g(V) mentioned above. i,j The value can be determined by (z); or, zero elements can be represented by -1, non-zero elements by 0, and the number of bits for the circular shift can be determined by the conversion function g(V) mentioned above. i,j The value can be determined by (z); or, a zero element can be represented by -1, a non-zero element can be represented by a value greater than or equal to 0, and the number of digits in a cycle can be indicated by the value of the non-zero element. This application does not limit this.

[0147] In this application, the values ​​of the non-zero elements of the basis matrix can be denoted as the first value, and the values ​​of the zero elements can be denoted as the second value. For example, the first value can be 1, and the second value can be 0; or, the first value can be 0, and the second value can be -1; or, the first value can be greater than or equal to 0, and the second value can be -1. The first value corresponds to the cyclic shift matrix in the parity check matrix, and the second value corresponds to the all-zero matrix in the parity check matrix.

[0148] Currently, the NR protocol defines two base maps: BG 1 and BG 2. BG 1 defines a base matrix with a dimension of 46×68 and a core matrix with a dimension of 4×26, and is mainly used for scenarios with high throughput requirements, high bit rate, and long code length. BG 2 defines a base matrix with a dimension of 42×52 and a core matrix with a dimension of 4×14, and is mainly used for scenarios with low throughput requirements, low bit rate, and short code length.

[0149] For example, the BG chosen for channel coding can be determined by the transport block size (TBS) and the code rate R. A possible correspondence between the chosen BG, TBS, and code rate R for channel coding is shown in Figure 5. When TBS ≤ 292, BG2 is chosen for channel coding. Alternatively, when TBS ≤ 3824 and R ≤ 0.67, BG2 is chosen for channel coding. Alternatively, when R ≤ 0.25, BG2 is chosen for channel coding. When 0.25 ≤ R and TBS ≤ 3842, BG1 is chosen for channel coding. When 292 ≤ TBS ≤ 3842 and R ≤ 0.67, BG1 is chosen for channel coding.

[0150] Raptor-like LDPC: Wireless network channel coding requires flexible and variable code rates to meet the needs of HARQ implementation. Generally speaking, raptor-like QC LDPC can easily support rate matching of LDPC codes and IR-HARQ. For example, a Laputa-like QC LDPC code has the characteristics shown in Figure 1: The LDPC parity-check matrix in Figure 1 consists of two matrices, part-1 and part-2. Part-1 is a higher-rate LDPC matrix, typically with a double-diagonal structure (parity bits in the core matrix) or a lower triangular structure. Part-1 can independently perform encoding and decoding as a higher-rate LDPC code and is also called the core matrix. Part-1 can include matrices A and B as shown in Figure 1. Part-2 can include two parts, namely a left matrix and a right matrix. The number of columns in the left matrix is ​​equal to the number of columns in the core matrix (as shown in matrix D in Figure 1). The right matrix is ​​an identity matrix, and the column weight of each column in this identity matrix is ​​1 (column weight refers to the number of non-zero elements in a column of the matrix) (as shown in matrix I in Figure 1). Part-2 can also be called an extended matrix. Part-2 and part-1 matrices can be combined to form a complete LDPC code.

[0151] The methods involved in this application are described below.

[0152] Figure 6 is a flowchart illustrating a communication method provided in an embodiment of this application. This communication method involves an encoding process and a decoding process; the encoding-related process can be referred to as the encoding method, and the decoding-related process as the decoding method. As shown in Figure 6, the method includes:

[0153] 601. The encoding device acquires the first bit sequence.

[0154] The length of the first bit sequence can be K, meaning the first bit sequence can include K bits. K is a positive integer. The first bit sequence can be called the information bit sequence or the bit sequence to be encoded, such as c in formula (1).

[0155] As an example, the first bit sequence may include cyclic redundancy check (CRC) bits. For instance, the encoding device acquires a transport block (TB), adds a CRC to the TB, selects the block class (BG) used for LDPC encoding, and segments the CRC-added transport block into code blocks based on the selected BG to obtain a code block (CB). Adding a CRC to the code block yields the first bit sequence. As another example, the first bit sequence may not include CRC bits. This application does not limit whether the first bit sequence includes CRC bits.

[0156] Generally, the encoding device can determine the value of K based on transmission resources, modulation order, and coding rate. As one possible implementation, the transmission resources are the number of available resource elements (REs) NRE, the coding rate is R, and the modulation order (i.e., the number of bits carried by each RE) is Q; then K = NRE * Q * R. As another possible implementation, using multiple-in multiple-out (MIMO) technology, the transmission resources can be the number of available REs across multiple layers NRE_MIMO; correspondingly, K = NRE_MIMO * Q * R. For example, NRE_MIMO = V * NRE_1, where V is the number of MIMO layers and NRE_1 is the number of available REs in each layer. The value of K can also be determined in other ways, which are not limited in this embodiment.

[0157] 602. The encoding device encodes the first bit sequence based on the first base matrix of the LDPC code to obtain the second bit sequence.

[0158] The first basis matrix includes a first submatrix, the values ​​of which are taken from the Galois field GF(2). m That is, the value of an element in the first submatrix is ​​less than or equal to 2. m -1. Where m is a positive integer greater than 1. The first basis matrix can also be called a non-binary basis matrix or a multi-element basis matrix. For example, when m is 3, the values ​​of the elements in the first submatrix are taken from GF(8), that is, the values ​​of the elements in the first submatrix are values ​​in the set {0,1,2,3,4,5,6,7}, and the first basis matrix can also be called an 8-element basis matrix.

[0159] For example, the above m can be predefined by the protocol, configured by higher-layer signaling (such as radio resource control (RRC) signaling), or configured by physical layer control information (such as downlink control information (DCI)).

[0160] For example, the first basis matrix has a Laptor-like structure, such as including a core matrix and an extended matrix. Alternatively, the structure of the first basis matrix can be as shown in Figure 7A, where it includes matrices A, B, C, D, and I. Matrices A and B correspond to the core matrix of the first basis matrix; matrix A corresponds to system bits; matrix B corresponds to parity bits in higher code rate scenarios; matrix C is an all-zero matrix; and matrices D and I correspond to low-density extended matrices. The first submatrix can be the first basis matrix or a part of the first basis matrix. For example, the first submatrix includes the core matrix of the first basis matrix, i.e., it includes matrices A and B. Alternatively, the first submatrix includes the core matrix and the extended matrix of the first basis matrix, i.e., it includes matrices A, B, D, and I. Alternatively, the first submatrix is ​​the first basis matrix, i.e., it includes matrices A, B, an all-zero matrix C, D, and I.

[0161] In one possible implementation, the encoding device determines one or more expansion factors, expands the elements of a first base matrix according to these expansion factors to obtain a parity check matrix, and encodes a first bit sequence based on the parity check matrix to obtain a second bit sequence. The one or more expansion factors include an expansion factor z corresponding to the first submatrix, and the elements of the first submatrix include a first element, which corresponds to a z×z matrix in the parity check matrix; where z is a positive integer. Based on the expansion factor z, each element in the first submatrix can be expanded into a z×z matrix.

[0162] The z×z matrix corresponding to the first element is the following matrix (for ease of description, it is referred to as matrix 1) or the z×z matrix corresponding to the first element is a circular shift matrix of the following matrix:

[0163] Where k represents the value of the first element, k is greater than or equal to 0 and less than or equal to 2. m An integer of -1.

[0164] The z×z matrix corresponding to the first element can be determined based on the offset value p corresponding to the first element in the offset matrix, where p is a positive integer. For example, the z×z matrix corresponding to the first element is the matrix obtained by cyclically shifting matrix 1 to the right by p bits. For instance, when the offset value corresponding to the first element is -1, the z×z matrix corresponding to the first element is a matrix of all zeros. When the offset value corresponding to the first element is 0, the z×z matrix corresponding to the first element is the matrix 1 mentioned above. When the offset value corresponding to the first element is 1, the z×z matrix corresponding to the first element is the matrix obtained by cyclically shifting matrix 1 to the right by 1 bit. And so on, without further listing. It is understandable that the correspondence between the value of the first element, the matrix of all zeros, and the offset value can also take other forms, which can be obtained based on predefined or pre-stored values. For example, the first value of the first element corresponds to a z×z matrix of all zeros, the second value corresponds to a z×z matrix with a cyclic shift of value #1, the third value corresponds to a z×z matrix with a cyclic shift of value #2, and so on.

[0165] For example, the values ​​of the elements in the first submatrix are taken from GF(2). m An element in the first submatrix can correspond to an m×m binary matrix. For example, element 0 in the first submatrix corresponds to an m×m matrix of all zeros. Furthermore, if element k in the first submatrix is ​​greater than 0, then element k represents the (k-1)th power of the m×m binary submatrix.

[0166] For example, if m is 3, and the values ​​of the elements in the first submatrix are taken from the GF(8) field, and the primitive polynomial of the GF(8) field is: p(x) = x 3 +x+1, then the binary submatrix F can be expressed as:

[0167] The seven non-zero values ​​in the GF(8) field correspond to different powers of the binary submatrix F: {F k :k=0,…,6}.

[0168] As an example, the encoding device determines multiple expansion factors, each of which can correspond to different parts of the first base matrix. For instance, the first base matrix includes a first submatrix and a second submatrix, and the multiple expansion factors include a first expansion factor z and a second expansion factor y. The first expansion factor z corresponds to the first submatrix, and the second expansion factor y corresponds to the second submatrix. An element in the first submatrix can be expanded into a z×z matrix, and an element in the second submatrix can be expanded into a y×y matrix. That is, an element in the first submatrix can correspond to a z×z matrix in the parity check matrix, and an element in the second submatrix can correspond to a y×y matrix in the parity check matrix. Here, y is a positive integer.

[0169] In this example, different parts of the first basis matrix can use different expansion factors, allowing for more flexible expansion of the first basis matrix.

[0170] As another example, the encoding device determines an expansion factor z, such that any element in the first basis matrix can be expanded into a z×z matrix, meaning any element in the first basis matrix corresponds to a z×z matrix in the parity check matrix. In this example, the expansion factors corresponding to the elements in the first basis matrix are all the same, making implementation simple.

[0171] In one possible implementation, the method shown in Figure 6 further includes: an encoding device acquiring a third bit sequence, encoding the third bit sequence according to the second basis matrix of the LDPC code, to obtain a fourth bit sequence. Here, the positions of non-zero elements in the second basis matrix are the same as those in the first basis matrix, and the value range of the elements in the second basis matrix is ​​{0,1}, that is, the value of the elements in the second basis matrix is ​​0 or 1. This second basis matrix can also be called a binary basis matrix.

[0172] For example, the second basis matrix has a Laptor-like structure, as shown in Figure 1. Further details regarding this second basis matrix can be found in the description within the 5G standard.

[0173] The positions of non-zero elements in the second basis matrix are the same as those in the first basis matrix. This can be understood as the first and second basis matrices having the same structure, except that the values ​​of the elements in the first submatrix of the first basis matrix are taken from GF(2). m The values ​​of the elements in the second basis matrix are GF(2). For example, the first basis matrix can be shown in Figure 7A, and the second basis matrix can be shown in Figure 7B.

[0174] As an example, the encoding device can store a second basis matrix, from which the first basis matrix can be determined. For instance, the first basis matrix can be determined by replacing the GF(2) field of the non-zero elements in the second basis matrix with GF(2). m ) domain obtained.

[0175] As another example, the encoding device stores a first basis matrix and a second basis matrix, and the encoding device can determine whether to use the first basis matrix or the second basis matrix for LDPC encoding according to business requirements.

[0176] As another example, the encoding device stores a second basis matrix and a first matrix, the first basis matrix being determined by the second basis matrix and the first matrix. The first matrix has the same dimensions as the second basis matrix, that is, the number of columns in the first matrix is ​​the same as the number of columns in the second basis matrix, and the number of rows in the first matrix is ​​the same as the number of rows in the second basis matrix. The positions of the non-zero elements in the first matrix are the same as the positions of the non-zero elements in the first basis matrix, and the values ​​of the non-zero elements in the first matrix are taken from GF(2).m The second basis matrix can be the matrix shown in Figure 7B, and the first matrix can be the matrix shown in Figure 7A. In the second basis matrix, an element 0 indicates that there is no value at the corresponding position, and an element 1 indicates that there is a value at the corresponding position, specifically the value of the element at the same position in the first matrix. That is, the first matrix is ​​used to indicate the GF(2) corresponding to the non-zero elements in the first basis matrix. m The values ​​of the domain, this first matrix can also be called a multivariate value matrix.

[0177] In one possible implementation, the value of the element in the i-th row of the first submatrix is ​​determined by the elements in the first set of values, which is related to the number of non-zero elements in the i-th row, where i is a positive integer.

[0178] The first set of values ​​can be a predefined set of values. For example, the first set of values ​​may be predefined by a standard or protocol. Alternatively, the first set of values ​​may be predefined by an encoding or decoding device. The encoding or decoding device stores the first set of values, and the encoding and decoding devices store the same first set of values.

[0179] For example, the value of a non-zero element in the i-th row of the first submatrix is ​​determined by an element in the first value set. For instance, the value of a non-zero element in the i-th row of the first submatrix is ​​a function of an element in the first value set. For example, the value of a non-zero element in the i-th row is equal to the value of an element in the first value set. Alternatively, if the value of an element in the first value set corresponds to a power of the binary submatrix, the value of a non-zero element in the i-th row is the value of an element in the first value set plus 1. This application does not limit the positional relationship between the element in the i-th row and its corresponding element in the first value set.

[0180] The number of elements in the first value set can be greater than or equal to the number of non-zero elements in the i-th row (i.e., the row weight of the i-th row). When the row weight of the i-th row changes, the corresponding first value set can change accordingly. In other words, two rows with different row weights in the first submatrix correspond to different value sets. The encoding device can determine the first value set corresponding to the i-th row based on the correspondence between row weights and value sets.

[0181] The encoding device can store the correspondence between row weights and value sets, and determine the first value set based on the correspondence between row weights and value sets and the row weight of the i-th row. For example, the correspondence between row weights and value sets can be stored as shown in Table 1 or Table 2. The value of an element in the value set shown in Table 1 or Table 2 represents the power of the corresponding binary submatrix, and the value in the first submatrix is ​​the corresponding value in the value set plus 1. For example, the element "0" in the value set corresponds to the element "1" in the first submatrix (because the element "0" in the basis matrix of the LDPC code indicates that there is no value at that position).

[0182] As an example, the number of elements in the first value set is equal to the number of non-zero elements in the i-th row. The value of a non-zero element in the i-th row corresponds to the value of an element in the first value set. That is, there is a one-to-one correspondence between the non-zero elements in the i-th row and the elements in the first value set.

[0183] Optionally, the minimum code distance and / or the number of minimum weight codewords in the second matrix corresponding to the first set of values ​​satisfy certain conditions. The minimum code distance of the second matrix refers to the minimum number of elements with the same position but different values ​​in any two rows of the second matrix. The minimum weight codeword refers to the minimum number of 1s in any row of the second matrix. The second matrix corresponding to the first set of values ​​can be obtained by replacing the elements in the tuple corresponding to the i-th row with the corresponding m×m matrix, or by replacing the non-zero elements in the i-th row with the corresponding m×m matrix. The tuple corresponding to the i-th row consists of the non-zero elements in the i-th row. For example, the first set of values ​​is the set with the largest minimum code distance among multiple sets of values ​​corresponding to the second matrix, and / or the first set of values ​​is the set with the fewest minimum weight codewords in the second matrix among multiple sets of values. This first set of values ​​can also be called the optimal tuple set. The multiple sets of values ​​are the possible sets of one or more non-zero elements in the i-th row. For example, the i-th row contains s non-zero elements, and any set of these multiple value sets includes s elements, where the value of any of these s elements ranges from 0 to 2. m -2 or 1~2 m -1. The values ​​of elements in any two of the multiple value sets are not exactly the same.

[0184] For example, when m is 2, the correspondence between row weight and value set can be shown in Table 1. That is, the values ​​of the elements in the first basis matrix corresponding to GF(4) can be determined by Table 1. As shown in Table 1, when the row weight of the i-th row is 3, the first value set is {0,1,2}, and the values ​​of the three non-zero elements in the i-th row are 1, 2, and 3 respectively, and the corresponding arrangement order can be arbitrary.

[0185] Table 1

[0186] For example, when m is 3, the correspondence between row weight and value set can be shown in Table 2. That is, the values ​​of the elements in the first basis matrix corresponding to GF(8) can be determined by Table 2. As shown in Table 2, when the row weight of the i-th row is 6, the first value set is determined as {0,1,2,3,4,5}, and the values ​​of the 6 non-zero elements in the i-th row are 1, 2, 3, 4, 5, and 6, respectively. The corresponding arrangement order can be arbitrary, and this application does not restrict it, as shown in the first row of the first basis matrix in Figure 7A. For example, the row weight of the third row of the first basis matrix shown in Figure 7A is 7. According to Table 2, the value set corresponding to the row weight of 7 is {0,1,2,3,4,5,6}, and the values ​​of the non-zero elements in the third row are 1, 2, 3, 4, 5, 6, and 7, respectively. The corresponding arrangement order can be arbitrary, and this application does not restrict it.

[0187] Table 2

[0188] As another example, the number of elements in the first value set can be greater than the row weight of the i-th row. For instance, the first value set can be any set of values ​​corresponding to a row weight greater than that of the i-th row. For example, if m is 3, and the row weight of the i-th row is 4, the first value set can be any set of values ​​corresponding to row weights of 5, 6, or 7 as shown in Table 2. The values ​​of the four non-zero elements in the i-th row correspond to any four values ​​in the set of values ​​corresponding to 5, 6, or 7.

[0189] In one possible implementation, the method shown in Figure 6 may also include:

[0190] As one example, the encoding device includes a network device, and the decoding device includes a terminal device. The encoding device can send modulation and coding scheme (MCS) information, and the decoding device receives the MCS information. As another example, the encoding device includes a terminal device, and the decoding device includes a network device. The decoding device can send MCS information, and the encoding device can receive the MCS information. As yet another example, the encoding device can send MCS information to the decoding device, and the decoding device can receive the MCS information.

[0191] The aforementioned MCS information can be used to indicate the coding rate and / or modulation order. Generally, the coding rate determines the ratio of the number of information bits before encoding to the number of bits after encoding. For example, if the coding rate is represented by R, then R = K / N. The modulation order determines the number of bits corresponding to a constellation point in a constellation diagram, or the number of bits corresponding to a modulation symbol after modulation. For instance, the encoding device can determine the coding rate and modulation order by acquiring the MCS information, and determine the value of K in conjunction with transmission resources. Furthermore, the encoding device can also determine the aforementioned value of z, etc. Then, encoding is performed based on the aforementioned value of z.

[0192] 603. The encoding device outputs the second bit sequence.

[0193] The length of the second bit sequence can be N, meaning it can include N bits. N is a positive integer. The second bit sequence can also be an encoded bit sequence, including information bits and check bits. For example, the second bit sequence is [cw] in formula (1). T .

[0194] Optionally, when the encoding device transmits the second bit sequence, it does not perform a puncturing operation, that is, all bits in the second bit sequence are transmitted.

[0195] 604. The encoding device sends the signal obtained after processing the second bit sequence.

[0196] Correspondingly, the decoding device receives the signal.

[0197] After the encoding device outputs the second bit sequence, it can further process the second bit sequence. This processing may include, but is not limited to, rate matching, modulation, multiple-in-multiple-out (MIMO) coding (MIMO precoding), subcarrier mapping, or inverse fast fourier transform (IFFT). The encoding device can then transmit the processed signal of the second bit sequence through the channel. The decoding device receives the transmitted signal and processes it (e.g., performs the inverse processing corresponding to the above processing) to obtain the second bit sequence.

[0198] 605. The decoding device obtains the second bit sequence.

[0199] The second bit sequence is the sequence to be decoded. For example, the decoding device can obtain the sequence to be decoded through demodulation. Demodulation is the inverse process of modulation, that is, the process of recovering the received signal into a bit sequence. For example, demodulation methods can include hard decision and soft decision. The output of hard decision demodulation is 0 or 1, and the output of soft decision demodulation is the log-likelihood ratio (LLR). Further explanation of how the decoding device obtains the sequence to be decoded can be found in step 604, etc., and will not be detailed here.

[0200] 606. The decoding device decodes the second bit sequence based on the first base matrix of the LDPC code to obtain the first bit sequence.

[0201] In one possible implementation, the decoding device determines one or more expansion factors, expands the elements in the first basis matrix according to the one or more expansion factors to obtain a parity check matrix, and decodes the second bit sequence based on the parity check matrix to obtain the first bit sequence.

[0202] For details on the specific implementation of the decoding device expanding the elements of the first base matrix according to the one or more expansion factors, please refer to the specific implementation of the encoding device expanding the elements of the first base matrix according to the one or more expansion factors, which will not be repeated here.

[0203] Decoding is the reverse process of encoding. Exemplary decoding methods that a decoding device can employ include, but are not limited to, hard-decision decoding, soft-decision decoding, or hybrid decoding methods. Examples of decoding methods include min-sum (MS) decoding and belief propagation decoding. For instance, the decoding device can initialize the input sequence to be decoded and perform iterative processing. After iteration, it performs hard-decision detection and verifies the hard-decision result. If the decoding result conforms to the verification equation, the decoding is successful, the iteration terminates, and the decision result is output. If the decoding result does not conform to the verification equation, iterative processing is performed again within the maximum number of iterations. If the maximum number of iterations is reached and verification still fails, the decoding fails. The decoding methods shown here are merely examples; this application does not limit other decoding processes. A description of the basis matrix or offset matrix used by the decoding device during decoding can be found below.

[0204] In this embodiment, steps 601 to 603 can be implemented by an encoding device, such as a chip, functional module, or device. For example, the sending step in step 604 can be implemented by an encoding device. Steps 605 and 606 can be implemented by a decoding device, such as a chip, functional module, or device. For example, the receiving step in step 604 can be implemented by a decoding device. In a specific implementation, the method shown in FIG6 can be divided into an encoding method and a decoding method. Optionally, the encoding method and the decoding method can each be referred to as a communication method.

[0205] In this embodiment, the range of values ​​for the elements in the first submatrix is ​​extended to GF(2). m The first submatrix is ​​set to 3, and the first submatrix is ​​the first base matrix (i.e., the elements in the first base matrix are taken from GF(8)). The performance comparison between the first base matrix (e.g., 8-ary LDPC code) provided in this application embodiment and the binary base matrix (e.g., 5G LDPC code) defined in the 5G standard can be shown in Figures 8A and 8B. Figure 8A shows the performance comparison between the first base matrix and the binary base matrix when the information bit length K = 400 and the code rate R = 0.4. Figure 8B shows the performance comparison between the first base matrix and the binary base matrix when the information bit length K = 400 and the code rate R = 0.33. As shown in Figure 8A or Figure 8B, under the same signal-to-noise ratio (i.e., E b Under the condition of / N0), the block error rate (BLER) of the octal LDPC code is less than that of the binary LDPC code, meaning that the performance of the octal LDPC code is higher than that of the binary LDPC code. Especially when the spread factor is greater than 10 and / or the code rate is between 0.4 and 0.3, the multi-ary LDPC code provided in this application embodiment has better performance.

[0206] Regarding the first submatrix, the embodiments of this application also provide the following implementation:

[0207] Implementation Method 1: The first submatrix includes the core matrix and the extended matrix of the first basis matrix. For example, the first submatrix includes the aforementioned matrices A, B, D, and I.

[0208] For example, the first submatrix may include a core matrix, an extended matrix, and a zero-matrix C, meaning the first submatrix is ​​the same as the first basis matrix. In this implementation, the first basis matrix does not include the second submatrix.

[0209] In this implementation, the values ​​of the elements in the first basis matrix are taken from GF(2). mThe expansion factor corresponding to the first submatrix applies to the first base matrix. In other words, when the encoding device performs LDPC encoding on the first bit sequence, it determines an expansion factor and expands the elements in the first base matrix using this expansion factor.

[0210] For example, the expansion factor corresponding to the first basis matrix is ​​selected from the set of expansion factors corresponding to the first basis matrix. The set of expansion factors corresponding to the first basis matrix can be a subset of the set of expansion factors corresponding to the second basis matrix, which can be the set of expansion factors corresponding to the binary basis matrix defined in the 5G standard.

[0211] For example, Table 3 shows several examples of the expansion factor set corresponding to the second base matrix. The expansion factor set corresponding to the second base matrix can include a combination of one or more sets of expansion factor sets shown in Table 3, wherein different expansion factor sets correspond to different code rates and code lengths. After the encoding device determines the expansion factor set corresponding to the first base matrix based on the code rate and code length, it can determine the expansion factor to be used (i.e., the expansion factor corresponding to the first base matrix) from the expansion factor set corresponding to the first base matrix based on the length K of the first bit sequence and the dimension of the first base matrix.

[0212] Table 3

[0213] It is understood that the set of expansion factors corresponding to the second basis matrix shown in Table 3 is merely an example and should not be construed as a limitation on the embodiments of this application. In the embodiments of this application, the set of expansion factors corresponding to the second basis matrix can also refer to the relevant provisions in the 5G standard, which will not be detailed here.

[0214] For example, due to GF(2 m Each symbol in the first base matrix contains m bits, meaning that the number of bits in each element of the first base matrix is ​​m times the number of bits in each element of the second base matrix. Therefore, to keep the maximum (N,K) parameters (such as the number of systematic bits and parity bits) of the first and second base matrices comparable, the spread factor of the first base matrix is ​​smaller than that of the second base matrix for the same (N,K) code parameters. For example, the spread factor of the first base matrix is ​​1 / m of the spread factor of the second base matrix.

[0215] As an example, the set of one or more expansion factors corresponding to the first base matrix includes the set of one or more expansion factors corresponding to the second base matrix; or, in other words, the set of one or more expansion factors corresponding to the first base matrix is ​​taken from a portion of the set of expansion factors corresponding to the second base matrix. For the same set of expansion factors, the range of code rate and / or code length corresponding to the set of expansion factors corresponding to the first base matrix can be different from the range of code rate and / or code length corresponding to the second base matrix. For example, the length of the range of code rate and / or code length corresponding to the set of expansion factors corresponding to the first base matrix is ​​greater than the length of the range of code rate and / or code length corresponding to the second base matrix.

[0216] For example, the set of expansion factors corresponding to the first base matrix may include a combination of one or more sets as shown in Table 4. Specifically, the range of code length and / or code rate corresponding to set index 0 in Table 4 differs from the range of codeword and / or code rate corresponding to set index 0 in Table 3; the range of code length and / or code rate corresponding to set index 1 in Table 4 differs from the range of codeword and / or code rate corresponding to set index 1 in Table 3; and the range of code length and / or code rate corresponding to set index 2 in Table 4 differs from the range of codeword and / or code rate corresponding to set index 2 in Table 3.

[0217] Table 4

[0218] As another example, under the same (N, K) code parameters, the size of the expansion factor corresponding to the first basis matrix is ​​approximately 1 / m of the expansion factor corresponding to the second basis matrix. The set of expansion factors corresponding to the first basis matrix can be selected from the M / m portion of the set of expansion factors corresponding to the second basis matrix, where M is the maximum value in the set of expansion factors corresponding to the second basis matrix.

[0219] For example, when m is 3, for the set of expansion factors with index 0, the maximum expansion factor corresponding to the second basis matrix can be 256. Therefore, the maximum expansion factor corresponding to the first basis matrix can be 256 / 3 (approximately 83). Thus, the set of expansion factors corresponding to the first basis matrix can be selected from the portion of the second basis matrix that is less than 83, i.e., the set of expansion factors corresponding to the first basis matrix is ​​{2, 4, 8, 16, 32, 64}. The set of expansion factors corresponding to the first basis matrix can include a combination of one or more sets as shown in Table 5.

[0220] Table 5

[0221] It is understood that the set of expansion factors shown in Table 5 can also be applied to cases where m is 4 or 5 or other values, and this application does not impose any restrictions on this.

[0222] Optionally, in some possible implementations, the set of expansion factors corresponding to the first base matrix may not be selected from the set of expansion factors corresponding to the second base matrix. For example, the encoding device may store a set of expansion factors or a table of expansion factors applicable to the first base matrix, that is, a set of expansion factors or a table of expansion factors corresponding to the first base matrix.

[0223] Implementation Method 2: The first submatrix is ​​a part of the first basis matrix (such as the core matrix). The first basis matrix also includes a second submatrix, in which the values ​​of the elements range from {0,1}. That is, the second submatrix is ​​a binary matrix, and the first basis matrix includes both a multivariate part and a binary part.

[0224] For example, the first submatrix includes the core matrix of the first basis matrix, such as the first submatrix including matrix A and matrix B. Alternatively, the first submatrix includes the core matrix and a matrix of all zeros, i.e., the first submatrix includes matrix A, matrix B, and matrix C. The second submatrix includes the extended matrix of the first basis matrix, such as the second submatrix including matrix D and matrix I. That is, the value of the core matrix in the first basis matrix is ​​taken from GF(2...). m The value of the extended matrix in the first basis matrix is ​​taken from GF(2). This first basis matrix can also be called a hybrid LDPC matrix or a hybrid matrix.

[0225] As an example, the first submatrix consists of a core matrix and a zero-based matrix C, and the second submatrix consists of an extension of the first base matrix. The first submatrix has the same number of columns as the second submatrix. Alternatively, the first submatrix is ​​the core matrix, the second submatrix is ​​the extension matrix, and the matrix D in both the first and second submatrixes has the same number of columns.

[0226] In this example, the first basis matrix can be achieved by replacing the values ​​of the elements in the core matrix portion of the second basis matrix with GF(2). m The values ​​in the first basis matrix are obtained by keeping the extended matrix part unchanged. This first basis matrix can be shown in Figure 9A.

[0227] In this example, since each element in the first submatrix corresponds to m bits and each element in the second submatrix corresponds to 1 bit, different expansion factors can be used for the first and second submatrixes when expanding the first base matrix. This ensures that the row and column sizes of the hybrid LDPC matrix correspond. That is, the expansion factors for the first and second submatrixes are different. For example, the expansion factor for the first submatrix is ​​smaller than the expansion factor for the second submatrix.

[0228] For example, the expansion factor corresponding to the second submatrix is ​​y, and the expansion factor corresponding to the first submatrix is ​​y. or Where y is a positive integer. This indicates rounding down. This indicates rounding up. The encoding device can determine the expansion factor y corresponding to the second submatrix based on the set of expansion factors corresponding to the second base matrix (or the binary base matrix specified in the 5G standard) (as shown in Table 3 above), and then determine the expansion factor corresponding to the first submatrix based on the expansion factor y corresponding to the second submatrix.

[0229] For example, the expansion factor corresponding to the first submatrix is ​​z, and the expansion factor corresponding to the second submatrix is ​​m×z; where z is a positive integer. For example, if m is 3, the expansion factor corresponding to the first submatrix is ​​z, and the expansion factor corresponding to the second submatrix is ​​3z. The encoding device can determine the expansion factor z corresponding to the first submatrix based on the set of expansion factors corresponding to the multivariate basis matrices (as shown in Table 4 or Table 5 above), and then determine the expansion factor y corresponding to the second submatrix based on the expansion factor z corresponding to the first submatrix.

[0230] By using the constraints between y and z mentioned above, it can be guaranteed that the final hybrid LDPC matrix, after expansion, will be a standard rectangular matrix.

[0231] As another example, the number of columns in the second submatrix is ​​m times the number of columns in the first submatrix.

[0232] In this example, the first basis matrix can be created by replacing an m×m submatrix in the second basis matrix (i.e., the binary basis matrix) with an element from the first submatrix. One row in the first submatrix corresponds to m rows in the second basis matrix. That is, the first basis matrix is ​​created by replacing some rows and columns of the second basis matrix with an element derived from GF(2). m The element values ​​of the first submatrix are replaced. The number of rows replaced in the second basis matrix is ​​a multiple of m. For example, if m = 3, the 3×3 submatrix of the second basis matrix is ​​replaced with one element from the first submatrix, and at least the first 3 rows of the second basis matrix are replaced with values ​​from the 8-element field. The first basis matrix can also be called a hybrid LDPC matrix.

[0233] For example, when m is 3, the first basis matrix can also be called an 8-element mixed LDPC matrix. Figure 9B shows an example of a binary basis matrix and an 8-element mixed LDPC matrix. As shown in Figure 9B, the first row of the 8-element mixed LDPC matrix is ​​obtained by replacing the first 3 rows of the binary basis matrix with the values ​​in the 8-element field. For example, the first element 4 in the first row corresponds to the first 3×3 submatrix in the binary basis matrix:

[0234] In this example, the expansion factors for the first and second submatrices are the same. Since the first submatrice corresponds to m bits and the second submatrice corresponds to 1 bit, and the number of columns in the second submatrice is m times the number of columns in the first submatrice, using the same expansion factor to expand the first and second submatrices ensures that the expanded matrix is ​​a standard rectangular matrix.

[0235] The apparatus provided in the embodiments of this application will be described below.

[0236] This application divides the device into functional modules according to the above method embodiments. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware or as software functional modules. It should be noted that the module division in this application is illustrative and only represents one logical functional division; other division methods may be used in actual implementation. The device of the embodiment of this application will be described in detail below with reference to Figures 10 to 14.

[0237] Figure 10 is a schematic diagram of an encoding device provided in an embodiment of this application. This encoding device is used to perform the actions executed by the encoding device in the above method embodiments. As shown in Figure 10, the encoding device may include a calculation unit 1001 and a storage unit 1002. The calculation unit can be used to perform encoding-related operations of the encoding device in the above method embodiments, and the storage unit 1002 is used to store relevant instructions and / or data involved in the above method embodiments, so that the encoding device implements the aforementioned method embodiments. For example, the storage unit 1002 is used to store at least one of the first base matrix, second base matrix, first value set, and expansion factor set shown in the above method embodiments.

[0238] For example, the computing unit 1001 is used to obtain a first bit sequence, encode the first bit sequence according to the first base matrix of the LDPC code to obtain a second bit sequence, and output the second bit sequence.

[0239] Optionally, the computing unit 1001 is also used to obtain the third bit sequence, encode the third bit sequence according to the second base matrix of the LDPC code to obtain the fourth bit sequence, and output the fourth bit sequence.

[0240] It is understood that specific descriptions of the first base matrix, the second base matrix, the first bit sequence, the second bit sequence, the third bit sequence, the fourth bit sequence, etc., can be found in the relevant descriptions in the above method embodiments, and will not be elaborated here.

[0241] For example, the calculation unit 1001 can also be used for at least one of the following operations: TB CRC calculation, BG selection, code block segmentation, CB CRC calculation, and code block concatenation. For instance, the calculation unit 1001 performs TB CRC calculation, BG selection, code block segmentation, CB CRC calculation, LDPC encoding, and code block concatenation to complete the encoding process.

[0242] Optionally, the encoding device shown in FIG10 may further include a control unit 1003, which is responsible for controlling the computing unit 1001 and the storage unit 1002.

[0243] Figure 11 is a schematic diagram of a decoding device provided in an embodiment of this application. This decoding device is used to perform the actions executed by the decoding device in the above method embodiments. As shown in Figure 11, the decoding device may include a calculation unit 1101 and a storage unit 1102. The calculation unit can be used to perform decoding-related operations of the decoding device in the above method embodiments, and the storage unit 1102 is used to store relevant instructions and / or data involved in the above method embodiments, so that the decoding device implements the aforementioned method embodiments. For example, the storage unit 1102 is used to store at least one of a first base matrix, a second base matrix, a first value set, an expansion factor set, etc.

[0244] For example, the calculation unit 1101 is used to obtain the second bit sequence and decode the second bit sequence according to the first basis matrix of the LDPC code to obtain the first bit sequence.

[0245] Optionally, the computing unit 1101 is also used to obtain the fourth bit sequence, and decode the fourth bit sequence according to the second basis matrix of the LDPC code to obtain the third bit sequence.

[0246] It is understood that specific descriptions of the first base matrix, the second base matrix, the first bit sequence, the second bit sequence, the third bit sequence, the fourth bit sequence, etc., can be found in the relevant descriptions in the above method embodiments, and will not be elaborated here.

[0247] For example, the calculation unit 1101 can also be used for at least one of the following operations: rate matching, HARQ merging, CB CRC check, and TB CRC check. For example, the calculation unit 1101 performs rate matching, HARQ merging, LDPC decoding, CB CRC check, and TB CRC check to complete the decoding process.

[0248] Optionally, the encoding device shown in FIG11 may further include a control unit 1103, which is responsible for controlling the computing unit 1101 and the storage unit 1102.

[0249] Figure 12 is a schematic diagram of a device provided in an embodiment of this application. As shown in Figure 12, the device includes a processing module 1201 and a transceiver module 1202. The transceiver module 1202 can implement corresponding communication functions, and the processing module 1201 is used to implement corresponding processing functions. For example, the transceiver module 1202 can also be referred to as an interface, a communication interface, a communication module, or an input / output interface, etc.

[0250] In some embodiments of this application, the device can be used to perform the actions performed by the encoding device in the above method embodiments. In this case, the encoding device can be the network device itself or a chip or functional module configurable in the network device, or the encoding device can be the terminal device itself or a chip or functional module configurable in the terminal device. The transceiver module 1202 is used to perform transceiver-related operations or input / output-related operations of the encoding device in the above method embodiments, and the processing module 1201 is used to perform processing-related operations of the encoding device in the above method embodiments.

[0251] For example, the processing module 1201 can be used to acquire a first bit sequence and encode the first bit sequence based on a first base matrix to obtain a second bit sequence; the transceiver module 1202 can be used to output the second bit sequence.

[0252] The processing module 1201 can also be used to determine one or more expansion factors.

[0253] For example, the processing module 1201 may include an acquisition module, an encoding module, etc. For instance, the processing module 1201 may also include a modulation module, etc.

[0254] As an example, transceiver module 1202 can be used to transmit the signal obtained after processing the second bit sequence. Transceiver module 1202 may include an radio frequency module, an antenna module, etc.

[0255] As another example, transceiver module 1202 can be used to output a second bit sequence. After outputting the second bit sequence, it can undergo other processing, such as rate matching, modulation, MIMO coding, subcarrier mapping, or IFFT. For example, transceiver module 1202 may include input / output modules, etc.

[0256] Reusing Figure 12, in some other embodiments of this application, the device can be used to perform the actions performed by the decoding device in the above method embodiments. In this case, the device can be the terminal device itself or a chip or functional module configurable in the terminal device, or the decoding device can be the network device itself or a chip or functional module configurable in the network device. The transceiver module 1202 is used to perform transceiver-related operations of the decoding device in the above method embodiments, and the processing module 1201 is used to perform processing-related operations of the decoding device in the above method embodiments.

[0257] For example, the transceiver module 1202 can be used to receive or input signals transmitted through the channel; the processing module 1201 can be used to process the signal to obtain a second bit sequence.

[0258] For example, the processing module 1201 can also decode the second bit sequence based on the first base matrix to obtain the first bit sequence.

[0259] The processing module 1201 can also be used to determine one or more expansion factors.

[0260] The processing module 1201 may also include an acquisition module, a decoding module, etc. For example, the processing module 1201 may also include a demodulation module, etc.

[0261] As an example, transceiver module 1202 can receive signals transmitted through a channel. Transceiver module 1202 may include a radio frequency module, an antenna module, etc.

[0262] As another example, transceiver module 1202 can receive a second bit sequence from other modules, such as inputting the second bit sequence, so that the processing module can decode the sequence to be decoded. For example, transceiver module 1202 may include input / output modules, etc.

[0263] Optionally, in the above embodiments, the apparatus may further include a storage module, which can be used to store instructions and / or data. The processing module 1201 can read the instructions and / or data in the storage module to enable the apparatus to implement the aforementioned method embodiments. For example, the storage module may also store the first basis matrix, the second basis matrix, the first value set, the expansion factor set, etc., as shown above.

[0264] For specific explanations of terms or steps in the above embodiments, please refer to the descriptions in the above method embodiments, which will not be detailed here.

[0265] The specific descriptions of the transceiver module and processing module shown in the above embodiments are merely examples. For the specific functions or execution steps of the transceiver module and processing module, please refer to the above method embodiments, which will not be described in detail here.

[0266] It is understandable that the module division in the above-mentioned device is merely a logical functional division. Each function can correspond to a functional module, or two or more functions can be integrated into one functional module. In actual implementation, all or some modules can be integrated into one physical entity, or they can be distributed across different physical entities. Furthermore, the above-mentioned functional modules can be implemented in hardware, software, or a combination of both.

[0267] In one example, the functional unit in any of the above devices may be one or more integrated circuits configured to implement the above methods, such as: one or more application-specific integrated circuits (ASICs), or one or more central processing units (CPUs), one or more microcontroller units (MCUs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0268] The apparatus of the embodiments of this application has been described above. The possible product forms of the apparatus are described below. Any product possessing the functions of the apparatus described in FIG. 12 above falls within the protection scope of the embodiments of this application. The following description is merely illustrative and does not limit the product form of the apparatus of the embodiments of this application to this.

[0269] In one possible implementation, in the device shown in FIG12, the processing module 1201 can be one or more processing circuits, and the transceiver module 1202 can be a transceiver circuit, or the transceiver module 1202 can also be a transmitting module and a receiving module. The transmitting module can be a transmitting circuit, and the receiving module can be a receiving circuit, which are integrated into a single device, such as a transceiver circuit. In the embodiments of this application, the processing circuit and the transceiver circuit can be coupled, etc., and the connection method of the processing circuit and the transceiver circuit is not limited in the embodiments of this application. In the process of performing the above method, the process of sending information in the above method can be the process of the processing circuit outputting the above information. When outputting the above information, the processing circuit outputs the above information to the transceiver circuit so that the transceiver circuit can transmit (or output). After the above information is output by the processing circuit, it may need to undergo other processing before reaching the transceiver circuit. Similarly, the process of receiving information in the above method can be the process of the processing circuit receiving the input above information. When the processing circuit receives the input information, the transceiver circuit receives the above information and inputs it into the processing circuit. Furthermore, after the transceiver circuit receives the aforementioned information, the information may need to undergo further processing before being input into the processing circuit.

[0270] Figure 13 is a schematic diagram of the structure of a device provided in an embodiment of this application. As shown in Figure 13, the device 130 includes one or more processing circuits 1320 and transceiver circuits 1310.

[0271] In some embodiments of this application, the apparatus can be used to perform the steps, methods, or functions performed by the encoding apparatus described above. For example, the processing circuit 1320 can be used to perform the functions or steps implemented by the processing module 1201 shown in FIG. 12, and the transceiver circuit 1310 can be used to perform the functions or steps implemented by the transceiver module 1202 shown in FIG. 12. Detailed descriptions of the processing circuit 1320 and the transceiver circuit 1310 can be found in FIG. 12 or the method embodiments shown above, and will not be elaborated further here.

[0272] In other embodiments of this application, the apparatus is used to perform the steps, methods, or functions performed by the decoding apparatus described above. For example, the processing circuit 1320 can be used to perform the functions or steps implemented by the processing module 1201 shown in FIG. 12, and the transceiver circuit 1310 can be used to perform the functions or steps implemented by the transceiver module 1202 shown in FIG. 12. Detailed descriptions of the processing circuit 1320 and the transceiver circuit 1310 can be found in FIG. 12 or the method embodiments shown above, and will not be elaborated further here.

[0273] For example, the processing circuitry may be one or more processors, or all or part of the circuitry within one or more processors. The transceiver circuitry may be a transceiver, an input / output circuit, or an interface circuit, etc.

[0274] For example, in various implementations of the apparatus shown in FIG13, the transceiver circuitry may include a receiver for performing a receiving function (or operation) and a transmitter for performing a transmitting function (or operation). The transceiver circuitry is also used to communicate with other devices / appliances via a transmission medium.

[0275] Optionally, the device 130 may further include one or more memories 1330 for storing program instructions and / or data. The memories 1330 are coupled to the processing circuitry 1320. The coupling in this embodiment is an indirect coupling or communication connection between devices, units, or modules, and can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processing circuitry 1320 may operate in conjunction with the memories 1330. The processing circuitry 1320 may execute the program instructions stored in the memories 1330. Optionally, at least one of the aforementioned memories may be included in the processing circuitry.

[0276] This application embodiment does not limit the specific connection medium between the transceiver circuit 1310, processing circuit 1320, and memory 1330. In this application embodiment, the memory 1330, processing circuit 1320, and transceiver circuit 1310 are connected via a bus 1340 in Figure 13. The bus is represented by a thick line in Figure 13. The connection methods between other components are only for illustrative purposes and are not intended to be limiting. The bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 13, but this does not mean that there is only one bus or one type of bus.

[0277] In the embodiments of this application, the processing circuit may be a general-purpose processing circuit, a digital signal processing circuit, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processing circuit may be a microprocessor circuit or any conventional processing circuit, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processing circuit, or being executed by a combination of hardware and software modules in the processing circuit, etc.

[0278] In this application embodiment, the memory may include, but is not limited to, non-volatile memory such as hard disk drive (HDD) or solid-state drive (SSD), random access memory (RAM), erasable programmable read-only memory (EPROM), read-only memory (ROM), or compact disc read-only memory (CD-ROM), etc. Memory is any storage medium capable of carrying or storing program code having instruction or data structure forms, and capable of being read and / or written by a computer (such as the device shown in this application), but is not limited to this. The memory in this application embodiment may also be a circuit or any other device capable of implementing storage functions, used to store program instructions and / or data.

[0279] For example, the processing circuit 1320 is mainly used to process communication protocols and communication data, control the entire device, execute software programs, and process the data of the software programs. The memory 1330 is mainly used to store software programs and data. The transceiver circuit 1310 may include a control circuit and an antenna. The control circuit is mainly used for converting baseband signals to radio frequency signals and processing radio frequency signals. The antenna is mainly used for transmitting and receiving radio frequency signals in the form of electromagnetic waves. Input / output devices, such as touch screens, displays, and keyboards, are mainly used to receive user input data and output data to the user.

[0280] When the device is powered on, the processing circuit 1320 can read the software program in the memory 1330, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processing circuit 1320 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit then performs RF processing on the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processing circuit 1320. The processing circuit 1320 converts the baseband signal into data and processes the data.

[0281] In another implementation, the radio frequency circuit and antenna can be set up independently of the processing circuit that performs baseband processing. For example, in a distributed scenario, the radio frequency circuit and antenna can be arranged remotely, independent of the device.

[0282] The apparatus shown in this application embodiment may have more components than those in Figure 13, and this application embodiment does not limit this. The methods performed by the processing circuit and transceiver circuit shown above are merely examples, and the specific steps performed by the processing circuit and transceiver circuit can be referred to the methods described above.

[0283] In another possible implementation, in the device shown in Figure 12, the processing module 1201 can be one or more logic circuits, and the transceiver module 1202 can be an input / output interface, or a communication interface, or an interface circuit, or an interface, etc. Alternatively, the transceiver module 1202 can also be a transmitting module and a receiving module, where the transmitting module can be an output interface and the receiving module can be an input interface, and the transmitting module and the receiving module are integrated into one module, such as an input / output interface.

[0284] Figure 14 is a schematic diagram of a device provided in an embodiment of this application. As shown in Figure 14, the device includes a logic circuit 1401 and an interface circuit 1402. That is, the processing module 1201 can be implemented using the logic circuit 1401, and the transceiver module 1202 can be implemented using the interface circuit 1402. The logic circuit 1401 can be a chip, a processing circuit, an integrated circuit, or a system-on-a-chip (SoC) chip, etc., and the interface circuit 1402 can be a communication interface, an input / output interface, pins, etc. For example, Figure 14 illustrates the device as a chip, which includes the logic circuit 1401 and the interface circuit 1402.

[0285] In this embodiment, the logic circuit and the interface can also be coupled to each other. The specific connection method of the logic circuit and the interface is not limited in this embodiment. For example, the logic circuit 1401 can be used to execute the functions or steps implemented by the processing module 1201 shown in FIG. 12, and the interface circuit 1402 can be used to execute the functions or steps implemented by the transceiver module 1202 shown in FIG. 12. For a detailed description of the logic circuit 1401 and the interface circuit 1402, please refer to FIG. 12 or the method embodiment shown above, which will not be detailed here.

[0286] The apparatus shown in the embodiments of this application can be implemented in hardware or software, and the embodiments of this application do not limit this.

[0287] This application also provides a communication system, which includes an encoding device and a decoding device, and the encoding device and the decoding device can be used to perform the methods in any of the foregoing embodiments.

[0288] In addition, this application also provides a computer program for implementing the operations and / or processes performed by various devices in the method provided in this application.

[0289] This application also provides a computer-readable storage medium storing computer code that, when executed on a computer, causes the computer to perform the operations and / or processes performed by the various devices in the methods provided in this application.

[0290] This application also provides a computer program product comprising computer code or a computer program that, when run on a computer, causes the operations and / or processes performed by various entities in the method provided in this application to be executed.

[0291] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or modules, or they may be electrical, mechanical, or other forms of connection.

[0292] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the technical effects of the solutions provided in the embodiments of this application.

[0293] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0294] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0295] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An encoding method characterized by, The method includes: Obtain the first bit sequence; encode the first bit sequence based on a first base matrix of a low-density parity-check (LDPC) code to obtain a second bit sequence; the first base matrix comprises a first sub-matrix, values of elements in the first sub-matrix being taken from a Galois field GF(2 m ), and the m is a positive integer greater than 1; Output the second bit sequence.

2. The method of claim 1, wherein, The first base matrix based on the LDPC code encodes the first bit sequence to obtain the second bit sequence, including: Determine one or more expansion factors; the one or more expansion factors include the expansion factor z corresponding to the first submatrix; The elements of the first base matrix are expanded according to the one or more expansion factors to obtain the parity check matrix; the elements in the first submatrix include a first element, which corresponds to the z×z matrix in the parity check matrix; wherein z is a positive integer; The first bit sequence is encoded based on the parity check matrix to obtain the second bit sequence; wherein the z x z matrix is a matrix as follows or the z x z matrix is a circulant matrix of a matrix as follows: Wherein, k represents the value of the first element.

3. A decoding method, comprising: The method includes: Obtain the second bit sequence; decoding the second bit sequence based on a first base matrix of a low-density parity-check (LDPC) code, to obtain a first bit sequence; the first base matrix comprises a first sub-matrix, values of elements in the first sub-matrix being taken from a Galois field GF(2 m ), and the m is a positive integer greater than 1.

4. The method of claim 3, wherein, The first basis matrix based on the LDPC code decodes the second bit sequence to obtain the first bit sequence, including: Determine one or more expansion factors; the one or more expansion factors include the expansion factor z corresponding to the first submatrix; The elements of the first base matrix are expanded according to the one or more expansion factors to obtain the parity check matrix; the elements in the first submatrix include a first element, which corresponds to the z×z matrix in the parity check matrix; wherein z is a positive integer; The second bit sequence is decoded based on the parity check matrix to obtain the first bit sequence; wherein the z x z matrix is a matrix as follows or the z x z matrix is a circulant matrix of a matrix as follows: Wherein, k represents the value of the first element.

5. The method according to any one of claims 1 to 4, characterized in that, The value of the element in the i-th row of the first submatrix is ​​determined by the elements in the first value set, which is related to the number of non-zero elements in the i-th row; i is a positive integer.

6. The method of claim 5, wherein, The first set of values ​​is related to the number of non-zero elements in the i-th row, including: the number of elements in the first set of values ​​is the same as the number of non-zero elements in the i-th row, and one element in the first set of values ​​corresponds to the value of one non-zero element in the i-th row.

7. The method according to any one of claims 1 to 6, characterized in that, The first base matrix also includes a second submatrix, in which the values ​​of the elements range from {0,1}.

8. The method of claim 7, wherein, The expansion factor corresponding to the first submatrix is ​​less than the expansion factor corresponding to the second submatrix.

9. The method of claim 8, wherein, The extension factor corresponding to the second sub-matrix is y, and the extension factor corresponding to the first sub-matrix is Or Wherein, the y is a positive integer, the Indicates rounding down, the Indicates rounding up.

10. The method of claim 8, wherein, The expansion factor corresponding to the first submatrix is ​​z, and the expansion factor corresponding to the second submatrix is ​​m×z; where z is a positive integer.

11. The method of claim 7, wherein, The number of columns in the second submatrix is ​​m times the number of columns in the first submatrix, and the expansion factor corresponding to the first submatrix is ​​the same as the expansion factor corresponding to the second submatrix.

12. The method according to any one of claims 7-11, characterized in that, The first submatrix includes the core matrix of the first basis matrix, and the second submatrix includes the extended matrix of the first basis matrix.

13. The method according to any one of claims 1 to 6, characterized in that, The first submatrix includes the core matrix and the extended matrix of the first basis matrix.

14. An encoding apparatus, comprising: Includes modules for performing the method as described in any one of claims 1-2, 5-13.

15. An encoding apparatus, comprising: It includes a processing circuit and a transceiver circuit, the transceiver circuit being used to input and / or output information, and the processing circuit being used to perform the method as described in any one of claims 1-2 and 5-13.

16. A decoding device, comprising: Includes modules for performing the method as described in any one of claims 3-4, 5-13.

17. A decoding device, comprising: It includes a processing circuit and a transceiver circuit, the transceiver circuit being used to input and / or output information, and the processing circuit being used to perform the method as described in any one of claims 3-4, 5-13.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program, which, when executed, performs the method as described in any one of claims 1-13.

19. A computer program product, characterised in that, When the computer program product is executed, the method described in any one of claims 1-13 is performed.

Images