Surface acoustic wave (SAW) devices including a superlattice and related methods
A semiconductor superlattice with constrained non-semiconductor monolayers addresses mobility and scattering issues, enhancing device performance through reduced scattering and improved material diffusion.
WO2026089776A9PCT designated stage Publication Date: 2026-07-02ATOMERA INC
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Patent Information
- Application Number
- PCT/US2025/031168
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-05-29
- Filing Date
- 2025-05-28
- Publication Date
- 2026-07-02
AI Technical Summary
Technical Problem
Existing semiconductor devices lack enhancements in charge carrier mobility and material diffusion, leading to inferior performance and scattering effects.
Method used
Incorporation of a semiconductor superlattice with constrained non-semiconductor monolayers, such as oxygen, within a crystal lattice to reduce scattering and enhance mobility, combined with piezoelectric properties for improved device functionality.
Benefits of technology
The superlattice structure enhances charge carrier mobility, reduces scattering, and provides piezoelectric properties, resulting in improved device performance and reduced material diffusion.
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Smart Images
Figure US2025031168_02072026_PF_FP_ABST
Abstract
An electronic device may include a poled region having a net electrical dipole moment and including a semiconductor layer and at least one non-semiconductor monolayer constrained within a crystal lattice of the silicon layer. The electronic device may further include a plurality of spaced apart alternating N-type and P-type regions within the poled region to align the net electrical dipole moment of the poled region, and at least one electrode associated with the poled region. The poled region may be a superlattice, for example.
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