Throughput improvements for low-temperature / BEOL-compatible highly scalable graphene synthesis methods including processing in retasked tools

The diffusion-couple synthesis method using commercial tools addresses the challenge of uniform temperature and pressure application for large-scale graphene synthesis, enhancing throughput and scalability within BEOL-compatible thermal budgets for semiconductor integration.

WO2026089778A2PCT designated stage Publication Date: 2026-04-30DESTINATION 2D INC +3
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
DESTINATION 2D INC
Filing Date
2025-06-03
Publication Date
2026-04-30

AI Technical Summary

Technical Problem

Existing methods for synthesizing high-quality graphene over large substrates at low temperatures and within a BEOL-compatible thermal budget are limited by the need for uniform application of temperature and pressure across the substrate surface, which is crucial for integrating graphene into mainstream electronics without damaging underlying devices.

Method used

A diffusion-couple synthesis method using commercial bonding tools, such as wafer bonding tools and hot-press systems, applies pressure and temperature simultaneously to substrates within a process chamber, enabling graphene growth on large substrates with near-zero temperature nonuniformity and mechanical uniformity, suitable for BEOL applications.

Benefits of technology

This method enhances throughput by allowing high-quality graphene synthesis on large substrates within the CMOS-compatible thermal budget, improving scalability and integration into semiconductor devices and other applications.

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Abstract

A diffusion-couple synthesis method using a modified or unchanged commercial bonding tool comprising: providing a substrate load which comprises at least two prepared substrates(AtLst2PrepSubs); wherein said tool can apply pressure and elevated temperature to said substrate within a process chamber; placing said substrate load within said process chamber; applying said pressure and said elevated temperature; wherein each of said AtLst2PrepSubs comprises a carbon source disposed directly atop a diffusion layer, the diffusion layer disposed directly atop an oxide layer, and a device substrate with the oxide layer disposed atop, one of said AtLsl2PrepSubs is disposed above another of said AtLst2PrepSubs. wherein the device substrate of one of said AtLst2PrepSubs is directly atop said carbon source of other of said AtLst2PrepSubs; and forming graphene at an interface between said oxide layer and said diffusion layer of each of said AtLst2PrepSubs.
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Citation Information

Patent Citations

  • Large-area wafer-scale CMOS-compatible 2d-material intercalation doping tools, processes, and methods, including doping of synthesized graphene

    US20240258118A1

  • Techniques, methods, and structures for rapid and efficient intercalation-doping of large-area multi- layered graphene sheets for transparent conductor applications, including solar cells and displays

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  • US202463618862P