Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and to a display panel and a display device. The display panel at least comprises a base substrate, a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked; a first trace is located in the first conductive layer; in a crossing region, a second trace comprises a first trace segment, a second trace segment, and a third trace segment that are sequentially connected; the first trace segment and the third trace segment are both located in the second conductive layer, and the second trace segment is located in the third conductive layer and is electrically connected to the first trace segment and the third trace segment by means of via holes; the orthographic projections of the first trace segment and the third trace segment on the base substrate are respectively located on two sides of the orthographic projection of the first conductive layer on the base substrate; and the second trace segment overlaps the first conductive layer.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese Patent Application No. 202411514985.X, filed on October 28, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0004] In the display industry, including OLED, LCD, and MLED, signal circuits need to be formed on the backplane to drive the devices. Gate layers, source / drain metal layers (SD layers), and shield layers are often used as signal traces due to their excellent conductivity, with traces being swapped or overlapped at points where they need to be intersected. Since thicker signal lines have lower resistance, metal layers are often made thicker to ensure panel uniformity when pursuing high PPI and high refresh rates. However, thicker metal layers lead to significant step differences, which can cause poor PVX (PVX) passivation layer coverage at the overlap of adjacent layers, resulting in short circuits. This is especially problematic when there is a large voltage difference between overlapping traces, leading to a high incidence of display panel defects.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device that improves the yield of the display panel by increasing the step difference between adjacent layers of traces in the cross area.

[0007] According to one aspect of this disclosure, a display panel is provided, including a first trace and a second trace; the display panel includes at least a substrate, a first conductive layer, a second conductive layer and a third conductive layer stacked sequentially.

[0008] The first trace is located in the first conductive layer;

[0009] The display panel has at least one crossover area; in the crossover area, the second trace includes a first trace segment, a second trace segment, and a third trace segment connected in sequence; wherein the first trace segment and the third trace segment are both located in the second conductive layer, and the second trace segment is located in the third conductive layer and is electrically connected to the first trace segment and the third trace segment through a via;

[0010] The orthographic projections of the first trace segment and the third trace segment on the substrate are respectively located on both sides of the orthographic projection of the first conductive layer on the substrate; the second trace segment overlaps with the first conductive layer.

[0011] In an exemplary embodiment of this disclosure, the second trace segment has a second trace segment end and a second trace segment overlap portion that overlaps with the first trace; the step difference between the second trace segment overlap portion and the substrate is greater than the step difference between the second trace segment end and the substrate.

[0012] In one exemplary embodiment of this disclosure, the step difference between the overlapping portion of the second trace segment and the substrate is 1 to 2 micrometers larger than the step difference between the end of the second trace segment and the substrate.

[0013] In one exemplary embodiment of this disclosure, the first trace has an overlapping portion that overlaps with the second trace segment overlap portion, and the step difference between the surface of the first trace overlap portion away from the substrate and the surface of the second trace segment overlap portion near the substrate is not less than 3 micrometers.

[0014] In one exemplary embodiment of this disclosure, in the cross-line region, the display panel has a cross-line insulation unit between the second conductive layer and the third conductive layer;

[0015] The second trace segment is formed on the surface of the cross-line insulation unit away from the substrate.

[0016] Along the extension direction of the second wiring, the cross-line insulation unit sequentially includes a first cross-line insulator unit, a second cross-line insulator unit, and a third cross-line insulator unit; the first cross-line insulator unit is provided with a first through hole, and the third cross-line insulator unit is provided with a second through hole; the second wiring segment is electrically connected to the first wiring segment through the first through hole, and is electrically connected to the third wiring segment through the second through hole; the second cross-line insulator unit overlaps with the first wiring; the second cross-line insulator unit has a protruding structure that protrudes from the plane where the first cross-line insulator unit and the third cross-line insulator unit are located.

[0017] In one exemplary embodiment of this disclosure, the slope angle of the second cross-line insulator unit does not exceed 45°.

[0018] In one exemplary embodiment of this disclosure, the first cross-line insulator unit, the second cross-line insulator unit, and the third cross-line insulator unit are located in the same organic layer.

[0019] In one exemplary embodiment of this disclosure, the second cross-line insulator unit includes a first main structure and a first protrusion structure located on the side of the first main structure away from the substrate. The first main structure, the first cross-line insulator unit, and the third cross-line insulator unit are located in the same organic layer, and the first protrusion structure is located in another organic layer.

[0020] In one exemplary embodiment of this disclosure, the second cross-line insulator unit includes a second protrusion structure and a second main body structure covering the second protrusion structure;

[0021] The second main structure, the first cross-line insulator unit, and the third cross-line insulator unit are located in an organic layer; the second protruding structure is located in another organic layer.

[0022] In an exemplary embodiment of this disclosure, the first wiring segment has a first branch wiring arranged parallel to the first wiring, and the third wiring segment has a second branch wiring arranged parallel to the first wiring;

[0023] The second routing segment includes multiple branch routings arranged side by side; one end of each branch routing is electrically connected to the first branch routing through a via, and the other end is electrically connected to the second branch routing through a via.

[0024] In one exemplary embodiment of this disclosure, in the second routing, the width of the branch routing is not less than the width of the first routing segment and the width of the third routing segment.

[0025] In one exemplary embodiment of this disclosure, the total number of branch traces in the second trace segment is not less than 6.

[0026] In one exemplary embodiment of this disclosure, in each branch of the second routing segment, the spacing between the outer edges of the two outermost branch routing segments is not less than 20 times the width of the first routing segment.

[0027] In an exemplary embodiment of this disclosure, the substrate further includes one or more gate layers, one or more source / drain metal layers and pixel electrode layers that are sequentially stacked on one side of the substrate.

[0028] The first conductive layer is a gate layer, the second conductive layer is a source / drain metal layer, and the third conductive layer is a pixel electrode layer.

[0029] In one exemplary embodiment of this disclosure, the pixel electrode layer includes a first conductive metal oxide layer, a metal layer, and a second conductive metal oxide layer stacked sequentially; wherein the metal layer is between 50 nm and 1000 nm.

[0030] In an exemplary embodiment of this disclosure, the display panel includes a display area and a first peripheral area located on at least one side of the display area; a gate driving circuit for driving pixel driving circuits in the display area is disposed in the first peripheral area, the gate driving circuit including a plurality of shift registers arranged sequentially along the column direction;

[0031] The first trace is located in the first outer area and extends along the column direction;

[0032] The second routing line is located in the first peripheral area and extends along the routing direction.

[0033] In an exemplary embodiment of this disclosure, the display panel has a first driving trace for loading a first driving signal to a shift register and a second driving trace for loading a second driving signal to a shift register in the first peripheral area. The first driving trace and the second driving trace extend along the column direction, and the second driving trace is located between the first driving trace and the shift register.

[0034] One end of the second trace is electrically connected to the first drive trace, and the other end is electrically connected to the shift register; the second drive trace is arranged to overlap with the second trace in the crossover area as the first trace.

[0035] In one exemplary embodiment of this disclosure, one of the first driving signal and the second driving signal is a high-level voltage signal, and the other is a low-level voltage signal.

[0036] According to another aspect of this disclosure, a display device is provided, including the aforementioned display panel.

[0037] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0039] Figure 1 is a cross-sectional schematic diagram of the cross-line area of ​​the display panel in one embodiment of this disclosure.

[0040] Figure 2 is a cross-sectional schematic diagram of the display area of ​​the display panel in one embodiment of this disclosure.

[0041] Figure 3 is a top view of the display panel in one embodiment of this disclosure.

[0042] Figure 4 is a top view of the display panel in one embodiment of this disclosure.

[0043] Figure 5 is a top view of the display panel in one embodiment of this disclosure.

[0044] Figure 6 is a cross-sectional schematic diagram of the cross-line area of ​​a display panel in the related technology.

[0045] Figure 7 is a cross-sectional schematic diagram of the cross-line area of ​​the display panel in one embodiment of the present disclosure.

[0046] Figure 8 is a cross-sectional schematic diagram of the cross-line area of ​​the display panel in one embodiment of this disclosure.

[0047] Figure 9 is a cross-sectional schematic diagram of the cross-line area of ​​the display panel in one embodiment of the present disclosure.

[0048] Figure 10 is a partial top view of the cross-line area of ​​the display panel in one embodiment of this disclosure.

[0049] The reference numerals in the attached figures are as follows: AA, display area; ANL, pixel electrode layer; BB1, first peripheral area; Buffer, buffer layer; CA, cross-line area; COML, common electrode layer; DA, cross-line insulating unit; DA1, first cross-line insulator unit; DA2, second cross-line insulator unit; DA21, second protrusion structure; DA22, second main structure; DA2D, first protrusion structure; DA2M, first main structure; DA2X, protrusion structure; DA3, third cross-line insulator unit; DH, row direction; DV, column direction; EL, organic light-emitting functional layer; FA, driving circuit layer; FB, pixel layer; GI, gate insulating layer; GOA, gate driving circuit; GT, gate layer; GT1, first gate layer; GT2, second gate layer; H1, first via; H2, second via; ITO1, first conductive metal oxide layer; ITO2, second conductive metal oxide layer. Layers; L1, First driving trace; L2, Second driving trace; LA, First trace; LA1, Overlap of the first trace; LB, Second trace; LB1, First trace segment; LB1D, First stub trace; LB2, Second trace segment; LB2A, End of the second trace segment; LB2B, Overlap of the second trace segment; LB2S, Branch trace; LB3, Third trace segment; LB3D, Second stub trace; LS, Metallic light-shielding layer; ML1, First conductive layer; ML2, Second conductive layer; ML3, Third conductive layer; PDC, Pixel driving circuit; PDL, Pixel definition layer; PNL, Display panel; PVX1, First passivation layer; PVX2, Second passivation layer; SBT, Substrate; SCL, Semiconductor layer; SD, Source / drain metal layer; SR, Shift register; CF, Color filter layer; PLN1, First planarization layer; PLN2, Second planarization layer. Detailed Implementation

[0050] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0051] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0052] This disclosure provides a display panel PNL, as shown in FIG1. ​​The display panel PNL includes a first trace LA and a second trace LB. The display panel PNL includes at least a substrate SBT, a first conductive layer ML1, a second conductive layer ML2, and a third conductive layer ML3 stacked sequentially. The first trace LA is located in the first conductive layer ML1. The display panel PNL has at least one cross-line region CA. In the cross-line region CA, the second trace LB includes a first trace segment LB1, a second trace segment LB2, and a third trace segment LB3 connected sequentially. The first trace segment LB1 and the third trace segment LB3 are both located in the second conductive layer ML2, and the second trace segment LB2 is located in the third conductive layer ML3 and is electrically connected to the first trace segment LB1 and the third trace segment LB3 through a via. The orthographic projections of the first trace segment LB1 and the third trace segment LB3 on the substrate SBT are respectively located on both sides of the orthographic projection of the first conductive layer ML1 on the substrate SBT. The second trace segment LB2 overlaps with the first conductive layer ML1. In related technologies, short circuits are prone to occur at the intersection of the second trace LB and the first trace LA. In this embodiment, the second trace LB includes a first trace segment LB1, a second trace segment LB2, and a third trace segment LB3. The orthographic projections of the first trace segment LB1 and the third trace segment LB3 on the substrate SBT are located on opposite sides of the orthographic projection of the first trace LA on the substrate SBT. The second trace segment LB2 is located in the third conductive layer ML3 and is electrically connected to the first trace segment LB1 and the third trace segment LB3 through vias. Thus, by placing the second trace segment LB2 of the second trace LB in the third conductive layer ML3 in the cross-line region CA, the step difference between the first trace LA and the second trace LB within the cross-line region CA is increased, thereby avoiding short circuits caused by poor insulation layer coverage, and especially reducing the occurrence of display panel defects caused by excessive voltage difference between the first trace LA and the second trace LB.

[0053] In one embodiment of this disclosure, the second trace segment LB2 has a second trace segment end LB2A and a second trace segment overlap portion LB2B that overlaps with the first trace LA; the step difference between the second trace segment overlap portion LB2B and the substrate SBT is greater than the step difference between the second trace segment end LB2A and the substrate SBT. In this embodiment, the step difference between the first trace LA and the second trace LB at the overlap position can be further increased, thereby further increasing the insulation layer thickness between the first trace LA and the second trace segment overlap portion LB2B, and further reducing the risk of short circuit between the first trace LA and the second trace LB in the cross-line region CA.

[0054] The structure of the display panel PNL of this disclosure will be described exemplarily below with reference to the accompanying drawings.

[0055] In one embodiment of this disclosure, referring to FIG2, the display panel includes a substrate SBT, a driving circuit layer FA, and a pixel layer FB stacked sequentially; the pixel layer is provided with sub-pixels; the driving circuit layer FA is provided with a pixel driving circuit for driving the sub-pixels.

[0056] The substrate SBT can be an inorganic material or an organic material. For example, in one embodiment of this disclosure, the substrate SBT can be made of glass materials such as soda-lime glass, quartz glass, or sapphire glass, or metal materials such as stainless steel, aluminum, or nickel. In another embodiment of this disclosure, the substrate SBT can be made of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or combinations thereof. In another embodiment of this disclosure, the substrate SBT can also be a flexible substrate, for example, the substrate SBT can be made of polyimide (PI). The substrate SBT can also be a composite of multiple materials. For example, in one embodiment of this disclosure, the substrate SBT may include a bottom film, a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer stacked sequentially.

[0057] The driving circuit layer FA is provided with pixel driving circuits for driving sub-pixels. In the driving circuit layer FA, any pixel driving circuit may include a transistor and a storage capacitor. In one example, the driving circuit layer is provided with a polycrystalline silicon semiconductor layer and / or a metal-oxide-semiconductor layer, such that the transistors in the driving circuit layer include at least metal-oxide-semiconductor transistors and / or polycrystalline silicon transistors (e.g., low-temperature polycrystalline silicon transistors). Further, these transistors may be thin-film transistors. Of course, in other embodiments of this disclosure, the polycrystalline silicon transistors may also be amorphous silicon transistors; correspondingly, the polycrystalline silicon semiconductor layer of the driving circuit layer FA may be replaced with an amorphous silicon semiconductor layer.

[0058] In one embodiment of this disclosure, the polysilicon transistor can be a top-gate thin-film transistor, a bottom-gate thin-film transistor, or a dual-gate thin-film transistor, depending on its ability to effectively control the transistor. The metal-oxide transistor can be a dual-gate thin-film transistor, where the channel region of the transistor is sandwiched between the top gate (the gate on the side furthest from the substrate) and the bottom gate (the gate on the side closest to the substrate); thus, the bottom gate can block light from the substrate side, preventing light from reaching the channel region of the transistor and causing malfunction. Of course, the metal-oxide transistor can also be a top-gate or bottom-gate thin-film transistor.

[0059] In some embodiments of this disclosure, the gate of the polysilicon transistor can be disposed in the same layer as a gate of the metal-oxide transistor; for example, the gate of the polysilicon transistor and the bottom gate of the metal-oxide transistor can be disposed in the same gate layer. In other embodiments, the gate of the polysilicon transistor and the top and bottom gates of the metal-oxide transistor can be disposed in different gate layers.

[0060] In one embodiment of this disclosure, the driving circuit layer includes multiple metal layers, wherein one metal layer can serve as a first conductive layer ML1, and another metal layer can serve as a second conductive layer ML2, with the second conductive layer ML2 located on the side of the first conductive layer ML1 away from the substrate SBT. Further, a third conductive layer ML3 can be located in the pixel layer. Of course, in other embodiments of this disclosure, the third conductive layer ML3 can also be located in the driving layer.

[0061] As an example, referring to Figure 2, the driving circuit layer FA includes a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, a first passivation layer PVX1, a source / drain metal layer SD, and a second passivation layer PVX2, which are sequentially stacked on one side of the substrate SBT. The semiconductor layer SCL is a metal-oxide-semiconductor layer, and the metal-oxide-semiconductor layer contains the active region of a metal-oxide-semiconductor transistor. The gate layer GT contains the gate of the metal-oxide-semiconductor transistor. In this disclosure, the active region of the transistor includes the channel region of the transistor and the source and drain electrodes located on both sides of the channel region; wherein the channel region maintains semiconductor characteristics, and the source and drain electrodes are conductive. In this disclosure, the source / drain metal layer SD can be one layer, two layers, or three layers. In the example of Figure 3, the source / drain metal layer SD is one layer, including the source / drain metal layer SD disposed on the side of the gate layer GT away from the substrate SBT.

[0062] For example, the gate layer GT material can be one or more of Mo (molybdenum), Ti (titanium), Al (aluminum), Nd (neodymium), and Cu (copper), or an alloy of the above materials. The gate layer GT can be a single-layer structure or a multi-layer composite structure. For example, the thickness of the gate layer GT is 400nm-800nm.

[0063] For example, the material of the first passivation layer PVX1 can be SiNx or SiOx, or a composite layer formed by the two, with a thickness of 400nm-800nm.

[0064] For example, the material of the second passivation layer PVX2 can be SiNx or SiOx, or a composite layer formed by both, with a thickness of 400nm-800nm.

[0065] In one example, referring to Figure 2, the driving circuit layer FA of the display panel PNL includes metal layers such as gate layer GT and source / drain metal layer SD stacked in sequence; the first gate layer GT1 can be used as ML1 for setting the first trace LA; the second gate layer GT2 can be used as the second conductive layer ML2 for setting the first trace segment LB1 and the third trace segment LB3.

[0066] In another example, the display panel PNL includes a substrate SBT and multiple gate layers GT and multiple source / drain metal layers SD sequentially stacked on one side of the substrate SBT. The first conductive layer ML1 can be one of the gate layers GT, and the second conductive layer ML2 can be one of the source / drain metal layers SD. Alternatively, the first conductive layer ML1 can be one of the gate layers GT, and the second conductive layer ML2 can be another gate layer GT on the side of the gate layer GT away from the substrate SBT. Alternatively, the first conductive layer ML1 can be one of the source / drain metal layers SD, and the second conductive layer ML2 can be another source / drain metal layer SD on the side of the source / drain metal layer SD away from the substrate SBT.

[0067] In one example, the driving circuit layer FA may further include a buffer layer disposed between the substrate SBT and the semiconductor layer SCL, wherein the semiconductor layer SCL and the gate layer GT are both located on the side of the buffer layer away from the substrate SBT. The material of the buffer layer can be an inorganic insulating material such as silicon oxide or silicon nitride. The buffer layer can be a single inorganic material layer or multiple stacked inorganic material layers.

[0068] In one example, the driving circuit layer FA may further include a metal light-shielding layer LS located between the buffer layer and the substrate SBT, the metal light-shielding layer LS shielding at least a portion of the transistor's channel region. Further, in some embodiments, the metal light-shielding layer LS may be electrically connected to the source / drain metal layers via vias, thus allowing the metal light-shielding layer LS to perform signal transmission, signal shielding, or other functions as needed. For example, a common electrode voltage may be applied to the metal light-shielding layer LS to enable it to achieve signal shielding. As another example, a portion of the metal light-shielding layer LS may be patterned as conductive lines so that the conductive lines located on the metal light-shielding layer LS can be used to transmit signals, such as touch signals.

[0069] For example, the metal light-shielding layer LS can be one or more of Mo (molybdenum), Ti (titanium), Al (aluminum), Nd (neodymium), and Cu (copper), or an alloy of the above materials. The metal light-shielding layer LS can be a single-layer structure or a multi-layer composite structure. For example, the thickness of the metal light-shielding layer LS is 400nm-800nm.

[0070] In one example, the metal light-shielding layer LS can also serve as the first conductive layer ML1, such that the second conductive layer ML2 can be the gate layer GT or the source / drain metal layer SD.

[0071] Referring to Figures 2 and 3, the pixel layer FB is provided with an array of light-emitting elements, and each light-emitting element emits light under the control of the pixel driving circuit. These light-emitting elements can serve as sub-pixels in embodiments of this disclosure. In this disclosure, the light-emitting elements can be organic light-emitting diodes (OLEDs), micro light-emitting diodes (Micro LEDs), quantum dot-organic light-emitting diodes (QD-OLEDs), quantum dot light-emitting diodes (QLEDs), or other types of light-emitting elements. For example, referring to Figure 2, in one embodiment of this disclosure, the light-emitting element is an organic light-emitting diode (OLED), and the display panel is an OLED display panel. Below, taking an organic light-emitting diode as an example, a feasible structure of the pixel layer FB will be described exemplarily.

[0072] In this example, the pixel layer FB can be disposed on the side of the driving circuit layer FA away from the substrate SBT. It may include a pixel electrode layer ANL, a pixel definition layer PDL, a support pillar layer, an organic light-emitting functional layer EL, and a common electrode layer COML, stacked sequentially. The pixel electrode layer ANL has multiple pixel electrodes in the display area of ​​the display panel PNL. The pixel definition layer PDL has multiple through-holes in the display area, each corresponding to one of the pixel electrodes, with each pixel opening exposing at least a portion of the corresponding pixel electrode. The support pillar layer includes multiple support pillars in the display area, located on the surface of the pixel definition layer PDL away from the substrate SBT, to support a fine metal mask (FMM) during the evaporation process. The organic light-emitting functional layer EL at least covers the pixel electrodes exposed by the pixel definition layer PDL. The organic light-emitting functional layer EL may include an organic electroluminescent material layer and may include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. The individual layers of the organic light-emitting functional layer (EL) can be fabricated using a vapor deposition process, and the pattern of each layer can be defined using a fine metal mask or an open mask during the vapor deposition process. A common electrode layer (COML) can cover the EL in the display area. Thus, the pixel electrode, the common electrode layer (COML), and the EL located between the pixel electrode and the common electrode layer (COML) form an organic light-emitting diode (OLED), and any one of these OLEDs can serve as a sub-pixel of the display panel.

[0073] Optionally, the display panel PNL may further include a color filter layer CF, which may be disposed on the side of the pixel layer FB away from the substrate SBT (top emission) or on the side of the pixel layer FB close to the substrate SBT (bottom emission). In the example of Figure 2, the color filter layer CF is disposed on the side of the driving circuit layer FA away from the substrate SBT, and a planarization layer PLN is disposed on the side of the color filter layer CF away from the substrate SBT. The planarization layer PLN, disposed on the side of the color filter layer CF away from the substrate SBT, provides a planarization surface for the pixel electrodes of the pixel layer FB.

[0074] For example, as shown in Figures 1 and 2, the pixel electrode layer ANL can serve as the third conductive layer ML3.

[0075] In one example, the pixel electrode layer ANL includes a first conductive metal oxide layer ITO1, a metal layer, and a second conductive metal oxide layer ITO2, which are stacked sequentially. Optionally, the metal layer in the pixel electrode layer ANL can be made of silver or aluminum.

[0076] In one example, the metal layer in the pixel electrode layer ANL can be made of Ag, with a thickness between 50 nm and 1000 nm. For instance, the metal layer in the pixel electrode layer ANL is Ag with a thickness of 500 nm.

[0077] Optionally, the display panel PNL may further include a thin-film encapsulation layer. The thin-film encapsulation layer is disposed on the surface of the pixel layer FB away from the substrate SBT, and may include alternately stacked inorganic and organic encapsulation layers. The inorganic encapsulation layer effectively blocks external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting functional layer EL and causing material degradation. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer FB away from the substrate SBT. The first inorganic encapsulation layer covers the display area and extends to the outside of the barrier; the organic encapsulation layer covers the display area and extends to the inside of the barrier; the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the barrier. On the outside of the barrier, the second inorganic encapsulation layer is in contact with the first inorganic encapsulation layer. In this way, the organic encapsulation layer is sealed by the first and second inorganic encapsulation layers, balancing the stress in the first and second inorganic encapsulation layers. The first and second inorganic encapsulation layers also seal the organic encapsulation layer, preventing it from contacting water and oxygen.

[0078] In one embodiment of this disclosure, referring to FIG3, the display panel PNL includes a display area AA and a first peripheral area BB1 located on at least one side of the display area AA. As shown in FIG4, a gate driving circuit GOA for driving the pixel driving circuit PDC in the display area AA is disposed in the first peripheral area BB1 of the display panel PNL. The gate driving circuit GOA includes a plurality of shift registers SR arranged sequentially along the column direction DV. The first trace LA is disposed in the first peripheral area BB1 and extends along the column direction DV; the second trace LB is disposed in the first peripheral area BB1 and extends along the row direction DH. That is, the intersection area of ​​the first trace LA extending along the column direction DV and the second trace LB extending along the row direction DH forms a cross-line area CA. In the cross-line area, the orthographic projection of the first trace LA on the substrate SBT and the orthographic projection of the second trace LB on the substrate SBT at least partially coincide.

[0079] In one embodiment of this disclosure, as shown in FIG5, the display panel PNL has a first driving trace L1 for loading a first driving signal to a shift register SR and a second driving trace L2 for loading a second driving signal to the shift register SR in the first peripheral area BB1. The first driving trace L1 and the second driving trace L2 extend along the column direction DV, and the second driving trace L2 is located between the first driving trace L1 and the shift register SR. One end of the second trace LB is electrically connected to the first driving trace L1, and the other end is electrically connected to the shift register SR; the second driving trace L2, as the first trace LA, overlaps with the second trace LB in the cross-line area CA.

[0080] As shown in Figure 6, in related technologies, a large thickness of the conductive layer leads to poor sealing of the boundary area of ​​the cross-line region CA, which easily causes short circuits in the metal traces (e.g., the first trace LA and the second trace LB) of the two overlapping conductive layers. This is especially true when the voltage between the two overlapping traces is high, making short circuits in the overlapping metal traces of the cross-line region more likely. In this embodiment of the present disclosure, the cross-line region CA adopts the method shown in Figure 1, by placing part of the second trace LB in the third conductive layer ML3, increasing the step difference between the first trace LA and the second trace LB, and avoiding short circuits in the cross-line region due to poor coverage.

[0081] For example, one of the first driving signal and the second driving signal is a high-level voltage signal, and the other is a low-level voltage signal. In this example, the trace carrying the high-level voltage signal overlaps with the trace carrying the low-level voltage signal in the crossing region. Due to the opposite electrical polarity of the voltages, the voltage difference between the two is large; the insulation layer between them is prone to failure under the influence of the high voltage difference, leading to a short circuit. However, in the embodiments of this disclosure, by setting a second trace segment LB2 at the third conductive layer ML3, the step difference between the trace carrying the high-level voltage signal and the trace carrying the low-level voltage signal in the crossing region is increased, and the insulation layer between them is thickened, thereby reducing the risk of insulation layer breakdown.

[0082] In one embodiment of this disclosure, the step difference between the second trace overlap portion LB2B and the substrate SBT is 1-2 micrometers larger than the step difference between the second trace end LB2A and the substrate SBT. Thus, the second trace overlap portion LB2B is further raised by 1-2 micrometers, which can further increase the insulation layer thickness between the second trace overlap portion LB2B and the first trace LA without excessively increasing the thickness of the display panel PNL, thereby further reducing the risk of short circuits.

[0083] In one embodiment of this disclosure, the first trace LA has an overlap portion LA1 that overlaps with the second trace segment overlap portion LB2B. The step difference between the surface of the first trace overlap portion LA1 away from the substrate SBT and the surface of the second trace segment overlap portion LB2B near the substrate SBT is not less than 3 micrometers. Thus, the thickness of the insulating layer between the second trace segment overlap portion LB2B and the first trace overlap portion LA1 reaches at least 3 micrometers. On the one hand, the increased thickness of the insulating layer improves the reliability of the insulation; on the other hand, by increasing the distance between the second trace segment overlap portion LB2B and the first trace overlap portion LA1, the electric field strength between them is reduced, thereby reducing the risk of insulation layer breakdown.

[0084] In one embodiment of this disclosure, as shown in FIG7, a cross-line insulating unit DA is disposed between the second conductive layer ML2 and the third conductive layer ML3 in the cross-line region CA. The second trace segment LB2 is formed on the surface of the cross-line insulating unit DA away from the substrate SBT. Along the extension direction of the second trace LB, the cross-line insulating unit DA sequentially includes a first cross-line insulator unit DA1, a second cross-line insulator unit DA2, and a third cross-line insulator unit DA3. The first cross-line insulator unit DA1 is provided with a first via H1, and the third cross-line insulator unit DA3 is provided with a second via H2; the second trace segment LB2 is electrically connected to the first trace segment LB1 through the first via H1, and is electrically connected to the third trace segment LB3 through the second via H2. The second cross-line insulator unit DA2 overlaps with the first trace LA; the second cross-line insulator unit DA2 has a protruding structure DA2X protruding from the plane where the first cross-line insulator unit DA1 and the third cross-line insulator unit DA3 are located. Thus, by setting the surface of the second cross-line insulator unit DA2 away from the substrate SBT as a plane that protrudes from the first cross-line insulator unit DA1 and the third cross-line insulator unit DA3 away from the substrate SBT, the thickness of the second cross-line insulator unit DA2 corresponding to the overlapping area of ​​the first trace LA is increased, thereby increasing the step difference between the second trace segment overlapping portion LB2B and the first trace LA, further avoiding the possibility of short circuits and improving the yield of the display panel.

[0085] For example, as shown in Figure 7, the protrusion of the second cross-line insulator unit DA2 causes it to form an "arch" or "mound" shape, creating a relatively gentle slope angle. Furthermore, the slope angle of the second cross-line insulator unit DA2 does not exceed 45°.

[0086] In one embodiment of this disclosure, referring to FIG7, the first cross-line insulator unit DA1, the second cross-line insulator unit DA2, and the third cross-line insulator unit DA3 are located in the same organic layer. Exemplarily, as shown in FIGS. 2 and 7, the cross-line insulator unit DA includes a first planarization layer PLN1 located between the second conductive layer ML2 (source / drain metal layer SD) and the third conductive layer ML3 (pixel electrode layer ANL). When fabricating the display panel, the material layer of the first planarization layer PLN1 can be formed first, and then the material layer of the first planarization layer PLN1 can be patterned to form the first planarization layer PLN1. For example, the material layer of the first planarization layer PLN1 can be formed first on the side of the color filter layer CF away from the substrate SBT, and then the material layer of the first planarization layer PLN1 can be patterned. Optionally, grayscale mask exposure technology can be used to expose and develop the material layer of the first planarization layer PLN1, so that a raised structure DA2X is formed in the region of the second cross-line insulator unit DA2. In this embodiment, in the cross-line region, grayscale mask exposure technology is used to expose the material layer of the first planarization layer PLN1 in grayscale, so that the second cross-line insulator unit DA2 is in the shape of a hill or an arch with a gentle tilt angle, which increases the step difference between the first trace LA and the second trace LB in the cross-line region.

[0087] For example, as shown in FIG7, the thickness of the first planarization layer PLN1 is 2000nm-3000nm; the maximum thickness of the protrusion structure formed on the first planarization layer is 1000nm-2000nm.

[0088] For example, the first planarization layer material may be at least one of acrylic resin, polyimide resin, and benzocyclobutene resin.

[0089] In another embodiment of this disclosure, as shown in FIG8, the second cross-line insulator unit DA2 includes a first main structure DA2M and a first protrusion structure DA2D located on the side of the first main structure DA2M away from the substrate SBT. The first main structure DA2M, the first cross-line insulator unit DA1, and the third cross-line insulator unit DA3 are located in the same organic layer, while the first protrusion structure DA2D is located in another organic layer. Thus, the first protrusion structure DA2D can further increase the step difference between the cross-line region CA, the first trace LA, and the second trace LB, reducing the risk of short circuit in the cross-line region CA.

[0090] For example, referring to Figures 2 and 8, the display panel PNL has a first planarization layer PLN1 on the side of the source / drain metal layer away from the substrate SBT. This first planarization layer PLN1 forms a first main structure DA2M, a first cross-line insulator unit DA1, and a third cross-line insulator unit DA3 in the cross-line region CA. After forming the first planarization layer PLN1, a second planarization layer PLN2 can be formed on the side of the first planarization layer PLN1 away from the substrate SBT. This second planarization layer PLN2 forms a first protrusion structure DA2D in the cross-line region CA using an exposure and development technique. Furthermore, the second planarization layer PLN2 is completely removed outside the cross-line region CA, retaining only the first protrusion structure DA2D within the cross-line region CA. Thus, instead of thinning the first planarization layer PLN1, by increasing the thickness of the second planarization layer, the formed first protrusion structure DA2D can further increase the step difference between the first trace LA and the second trace LB in the cross-line region CA, reducing the risk of short circuits in the cross-line region CA.

[0091] In another embodiment of this disclosure, as shown in FIG9, the second cross-line insulator unit DA2 includes a second protruding structure DA21 and a second main body structure DA22 covering the second protruding structure DA21. The second main body structure DA22, the first cross-line insulator unit DA1, and the third cross-line insulator unit DA3 are located in one organic layer; the second protruding structure DA21 is located in another organic layer.

[0092] For example, referring to Figures 2 and 9, the second protrusion structure DA21 is located in the black matrix layer, and the second main structure DA22 is the first planarization layer PLN1.

[0093] For example, during the fabrication of the display panel PNL, a color filter layer CF can be formed on the side of the source / drain metal layer SD away from the substrate SBT. This color filter layer CF includes multiple color resist units and a black matrix layer. A second protrusion structure DA21 can be formed in the line-crossing region CA of the black matrix layer. Further, the second protrusion structure DA21 is formed in the portion of the black matrix layer located in the line-crossing region CA using grayscale exposure technology. Of course, in other embodiments of this disclosure, the second protrusion structure DA21 can also be disposed in the same layer as the color resist units.

[0094] After the color filter layer is formed, a first planarization layer PLN1 is formed. The first planarization layer PLN1 forms a first cross-line insulator unit DA1, a second main structure DA22 and a third cross-line insulator unit DA3 in the cross-line region CA.

[0095] Generally, the source and drain metal layers are thicker than the pixel electrode layers. Considering that placing the second trace segment LB2 on the pixel electrode layer may lead to uneven charge distribution and current concentration at the edges, resulting in tip discharge and affecting the yield of the display panel.

[0096] In one embodiment of this disclosure, referring to FIG10, the first trace segment LB1 has a first branch trace LB1D arranged parallel to the first trace LA, and the third trace segment LB3 has a second branch trace LB3D arranged parallel to the first trace LA. The second trace segment LB2 includes a plurality of branch traces LB2S arranged side by side; one end of each branch trace LB2S is electrically connected to the first branch trace LB1D through a via, and the other end is electrically connected to the second branch trace LB3D through a via. That is, the second trace segment LB2 is divided into multiple branch traces LB2S arranged side by side, and each branch trace LB2S is electrically connected to the first branch trace LB1D and the second branch trace LB3D through a via. By increasing the projected area of ​​the second trace segment LB2 on the substrate SBT, the insufficient thickness of the third conductive layer is compensated, thereby improving the performance of the display panel. In addition, the second trace segment LB2 has multiple parallel branch traces LB2S, which avoids the problem of charge concentration at the edge caused by the excessive area of ​​the second trace segment LB2, suppresses tip discharge, and improves the reliability of the display panel PNL.

[0097] For example, as shown in Figures 1 and 10, the second trace segment LB2 has a connection structure at its end, which connects the ends of the branch traces LB2S to each other; the connection structure is electrically connected to the first branch trace LB1D and the second branch trace LB3D through vias.

[0098] In one example, as shown in Figure 10, the first trace LA has an overlapping area with the branch trace LB2S, which can be partially cut out. For example, the overlapping area is cut out at the middle position. Of course, it is also possible to cut out other positions in the overlapping area while ensuring that the first trace LA is electrically conductive. In this way, the parasitic capacitance of the overlapping area between the first trace LA and the branch trace LB2S can be reduced, further improving the performance of the display panel.

[0099] The middle area of ​​the overlapping part LA1 of the first trace corresponding to the cross-line area CA is hollowed out.

[0100] In one embodiment of this disclosure, in the second trace LB, the width of the branch trace LB2S is not less than the width of the first trace segment LB1 and the width of the third trace segment LB3. For example, in the second trace segment LB2, the total number of branch traces LB2S is not less than six. Thus, the resistance of the second trace segment LB2 can be reduced by using as many branch traces LB2S as possible.

[0101] In one embodiment of this disclosure, among the branch traces LB2S of the second trace segment LB2, the spacing between the outer edges of the two outermost branch traces LB2S is not less than 20 times the width of the first trace segment LB1. This allows for a larger total width of the second trace segment LB2, minimizing its resistance.

[0102] In one example of this disclosure, the display panel PNL illustrated in Figures 2 and 7 can be prepared using the following method. This preparation method includes:

[0103] S1. A metal light-shielding layer LS, a buffer layer Buffer, a semiconductor layer SCL, and a gate insulating layer GI are sequentially formed on a glass substrate.

[0104] S2. A gate layer GT is formed on the side of the gate insulating layer GI away from the glass substrate. In the display area, the gate layer GT forms the gate of the transistor in the driving circuit layer through processes such as exposure and etching. In the non-display area, the gate layer GT is patterned to form various signal traces (e.g., driving power supply voltage trace VDD, reference power supply voltage trace VSS, and clock signal trace CLK for connection to GOA). One of these traces can serve as the first trace LA. The gate layer GT is made of copper and has a thickness of 400 nm.

[0105] S3. A first passivation layer PVX1 is formed on the side of the gate layer GT away from the glass substrate. The first passivation layer PVX1 is a SiOx material with a thickness of 400 nm.

[0106] S4. A source / drain metal layer SD is formed on the side of the first passivation layer PVX1 away from the glass substrate. In the display area of ​​the display panel, the source / drain metal layer SD forms connection traces. In the non-display area of ​​the display panel, the source / drain metal layer SD can form the first trace segment LB1 and the third trace segment LB3 of the second trace LB described in this disclosure. The source / drain metal layer SD is made of copper and has a thickness of 400 nm.

[0107] S5. A second passivation layer PVX2 is formed on the side of the source / drain metal layer SD away from the glass substrate. The second passivation layer PVX2 is a 400nm thick SiOx material.

[0108] S6. A color filter layer CF is formed on the side of the second passivation layer PVX2 away from the glass substrate. A first planarization layer PLN1 is formed on the side of the color filter layer CF away from the glass substrate. The thickness of the first planarization layer PLN1 is 2µm. In the cross-line region of the first peripheral region BB1, grayscale mask exposure technology is used to expose the first planarization layer PLN1 in grayscale to form a first planarization layer with a raised "mound structure".

[0109] S7. A pixel electrode layer is formed on the side of the first planarization layer PLN1 away from the substrate SBT. The pixel electrode layer includes a first conductive metal oxide layer ITO1, an Ag layer, and a second conductive metal oxide layer ITO2 stacked together. The first conductive metal oxide layer ITO1 is 70 nm, the Ag layer is 500 nm, and the second conductive metal oxide layer ITO2 is 12 nm. The pixel electrode layer can serve as the third conductive layer ML3 of this disclosure. A second trace segment LB2 located on the third conductive layer ML3 is electrically connected to the first trace segment LB1 and the third trace segment LB3 located on the second conductive layer ML2 through a via.

[0110] S8. A pixel definition layer PDL, a support pillar layer, an organic light-emitting functional layer EL, and a common electrode layer COML are sequentially formed on the side of the pixel electrode layer away from the substrate SBT to form a pixel layer FB; a thin film encapsulation layer is formed on the side of the pixel layer FB away from the substrate SBT.

[0111] This disclosure also provides a display device, which includes the aforementioned display panel (PNL). Exemplarily, the display device may include, but is not limited to, any product or component with display functionality such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This disclosure does not limit the scope of the application.

[0112] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that, It includes a first trace and a second trace; the display panel includes at least a substrate, a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence; The first trace is located in the first conductive layer; The display panel has at least one crossover area; in the crossover area, the second trace includes a first trace segment, a second trace segment, and a third trace segment connected in sequence; wherein the first trace segment and the third trace segment are both located in the second conductive layer, and the second trace segment is located in the third conductive layer and is electrically connected to the first trace segment and the third trace segment through a via; The orthographic projections of the first trace segment and the third trace segment on the substrate are respectively located on both sides of the orthographic projection of the first conductive layer on the substrate; the second trace segment overlaps with the first conductive layer.

2. The display panel according to claim 1, characterized in that, The second trace segment has a second trace segment end and a second trace segment overlap portion that overlaps with the first trace; the step difference between the second trace segment overlap portion and the substrate is greater than the step difference between the second trace segment end and the substrate.

3. The display panel according to claim 2, characterized in that, The step difference between the overlapping portion of the second trace segment and the substrate is 1 to 2 micrometers larger than the step difference between the end of the second trace segment and the substrate.

4. The display panel according to claim 3, characterized in that, The first trace has an overlapping portion that overlaps with the second trace segment, and the step difference between the surface of the first trace overlapping portion away from the substrate and the surface of the second trace segment overlapping portion near the substrate is not less than 3 micrometers.

5. The display panel according to claim 1, characterized in that, In the cross-line area, the display panel has a cross-line insulation unit between the second conductive layer and the third conductive layer; The second trace segment is formed on the surface of the cross-line insulation unit away from the substrate. Along the extension direction of the second wiring, the cross-line insulation unit sequentially includes a first cross-line insulator unit, a second cross-line insulator unit, and a third cross-line insulator unit; the first cross-line insulator unit is provided with a first through hole, and the third cross-line insulator unit is provided with a second through hole; the second wiring segment is electrically connected to the first wiring segment through the first through hole, and is electrically connected to the third wiring segment through the second through hole; the second cross-line insulator unit overlaps with the first wiring; the second cross-line insulator unit has a protruding structure that protrudes from the plane where the first cross-line insulator unit and the third cross-line insulator unit are located.

6. The display panel according to claim 5, characterized in that, The slope angle of the second cross-line insulator unit does not exceed 45°.

7. The display panel according to claim 5, characterized in that, The first cross-line insulator unit, the second cross-line insulator unit, and the third cross-line insulator unit are located in the same organic layer.

8. The display panel according to claim 5, characterized in that, The second cross-line insulator unit includes a first main body structure and a first protrusion structure located on the side of the first main body structure away from the substrate. The first main body structure, the first cross-line insulator unit, and the third cross-line insulator unit are located in the same organic layer, and the first protrusion structure is located in another organic layer.

9. The display panel according to claim 5, characterized in that, The second cross-line insulator unit includes a second protruding structure and a second main body structure covering the second protruding structure; The second main structure, the first cross-line insulator unit, and the third cross-line insulator unit are located in an organic layer; The second protrusion structure is located in another organic layer.

10. The display panel according to claim 1, characterized in that, The first routing segment has a first branch routing line arranged parallel to the first routing line, and the third routing segment has a second branch routing line arranged parallel to the first routing line; The second routing segment includes multiple branch routings arranged side by side; one end of each branch routing is electrically connected to the first branch routing through a via, and the other end is electrically connected to the second branch routing through a via.

11. The display panel according to claim 10, characterized in that, In the second routing, the width of the branch routing is not less than the width of the first routing segment and the width of the third routing segment.

12. The display panel according to claim 10, characterized in that, In the second routing segment, the total number of branch routings is no less than 6.

13. The display panel according to claim 10, characterized in that, In each branch of the second routing segment, the distance between the outer edges of the two outermost branch routing segments is not less than 20 times the width of the first routing segment.

14. The display panel according to claim 1, characterized in that, The substrate further includes one or more gate layers, one or more source / drain metal layers and pixel electrode layers that are sequentially stacked on one side of the substrate. The first conductive layer is a gate layer, the second conductive layer is a source / drain metal layer, and the third conductive layer is a pixel electrode layer.

15. The display panel according to claim 14, characterized in that, The pixel electrode layer includes a first conductive metal oxide layer, a metal layer, and a second conductive metal oxide layer stacked sequentially; wherein the metal layer is between 50nm and 1000nm.

16. The display panel according to claim 1, characterized in that, The display panel includes a display area and a first peripheral area located on at least one side of the display area; a gate driving circuit for driving pixel driving circuits in the display area is provided in the first peripheral area, and the gate driving circuit includes a plurality of shift registers arranged sequentially along the column direction; The first trace is located in the first outer area and extends along the column direction; The second routing line is located in the first peripheral area and extends along the routing direction.

17. The display panel according to claim 16, characterized in that, The display panel has a first driving trace for loading a first driving signal to a shift register and a second driving trace for loading a second driving signal to a shift register in the first peripheral area. The first driving trace and the second driving trace extend along the column direction, and the second driving trace is located between the first driving trace and the shift register. One end of the second trace is electrically connected to the first drive trace, and the other end is electrically connected to the shift register; the second drive trace is arranged to overlap with the second trace in the crossover area as the first trace.

18. The display panel according to claim 17, characterized in that, One of the first driving signal and the second driving signal is a high-level voltage signal, and the other is a low-level voltage signal.

19. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 18.

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