Machine language instructions and a processor

Abstract

A machine language instruction which, when executed by a processor which comprises a memory and a vector register, causes the processor to load as data in the vector register a two-dimensional array of elements stored in the memory. Also, a machine language instruction which, when executed by a processor which comprises a memory and a vector register, causes the processor to store in the memory as a two-dimensional array of elements, data stored in the vector register. Also, a processor which comprises a memory and a vector register.

Description

[0001] MACHINE LANGUAGE INSTRUCTIONS AND A PROCESSOR

[0002] TECHNICAL FIELD

[0003] The present invention relates to machine language instructions. The present invention also relates to a processor.

[0004] STATE OF THE ART

[0005] There are known conventional processors such as central processing units (CPUs) or graphic processing units (GPUs) which comprise a memory and vector registers, wherein the memory is capable of storing two-dimensional (2D) arrays of data, and each vector register is capable of storing a vector which may also be considered as being a one-dimensional (1 D) array of data. The 2D array of data may also be referred to as “2D array of elements”, and it may be understood that said 2D array of elements comprises rows and columns. It is noted that a 2D array of elements may also be called “tile” or “2D tile”, and the vector may also be called “1 D tile” or “1 D array”. Typically, the elements that form the aforementioned 2D and 1 D arrays comprise bytes, wherein each byte comprises a plurality of bits. Similarly, the 1 D array of data may also be referred to as “1 D array of elements”. Typically, for a processor which comprises vector registers, the vector registers are included in a vector register file of the processor.

[0006] There are also known computing applications of the aforementioned conventional processors, wherein said known applications involve the transfer of a 2D array of data between the processor’s memory and the processor’s vector registers. For example, in Machine Learning (ML) the weights or parameters of a layer in a Deep Neural Network are typically encoded as a matrix, and to obtain better locality and achieve higher performance, ML algorithms typically involve traversing matrices tile by tile, each tile being a 2D sub-matrix i.e. a two-dimensional array within the matrix. However, a problem with the aforementioned conventional processors, is that for the purpose of these processors eventually fetching or storing an entire 2D tile from / to their memory, they must perform a plurality of corresponding fetching (loading) or storing steps, wherein in each step there is fetched or stored, respectively, a corresponding row of the 2D tile, and wherein for executing each fetching or storing step, the processor must directly receive a corresponding machine language instruction. Consequently, these conventional processors may be very slow and inefficient in applications that involve storing in the memory of the processor, or loading from the memory of the processor, 2D arrays of data. Given this drawback of many known conventional processors, there is needed a way for overcoming said drawback. DESCRIPTION OF THE INVENTION

[0007] The present invention overcomes the aforementioned drawback of known conventional processors. Advantageously, the present invention allows for accelerating the fetching by the processor of a two-dimensional array of elements stored in a memory of the processor. Likewise, the present invention also allows for accelerating storing a two-dimensional array of elements to the memory of the processor. Consequently, the present invention may significantly improve the computational resources, such as the power consumption and computational time, required for the execution of algorithms that involve the frequent transfer of 2D arrays of elements, e.g. tiles or sub-matrices of matrices, to or from the memory of the processor, wherein the said transfer may have the form of fetching from the memory a 2D array of elements, or storing to the memory the 2D array of elements. Hence, the present invention may be of great use in various modern computing applications, e.g. in machine learning, that involve the use of one or more of the aforementioned algorithms.

[0008] A first aspect of the invention concerns a machine language instruction which, when executed by a processor which comprises a memory and a vector register, causes the processor to load as data in the vector register a two-dimensional array of elements stored in the memory. It is noted that the 2D array of elements may also be called “2D array of data”, or “2D tile”, or “tile”, or “2D matrix”, or “2D submatrix”, or “matrix” or “submatrix”. Preferably, the 2D array of elements is a tile (i.e. a 2D tile) or submatrix of a matrix stored in the memory of the processor. It also noted that preferably the processor comprises a plurality of vector registers, and the aforementioned vector register belongs to the plurality of vector registers. It is also noted that preferably the memory of the processor may be a main memory of the processor.

[0009] It may be understood that the first aspect of the invention may advantageously accelerate the process of loading the 2D array of elements from the memory of the processor to the vector register of the processor, because it allows for using a single machine language instruction for the performance of said loading. It is noted that the elements stored in the memory preferably are bytes stored in the memory, with each element comprising one or more bytes, and each byte comprising a plurality of bits. Also, the data loaded to the vector register as a result of the execution of the machine language instruction of the first aspect of the invention, may also be called “vector”, or “1 D array of elements” or “1 D tile”, or “1 D array of data”, wherein 1 D means “one-dimensional”. Also, since the machine language instruction may cause the processor to load a vector to the vector register, may also be called “vector load instruction”. Therefore, the machine language instruction of the first aspect of the invention allows for directly fetching a 2D tile from the memory of the processor, and for loading the fetched 2D tile as a vector to the vector register of the processor. Consequently, the machine language instruction of the first aspect of the invention, and the processor that is suitable for executing said machine language instruction of the first aspect of the invention, may effectuate the loading of the vector faster compared to conventional processors and corresponding conventional machine language instructions which may only effectuate the fetching and loading of the 2D tiles via a series of fetching and loading steps, wherein in each step is for transferring and loading only a corresponding row of the 2D tile, and each step requires that the processor receives and executes a corresponding conventional machine language instruction that concerns the respective row to be fetched and loaded from the memory to a vector register. In contrast, the present invention may advantageously allow for the processor to fetch the entire 2D tile, and load the latter to the vector register, via the processor receiving once a single machine language instruction which is according to the first aspect of the invention.

[0010] In a preferred embodiment of the first aspect of the invention, which herein is also referred to as “first exemplary embodiment”, the machine language instruction comprises information which indicates the vector register, a base address of a region of the memory where the array of elements is stored, and a description of the array of elements. This information may advantageously facilitate the identification by the processor, of the vector register to which the data are to be loaded as a result of the processor executing the machine language instruction. Also, this information may facilitate the identification of the array of elements that should fetched from the memory, and of the memory’s region that stores the array of elements to be fetched. It is noted that the aforementioned possible identification of the vector register, may be particularly advantageous and useful in the preferable case that the processor comprises a plurality of vector registers. It is also noted that preferably the memory comprises blocks (i.e. memory blocks) for storing in the blocks information / data / elements. In the latter case the aforementioned region of the memory may be the particular block or blocks into which the array of elements is stored.

[0011] In a preferred embodiment which is according to the aforementioned first exemplary embodiment, the description of the array of elements indicates at least the following: a number of rows of the array of elements; a number of elements per row, a width of the array, and a row stride. Since in the latter case the machine language instruction, i.e. the vector load instruction, indicates the row stride, it may also be called “vector load with row stride” (VLRS) instruction. Considering that typically a 2D array of data, i.e. a matrix, that is stored in a memory of a processor consists of bytes, wherein each byte consists of a plurality of bits, the term “row stride” may be understood as referring to the number of bytes of a row in the matrix. For example, if the matrix that has dimensions M x N, i.e. M rows and N columns, and each individual element has B bytes, then the row stride is N x B. The indication of the number of rows, the number of the elements per row, the width of the array, and the row stride, may advantageously facilitate the localization by the processor of the memory’s region or blocks in which the 2D array of elements is stored, and, hence, may advantageously improve the efficiency and speed with which the processor may execute the instruction. Also, in the optional case that the array of elements comprises active and inactive elements as mentioned further below, the aforementioned identification of the number of rows, the number of the elements per row, the width of the array, and the row stride, may advantageously facilitate the identification by the processor of the inactive elements, and the optional execution by the processor of the also mentioned further below padding with zeros of part of the data.

[0012] In a preferred embodiment of the first aspect of the invention, the array of elements comprises active and inactive elements, and the machine language instruction when executed by the processor further causes the processor to pad with zeros a part of the data, said part corresponding to the inactive elements. The latter embodiment may advantageously optimize the suitability of the machine language instruction for the execution by the processor of matrix processing algorithms which work with fixed-size tiles and may be applied for the processing of one or more matrices stored in the memory. In the latter case, it may be possible that a tile or submatrix that is to be transferred as part of the execution of the matrix processor algorithm, may contain elements which are beyond the boundaries of a matrix stored in the memory. Hence, part of the tile may belong to and be within the boundaries of the matrix, and part of the tile may be outside the boundaries of the matrix and not belong to the latter. In the latter case, the tile’s elements that are not part of the matrix, may be considered as being inactive elements, and their padding with zeros “0” may facilitate the application of the machine language instruction for the execution of an algorithm for the processing of the matrix.

[0013] A second aspect of the invention concerns a machine language instruction which, when executed by a processor which comprises a memory and a vector register, causes the processor to store in the memory as a two-dimensional array of elements, data stored in the vector register. The machine language instruction of the second aspect of the invention may also be called “vector store instruction” because it can be considered as being an instruction that allows for storing in the processor’s memory and in the form of a two-dimensional array, a vector (1 D array of elements) that is stored / located in the vector register. Also, the instruction of the second aspect of the invention may also be called “second machine language instruction” so that is easily distinguished from the instruction of the first aspect of the invention which may similarly be called “first machine language instruction”. It may be understood that both the first and the second machine language instructions serve the common purpose of facilitating and optimizing the transfer, between the memory and the vector register, of information or data concerning a 2D array of elements. Hence, the first and the second instructions may form a set of instructions which may advantageously serve for effectuating via a single instruction each time, the transfer of said information or data, with the first machine language instruction being for the transfer of the information from the memory to the vector register, and the second machine language instruction being for transferring the information from the vector register to the memory.

[0014] In a preferred embodiment of the second aspect of the invention, which herein is also referred to as “second exemplary embodiment”, the machine language instruction comprises information which indicates the vector register, a base address of a region of the memory where the array of elements should be stored, and a description of the array of elements. This information may advantageously facilitate the identification by the processor, of the vector register that holds the data to be transferred to the memory, and may also facilitate the identification of the memory’s region in which the array of elements should be stored. It is noted that the aforementioned possible identification of the vector register may be particularly advantageous and useful in the preferable case that the processor comprises a plurality of the vector registers. It is also noted that preferably the memory comprises blocks (i.e. memory blocks) for storing information / data / elements in the blocks. In the latter case, the aforementioned region of the memory may be the particular block or blocks to which the array of elements should be stored.

[0015] In a preferred embodiment which is according to the aforementioned second exemplary embodiment, the description of the array of elements indicates at least the following: a number of rows of the array of elements; a number of elements per row, a width of the array, and a row stride. Since in the latter case the machine language instruction, i.e. vector store instruction, indicates the row stride, it may also be called “vector store with row stride” (VSRS) instruction. As mentioned further above, the term “row stride” may be understood as referring to the number of bytes of a row in the matrix. The indication of the number of rows, the number of the elements per row, the width of the array, and the row stride, may advantageously facilitate the localization by the processor of the memory’s region or blocks in which the 2D array of elements is to be stored, and, hence, may advantageously improve the efficiency and speed with which the processor may execute the machine language instruction.

[0016] In a preferred embodiment of the second aspect of the invention, when the data comprises active and inactive elements, the machine language instruction when executed by the processor further causes the processor to store in the memory the active elements and not store the inactive elements. In the latter case, the instruction may advantageously facilitate the copying / storing / writing into the memory, of only the active elements.

[0017] In some preferred embodiments of the first or the second aspect of the invention, the machine language instruction conforms with the RISC-V instruction set architecture. Hence, the machine language instruction may preferably conform with the RISC-V instruction format or RISC-V instruction coding. This may advantageously allow for the use of the instruction with RISC-V processors targeting a variety of end applications.

[0018] In some preferred embodiments of the first or second aspect of the invention, each element is 8, 16, 32 or 64 bits in size. This may advantageously benefit the versatility of the invention.

[0019] In some preferred embodiments of the invention, the memory comprises memory blocks suitable for storing elements of the array of elements; the processor further comprises an address generation unit which is configured to receive the machine language instruction; the machine language instruction is further configured to cause the address generation unit to generate memory addresses of the memory blocks which store or should store the elements of the array of elements, and preferably to also generate a count to indicate a number of elements in each block. In the latter case, the address generation unit may advantageously facilitate the expedient execution of the instruction by the processor.

[0020] A third aspect of the invention concerns a processor which comprises a memory and a vector register and is configured to execute a machine language instruction which is according to first or the second aspect of the invention. Preferably, the processor comprises a plurality of vector registers which include the aforementioned vector register. More preferably the processor comprises a vector register file which comprises the plurality of vector registers.

[0021] In some preferred embodiments of the invention, the processor is any of a central processor unit (CPU), a graphics processing unit (GPU) or a core of a central or graphics processing unit. Hence, the present invention may advantageously be utilized for improving the functionality of different types of processors. Also, in a very preferred embodiment of the invention, the processor is compatible with the RISC-V instruction set architecture.

[0022] In a preferred embodiment of the third aspect of the invention, which herein is also referred to as “third exemplary embodiment”, the memory comprises memory blocks suitable for storing elements of the array of elements; the processor further comprises an address generation unit which is configured to receive the machine language instruction; the address generation unit when it receives the machine language instruction during an operation of the processor, is configured to generate memory addresses of the memory blocks that store or should store the elements of the array of elements, and preferably to also generate a count to indicate a number of elements in each block. The address generation unit in the latter embodiment may advantageously facilitate the expedient execution of the machine language instruction by the processor.

[0023] In a preferred embodiment which is according to the aforementioned third exemplary embodiment, the processor further comprises a load store unit which is connected to the address generation unit, the memory and the vector register, and is configured to receive from the address generation unit the generated sequence of memory addresses and either read the memory and write the vector register when the machine language instruction is a vector load instruction according to the first aspect of the invention, or read the vector register and write the memory when the machine language instruction is a vector store instruction according to second aspect of the invention. Hence, in the latter embodiments, the address generation unit in combination with the load store unit may advantageously facilitate a correct and expedient execution of the instruction by the processor.

[0024] In a very preferred embodiment, which is according to the aforementioned third exemplary embodiment, the processor further comprises a control and status register which is connected to the address generation unit, and contains information regarding the configuration of the vector register, said information preferably including an indication of a length of data stored in the vector register. In the latter case, the control and status register may facilitate the operation of the address generation unit for the expedient execution of the instruction received by the processor.

[0025] A fourth aspect of the invention concerns a computer-readable medium or data carrier comprising a machine language instruction of the first or of the second aspect of the invention. The computer-readable medium may be a computer-storage medium or a data carrier, and may have stored thereon a vector load instruction which is according to the first aspect of the invention, and / or a vector store instruction which is according to the second aspect of the invention. In some non-limiting examples, the aforementioned computer storage medium may be hard-drive, a memory card, a flash memory, a cache memory, a random access memory (RAM) or a read-only memory.

[0026] It may be understood that the instructions of the first and second aspect of the invention may be using the processor of the third aspect of the invention. Hence, it may be understood that any optional or preferable features mentioned herein with respect to any of the first, second, third or fourth aspect of the invention, may correspond to respective optional or preferable features of any of the other aspects of the invention, and vice versa.

[0027] Additional advantages and features of the invention will become apparent from the detailed description that follows and will be particularly pointed out in the appended claims.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To complete the description and in order to provide for a better understanding of the invention, a set of drawings is provided. Said drawings form an integral part of the description and illustrate embodiments of the invention, which should not be interpreted as restricting the scope of the invention, but just as examples of how the invention can be carried out. The drawings comprise the following figures:

[0030] Fig. 1 illustrates a block diagram of preferred embodiment of a processor according to the invention.

[0031] Fig. 2 schematically illustrates an example of vector load operation performed with a preferred embodiment of the invention.

[0032] Fig. 3 schematically illustrates an example of a vector store operation performed with a preferred embodiment of the invention.

[0033] Fig. 4 schematically illustrates an example of tiles to be loaded to vector registers of a vector register file of a processor which is according to a preferred embodiment of the invention, wherein parts of the tiles are outside the boundaries a matrix stored in a memory of the processor.

[0034] Fig. 5 schematically illustrates the encodings of some preferred embodiments of a vector load instruction of the first aspect of the invention.

[0035] Fig. 6 schematically illustrates the encodings of some preferred embodiments of a vector store instruction of the second aspect of the invention.

[0036] Fig. 7 illustrates a block diagram of preferred embodiment of a processor according to the invention.

[0037] Fig. 8 schematically illustrates an example of a 2D array of elements processed with a preferred embodiment of the invention.

[0038] DESCRIPTION OF A WAY OF CARRYING OUT THE INVENTION

[0039] The following description is not to be taken in a limiting sense but is given solely for the purpose of describing the broad principles of the invention. Next embodiments of the invention will be described by way of example, with reference to the above-mentioned drawings, showing embodiments according to the invention, and some related operations and other information.

[0040] A preferred embodiment of a processor of the third aspect of the invention is explained next with reference to Fig. 1. Specifically, Fig. 1 is a block diagram which schematically illustrates a processor 1 which is according to the third aspect of the invention and comprises a memory 2 and a vector register 3. The memory 2 is a main memory of the processor. Also, the processor 1 of Fig. 1 is configured to execute a preferred embodiment of a “vector load” machine language instruction which is according to the first aspect of the invention, and a preferred embodiment of a “vector store” machine language instruction which is according to the second aspect of the invention. The vector load machine language instruction when executed by the processor 1 causes the processor to load as data in the vector register 3 a two-dimensional (2D) array of elements stored in the memory 2. Hence, the vector load machine language instruction that is executable by the processor of Fig.1 , causes the processor to copy / load the 2D array of elements, i.e. a tile, from the memory to the vector register of the processor. Also, the vector store machine language instruction when executed by the processor 1 causes the processor to store in the memory 2 as a two-dimensional array of elements, data stored in the vector register 3. It is noted that the data stored in the vector register 3 may be considered as being a vector or 1 D array of elements.

[0041] Another very preferred embodiment is explained next and concerns a processor which is according to the one of Fig. 1 and is configured to execute a very preferred embodiment of an instruction that is a VLRS instruction and is according to the first aspect of the invention, and a very preferred embodiment of an instruction that is a VSRS instruction and is according to the second aspect of the invention. The VLRS instruction comprises the following: first information “vd” which indicates the vector register to which the data should be loaded; a base address “rs2” of a region of the memory where the array of elements is stored; and a description “rs1” of the array of elements. Said description rs1 of the array of elements indicates, i.e. contains, information regarding the following: a number of rows of the array of elements; a number of elements per row, a width of the array, and a row stride. The VSRS instruction comprises the following: second information “vs” which indicates the vector register to which the data (vector) is stored; a base address “rs2” of a region of the memory where the array of elements should be stored; and a description “rs1” of the array of elements. The description rs1 of the array of elements indicates at least the following: a number of rows of the array of elements; a number of elements per row, a width of the array, and a row stride. Each element preferably is 8, 16, 32 or 64 bits in size. When each element is 8, 16, 32 or 64 bits in size, the corresponding embodiment of the VLRS instruction may be referred to as vlrse8, vlrse16, vlrse32, or vlrse64 instruction, respectively. Similarly, when each element is 8, 16, 32 or 64 bits in the corresponding embodiment of the VSRS instruction may be referred to as vsrse8, vsrse16, vsrse32, or vsrse64 instruction, respectively.

[0042] In the latter preferred embodiment, the VLRS instruction is also configured to cause the following: when the array of elements comprises active and inactive elements, the machine language instruction when executed by the processor further causes the processor to pad with zeros a part of the data, said part corresponding to the inactive elements. Causing the processor to do the aforementioned padding with zeros of the part of the data that corresponds to the inactive elements, may be advantageous when working with fixed-sized tiles part of which fall outside the boundaries of a matrix stored in the memory. Fig. 4 illustrates examples of tiles. Each of the tiles shown in Fig. 4 comprises a corresponding part which is composed of inactive elements which are outside the boundaries of a matrix stored in the memory of the processor. In Fig. 4, the boundaries of the width and length of the matrix are indicated by the double arrows with the dashed lines. As indicated in Fig. 4, for the inactive elements a padding with zeros will be applied according to the VLRS instruction.

[0043] An example of a vector load operation that may be performed with the vlrse32 instruction is explained next with reference to Fig. 2. The operation illustrated in Fig. 2 concerns copying a tile composed of 8 elements. In Fig. 2 each of the 8 elements is indicated with a corresponding number from 0 to 7. The tile is a sub-matrix that belongs to a matrix stored in the memory of the processor. The tile comprises 2 rows, and there are 4 elements per row. With the operation of Fig. 2, the tile is copied / loaded to a vector register within a vector register file.

[0044] It can be understood that the instruction used for the operation shown in Fig. 2 employs two integer registers and one vector register: vd, (rs2), rs1 , wherein vd is the destination vector register where the tile will be written; rs2 is the base address of the tile in memory; and rs1 contains a description of the tile. More specifically, with respect to the operation shown in Fig. 2, rs1 encodes the following information: the number of active elements on each row of the tile (bits 63 to 56); the number of rows of the tile (bits 55 to 48); the tile width, used to determine the padding (bits 47 to 40); the row stride: number of bytes between two consecutive elements in the column (bits 39 to 0).

[0045] An example of a vector store operation that may be performed with the vsrse32 instruction is explained next with reference to Fig. 3. The operation illustrated in Fig. 3 concerns copying a vector composed of 8 elements each of which in Fig. 3 is indicated with a corresponding number from 0 to 7. The tile is copied / stored as a tile to the memory, wherein the tile is a submatrix that belongs to a matrix stored in the memory of the processor. The tile comprises 2 rows, and there are 4 elements per row. It can be understood that the instruction used for the operation shown in Fig. 3 has two integer registers and one vector register: VSRS vs, (rs2), rs1 , wherein vs is the source vector register that contains the tile; rs2 is the base main memory address where the tile will be written, and rs1 contains a description regarding the 2D array of elements. Specifically, with respect to the operation shown in Fig. 3, rs1 encodes the following information: the number of active elements on each row of the tile; the number of rows of the tile; the tile width; the row stride.

[0046] Some of the aforementioned information concerning the vlrse8, vlrse16, vlrse32, vsrse8, vsrse16 and vsrse32 instructions which are mentioned further above, is further shown in Table 1 provided below.

[0047] Table 1

[0048] A pseudo code for some of the aforementioned VLRS instructions, is provided below in Table

[0049] 2. It is noted that in the pseudo code shown below, VLEN refers to the size of a vector register in bits, whereas VL is the current vector length in number of elements.

[0050] Table 2

[0051]

[0052] Based on the information provided above, the respective VLRS instructions are mapped as shown in Table 3 below:

[0053] Table 3

[0054] A pseudo code for some of the aforementioned VSRS instructions, is provided below in Table 4. Table 4

[0055] Based on the information provided above, the respective VSRS instructions are mapped as shown in Table 5 below: Table 5

[0056] The vlrse8, vlrse16 and vlrse32 instructions which are mentioned further above, employ the custom-3 opcode in RISC-V, and their encoding (i.e. the encoding of the instruction) is shown in Fig. 5. Likewise, the vsrse8, vsrse16 and vsrse32 instructions which are mentioned further above, also employ the custom-3 opcode in RISC-V, and their encoding is shown in Fig. 6. It is noted that in Fig. 5 and Fig. 6, “func6” refers to a 6-bit function field, and “func3” refers to a 3-bit function field.

[0057] Another preferred embodiment of a processor of the third aspect of the invention is explained next with reference to Fig. 7. Fig. 7 schematically illustrates a processor 10 which comprises a memory 2 and a vector register file 7. The vector register file 7 comprises a plurality of vector registers. In the embodiment of Fig. 7, the memory 2 comprises memory blocks suitable for storing elements of the array of elements. Also, the processor 10 further comprises an address generation unit 6 which is configured to receive the machine language instruction. The address generation unit (AGU) 6 when it receives the machine language instruction during an operation of the processor 10, is configured to generate memory addresses of the memory blocks that store or should store the elements of the array of elements, and to also generate a count to indicate a number of elements in each block. Also, the processor 10 of Fig. 7 further comprises a load store unit (LSU) 5 that is connected to the address generation unit, the memory 2 and the vector register file 7. The LSU 5 is configured to receive from the AGU 6 the generated sequence of memory addresses and either read the memory and write the vector register when the machine language instruction is a vector load instruction according to first aspect of the invention, or read the vector register and write the memory when the machine language instruction is a vector store instruction according to second aspect of the invention. Hence, as illustrated by respective arrows in Fig. 7, the LSU 5 may perform a memory request, such as a request for writing a 2D tile onto the memory, or a request for fetching the data of a 2D tile stored in the memory. Also, the LSU 5 may receive from the memory a response or requested data. Also, the LSU 5 may write data onto the vector registers of the vector register file, and may read data from said data registers, via respective write and read ports. The embodiment of Fig. 7 also comprises a control and status register 8 which is connected to the address generation unit 6. The control and status register (GSR) 8 contains information regarding the configuration of the vector register. The information contained in the GSR 8 includes an indication of a length of data stored in the vector register. The GSR 8 is configured to provide said information to the AGU 6. Hence, the AGU may receive from the GSR information regarding the length of the vectors (i.e. the vector length) stored in the vector registers of the vector register file 7.

[0058] From the above, the following may be understood regarding the processor of Fig. 7. The Address Generation Unit (AGU) may receive the information of the instruction and the information regarding the current configuration of the vector registers. The Control and Status Register (CSR) may contain the information regarding the current configuration of the vector registers. More specifically, the CSR may contain the number of elements that can be fit in a vector register, i.e. the Vector Length (VL). The Load Store Unit (LSU) may send read / write requests to the memory, and may process the responses. It is noted that preferably the memory 2 of the embodiment of Fig. 7 is a random access memory. The LSU may also have access to the Vector Registers through a write port and a read port. The memory accepts read and write requests. The Vector Registers can be read and written by the LSU. An example of an operation concerning the execution of a VSRS or VLRS instruction by the embodiment of Fig. 7 is described next. The AGU receives the information of the instruction, i.e. the opcode and the data from registers rs1 and rs2, and generates a sequence of memory addresses for the LSU. The memory 2 of the processor of Fig. 2 is split in blocks of a fixed size, known as memory blocks or memory lines, and all the accesses are done at block-level granularity. Therefore, in the embodiment of Fig. 7 the AGU is a hardware unit that will generate the addresses of the memory blocks that contain or should contain elements of the 2D tile indicated or specified by the VLRS / VSRS instruction.

[0059] Another example of an operation concerning the execution of a VLRS instruction by the embodiment of Fig. 7 is described next with reference to Fig. 8 which shows a matrix stored in the memory, starting at address A. The matrix of Fig. 8 has 4 rows and 16 columns, and the size of each individual element is 4 bytes. In this example, the size of a memory block is 32 bytes and, hence, the Matrix occupies 8 memory blocks. Given this matrix, a programmer in this specific example wants to fetch the 2D tile containing elements from 0,0 to 1 ,9. To this end, the programmer uses a VLRS instruction with the following parameters: Base address = A; Number of elements per row = 10; Number of rows of the tile = 2; Tile width = 10; Row stride = 64. Furthermore, before the execution of the VLRS, the programmer sets the VL (vector length) to 20 in the CSR. The AGU will proceed as follows when receiving the VLRS. First, it will compute the total number of memory blocks that must be fetched. In this case, each row of the 2D tile has 10 elements of 4 bytes, a total of 40 bytes. Since the size of the memory block is 32 bytes, it means that 2 memory blocks must be fetched per row. Because the number of rows in the 2D tile is 2, a total of 4 memory blocks must be fetched. Second, the AGU will generate the starting address for each memory block, and it will also generate a count to indicate the useful elements in each block. The 4 memory blocks will be fetched as follows:

[0060] 1. The first memory block has address A (the base address of the 2D tile). The AGU will generate address A and it will set the number of elements to 8 (all elements in the block are useful). The LSU will receive this address and element count and it will generate a memory read request to fetch the first block. The memory will respond with the data (32 bytes of the block) to the LSU. Finally, the LSU will write elements from 0,0 to 0,7 in the destination vector register. Hence, the first memory block is formed by elements 0,0 to 0,7.

[0061] 2. AGU will add block size (32 bytes) to A, generating address A+32 for the next request. Furthermore, the element count will be set to 2, as there are only 2 useful elements in this memory block. Hence, the second memory block that will be fetched is formed by elements 0,8 and 0,9

[0062] 3. Since the AGU has completed the first row of the tile, now it will add the row stride to A to generate the address of the first block in the second row of the tile. It will send address A + row stride to the LSU and it will set element count to 8. Hence, the third memory block that will be fetched is formed by elements 1 ,0 to 1 ,7.

[0063] 4. Finally, AGU will generate address A + row stride + 32, i.e. the address of the last memory block for the 2D tile. It will send this address to the LSU and it will set element count to 2. Therefore, the AGU receives the information of VLRSA / SRS instructions and it generates the addresses of all the memory blocks that contain elements that are inside the 2D tile, and the corresponding element count within each block. The LSU will use this information to read memory and write the vector register (for VLRS), or read the vector register and write the data into memory (for VSRS). In this text, the term “comprises” and its derivations (such as “comprising”, etc.) should not be understood in an excluding sense, that is, these terms should not be interpreted as excluding the possibility that what is described and defined may include further elements, steps, etc.

[0064] The invention is obviously not limited to the specific embodiment(s) described herein, but also encompasses any variations that may be considered by any person skilled in the art (for example, as regards the choice of materials, dimensions, components, configuration, etc.), within the general scope of the invention as defined in the claims.

Claims

CLAIMS1. A machine language instruction which, when executed by a processor which comprises a memory and a vector register, causes the processor to load as data in the vector register a two-dimensional array of elements stored in the memory.

2. A machine language instruction according to claim 1 , wherein the machine language instruction comprises information which indicates the vector register, a base address of a region of the memory where the array of elements is stored, and a description of the array of elements.

3. A machine language instruction according to claim 2, wherein the description of the array of elements indicates at least the following: a number of rows of the array of elements; a number of elements per row, a width of the array, and a row stride.

4. A machine language instruction according to any of the preceding claims, wherein when the array of elements comprises active and inactive elements, the machine language instruction when executed by the processor further causes the processor to pad with zeros a part of the data, said part corresponding to the inactive elements.

5. A machine language instruction which, when executed by a processor which comprises a memory and a vector register, causes the processor to store in the memory as a two- dimensional array of elements, data stored in the vector register.

6. A machine language instruction according to claim 5, wherein the machine language instruction comprises information which indicates the vector register, a base address of a region of the memory where the array of elements should be stored, and a description of the array of elements.

7. A machine language instruction according to claim 6, wherein the description of the array of elements indicates at least the following: a number of rows of the array of elements; a number of elements per row, a width of the array, and a row stride.

8. A machine language instruction according to any of claims 5-7, wherein when the data comprises active and inactive elements, the machine language instruction when executed by the processor further causes the processor to store in the memory the active elements and not store the inactive elements.

9. A machine language instruction according to any of the previous claims, wherein the machine language instruction conforms with the RISC-V instruction set architecture.

10. A machine language instruction according to any of the preceding claims, wherein each element is 8, 16, 32 or 64 bits in size.11 . A machine language instruction according to any of the preceding claims, wherein the memory comprises memory blocks suitable for storing elements of the array of elements; the processor further comprises an address generation unit which is configured to receive the machine language instruction; the machine language instruction is further configured to cause the address generation unit to generate memory addresses of the memory blocks which store or should store the elements of the array of elements, and preferably to also generate a count to indicate a number of elements in each block.

12. A processor which comprises a memory and a vector register and is configured to execute a machine language instruction which is according to any of the previous claims.

13. A processor according to claim 12, wherein the processor is any of a central processor unit, a graphics processing unit or a core of a central or graphics processing unit, preferably the processor being compatible with of the RISC-V instruction set architecture.

14. A processor according to any of claims 12-13, wherein the memory comprises memory blocks suitable for storing elements of the array of elements; the processor further comprises an address generation unit which is configured to receive the machine language instruction; the address generation unit when it receives the machine language instruction during an operation of the processor, is configured to generate memory addresses of the memory blocks that store or should store the elements of the array of elements, and preferably to also generate a count to indicate a number of elements in each block.

15. A processor according to claim 14, further comprising: a load store unit that is connected to the address generation unit, the memory and the vector register, and is configured to receive from the address generation unit the generated sequence of memory addresses and either read the memory and write the vector register whenthe machine language instruction is according to claim 1 , or read the vector register and write the memory when the machine language instruction is according to claim 5.

16. A processor according to any of claims 14-15, further comprising a control and status register which is connected to the address generation unit and contains information regarding the configuration of the vector register, said information preferably including an indication of a length of data stored in the vector register.

Images