Method and apparatus for polar encoding in communication and broadcasting system

Abstract

The present disclosure relates to a 5G or 6G communication system for supporting a data transmission rate higher than a 4G communication system such as LTE. A method performed by an electronic device, according to an embodiment of the present disclosure, may comprise the steps of: identifying L partial input vectors on the basis of an input vector; identifying L matrices related to L layers of a deep polar code, wherein an I layer input vector for an I (2≤l≤L) matrix from among the L matrices comprises information bits, connection bits, and frozen bits, and an I partial input vector from among the L partial input vectors corresponds to the information bits of the I layer input vector; and generating a codeword vector corresponding to the input vector, on the basis of the deep polar code.

Description

Polar encoding method and device in communication and broadcasting systems

[0001] The present disclosure relates to an apparatus and method for correcting errors occurring in wired and wireless channels by utilizing polar codes in communication and broadcasting systems.

[0002] Looking back at the evolution of wireless communication through successive generations, technologies have been developed primarily for human-oriented services, such as voice, multimedia, and data. Following the commercialization of 5G (5th-generation) communication systems, connected devices, which have been increasing explosively, are expected to be connected to communication networks. Examples of networked objects include vehicles, robots, drones, home appliances, displays, smart sensors installed in various infrastructures, construction machinery, and factory equipment. Mobile devices are expected to evolve into various form factors, such as augmented reality glasses, virtual reality headsets, and holographic devices. In the 6G (6th-generation) era, efforts are underway to develop improved 6G communication systems to connect hundreds of billions of devices and objects to provide diverse services. For this reason, 6G communication systems are referred to as "Beyond 5G" systems.

[0003] In the 6G communication system predicted to be realized around 2030, the maximum transmission speed is tera (i.e., 1,000 gigabit) bps, and the wireless latency is 100 microseconds (μsec). In other words, compared to the 5G communication system, the transmission speed in the 6G communication system is 50 times faster, and the wireless latency is reduced to one-tenth.

[0004] To achieve such high data transmission speeds and ultra-low latency, 6G communication systems are being considered for implementation in the terahertz band (e.g., the 95 GHz to 3 terahertz (3 THz) band). In the terahertz band, due to more severe path loss and atmospheric absorption compared to the millimeter wave (mmWave) band introduced in 5G, the importance of technology capable of guaranteeing signal reach, or coverage, is expected to increase. As key technologies to ensure coverage, radio frequency (RF) devices, antennas, new waveforms that offer better coverage than orthogonal frequency division multiplexing (OFDM), beamforming, and multi-antenna transmission technologies such as massive multiple-input and multiple-output (MIMO), full-dimensional MIMO (FD-MIMO), array antennas, and large-scale antennas must be developed. In addition, new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing technology using orbital angular momentum (OAM), and reconfigurable intelligent surface (RIS) are being discussed to improve coverage of terahertz band signals.

[0005] In addition, to improve frequency efficiency and system network, development is underway in 6G communication systems for full duplex technology, in which uplink and downlink simultaneously utilize the same frequency resources at the same time; network technology that integrates satellites and HAPS (high-altitude platform stations); network structure innovation technology that supports mobile base stations and enables network operation optimization and automation; dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction; AI-based communication technology that utilizes AI (artificial intelligence) from the design stage and internalizes end-to-end AI support functions to realize system optimization; and next-generation distributed computing technology that realizes services of complexity exceeding the limits of terminal computing capabilities by utilizing ultra-high performance communication and computing resources (mobile edge computing (MEC), cloud, etc.). In addition, attempts are continuing to further strengthen connectivity between devices, further optimize networks, promote the softwareization of network entities, and increase the openness of wireless communication through the design of new protocols to be used in 6G communication systems, the implementation of hardware-based security environments, the development of mechanisms for the safe utilization of data, and the development of technologies regarding privacy maintenance methods.

[0006] Due to the research and development of such 6G communication systems, it is expected that a new dimension of hyper-connected experience will become possible through the hyper-connectivity of 6G communication systems, which encompasses not only connections between objects but also connections between people and objects. Specifically, it is projected that 6G communication systems will enable the provision of services such as truly immersive extended reality (XR), high-fidelity mobile holograms, and digital replicas. Furthermore, services such as remote surgery, industrial automation, and emergency response, which are provided through 6G communication systems with enhanced security and reliability, will be applied in various fields including industry, healthcare, automotive, and home appliances.

[0007] - References

[0008] [1] E. Arikan, “Channel Polarization: a method for constructing capacity-achieving codes for symmetric binary-input memoryless channels,” IEEE Trans. Information Theory, vol. 55, no. 7, pp. 3051-3073, 2009.

[0009] [2] I. Tal and A. Vardy, “List Decoding of Polar Codes,” IEEE Transactions on Information Theory, vol. 61, no. 5, pp. 2213-2226.

[0010] [3] G. Choi and N. Lee, “Deep Polar Codes,” in IEEE Transactions on Communications, vol. 72, no. 7, pp. 3842-3855, July 2024.

[0011] [4] D. Han, M. Jang, D. Lee, S. Myung and N. Lee, “Practical Decoding for Deep Polar Codes,” 2024 IEEE Globecom Workshops, Cape Town, South Africa, pp. 1-6, Dec. 2024.

[0012] [5] M. Rowshan, SH Dau and E. Viterbo, “On the Formation of Min-Weight Codewords of Polar / PAC Codes and Its Applications,” in IEEE Transactions on Information Theory, vol. 69, no. 12, pp. 7627-7649, Dec. 2023.

[0013] The above information is provided for background information only to aid in understanding the present disclosure. No determination or claim has been made as to whether any of the above contents can be applied as prior art to the present disclosure.

[0014] Various embodiments of the present disclosure may provide polar encoding methods and devices in communication and broadcasting systems.

[0015] The technical problems to be solved in the various embodiments of the present disclosure are not limited to those mentioned above, and other technical problems not mentioned may be considered by those skilled in the art from the various embodiments of the present disclosure described below.

[0016] A method performed by an electronic device according to one embodiment of the present disclosure may include: identifying an input vector for a deep polar code; identifying L matrices associated with L layers of the deep polar code, wherein an l-layer input vector for l (2≤l≤L) of the L matrices comprises information bits, connection bits, and frozen bits, and the information bits of the l-layer input vector are associated with l of the L parts of the input vector; and generating a codeword vector corresponding to the input vector based on the deep polar code.

[0017] According to one embodiment of the present disclosure, in generating the codeword vector, the connecting bit of the l-th level input vector is associated with the output of the l-1 matrix for the l-1-th level input vector, and the sub-channel index associated with the connecting bit of the l-th level input vector is It includes indices, and among the connection bits of the above l-layer input vector, the above Related to the index A freeze bit can be mapped to the connection bits.

[0018] According to one embodiment of the present disclosure, a preset polar sign sequence Based on this, a set of information indices corresponding to the first layer among the above L layers is identified, and based on the set of information indices corresponding to the first layer, the minimum Hamming weight is identified, and the above The indices are the minimum Hamming weights among the row vectors in the l matrix. Corresponding to at least some of the row vectors having, and the minimum Hamming weight among the row vectors in the l matrix The number of row vectors having is It may be less than.

[0019] According to one embodiment of the present disclosure, an information index set corresponding to the first layer and the minimum Hamming weight Based on, a maximum information index set including an information index set corresponding to the first layer and an information index set corresponding to the l layer is identified, and the The maximum value of Is class It is the smaller value among them, is the set of information indices corresponding to the first layer and the minimum Hamming weight It is the number of elements included in the intersection of the set of bit indices of row vectors having, and is the set excluding the elements included in the information index set corresponding to the first layer from the maximum information index set, the information index set corresponding to the first layer, and the minimum Hamming weight It may be the number of elements included in the intersection of the set of bit indices of row vectors having.

[0020] According to one embodiment of the present disclosure, the above The index is the above minimum Hamming weight Among row vectors having It satisfies, and And, is the above-mentioned maximum information index set, and is the binary support of vector x, and is the minimum Hamming weight in the polar sign generation matrix It is a specific row vector having, is in the above polar sign generation matrix It is a specific row vector corresponding to, and And, And, N may be the codeword length corresponding to the above-mentioned deep polar code.

[0021] According to one embodiment of the present disclosure, the set of connection indices associated with the connection bits of the l-layer input vector comprises: the information index set included in the set of information indices corresponding to the first layer. k indices; and the highest reliability included in the set excluding the element of the information index set corresponding to the first layer from the maximum information index set. It includes indices, and among the connection bits of the l-layer input vector, the one with the highest reliability Related to the index Information bits can be mapped to the connection bits.

[0022] According to one embodiment of the present disclosure, in the information index set corresponding to the first layer, the The lowest confidence level excluding the index Includes indexes, can be the codeword length corresponding to the first layer above.

[0023] According to one embodiment of the present disclosure, the size of the set of linked indices is And, It can be an integer.

[0024] According to one embodiment of the present disclosure, the step of transmitting the codeword vector is further included, and L=2.

[0025] An electronic device according to one embodiment of the present disclosure may include at least one transceiver; one processor connected to communicate with the at least one transceiver; and a memory that stores instructions for: identifying an input vector for a deep polar code; identifying L matrices associated with L layers of the deep polar code, wherein an l-layer input vector for l (2≤l≤L) of the L matrices comprises information bits, connection bits, and frozen bits, and wherein the information bits of the l-layer input vector are associated with l of the L parts of the input vector; and generating a codeword vector corresponding to the input vector based on the deep polar code.

[0026] According to one embodiment of the present disclosure, in generating the codeword vector, the connecting bit of the l-th level input vector is associated with the output of the l-1 matrix for the l-1-th level input vector, and the sub-channel index associated with the connecting bit of the l-th level input vector is It includes indices, and among the connection bits of the above l-layer input vector, the above Related to the index A freeze bit can be mapped to the connection bits.

[0027] According to one embodiment of the present disclosure, a preset polar sign sequence Based on this, a set of information indices corresponding to the first layer among the above L layers is identified, and based on the set of information indices corresponding to the first layer, the minimum Hamming weight is identified, and the above The indices are the minimum Hamming weights among the row vectors in the l matrix. Corresponding to at least some of the row vectors having, and the minimum Hamming weight among the row vectors in the l matrix The number of row vectors having is It may be less than.

[0028] According to one embodiment of the present disclosure, an information index set corresponding to the first layer and the minimum Hamming weight Based on, a maximum information index set including an information index set corresponding to the first layer and an information index set corresponding to the l layer is identified, and the The maximum value of Is class It is the smaller value among them, is the set of information indices corresponding to the first layer and the minimum Hamming weight It is the number of elements included in the intersection of the set of bit indices of row vectors having, and is the set excluding the elements included in the information index set corresponding to the first layer from the maximum information index set, the information index set corresponding to the first layer, and the minimum Hamming weight It may be the number of elements included in the intersection of the set of bit indices of row vectors having.

[0029] According to one embodiment of the present disclosure, the above The index is the above minimum Hamming weight Among row vectors having It satisfies, and And, is the above-mentioned maximum information index set, and is the binary support of vector x, and is the minimum Hamming weight in the polar sign generation matrix It is a specific row vector having, is in the above polar sign generation matrix It is a specific row vector corresponding to, and And, And, N may be the codeword length corresponding to the above-mentioned deep polar code.

[0030] According to one embodiment of the present disclosure, the set of connection indices associated with the connection bits of the l-layer input vector comprises: the information index set included in the set of information indices corresponding to the first layer. k indices; and the highest reliability included in the set excluding the element of the information index set corresponding to the first layer from the maximum information index set. It includes indices, and among the connection bits of the l-layer input vector, the one with the highest reliability Related to the index Information bits can be mapped to the connection bits.

[0031] According to one embodiment of the present disclosure, in the information index set corresponding to the first layer, the The lowest confidence level excluding the index Includes indexes, can be the codeword length corresponding to the first layer above.

[0032] According to one embodiment of the present disclosure, the size of the set of linked indices is And, It can be an integer.

[0033] The various embodiments of the present disclosure described above are merely some of the preferred embodiments of the present disclosure, and various embodiments reflecting the technical features of the various embodiments of the present disclosure can be derived and understood by those skilled in the art based on the detailed description to be described below.

[0034] Various embodiments of the present disclosure may provide polar encoding methods and devices in communication and broadcasting systems.

[0035] The effects obtainable from the various embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art based on the following detailed description.

[0036] The drawings attached below are intended to aid in understanding various embodiments of the present disclosure and provide various embodiments of the present disclosure together with the detailed description. However, the technical features of the various embodiments of the present disclosure are not limited to specific drawings, and the features disclosed in each drawing may be combined with one another to form new embodiments. Reference numerals in each drawing denote structural elements.

[0037] FIG. 1 illustrates an example of an encoding process using polar symbols according to embodiments of the present disclosure.

[0038] Figure 2 illustrates a codeword vector generated through an encoding process being transmitted through a channel.

[0039] FIG. 3 illustrates an example of a decoding process using polar codes according to embodiments of the present disclosure.

[0040] FIG. 4 illustrates an example of a graph corresponding to polar symbols in a communication system or broadcasting system according to embodiments of the present disclosure.

[0041] FIG. 5 illustrates an element process for performing LLR (log-likelihood ratio) calculation and sequential removal in a polar code decoding method and apparatus according to an embodiment of the present disclosure.

[0042] FIG. 6a illustrates an example of a polar encoding method when rate matching is not used, where the length of the parent code N=16, the number of information bits (K) is 5, and the number of CRC bits is 3.

[0043] FIG. 6b illustrates another example of a polar coding method in which rate matching is not used when the length of the parent code N=16, the number of information bits (K) is 5, and the number of CRC bits is 3.

[0044] FIG. 6c illustrates an example of how information bits (including CRC) are mapped when considering perforation and shortening.

[0045] Figure 6d illustrates another example of how information bits (including CRC) are mapped when considering perforation and shortening.

[0046] FIG. 7 is a drawing for illustrating an example of a polar symbol according to an embodiment of the present disclosure.

[0047] FIG. 8 is a diagram showing an example of a two-layer deep polar code according to one embodiment of the present disclosure.

[0048] FIG. 9 is a diagram showing an example of an L-layer Deep Polar Code according to one embodiment of the present disclosure.

[0049] Figure 10 shows the error probability for ML (Maximum Likelihood) decoding. This is a graph showing an example of performance.

[0050] FIG. 11 is a drawing showing an example of nested subcodes according to one embodiment of the present disclosure.

[0051] FIG. 12 shows an example of an affine subspace according to one embodiment of the present disclosure.

[0052] FIG. 13 is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0053] FIG. 14a is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0054] FIG. 14b is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0055] FIG. 14c is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0056] FIG. 14d is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0057] FIG. 14e is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0058] FIG. 14f is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0059] FIG. 14g is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0060] FIG. 14h is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0061] FIG. 14i is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0062] FIG. 14j is a drawing for illustrating an example of a lower limit of codeword weight according to one embodiment of the present disclosure.

[0063] FIG. 15 is a drawing for illustrating an example of a case where AS is generated in a deep polar symbol to which an embodiment of the present disclosure is applicable.

[0064] FIG. 16 is a diagram illustrating an example of a method for determining the number of total minimum weight codewords in a deep polar code to which an embodiment of the present disclosure is applicable.

[0065] FIG. 17 is a diagram illustrating an example of a method for determining the number of total minimum weight codewords in a deep polar code to which an embodiment of the present disclosure is applicable.

[0066] FIG. 18 is a drawing for explaining the principle of row invalidation according to one embodiment of the present disclosure.

[0067] FIG. 19 is a drawing for explaining the principle of row invalidation according to one embodiment of the present disclosure.

[0068] FIG. 20 is a drawing for explaining the principle of row invalidation according to one embodiment of the present disclosure.

[0069] FIG. 21 is a drawing for explaining the principle of row invalidation according to one embodiment of the present disclosure.

[0070] FIG. 22 is a drawing for explaining the principle of row invalidation according to one embodiment of the present disclosure.

[0071] FIG. 23 is a drawing for explaining the principle of row invalidation according to one embodiment of the present disclosure.

[0072] FIG. 24 is a drawing for explaining the principle of row invalidation according to one embodiment of the present disclosure.

[0073] FIG. 25 is a diagram illustrating an example of a deep polar code process based on row invalidation according to one embodiment of the present disclosure.

[0074] FIG. 26 is an experimental example relating to the expected performance improvement when using a deep polar encoding process based on row invalidation according to one embodiment of the present disclosure.

[0075] FIG. 27 shows the number of rows that are invalidated in an L-layer deep polar code according to one embodiment of the present disclosure. This shows an example of a method for determining.

[0076] FIG. 28 is for an L-layer deep polar code design algorithm according to one embodiment of the present disclosure.

[0077] FIG. 29 is a drawing showing an example of the operation of an electronic device according to one embodiment of the present disclosure.

[0078] FIG. 30 is a block diagram of a terminal or user equipment (3000) according to one embodiment of the present disclosure.

[0079] FIG. 31 is a block diagram of a base station (3100) according to one embodiment of the present disclosure.

[0080] FIG. 32 is a block diagram of a network entity (3200) that performs network functions according to one embodiment of the present disclosure.

[0081] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0082] In describing the embodiments, technical details that are well known in the art to which this disclosure belongs and are not directly related to this disclosure are omitted. This is intended to convey the essence of this disclosure more clearly without obscuring it by omitting unnecessary explanations.

[0083] For the same reason, some components in the attached drawings have been exaggerated, omitted, or schematically depicted. Additionally, the size of each component does not entirely reflect its actual dimensions. Identical or corresponding components in each drawing have been assigned the same or different reference numbers.

[0084] The advantages and features of the present disclosure, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure is complete and to fully inform those skilled in the art of the scope of the disclosure, and the present disclosure is defined only by the scope of the claims. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present disclosure, if it is determined that a detailed description of a related function or configuration might unnecessarily obscure the essence of the present disclosure, such detailed description is omitted. Additionally, the terms described below are defined considering their functions in the present disclosure, and these may vary depending on the intentions or conventions of the user or operator. Therefore, their definitions should be based on the content throughout the specification.

[0085] In the present disclosure, it will be understood that each block of the process flow diagrams and combinations of the flow diagrams may be performed based on computer program instructions. Since these computer program instructions may be optionally loaded into at least one processor of a general-purpose computer, a computer for special purposes, or other programmable data processing equipment, the instructions performed through any one or any combination of at least one processor of the computer or other programmable data processing equipment create means for performing the functions described in the flow diagram block(s). Since these computer program instructions may also be stored in computer-available or computer-readable memory that can be directed toward the computer or other programmable data processing equipment to implement the functions in a specific manner, the instructions stored in computer-available or computer-readable memory may also produce a manufactured item containing means of instruction for performing the functions described in the flow diagram block(s). Since computer program instructions can be loaded onto a computer or other programmable data processing equipment, instructions that perform a series of operation steps on the computer or other programmable data processing equipment to create a process executed by the computer can also provide steps for executing the functions described in the flowchart block(s).

[0086] Additionally, each block may represent a module, segment, or part of code containing one or more executable instructions for executing a specified logical function(s). It should also be noted that in some alternative execution examples, the functions mentioned in the blocks may occur out of order. For example, two blocks (or functions) described in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order according to the corresponding function.

[0087] As used in the embodiments of the present disclosure, the term “part” refers to a software or hardware component, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), and the “part” performs certain roles. However, the term including “part” is not limited to software or hardware. The “part” may be configured to reside in an addressable storage medium or may be configured to run on one or more processors. Thus, by example, the “part” includes components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and “parts” may be combined into a smaller number of components and “parts” or further separated into additional components and “parts.” In addition, the components and 'parts' may be implemented to utilize one or more CPUs (central processing units) within the device or secure multimedia card. Also, in the embodiments, the 'parts' may include one or more processors.

[0088] As stated above, it should be noted that the blocks of each flowchart and combinations of flowcharts described in this disclosure may be executed by one or more computer programs including instructions. The entirety of one or more computer programs may be stored in a single memory device, or one or more computer programs may be divided into different parts and stored across multiple memory devices.

[0089] Additionally, any / any function or operation described in this disclosure may be processed by a single processor or a combination of processors. The single processor or combination of processors is a circuitry that performs processing and may include an application processor (AP, e.g., a central processing unit (CPU)), a communication processor (CP, e.g., a modem), a graphics processing unit (GPU), a neural network processing unit (NPU) (e.g., an artificial intelligence (AI) chip), a Wi-Fi chip, a Bluetooth® chip, a global positioning system (GPS) chip, a near-field communication (NFC) chip, a connectivity chip, a sensor controller, a touch controller, a fingerprint sensor controller, a display driver integrated circuit (IC), an audio codec (CODEC) chip, a universal serial bus (USB) controller, a camera controller, an image processing IC, a microprocessor unit (MPU), a system-on-chip (SoC), an IC, or similar circuitry.

[0090] Additionally, it should be noted that various embodiments in the claims and description of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

[0091] Such software may be stored on a non-transitory computer-readable storage medium. A non-transitory computer-readable storage medium stores one or more computer programs (software modules), and said one or more computer programs include computer-executable instructions that operate an electronic device to perform a method according to the present disclosure when executed alone or collectively by one or more processors of an electronic device.

[0092] The software may be stored in a transient or non-transient storage device, for example, in the form of read-only memory (ROM) (whether or not it is erasable or rewritable), or random access memory (RAM), memory chips, devices, or integrated circuits (ICs). Additionally, the software may be stored in the form of an optically or magnetically readable medium, for example, a compact disc (CD), a digital multifunction disc (DVD), a magnetic disc, or a magnetic tape. It should be understood that the storage device and the storage medium are examples of non-transient machine-readable storage media suitable for storing programs for implementing various embodiments of the present disclosure. Accordingly, various embodiments of the present disclosure may provide a program containing code for implementing a device or method according to any one of the claims of this specification, and a non-transient machine-readable storage medium storing such program.

[0093] In the following disclosure, determining the priority between A and B may be referred to in various ways, such as selecting the one with the higher priority according to a predetermined priority rule and performing the corresponding action, or omitting or dropping the action for the one with the lower priority.

[0094] Hereinafter, 'A or B' as described in the present disclosure may be understood as 'A and / or B', which may be understood as including 'A', or 'B', or 'A and B'.

[0095] Additionally, 'at least one of A, B, and C' described in the present disclosure may be understood to include 'A', or 'B', or 'C', or 'any combination of A, B, and C'.

[0096] Additionally, 'at least one of A, B, or C' described in the present disclosure may be understood to include 'A', or 'B', or 'C', or 'any combination of A, B, and C'.

[0097] Additionally, 'A / B' as described in the present disclosure may be understood as 'A and / or B', which may be understood as including 'A', or 'B', or 'A and B'.

[0098] Additionally, 'A, B' described in the present disclosure may be understood as 'A and / or B', which may be understood as including 'A', or 'B', or 'A and B'.

[0099] Additionally, 'A and B' described in the present disclosure may be understood as 'A and / or B', which may be understood as including 'A', or 'B', or 'A and B'.

[0100] Furthermore, the phrase "when conditions A and B are satisfied" as described in the present disclosure is not necessarily limited to cases where both conditions A and B are satisfied, but may be understood to include cases where either condition A or condition B is satisfied individually, cases where both conditions A and B are satisfied, or cases where one or more additional conditions are satisfied together.

[0101] Furthermore, throughout this specification, ordinal terms (and similar modifiers) such as 'first', 'second', 'third', etc. are used solely for the purpose of distinguishing various instances, occurrences, configurations, messages, stages, or aspects of elements, operations, or information, as described below. Unless clearly required otherwise by the context, the use of such ordinal terms does not require that the elements, operations, or information distinguished by such terms be structurally different, numerically distinct, or essentially different. For example, 'first signal' and 'second signal' may represent instances of the same signal transmitted at different times, signals containing the same core information even with some variations, or signals having different content or characteristics depending on the specific context. Similarly, 'first value' and 'second value' may represent the same magnitude measured or applied in different situations, or may represent different magnitudes. Such interpretation must be determined based on the specific technical context, function, and relationship described in the relevant parts of the specification and claims.

[0102] Furthermore, although terms such as "first," "second," etc., as used in this disclosure are used for various elements such as information, objects, actions, and sequences, they are not intended to limit such elements to a specific order. These terms may be understood merely as distinguishing one element from another. For example, a first element may be referred to as a second element, and likewise, a second element may be referred to as a first element.

[0103] Additionally, the terms 'first' and 'second' described in this disclosure may be understood to refer to identical or different elements. For example, if an element is information, the first information and the second information may both be information, and depending on the case, they may be the same information or different information.

[0104] Furthermore, the expressions 'if' and 'in case that' described in this disclosure or claims may be interpreted, depending on the context, as meaning 'when or upon,' 'in response to,' 'based on,' or 'according to,' and these expressions may be used interchangeably. In addition, other expressions having substantially the same meaning may be used as substitutes, provided that they do not impair the technical features of this disclosure.

[0105] Additionally, the term "not perform" as used in this disclosure or claims may be understood, depending on the context, to mean to omit or skip the corresponding step. Such a term may be replaced with other terms having the same or substantially similar meaning.

[0106] Additionally, the phrase "transmitting a message containing A and B" as described in this specification may be interpreted to include not only (i) cases where A and B are transmitted as a single message, but also (ii) cases where A and B are transmitted individually through multiple messages (e.g., transmitting a first message containing A and a second message containing B). This interpretation may also apply to cases where messages containing two or more items, such as A, B, and C, are transmitted together or individually.

[0107] In addition, 'transmitting a message containing A and transmitting a message containing B' can also be interpreted as transmitting a single message containing A and B.

[0108] In the specific embodiments of the present disclosure described below, terms or components included in the disclosure will be expressed in the singular or plural form according to the specific embodiments presented. However, the singular or plural expression is selected to suit the circumstances presented for convenience of explanation, and the present disclosure is not limited to singular or plural components; even if a component is expressed in the plural form, it may be composed in the singular form, and even if a component is expressed in the singular form, it may be composed in the plural form.

[0109] The drawings or flowcharts described below illustrate exemplary methods that may be implemented in accordance with the principles of the present disclosure, and various modifications may be made to the methods illustrated in the flowcharts of the present disclosure. For example, although illustrated as a series of steps, the various steps of each drawing or flowchart may overlap, occur in parallel, occur in a different order, or occur multiple times. In other examples, any step may be omitted or replaced with another step.

[0110] The methods and devices proposed in the embodiments of the present disclosure below are not limited to each embodiment and may be utilized as a combination of all or part of the embodiments proposed in the disclosure. Accordingly, the embodiments of the present disclosure may be applied with some modifications within the scope that does not deviate significantly from the scope of the present disclosure, at the judgment of a person skilled in the art.

[0111] In this case, any wording mentioned in different embodiments may be used interchangeably, combined, or substituted if the concepts correspond. For example, regarding the same or corresponding concepts, even if the expression 'A' is used in one embodiment and the expression 'B' is used in another embodiment, they may be understood by interchangeably, substituted, or combined.

[0112] Terms used in the following description to identify connection nodes, terms referring to network entities, terms referring to messages, terms referring to interfaces between network entities, terms referring to various identification information, etc., are examples provided for the convenience of explanation. Accordingly, the present disclosure is not limited to the terms described below, and other terms referring to objects having equivalent technical meanings may be used. Furthermore, where appropriate, such terms may be replaced with terms defined in the 3GPP (3rd generation partnership project) Technical Specifications (TS).

[0113] Hereinafter, the base station, as the entity performing resource allocation for terminals, may be at least one of gNode B, eNode B, Node B, BS (base station), wireless access unit, base station controller, or a node on a network. Additionally, the base station of the present disclosure may include a structure split into a central unit (CU) and a distributed unit (DU). In such a structure, the CU is responsible for the upper layer of the control and user plane, and the DU is responsible for wireless resource processing of the lower layer. The embodiments of the present disclosure can be equally applied to a 5G base station structure in which functions are separated into the CU and DU as described above.

[0114] The terminal may include a UE (user equipment), MS (mobile station), cellular phone, smartphone, computer, or a multimedia system capable of performing communication functions.

[0115] In the present disclosure, a downlink (DL) refers to a wireless transmission path of a signal transmitted by a base station to a terminal, and an uplink (UL) refers to a wireless transmission path of a signal transmitted by a terminal to a base station.

[0116] In addition, while a 5th generation mobile communication system (5G, new radio, NR) and a 6th generation mobile communication system (6G) may be described below as examples, embodiments of the present disclosure may also be applied to other communication systems having similar technical backgrounds or channel types. For example, new advanced mobile communication systems developed after 5G and 6G may be included therein. Furthermore, the present disclosure may be applied to other communication systems (e.g., Wi-Fi systems) with some modifications made in the judgment of a person with skilled technical knowledge, without significantly departing from the scope of the present disclosure.

[0117] In the following description, the terms "physical channel" and "signal" may be used interchangeably with "data" or "control signal." For example, PDSCH (physical downlink shared channel) is a term referring to a physical channel through which data is transmitted, but PDSCH may also be used to refer to data. That is, in this disclosure, the expression "transmits a physical channel" may be interpreted as equivalent to the expression "transmits data or a signal through a physical channel."

[0118] In describing the present disclosure below, the term "upper layer signaling" may be a signaling corresponding to at least one or a combination of at least one of MIB (master information block), SIB (system information block), SIB M (M=1, 2, …), RRC (radio resource control), MAC (medium access control), CE (control element), NAS (non-access stratum) signaling, or application layer messages. The RRC signaling may also be referred to as L3 signaling (layer 3 signaling).

[0119] Additionally, L1 signaling may be a signaling method corresponding to at least one or a combination of at least one of the following: a physical layer channel or signaling of a PDCCH (physical downlink control channel), a DCI (downlink control information), a UE-specific DCI, a group common DCI, a common DCI, a scheduling DCI (e.g., a DCI used for the purpose of scheduling downlink or uplink data), a non-scheduling DCI (e.g., a DCI not used for the purpose of scheduling downlink or uplink data), a PUCCH (physical uplink control channel), or an UCI (uplink control information). The above L1 signaling may also be referred to as physical layer signaling.

[0120] Hereinafter, the expression in the present disclosure or claims that information can be configured from a base station may mean that, depending on the context, a terminal receives said information from a base station through physical layer signaling or upper layer signaling, and such expression may be replaced with other terms having the same or substantially similar meaning.

[0121] The operating principle of the present disclosure will be explained in detail below with reference to the attached drawings.

[0122] When transmitting and receiving data between a transmitter and a receiver in communication or broadcasting systems, data errors may occur due to noise or interference in wired or wireless channels. To effectively identify and process such errors occurring in communication channels at the receiver, coding methods include error detection codes and error correction codes. Error detection codes are a method for verifying whether received data contains errors, while error correction codes are designed to enable the receiver to correct errors contained in the received data on its own. Error correction codes are also referred to as channel coding or forward error correction (FEC).

[0123] Various error correction methods exist, and representative error correction codes include convolutional codes, turbo codes, low-density parity-check codes (LDPC), and polar codes. Among these, turbo codes, low-density parity-check codes, and polar codes demonstrate excellent performance by approaching or achieving theoretical channel capacity, and are currently used in various communication and broadcasting systems.

[0124] Polar codes are channel codes that achieve point-to-point channel capacity in binary discrete memoryless channels (B-DMCs) by utilizing the channel polarization phenomenon [1]. The encoding process of polar codes is defined by a generator matrix that is repeatedly constructed from a polarization kernel of size 2×2. The decoding process of polar codes is performed using successive cancellation (SC) and is characterized by estimating each encoded input bit one by one sequentially.

[0125] During this encoding and decoding process, the channels for each bit are combined and then separated, thereby converting each bit into a polarized sub-channel. These sub-channels are also called synthetic channels, and some sub-channels are classified as superior channels with high channel capacity, while others are inferior channels with low capacity. As the code length increases, the capacity of the superior channels approaches 1, while the capacity of the inferior channels converges to 0. Through this, information bits are allocated to the superior channels, and frozen bits (which contain no information) are allocated to the inferior channels, thereby maximizing the overall channel capacity.

[0126] SC decoding can theoretically achieve channel capacity when the code length is very long. However, in practice, when the code length is finite, the performance of SC decoding is relatively poor. To compensate for this disadvantage, improved decoding techniques such as SC-list (SCL) decoding, SC-stack (SCS) decoding, and SC-flip (SCF) decoding have been proposed. In particular, SCL decoding [2] is the most widely used today because it improves decoding performance by considering multiple paths or lists while estimating bits sequentially, just like SC decoding.

[0127] SCL decoders perform well even with short code lengths, and for this reason, 5G NR, the 5G communication standard, mainly uses polar codes when transmitting short-length control information.

[0128] It should be noted that the terms used to refer to signals, resources, operation states, data, channels, network objects, and components of a device as described in the following description of the present disclosure are exemplary and that the present disclosure is not limited to specific terms.

[0129] In this disclosure, expressions such as 'greater than or equal to', 'less than or equal to', 'greater than', and 'less than' may be used when describing specific conditions, but these are not intended to limit the scope of specific conditions and may be interpreted flexibly.

[0130] In this disclosure, terms used in some communication and broadcasting standards, such as the 3rd Generation Partnership Project (3GPP), are described as examples, but this is merely for convenience of explanation, and various embodiments of this disclosure can be easily applied to other communication and broadcasting systems.

[0131] Various terms are used to refer to channel coding in the course of describing the present disclosure. For example, channel coding may be referred to as error correction codes (ECC) or forward error correction (FEC).

[0132] The channel encoding operation performed by the transmitter is referred to as channel encoding, or simply encoding, encoding, etc., and the device performing this operation may be referred to as a channel encoder, encoder, or encoding unit, etc. The operation performed by the receiver is referred to as channel decoding, decoding, decoding, decoding, etc., and the device performing this operation may be referred to as a channel decoder, decoder, decoder, or decoder, etc. These terms are expressions that are easily understood by a person with ordinary knowledge in the technical field to which this disclosure belongs. In this disclosure, the transmitter may be a base station and the receiver may be a terminal, and conversely, the transmitter may be a terminal and the receiver may be a base station.

[0133] Mathematical symbols commonly used in the process of describing the present disclosure are utilized. These symbols are expressions that are easily understood by a person skilled in the art to which the present disclosure pertains. The following mathematical symbols are primarily used in the present disclosure.

[0134] - Calligraphic characters (e.g., ) represents a set.

[0135] - Unless otherwise noted, the index of the first element of a set, sequence, or vector is assumed to start from 0. This implies zero-based numbering.

[0136] - sign represent the set of natural numbers, the set of integers, and the set of real numbers, respectively.

[0137] - sign represents a binary field.

[0138] - For a non-negative integer n, represents a set consisting of n consecutive integers from 0 to n-1. That is, am.

[0139] - Boldface lowercase (e.g., a) represents a vector, and boldface uppercase (e.g., A) represents a matrix. Vectors are considered row vectors unless otherwise noted.

[0140] - For vector a and matrix A, and represents each transpose.

[0141] - For vector a and non-negative integers i, j, represents a subvector consisting of consecutive elements from the i-th element to the j-th element of vector a. That is, Is am.

[0142] Polar codes are error correction codes proposed by E. Arikan and are the first error correction codes proven to achieve channel capacity, which is the limit of data transmission performance in binary discrete non-memory channels, while having low coding and decoding complexity that is feasible to implement [1]. Polar codes and sequential removal-based decoding methods provide excellent error correction performance even with short code lengths compared to other channel codes. Due to these advantages, polar codes are used in the 3GPP New Radio (NR), a 5th generation (5G) mobile communication standard, when transmitting short-length control information.

[0143] FIG. 1 illustrates an example of an encoding process using polar symbols according to embodiments of the present disclosure.

[0144] vector is an information vector that the transmitter intends to send to the receiver, and the dimension A of the vector is the number of information bits.

[0145] The above information vector a (101) can be encoded by external encoding (110). The outer codeword vector generated by external encoding is b (111) is defined as follows. Here, K represents the length of the external codeword vector and is greater than or equal to A. In one embodiment, concatenated external coding may not be used, in which case the external codeword vector b becomes equal to the information vector a and K=A. In another embodiment, one or more types of concatenated external coding may be used, in which case K>A.

[0146] Contiguous external coding techniques used in the embodiments of the present disclosure include cyclic redundancy check (CRC) codes, parity check codes, convolution codes, etc., and the specific form or configuration of the coding method is not restricted. In addition, contiguous external coding techniques not described in the present disclosure may also be used.

[0147] As described above, it should be noted that two or more types of encodings may be used as concatenated external encodings. For example, when transmitting uplink control information (UCI) between 12 and 19 bits in a 5G NR uplink pole encoding system, the corresponding UCI information vector a is first encoded with a CRC code and then re-encoded with a PC code implemented using a linear feedback shift register (LFSR). The first concatenated code, the CRC code, generates 6 parity bits, and the second PC code generates 3 parity bits. In this case, the external encoding (110) in FIG. 1 generates a total of 9 parity bits, which can be expressed as K=A+9.

[0148] The generated external codeword vector b (111) is a binary vector (112) and multiplexed, encoder input vector (122) is constructed. The operation of constructing the encoding input vector u based on the external codeword vector b in this way is referred to as rate profiling, sub-channel allocation, etc. (120).

[0149] Here, the length N of the encoding input vector u represents the magnitude of the polar code to be performed later, i.e., the code length, and is determined as a power of 2 when using a binary polar code. That is, for any natural number n, is It is. In general, N > K, and the mother code rate of the polar code is determined as K / N. N can be determined by considering at least one of the following factors: the number of codeword bits to be transmitted through the channel, the modulation order, the data rate, the channel state, the number of MIMO antennas, and the number of layers.

[0150] A binary vector f is called a frozen bit vector and consists of bits inserted to achieve channel polarization when using polar codes. The frozen bit has a fixed value, which is recognized as identical by the transmitter and receiver through pre-determined or pre-configured settings. The value of the frozen bit can be set to either 0 or 1, but is generally set to 0.

[0151] By the above rate profiling (120), vectors b and f are multiplexed to form a binary vector u of length N. That is, K elements in u are determined by b, and the remaining NK elements are filled by f. Specifically, the positions of the K elements in u whose values ​​are determined by b and which are formed are index sets of the same size. (121) is determined by. For example, N=8, K=4, In this case, at Each element of is Each element is mapped to determine the value. Element for The mapping of is performed according to a predefined method. The remaining elements Each is a binary vector It is determined by each element of.

[0152] The process of generating the above u can be implemented without explicitly performing multiplexing. For example, if all freeze bits are set to 0, first initialize all elements of u to 0, and then the set u can be generated by mapping elements of b to locations specified by . This method is merely one example, and rate profiling can also be performed through other methods as long as the same desired result is obtained.

[0153] Additionally, the encoding input vector u generated by rate profiling may include a parity bit. The parity bit may be a parity bit generated in a contiguous external encoding that is placed by the rate profiling process, or it may be generated through operations during the rate profiling process. The parity bit used in the polar code is causally generated and placed in the encoding input vector u to be utilized in the receiver's sequential bit decoding operation. Here, the meaning of the parity bit being causally generated is that the parity bit of the encoding input vector u is generated based on other preceding bits that are earlier (smaller index).

[0154] For example, if the i-th bit u_i in u is the parity bit, it is the set of preceding bits. It is determined by a linear combination of all or some elements. In other words, parity bits is generated by [Mathematical Formula 1].

[0155] [Mathematical Formula 1]

[0156]

[0157] In [Mathematical Formula 1] is parity beat Leading bit for the generation of It is a coefficient for, and all operations are performed on the binary field. Parity bit according to [Equation 1] are leading bits It is determined by the binary sum of the elements of the subset of.

[0158] The reason for generating parity bits causally in this way is that the polar code decoder sequentially estimates the bits of the encoding input vector u in ascending order of index. Once parity bits are generated causally, the decoder can determine the value of the parity bit based on the estimation results of the preceding bits and the parity check formula of [Equation 1], and utilize this during the decoding process. This will be discussed in detail later when explaining the polar code decoder.

[0159] As a result of the rate profiling operation, at least one element of u is determined by the information vector a. Also, as a result of the rate profiling operation, at least one element of u is determined by f and its value is fixed. In addition, as a result of performing the rate profiling operation, some elements of u may be set as parity bits. In summary, u consists of an information bit, a freeze bit, and a parity bit, among which the information bit and the freeze bit are mandatory elements, and the parity bit is an optional element.

[0160] The encoded input vector u (122) generated by rate profiling is encoded (130) with polar codes, and through this process, the encoded output vector x∈ (131) is generated. The encoding process of the polar code above involves a generator matrix in u. It is the process of obtaining x by multiplying.

[0161] Specifically, x is generated by [Equation 2].

[0162] [Mathematical Formula 2]

[0163]

[0164] In [Equation 2], the encoded input vector u and the encoded output vector x are both row vectors of length N.

[0165] In one embodiment, the generating matrix G of [Equation 2] is defined as in [Equation 3].

[0166] [Mathematical Formula 3]

[0167]

[0168] The generating matrix defined by [Equation 3] is in the form presented in [1], where polar signs were first proposed. In the above [Equation 3] It is called the polarization kernel. It is defined as. Superscript for the polarization kernel F The operation refers to n Kronecker powers. The above Kronecker power is , It refers to iterative matrix operations such as... As a result, is a binary matrix of size N×N. Also, is a bit-reversal permutation matrix of size N×N. This relates to an operation that represents each element index of a given vector in binary, inverts it to create a new index, and arranges it. For example, a vector of length 8 go When multiplied by, it becomes a vector with bit-inverted permutations of the indices is generated.

[0169] In another embodiment, the generating matrix G of [Equation 2] is defined as in [Equation 4].

[0170] [Mathematical Formula 4]

[0171]

[0172] The generating matrix G in [Equation 4] is a bit inversion permutation matrix It is defined without, and this type of generation matrix is ​​considered in 5G systems defined by 3GPP, etc.

[0173] Subsequently, unless otherwise noted, the generating matrix of [Equation 4] It is considered that is used. The following description and the content of this disclosure refer to the generating matrix defined in [Equation 3]. Even in a system that takes this into account, it can be applied in the same way by performing a simple additional operation (e.g., applying a bit inversion permutation or its inverse permutation to either the encoded input vector u or the encoded output vector x). Therefore, the application of Equation 3 is not excluded. Whether the generated matrix includes a bit inversion permutation does not affect the operation, characteristics, and effects of the present disclosure.

[0174] For an effective explanation of the present disclosure, a simple example of a polar sign of length 8 is presented as [Example 1] with reference to FIG. 1. First, an information vector of length 3 is given (101). The external encoding (110) process generates a 1-bit parity bit, and an external codeword vector b (111) of length 4 is It is generated. The generated external codeword vector b is mapped to the encoding input vector u (122) by rate profiling (120). In this example, If so, the encoded input vector is It is given as such. According to the above external codeword vector generation relationship, the encoding input vector u is It is the same as, and parity bit silver It is causally generated by u_5. This encoded input vector u is multiplied by the generated matrix G (130) to generate the encoded output vector x (131).

[0175] Figure 2 illustrates that a codeword vector generated through the above encoding process is transmitted through a channel.

[0176] The generated encoded output vector x (131) is transmitted through the binary input channel (210), and the receiver receives the corresponding received symbol vector Receive (211). Here, the alphabet of the receiving symbol It is determined by the channel type and must be a binary field It is not necessary. The transition from x to y mentioned above may include not only the process of transmitting a signal through a physical channel, but also various operations performed by the transmitter and receiver. The processes performed by the transmitter and receiver may include at least one of rate matching and rate dematching, interleaving and deinterleaving, scrambling and descrambling, modulation and demodulation.

[0177] - Code rate adjustment and inverse adjustment refer to the process of adjusting the code length and code rate to be transmitted through a channel by modifying the codeword vector x using methods such as repetition, puncturing, or shortening.

[0178] - Interleaving and reverse interleaving are processes that change the arrangement of bits.

[0179] - Scrambling and reverse scrambling are processes that transform the values ​​of bits according to a given pattern.

[0180] Modulation and demodulation are the processes of converting generated bits into physical signals and restoring them back into received symbols.

[0181] Each of these processes is a concept that can be clearly understood by a person of ordinary knowledge in the art to which this disclosure belongs. The binary input channel (210) can be defined as an end-to-end transition from x to y, including all intermediate processes.

[0182] Figure 3 relates to a process in which a receiver performs decoding of polar codes based on a received symbol vector to obtain an estimated value of an information vector.

[0183] The ultimate goal of the polar code system is for the receiver to accurately estimate the information vector a (101) transmitted by the transmitter without error. In other words, the receiver's estimate Probability that is different from the information vector a transmitted by the transmitter The goal is to minimize [this]. In terms of system configuration, the encoding and decoding operations of polar codes performed by the transmitter and receiver must be designed to achieve this goal.

[0184] The decoder can perform decoding using the log likelihood ratio (LLR) for each transmitted bit. The LLR is a value calculated in logarithmic units as the probability ratio for the value of each bit based on observations received through the channel. For example, the LLR for the i-th bit x_i of a binary vector x is defined as [Equation 5] based on the corresponding observation y_i.

[0185] [Mathematical Formula 5]

[0186]

[0187] In other embodiments, LLR may be defined in a form different from [Equation 5]. For example, in [Equation 5], the probability when the bit value is 0 is considered in the numerator and the probability when the bit value is 1 is considered in the denominator, but this can be set in the opposite way, and in this case, the same result can be obtained by changing only the sign of the LLR defined in [Equation 5]. In addition, the LLR for each transmitted bit can be calculated or obtained in various ways. In particular, when a signal is generated and transmitted using high-order modulation, multiple bits are bundled together into a single symbol for transmission, so the LLR for each bit within the symbol can be calculated through an appropriate procedure.

[0188] The calculation process of LLR is clearly understood by those skilled in the art to which this disclosure pertains. This disclosure may be applied to various forms of received symbol vectors and variations thereof, but is not limited to specific forms.

[0189] LLR vector for binary vector x calculated based on received symbol vector y (211) It is denoted as such. The LLR calculation is deemed to be calculated according to [Equation 5], but the embodiments of the present disclosure are not limited to any specific LLR calculation method or definition.

[0190] According to [Equation 5], if the probability of a bit value of 0 for the target bit is high, the LLR becomes positive, and conversely, it becomes negative. In the operation of a binary-input channel, since a punctured bit contains no information or observation results, the probability for bit values ​​0 and 1 is equal, and accordingly, the LLR becomes 0. In the case of a shortened bit, although the bit was not transmitted, the receiver knows its value, so the LLR can be set to a positive value (bit value 0) or a negative value (bit value 1) with the maximum absolute value. If a bit is transmitted two or more times in a binary-input channel, the LLR for each repeated bit can be calculated, and then soft combining them can be used to calculate the LLR of the target bit. Here, soft combining can be performed by adding each LLR.

[0191] Now, an example of the polar code decoding operation (310) will be described in detail. The polar code decoding operates using the successive-cancellation (SC) method proposed in [1]. Other SC-based decoding methods include SC-list (SCL) decoding, SC-stack (SCS) decoding, and SC-flip (SCF) decoding. SC-based decoding uses an encoding input vector sorted in ascending order of index, i.e., It is characterized by decoding each bit sequentially one by one. Specifically, SC-based sequential decoding is performed by the following procedure.

[0192] 1. Initialize decryption bit index i to 0.

[0193] 2. The i-th bit by sequential operation In the decoding operation of, the estimated value of the preceding bits This is given. When the initial i=0, no estimated value of any bit exists.

[0194] 3. LLR vector Λ for the encoded input vector x calculated based on the received symbol vector y, and the estimated values ​​of the previously decoded bits , and based on probabilities regarding estimates, etc. Calculate the LLR (or an equivalent probability-based metric) for . Here The LLR calculated for is also referred to as a posteriori LLR (AP-LLR) to distinguish it from the LLR for x.

[0195] 4 Based on post-LLR Estimated value of Obtains. At this time, the bit The method of determining the estimated value varies depending on whether it is an information bit, a freeze bit, or a parity bit.

[0196] A. If is an information bit, the estimated value based on the calculated posterior LLR It can be determined. Based on the definition of [Equation 5], if the posterior LLR is greater than 0, it can be estimated as bit 0, and if it is less than 0, it can be estimated as bit 1.

[0197] B. If it is a frozen bit, it is a preset fixed value regardless of the calculated LLR. Determines.

[0198] C. If is a parity bit, the estimated value of the preceding bits based on the parity check formula defined in the code structure As a linear combination of It can be determined. Another method is to obtain both an LLR-based estimate and a parity check-based estimate and compare the two to determine the validity of the decoding result. How the parity bit is handled can be determined in advance by the decoder settings or can be changed depending on the situation.

[0199] Increment the decode bit index i by 1, and repeat steps 2 and 3 above. Through this sequential decoding and estimation, the next bit to the decoding of Estimated value of This is reflected using a successive cancellation method. In this process, the decode bit index i becomes N-1, and the last bit It continues until decoding and estimation for is completed.

[0200] As described above, decoding for each bit is performed based on the bit value estimated from the previous decoding. For example, bit The decoding of is an estimate of the preceding bits and probability information or equivalent metrics regarding this are used. Here, each partial bit vector or sequence This is referred to as a list or path. Additionally, the probability information obtained while performing decoding for each path, or a metric equivalent to such probability information, is called a path metric (PM). PM is defined as the probability of the path's estimation and its equivalent value, and can be calculated in various ways. For example, PM can be defined as the logarithm of the reciprocal of the path's estimation probability; in this case, it can be determined that the smaller the PM, the higher the probability that the path's estimation is correct, and the larger the PM, the lower the probability that the path's estimation is correct.

[0201] SC decoding is a method that selects only one path during the sequential decoding process. The sequential bit decoding process can be interpreted as performing a search from the root in a binary decision tree, and SC decoding can be viewed as performing a depth-first search (DFS) in this binary decision tree.

[0202] On the other hand, SCL decoding is a method that considers multiple candidates by maintaining a predetermined list size of L paths when decoding each bit. If the list size L is set to 1, it will perform the same operation as SC decoding, although there may be differences in the details of the operation.

[0203] The SCL decoder is a bit Performing sequential decoding up to L paths It has. Here, l is an index representing a path and has values ​​from 0 to L-1. In the case of a sequential decoding initial with a small bit index to be decoded, the number of valid paths may be less than L. In this case, the decoder may proceed to the next process only for valid paths, or perform the process for all paths and then ignore the decoding results for invalid paths.

[0204] SCL decoder After completing the decoding for, the next bit is Let us consider a situation where decoding and estimation are performed sequentially. For each path index l and Calculate the path metric PM for. From L paths Since two paths are derived for , the total number of candidate paths considered at this stage is 2L. The SCL decoder selects L paths from these 2L candidate paths and discards the rest. The number of paths considered after decoding and estimating each bit is limited to L, and this limitation allows decoding to be processed within the given limited physical resources (memory, computing device, etc.) and computing power.

[0205] The process of selecting the above path is It can vary depending on whether it is an information bit, a freeze bit, or a parity bit. For example, If is an information bit, L paths can be selected based on the PM updated for that estimated value. On the other hand, If it is a frozen bit, the estimated value is a fixed value determined in advance. By determining, L paths can be selected. Finally If is the parity bit, the estimation of the preceding bits Estimated value based on the given parity-check equation based on You can determine L paths or determine the validity of each of the L paths.

[0206] Using parity bits generated by concatenated external codes during or after SCL decoding can improve validity determination for each path.

[0207] Among various external concatenation codes, cyclic redundancy check (CRC) codes are generally used to determine the validity of the final paths obtained after SCL decoding is finished. For example, in a 5G NR polar code system, CRC codes of various lengths and forms are used as external concatenation codes depending on the situation. Generally, parity bits generated by the CRC code are placed consecutively after the external codeword vector b (111) shown in FIG. 1, but in some situations, the parity bits may be distributed. This is not mandatory, and embodiments of the present disclosure are not restricted to the placement of parity bits of a specific CRC code.

[0208] For example, after the final decoding, the SCL decoder, L estimated candidates for Each estimation candidate includes the codeword of the contiguous CRC code, so the validity of each estimation candidate can be determined by performing decoding of the CRC code. The order of estimation candidates to perform decoding of the CRC code can be determined based on PM. The above CRC code is a contiguous outer code that extends the minimum distance of the entire codeword and improves the performance of ML-like decoding, such as maximum likelihood (ML) decoding or SCL decoding.

[0209] Among various peripheral concatenation codes, the parity-check code (PC) is generally used to guide each path to a valid path during SCL decoding. For example, in 5G NR uplink pole coding systems, a PC code that generates a 3-bit parity bit is used when processing information vectors of 12 to 19 bits. Unlike the aforementioned CRC code, the parity bits of the PC code are generally used individually.

[0210] For example, let us consider the case where an SCL decoder performs decoding on the parity bit placed at the i-th position. In this case, the SCL decoder L paths for It has. For path l, the estimate It can be determined as in [Equation 6] based on the corresponding parity check formula [Equation 1].

[0211] [Mathematical Formula 6]

[0212]

[0213] generated by [Mathematical Formula 6] It is valid in terms of the PC code used. Therefore, the use of the parity bit of this PC code is the i-th bit Ensure that a path including a valid estimate is selected for this. For example, based on LLR, PM, etc. In that it prevents errors that may occur when estimating, the estimation of parity bits such as [Equation 6] can be viewed as error correction.

[0214] FIG. 4 illustrates an example of a graph corresponding to polar symbols in a communication system or broadcasting system according to embodiments of the present disclosure.

[0215] Referring to FIG. 4, FIG. 4 shows a polar sign generation matrix of size N of 8. An example of a binary graph (410) for is illustrated. The binary graph consists of variable nodes (431) represented by circles, check nodes (432) represented by squares, and edges (433) connecting these nodes. Variable nodes represent individual bits, and check nodes represent linear constraints on the bits of connected neighboring variable nodes. Specifically, check nodes indicate that the modulo-2 sum of all bits corresponding to neighboring variable nodes is 0.

[0216] In a polarized bipartite graph, the connection between variable nodes and check nodes is determined by the configuration of the generating matrix G. As shown in [Equation 3] and [Equation 4], since the generating matrix G is generated by the Kronecker power of the polarization kernel F, the entire bipartite graph (410) has a form in which the graph of the polarization kernel (420) is connected iteratively and regularly. Specifically, the polarization kernel (420) is a linear transformation for input size 2 and output size 2 It describes the relationship and shows a Z-shaped form. Since the generating matrix G is made of a continuous Kronecker power of F, the configuration of the polarization kernel (420) of the entire binary graph (410) consists of a regular arrangement of Z-shaped graphs as shown in FIG. 4.

[0217] The graph of the length N polar code configured as described above consists of n+1 stages. When using the symbol t as the stage index of the graph, the stage index for the leftmost variable nodes of the graph is denoted as t=0, and the stage index for the rightmost variable nodes of the graph is denoted as t=n. Among these, the N variable nodes (440) of the leftmost stage (t=0) correspond to the encoded input bit vector u, and the variable nodes (450) of the rightmost stage (t=n) correspond to the encoded output bit vector x.

[0218] The encoding process of polar codes by multiplication of the generating matrix G shown in [Equation 3] can be understood on the graph of FIG. 4. On the graph of FIG. 4, the encoding input bit vector u is assigned to N variable nodes (440) at the leftmost step (t=0). Then, the bit values ​​of the variable nodes are determined to satisfy the relationship of the check nodes in ascending order of the step index t (from left to right). In other words, the encoding process can be understood as an operation of updating bit values ​​according to the relationship between the variable nodes and the check nodes sequentially from the left to the right step of the graph shown in FIG. 4. Encoding by multiplication of the generating matrix of [Equation 2] can be implemented and realized in any way, and the method using the graph also produces the same encoding result.

[0219] The SC-based decoding of polar codes can also be understood as a belief-propagation operation on the graph of FIG. 3. As the first step of decoding, the LLR given for the codeword bit vector x (received vector y in reception) is mapped to or input into N variable nodes (450) of the rightmost step (t=n) of the graph. Then, through a series of operations, the posterior LLR (a-posteriori LLR, AP-LLR) of the encoding input bit vector u corresponding to the variable nodes of the leftmost step (t=0) of the graph is calculated one by one sequentially. The AP-LLR of each bit is obtained by sequentially calculating and updating the LLR of the variable nodes for each step from the right side of the graph to the left (i.e., in descending order of the step index). That is, the initial LLR is given at the t=n step, and from this, the LLR values ​​for some variable nodes of each step are calculated in the order t=n-1, n-2, ... Through this process, the AP-LLR value for the variable node at step t=0 is calculated.

[0220] The detailed LLR calculation process on the polar sign graph is as follows. As described above, the entire bipartite graph is composed of a Z-shaped polarization kernel (420) of the polarization kernel as a basic element, and all LLR (log-likelihood ratio) values ​​are calculated on this basic element.

[0221] FIG. 5 illustrates an element process for performing LLR (log-likelihood ratio) calculation and sequential removal in a polar code decoding method and device of a communication system or broadcasting system according to an embodiment of the present disclosure.

[0222] Referring to Fig. 5, the process of calculating LLR on the above primitive is illustrated. In this Z-shaped primitive graph, the bit vectors corresponding to the two left variable nodes , the bit vectors corresponding to the two variable nodes on the right It is decided to write it as follows. The relationship between a and b due to the polarization kernel F can be expressed mathematically as follows.

[0223] [Mathematical Formula 7]

[0224]

[0225] bit The LLR values ​​corresponding to each Let's write it as follows. In the decoding for each primitive, the nodes corresponding to the two variables on the right is given, and by the decoding process One of the LLR values ​​is calculated. According to the sequential decoding method of the polar codes described above, After the LLR value of is calculated and estimated, based on this The LLR value of is calculated and estimated. First It can be calculated using the function f(510) of Fig. 5.

[0226] [Mathematical Formula 8]

[0227]

[0228] [Equation 8] is a method for accurately calculating the LLR value based on the relationship between bits, and for simpler calculation and implementation, it can be obtained by approximating it with the function f' as shown in the following equation.

[0229] [Mathematical Formula 9]

[0230]

[0231] The function in the above equation is a function that returns the sign of the input value, outputting 1 if the input value is greater than 0 and -1 if it is less than 0.

[0232] bits according to the decoding process estimation of If this is obtained or becomes available, through the function g(420) of FIG. 4 Calculate.

[0233] [Mathematical Formula 10]

[0234]

[0235] As described above, in SC-based decoding methods and devices, bit decoding and estimation are performed sequentially according to the bit index. Therefore, Decoding and estimation regarding must It is performed after checking or estimating the value of.

[0236] The calculation process of LLR described using Figure 5 above pertains to the basic components of the polarization kernel, which may be connected to other variable nodes and check nodes as part of the overall graph. If the basic components are not located at the leftmost step (t=0), the calculated above class It is passed to other Z-shaped fundamentals connected to the left (i.e., the side where step index t is 1 smaller). The corresponding steps are then performed identically on the passed fundamental components. In this way, decoding proceeds from step t=n in descending order of step indices (i.e., in order where t becomes smaller). When the LLR value of the encoded input bit of the variable node at the far left of the graph (step t=0) is obtained, the bit value is estimated based on the said LLR value. If the bit is a fixed bit, a pre-determined value (e.g., 0) can be assigned regardless of the calculated LLR value. If the bit is a parity bit, the value can be determined based on the previously estimated or determined bit. If the bit is an information bit, the hard-decision result of the updated LLR value can be assigned to that bit. Encoded Input Bit The finally calculated AP-LLR for If written as such, the decoder estimates based on this value Determines. For example, if LLR is defined so that positive numbers correspond to bit 0 and negative numbers correspond to bit 1, it is estimated as shown in the following mathematical formula. is determined.

[0237] [Mathematical Formula 11]

[0238]

[0239] In the case of floating-point operations, if the LLR value is 0, the bit value is determined by a predetermined rule. The predetermined rule method may be random determination.

[0240] The bit estimated as a result of decoding is passed from left to right along the graph to the variable nodes within the range available at the current decoding stage, and is used for the LLR calculation of other variable nodes as in the process of [Equation 10]. This process can be understood as a sequential elimination operation that reflects and removes the results decoded so far from the received vector or LLR to be decoded, thereby facilitating the decoding of the next bit. This sequential elimination process can also be understood in terms of Z-shaped basic components, such as the functions g (520) and SC (530) in FIG. 4. As decoding proceeds estimation of Once this is obtained, it is reflected in the graph as with the previously examined function g(520) and through [Equation 10] Enables calculation. Decoding proceeds estimation of If obtained, this is reflected in the graph as in SC(530) estimator of It enables the calculation of. Specifically, depending on the relationship of the polarization kernel It is determined as such. When the bit corresponding to the right variable node of the basic component is estimated in this way, this value is then passed to other Z-shaped basic components connected to the right side of the graph (i.e., the side where the step index t is 1 greater). According to the above decoding procedure and process, the bits of the encoded input bit vector u are decoded one by one in ascending order of index. The process of sequentially estimating and determining bits in the above SC-based decoding process can be understood based on a binary decision tree.

[0241] Below, we will explain the rate profiling and sub-channel allocation (120) of FIG. 1 in more detail.

[0242] The SC decoder for polar codes uses the encoded input bit vector u Decode sequentially one by one in ascending order of index to estimate the value It obtains. That is, the SC decoder Decoding is performed on the bits in sequence. Bits that have already been decoded and estimated can be removed from the received vector y or equivalent decoding target and used to facilitate the decoding of the next bit. Because of this characteristic, the decoding operation may be referred to as successive cancellation (SC).

[0243] Vector channel by the operation of the above SC decoding is channel-splitting into binary-input channels for each bit of u. The channel-splitting binary-input channels may be referred to as sub-channels, split channels, polarized channels, etc. Hereinafter, the term "sub-channel" is used in this disclosure. In SC decoding, the decoding for the i-th bit u_i is performed using the observation result y of the given channel and the previously estimated It is performed based on. Under the premise that the previously estimated bits are accurate (i.e., The side channel for ), u_i is It is written as such, and in [1] it is defined as [Equation 12].

[0244] [Mathematical Formula 12]

[0245]

[0246] The above is the probability of y occurring given u It means that through the channel combining and separating processes described above, the subchannel for u_i This becomes polarized. That is, a set of side channels Some of these become excellent binary-input subchannels with a channel capacity close to 1, while the rest become poor binary-input subchannels with a channel capacity close to 0. The channel capacity of subchannel u_i is determined by index i, and in designing polar codes, the bit-by-bit subchannel capacity is deterministic. Therefore, the most important operating principle of a polar code system is to allocate information bits to indices in u that have high channel capacity, and to fix the values ​​of the remaining indices without allocating information bits. Bits to which information is not allocated are referred to as frozen bits (or fixed bits), and their values ​​are usually fixed at 0.

[0247] The encoding input vector u for polar codes can be composed of frozen bits (or fixed bits), parity bits, and information bits. These bits may be referred to by various other names; for instance, the parity bit is often called a dynamic frozen bit. Additionally, bits other than the fixed bits are sometimes called unfrozen bits. An information bit is a bit that carries information and can have a bit value of either 0 or 1, and in polar codes, information bits can be allocated to subchannels with high channel capacity. A fixed bit is a bit whose value is fixed and can be allocated to subchannels with low channel capacity. The value of a fixed bit is usually determined to be 0, but it is not strictly limited to this (i.e., the value of the fixed bit can also be determined to be 1). These fixed bits are used for channel polarization and can be interpreted as improving the channel capacity of other subchannels in exchange for sacrificing information by fixing the bits. In polar codes, the parity bit is similar to a fixed bit in that it does not carry information, but its value is not fixed to a specific value and is causally generated based on preceding bits (bits with smaller indices). The causally generated parity bit is used to improve error correction performance or error detection performance by using or checking the decoding result of the previously decoded and estimated information bit in the SC-based decoding method and device described below. According to one embodiment, the parity bit may be a cyclic redundancy check (CRC) bit. Additionally, according to one embodiment, the parity bit may further include a parity check (PC) bit defined by 3GPP.

[0248] Below, the encoding process will be explained in more detail based on FIGS. 6a to 6d. FIG. 6a illustrates an example of a polar encoding method without rate matching when the length of the parent code N=16, the number of information word bits (K) is 5, and the number of CRC bits is 3. The bit sequence following the outer code encoding in FIG. 1 is is. At this time, the bit sequence by the subchannel allocation (or subchannel mapping) of Fig. 1 above is a polar sign input bit sequence Based on the given polar code sequence [15, 14, 13, 11, 7, 12, 10, 9, 6, 5, 3, 8, 4, 2, 1, 0], it is mapped as follows. Since the number of input bits is 8, if 7 indices are selected in order of high reliability from the polar code sequence, they are mapped or assigned to polar input bits with indices [15, 14, 13, 11, 7, 12, 10, 9]. Frozen bits are input to the polar code input bit sequence u for which the outer code encoding output bit sequence value does not correspond. This process is also called rate-profiling. The polar code input bit sequence u is polar encoded and transmitted based on Equation 2. The polar encoding is also referred to as polar code transform. In addition, although not shown in FIG. 6a, a predetermined encoding example prior to polar code conversion can be coded by a convolution code. This is intended to map predetermined parity bits based on the input bit sequence rather than inputting a '0' value to the frozen bits.

[0249] In FIG. 6a, the polar code sequence is a sequence in which the subchannel indices of u are sorted in order of channel capacity, representing the order of indices where information word bits are mapped to the u vector. In the above embodiment, the polar code sequence is [15, 14, 13, 11, 7, 12, 10, 9, 6, 5, 3, 8, 4, 2, 1, 0], and since the number of one bits of information word bits (including CRC bits) input to the polar encoder is 7, the information word bits are mapped to the bits having indices corresponding to the first 7 numbers in the polar code sequence. According to FIG. 6a The information bits are mapped to the polar code input bits. Frozen bits are input to the polar code input bit sequence u, which does not correspond to the outer code encoding output bit sequence value. This process is also called rate-profiling. The polar code input bit sequence u is polar encoded and transmitted based on Equation 2. This polar encoding is also referred to as polar code transformation. Additionally, although not shown in FIG. 6a, it can be coded by a convolution code as a specific encoding example prior to polar code transformation. This is intended to map specific parity bits based on the input bit sequence rather than inputting a '0' value to the frozen bits.

[0250] The order of the polar code sequence in the above embodiment was in order of high channel capacity (or reliability), but it may be expressed in order of low channel capacity (or reliability). When the polar code sequence is expressed in order of low channel capacity, information words are mapped starting from the indices excluding the number of bits to which the frozen bit is mapped. Furthermore, the order in which the information word bits are mapped to the polar code input bits may vary, and the index of the polar code input bit selected according to the number of information word bits is determined by the polar code sequence.

[0251] For example, in FIG. 6b, since the polar code sequence is identical, the positions where the information bits are mapped (or the indices of the polar code input bits) are identical, but it is shown that the information bits can be mapped to the polar code input bits in a different order. FIG. 6b is a diagram illustrating another example of a polar encoding method when rate matching is not used, where the length of the parent code N=16, the number of information bits (K) is 5, and the number of CRC bits is 3. According to FIG. 6b, the information bits are mapped to the polar code input bits as follows. .

[0252] As shown in FIGS. 6a and 6b, the size N of the mother codeword of the polar code, the number of information bits K, the number of CRC bits, and the polar code sequence are identical, so the positions of the bits where the information bits (including CRC bits) are mapped are identical. However, it is illustrated that the mapping order may vary according to a predetermined rule. The said predetermined rule uses a method pre-set in the transmitter and receiver. The said polar code sequence refers to the priority in which information bits are assigned among the polar code input bits, and the mapping index order can be defined in various ways.

[0253] Figures 6c and 6d below illustrate the method of mapping information bits (including CRC) when considering piercing and shortening. In the case of piercing and shortening, the polar code input bits corresponding to the piercing bit and the shortening bit are set as frozen bits. Figure 6c is a diagram illustrating an example of the method of mapping information bits (including CRC) when considering piercing and shortening. As shown in Figure 6c, the polar code output bits middle If the bits are punched, the corresponding polar sign input bits A zero (“0”) bit is input. The above It is not perforated and transmitted. As in this example, the polar code input bits, which are to be input as information words based on the polar code sequence, are input as “0” bits by perforation. Frozen bits are input to the polar code input bit sequence u, which does not correspond to the outer code encoding output bit sequence value. This process is also called rate-profiling. The polar code input bit sequence u is polar encoded and transmitted based on Equation 2. The polar encoding is also referred to as polar code transformation. Additionally, although not shown in Fig. 6c, it can be coded by a convolution code as a specific encoding example prior to polar code transformation. This is intended to map specific parity bits based on the input bit sequence rather than inputting a '0' value to the frozen bits.

[0254] FIG. 6d illustrates another example of how information bits (including CRC) are mapped when considering perforation and shortening. That is, as shown in FIG. 6d, the polar sign output bits middle If the bits are short, the corresponding polar sign input bits 5 is input with a zero “0” bit, which is the polar sign output bits. Make this zero “0”. The above It is not shortened and transmitted. As in this example, the polar code input bits, which are to be input as information words based on the polar code sequence, are input as “0” bits through puncturing or shortening. Frozen bits are input to the polar code input bit sequence u, which does not correspond to the outer code encoding output bit sequence value. This process is also called rate-profiling. The polar code input bit sequence u is polar encoded and transmitted based on Equation 2. The polar encoding is also referred to as polar code transformation. Additionally, although not shown in Fig. 6d, it can be coded by a convolution code as a specific encoding example prior to polar code transformation. This is intended to map specific parity bits based on the input bit sequence rather than inputting a value of '0' to the frozen bits.

[0255] Below, we will first define the side-channel index and explain in more detail the method of taking short lengths in order as needed. The PC bit is determined from the above index by the following rule. least reliable bit indices Among the most reliable bit indices, minimum row weight highest reliability and the minimum row weight in .

[0256]

[0257]

[0258]

[0259] In SCL decoding, the list size L is the most important parameter determining decoding performance and complexity. A larger list size L allows for decoding to be performed by examining many possibilities; consequently, decoding performance improves, but complexity increases. As an extreme example, in a polar code with code dimension K, the number of possible codewords is This is because in SCL decoding, the list size L is the number of candidate codewords considered during the sequential decoding process, so if the list size L can be set to 2^K, this SCL decoding will operate identically to the optimal ML decoding.

[0260] The complexity of SCL decoding of list size L for processing polar codes of parent code size N is generally determined by [Equation 13].

[0261] [Mathematical Formula 13]

[0262]

[0263] In [Equation 13] is a big-O function widely used to represent approximate complexity. As shown in [Equation 13], the complexity of SCL decoding is determined by the size of the parent code N and the list size L. The size of the parent code N is determined by the given polar code and cannot be changed arbitrarily, whereas the list size L is selectable from a system perspective. Therefore, to operate the decoder effectively, it is important to determine an appropriate list size L that fits the given requirements and constraints.

[0264] Code dimension K is the number of information bits to be encoded using polar codes. In 5G NR, polar codes are used to transmit control information, and control information is typically shorter than data information. Accordingly, the maximum code dimension K supported by the 5G NR polar code system is 140 bits for the downlink (DL) and 1706 bits for the uplink (UL). Since the maximum code dimension K is not large, the 5G NR polar code system was designed with the following two constraints.

[0265] - The maximum parent code size N is constrained to 1024.

[0266] - The maximum number of segments is limited to 2.

[0267] On the other hand, the number of bits in control information is expected to increase in next-generation communication systems such as 6G. For instance, the Precoding Matrix Indicator (PMI) within uplink control information (UCI) is steadily increasing due to factors such as the increase in the number of antennas used in MIMO systems and increased bandwidth. For instance, while the PMI was around 100 bits in 4G, it increased to over 600 bits in 5G, and is expected to grow to thousands of bits in 6G. Furthermore, there is a possibility that polar codes will be used to transmit data information beyond just control information. In this case, the assumed range for the code dimension K could increase from the current hundreds of bits to thousands or even tens of thousands of bits. Based on these expectations, polar codes in next-generation communication systems like 6G create the possibility that parent codes of a larger size N will be defined.

[0268] To improve the performance of short polar codes, methods to reduce the number of minimum weight codewords are being studied as a way to enhance the performance of ML decoding. It is known that the performance of SCL decoding for short lengths approaches that of ML. A minimum weight codeword refers to a codeword that has the smallest Hamming weight (the number of 1s included in a binary codeword) in a given code. In relation to SNR, ML decoding performance can be approximated by the number of minimum weight codewords, and ML decoding performance can be improved as the number of minimum weight codewords decreases.

[0269] Techniques for concatenating an outer code in front of a polar code are being discussed as a method to reduce the number of minimum weight codewords. For example, parity check polar codes and CRC polar codes can be understood as examples of such outer code concatenation techniques. Meanwhile, the Deep Polar Code, proposed as one of the outer code concatenation methods, exhibits superior performance compared to polar codes concatenated with CRC.

[0270] One embodiment of the present disclosure proposes a method for improving the performance of a deep polar code. One embodiment of the present disclosure proposes a method for setting parameters for designing a deep polar code. One embodiment of the present disclosure proposes that when setting a connection set for external encoding of a deep polar code, if a subchannel carrying information bits is frozen in the inner layer, an affine subspace (AS) capable of containing a minimum weight codeword cannot be formed. An encoding method based on this principle according to one embodiment of the present disclosure is proposed.

[0271] In the description of an embodiment of the present disclosure, commonly used mathematical symbols are utilized. These symbols are expressions that are easily understood by a person skilled in the art to which the present disclosure pertains. In the following description of an embodiment of the present disclosure, the following mathematical expressions may be used.

[0272] - s <t 를 만족하는 두 음이 아닌 정수 For this, [s,t] represents the set of consecutive integers from s to t, and is defined as [s,t]={s,s+1,… ,t-1,t}.

[0273] - Binary vector Regarding, <x>represents the binary support of vector x. am.

[0274] - Binary vector For this, wt(x) represents the Hamming weight of vector x. That is, 0 ≤ wt(x) ≤ 1.

[0275] - When, an arbitrary integer value For, the corresponding binary vector of length n It is written as, am.

[0276] As described above, the polar code is an error correction code proposed by E. Arikan and is the first error correction code proven to achieve channel capacity, which is the limit of data transmission performance in binary discrete memoryless channels (B-DMC), while having low coding and decoding complexity that is feasible to implement [1]. The polar code is a channel code that achieves channel capacity in a simple and effective manner by utilizing a phenomenon called channel polarization. In the process of transmitting multiple bits through independent bit channels, if coding using a structured generator matrix and successive cancellation (SC) decoding are used, the channel for each bit is transformed into a virtual polarized synthesized channel. In this process, some synthesized channels become excellent channels with a channel capacity close to 1, while the remaining synthesized channels become poor channels with a minimum channel capacity close to 0. In this case, the total sum of the channel capacities of the composite channels remains the same before and after the change. As the code length increases, channel polarization is maximized, so the superior channel has a channel capacity of 1, and the inferior channel has a channel capacity of 0. Therefore, theoretically, the transmitter can easily and effectively achieve the channel capacity for a given channel by transmitting the information bit to be sent to the superior channel and allocating a frozen bit to the inferior channel. In this process, the receiver knows the location and value of the frozen bit.

[0277] Decoding methods based on polar codes and successive cancellation (SC) provide superior error correction performance even with short code lengths compared to other channel codes. SC decoding methods for polar codes are easily modified and extended to near-ML or ML-like decoding methods such as SCL (SC-list) decoding, SCS (SC-stack) decoding, and SC-flip (SCF) decoding. These improved decoding algorithms achieve superior error correction performance. Due to these advantages, polar codes are used in the 3GPP New Radio (NR) standard for 5th generation (5G) mobile communication when transmitting short-length control information.

[0278] FIG. 7 is a diagram illustrating an example of a polar symbol according to an embodiment of the present disclosure. A polar symbol can be defined algebraically as follows. Information set The polar sign C(I) defined by (N=2^n,K) is a vector space (space) As a K-dimensional vector subspace of which forms a basis Indexed by It can be defined as the set of rows. Polar matrix It can be defined recursively as follows.

[0279]

[0280] Here, That is, when the sign magnitude is N and the size of the information vector to be encoded, which may include external codeword bits, is K, the polar code is a finite set of indices of the same size as the information vector. Polar sign generation matrix indexed by spanned by the row vectors It can be interpreted as a K-dimensional vector subspace of. The above index set polar signs having It can be written as.

[0281] Figure 7 shows an 8×8 matrix that is recursively defined / generated in this way. exemplifies. is an 8×8 binary matrix, and each row can be a basis vector that can be used for codeword generation. three rows of An information set It may be a row corresponding to.

[0282] In this case, polar sign It can be defined as follows.

[0283]

[0284] Is It can be a combination of row vectors indexed by. That is, polar sign Is It can be a 3-dimensional vector subspace spanned by.

[0285] Deep Polar Code

[0286] To improve error correction performance in short lengths, deep polar codes were proposed as one of the external coding concatenation schemes for polar codes [3]. The length of the codeword generated by the encoder of a deep polar code is denoted as N, and the length of the information bits being encoded is denoted as K. In this case, K may include bits generated through additional external coding, such as CRC bits. A (N,K) deep polar code composed of two or more L layers consists of L 4-tuples It can be defined as a dog. The l-th tuple Each element of can have the following meanings and characteristics:

[0287] - : Represents the length of the intermediate codeword generated in the l-th layer. At this time It satisfies the relationship equation. Also Therefore, both notations should be used interchangeably.

[0288] - : Represents the number of information bits encoded in the lth layer. Satisfies the constraints of.

[0289] - : Represents the set of indices of the sidechannels where the information bits of the lth layer are inserted, and This is called an information index set.

[0290] - : Represents a set of indices of side channels into which intermediate codeword bits generated in the l-1th layer are inserted. Igo is This is called a set of linked indices.

[0291] In the definition of the deep polar code above, the index set, although not included in the tuples of each layer A set of indices of information bits in and the set of indices where the intermediate codeword bits are mapped Additionally, define a subset of indices excluding as a frozen set, and It can be written as. That is, am.

[0292] In summary, (N,K) L-layer (L≥2) deep polar code It can be defined by the following set of parameters.

[0293]

[0294]

[0295] Encoding of deep polar codes

[0296] FIG. 8 is a diagram illustrating an example of a two-layer deep polar code according to an embodiment of the present disclosure. Referring to FIG. 8, among the input data d=[1 0 0 1],

[0010] is used as an information bit in the first layer, an index set It is mapped to the position corresponding to it. A freeze bit is inserted at the corresponding position. There are no connection bits in the first layer ( Input vector in the first layer [1 0 0 0] is Output vector according to It is converted to [1 1 1 1]. Output vector [1 1 1 1] can be mapped to a connection bit in the second layer ( Among the input data d=[1 0 0 1],

[0001] is used as an information bit in the index set of the second layer. It is mapped to the position corresponding to {6,7}. A freeze bit is inserted at the position corresponding to it. Input vector in the second layer silver Output vector according to It is converted into. For more details, refer to the description of the L-layer deep polar code below.

[0297] FIG. 9 is a diagram illustrating an example of an L-layer Deep Polar Code according to an embodiment of the present disclosure. Referring to FIG. 9, the input vector is L subvectors by a bit splitter It can be divided, and the divided subvectors as information bits at each layer It can be mapped / inputted to the position corresponding to it. Number of information bits at each layer satisfies the following constraints. And also am.

[0298] If you refer to the first layer, It is mapped to the position corresponding to this information bit, and the remaining positions are (Freeze bit) is mapped. Configured in this way. silver Depending on It is converted into, and the output of the first layer The connection bit in the second layer It can be used as. Referring to the second layer, It is mapped to a position corresponding to this information bit, and The connection bit is mapped, and at the remaining positions, (Freeze bit) is mapped. Configured in this way. silver Depending on It is converted into, and the output of the second layer The connection bit in the third layer It can be used as. Encoded sequentially in this way, at the last layer L Consisting of this It can be converted to x by.... This is explained in more detail below.

[0299] The following describes the encoding of (N,K) deep polar codes composed of two or more L layers. Vector is an information vector that the transmitter intends to send to the receiver, and the dimension K of the vector is the number of information bits. Vector d may include external codeword bits generated due to additional external coding applied prior to the encoding of the deep polar code. The information vector d consists of L sub-vectors The contiguous of ) It can also be expressed as, and the l-th subvector is a negative information vector encoded in the l-th layer.

[0300] Subvector in the first layer is a binary vector and multiplexed, the first layer encoding input vector Constructs. In this case, the sub-vector is a vector index set in It is mapped to the location corresponding to. That is, is a binary vector This is referred to as a freeze bit vector and consists of bits inserted to achieve channel polarization when undergoing polar coding. The freeze bits have a fixed value, which is recognized as identical by the transmitter and receiver through pre-determined or pre-configured. The value of the freeze bits can be set to any value between 0 and 1, but is generally set to 0. For ease of explanation, it is assumed below that all freeze bits have a value of 0, but the disclosures of the present invention are not limited thereto. The operation of constructing an coding input vector based on such a sub-information vector (or a sub-external codeword vector if additional external coding is applied) is referred to as sub-channel allocation or rate profiling.

[0301] The first layer encoding input vector generated by the above rate profiling is encoded similarly to polar coding, and through this process, the intermediate codeword, which is the Layer 1 encoding output vector, is is generated. The above encoding process polar sign generator matrix The transpose of Multiply by It is the process of obtaining.

[0302] Specifically is generated by [Mathematical Formula 14].

[0303] [Mathematical Formula 14]

[0304]

[0305] Input vector in [Equation 14] and output vector are all lengths It is the row vector.

[0306] In one embodiment, the generating matrix of [Equation 14] is defined as in [Equation 15].

[0307] [Mathematical Formula 15]

[0308]

[0309] In the above [Equation 15] It is called the polarization kernel or Arikan kernel. It is defined as. Polarization kernel superscript for The operation refers to n Kronecker powers. The above Kronecker power is It refers to recursive matrix operations such as... At this time am.

[0310] The above first layer output vector It is passed to the second layer. The decoder is the second layer information subvector and layer 2 freezing vector And vector By multiplexing, the Layer 2 input vector through rate profiling Constructs. Information sub-vector is a set Mapped to the corresponding location, and the intermediate codeword received from the first layer is a set It is mapped to the location of. That is, Igo is, and at this time It satisfies. Layer 2 input vector The bits of the freeze vector are mapped to the remaining indices of am.

[0311] The second layer encoding input vector generated by the above second layer rate profiling The transposed polar sign generating matrix Multiplying by the intermediate codeword, which is the Layer 2 output vector You can obtain. Specifically is generated by [Equation 16] and passed to the next layer.

[0312] [Mathematical Formula 16]

[0313]

[0314] The deep polar code encoder repeats the above rate profiling, intermediate coding using the transpose of the polar code generation matrix, and intermediate codeword delivery layer by layer up to the L-1 layer. As an example, 2≤l <L 인 임의의 정수 값 l에 대하여, 제l계층에서 부호화기는 다음의 일련의 동작들을 수행할 수 있다.

[0315] The deep polar code encoder uses the Layer 1-1 output vector received from the previous layer and the partial information vector encoded at that layer And freezing vector Multiplexing the input vector Constitutes. At this time, u And the first layer frozen index set is It is defined as, It satisfies the layer 1 encoding input vector is the polar sign generation matrix Layer 1 encoded output vector using the transpose of forms.

[0316] The output vector of the previous layer passed to the last L layer It is called. The deep polar code encoder is the previous output vector , my L-layer information vector And freezing vector Layer L encoding input vector rate-profiled through multiplexing It constitutes. At this time, as mentioned in the definition of the above dip polar symbol, is. Unlike the previous layers, the encoder uses the conventional polar code generation matrix instead of the transpose to generate the output vector. That is, the codeword of the deep polar code finally obtained is a rate-profiled vector polar sign generation matrix It is obtained by multiplying. That is, is. Or, for the simplification of notation It can also be expressed as.

[0317] The L-layer deep polar code described above can be understood as a concatenation of L linear filters. That is, the L-layer deep polar code can be understood as a linear transformation. In other words, the (N,K) L-layer (L≥2) deep polar code D is a linear code (Proposition 1) [4].

[0318] Figure 10 shows the error probability for ML (Maximum Likelihood) decoding. This is a graph showing an example of performance. The horizontal axis represents the noise intensity E relative to the symbol energy. [dB], vertical axis is error probability It represents.

[0319]

[0320] - : Minimum Hamming distance

[0321] - : Number of codewords with minimum Hamming distance

[0322] - : Number of codewords with twice the minimum Hamming distance

[0323] - : Q-function (decreases as d increases)

[0324] Referring to the formula, it can be seen that the error probability depends heavily on the distance distribution of the nearest codewords. Each curve in the graph is different class Showing the results for the combination of, It can be seen that the smaller this is, the lower the error probability. Meanwhile, arbitrary linear sign Regarding this, the relationship between the minimum Hamming distance and the minimum Hamming weight may be as follows.

[0325]

[0326] Minimum Hamming distance are two different codewords Hemming distance between livers It is defined as the smallest value among them. Due to linearity, the binary sum of two codewords becomes a different codeword, so It can be expressed as. Therefore Therefore, the problem of finding the minimum distance is equivalent to finding the smallest Hamming weight among non-zero (0) vector codewords, and the smallest Hamming weight of codewords excluding zero vectors is the minimum Hamming weight. It is denoted as such. That is, for a linear code, it can be seen that the minimum Hamming distance and the non-zero minimum Hamming weight are the same. Since the deep polar code also possesses this linearity, the minimum Hamming distance and the minimum Hamming weight are the same.

[0327] The error probability described above The relationship between and minimum distance can be explained in more detail as follows.

[0328]

[0329] is the transmitted codeword and decoding result It represents the probability of being different, that is, the ML decoding error probability. Is When transmitted, the decoder It is the probability of selecting, called the pairwise error probability (PEP). Total error probability is the sum of PEPs for all possible invalid codewords It can be less than or equal to this, and this can be called a union bound.

[0330] In linear block codes, symmetry exists, so the error probability for any transmitted codeword is the same. Therefore, the error probability can be calculated based on a single codeword (e.g., the zero vector). Thus, the error probability is It can be.

[0331] In the AWGN (Additive White Gaussian Noise) channel, the PEP is the Hamming distance between two codewords. It depends only on. Consequently, the total error probability is the number of codewords located d away from the all-zero vector. Depending on It can be expressed as such. Therefore, it can be seen that the error rate decreases when d_min is increased and / or the number of minimum weight codewords A_(d_min ) is decreased.

[0332] In relation to the above, one embodiment of the present disclosure proposes a method for reducing the number of minimum weight codewords A_(d_min ).

[0333] partial order

[0334] According to the algebraic definition of the polar code above, it can be considered that the polar code is defined by the set of indices I used for rate profiling. Therefore, in the design and development of polar codes, a criterion is required to identify polarized bit channels with high reliability after channel polarization caused by polarization. The reliability of each bit channel after polarization depends on the type of channel and the signal-to-noise ratio (SNR) value. However, identifying and selecting bit channels with high reliability according to a given channel environment requires high complexity and can cause significant delays. Therefore, methods have been proposed to rank bit channel reliability independent of the SNR value. For example, as described above, the 5th generation mobile communication standard 3GPP New Radio (NR) defines a single polar code sequence of length 1024 that indicates the reliability order of polarized bit channels.

[0335] arbitrary index Regarding, is called the i-th synthetic bit channel obtained through the polarization of 2^n underlying channels W. Any two distinct integers Regarding this, if a relationship can be established based on one of the following rules, j is said to dominate i, and denoted as and composite channel The reliability of the synthetic channel It means something higher.

[0336] - (Weight-based rule): All indices About am.

[0337] - (Location-based rule): and i and j are s <t 인 두 인덱스 s It differs only in, and am.

[0338] (N,K) polar signs It is said that it follows a partial order if the condition i≤j for all i∈I and j∈[0,N-1] implies j∈I.

[0339] affine subspace

[0340] (N,K) polar signs For each bit channel index to which the information bit is mapped, For, the corresponding linear subspace affine subspace (AS) It can be defined according to [Equation 17].

[0341] [Mathematical Formula 17]

[0342]

[0343] In [Equation 17] It is called the leading row, and represents the sum in GF(2). In the notation of AS, if the set of indices I of a given polar sign is clear, it can be omitted for simplification. It can also be written as . can be understood as a fixed offset vector, and can be any vector in a given linear subspace. can correspond to a subset of information rows less than or equal to i.

[0344] By the definition according to [Equation 17] above, the two polar signs AS derived by different preceding rows and They are essentially disjoint. Assume that any vector x is included in the intersection of two affine subspaces. . Here, i <j 이다. 이에 따르면, 다음이 성립한다.

[0345]

[0346] Based on this, the following can be derived.

[0347]

[0348] The above formula go This implies that it must be expressed as a linear combination of the rows below it; however, a contradiction arises because in a generating matrix, a row at a higher index cannot be expressed as a linear combination of rows at a lower index. Therefore, x is It cannot be included in. ,

[0349] Therefore, two polar signs AS (affine subspace) induced by different preceding rows and It is inherently disjoint. This is called disjointness between affine subspaces.

[0350] Therefore, the set of codewords excluding codeword 0, which has a Hamming weight of 0. as in mathematical formula 18 It can be divided into several subspaces.

[0351] [Mathematical Formula 18]

[0352]

[0353] FIG. 11 illustrates an example of nested subcodes according to an embodiment of the present disclosure. Referring to FIG. 11, each row of the generator matrix is ​​a different codeword generation vector is. For example, the three rows at the bottom If considered, the polar code generated by these It can be. Here, ...can be satisfied. That is, a containment relationship can be satisfied between the polar signs generated each time a specific index is removed from I one by one. Here, It can be understood as follows. Generalized, As elements of are sequentially excluded one by one, the following inclusion relationship is established: ( [a, b]={a, a+1,...,b-1, b})

[0354]

[0355] FIG. 12 illustrates an example of an affine subspace according to one embodiment of the present disclosure. Referring to FIG. 12, each row of the generator matrix is ​​a different codeword generation vector g_i. For example, considering the bottom three rows g_5, g_6, and g_7, the polar codes generated by them It can be. Here, as described with reference to FIG. 11 This can be established. In addition, as explained in Equation 17 The affine subspace of can be configured.

[0356] Minimum Hamming weight of polar signs

[0357] Generation matrix of polar signs with sign magnitude N In this case, the Hamming weight of the i-th row vector is the lower bound of the weight of any combination of the row itself and the subset of the row vectors below it. This can be expressed by [Equation 19].

[0358] [Mathematical Formula 19]

[0359]

[0360] In [Equation 19] is. Therefore, any polar sign For this, the minimum Hamming weight can be calculated as follows.

[0361] [Mathematical Formula 20]

[0362]

[0363] Based on [Equation 20], polar sign The minimum Hamming weight of the index set polar sign generation matrix indexed by It can be seen that it is the minimum weight of the row vectors.

[0364] polar sign generating matrix The row vector is defined as a set of indices with arbitrary Hamming weights w>0, i.e., [Equation 21].

[0365] [Mathematical Formula 21]

[0366]

[0367] The result w according to the above [Mathematical Formula 20] is a codeword with the minimum Hamming weight It implies that it is part of an AS having a preceding row which is a row vector within an index set I satisfying . More specifically, having a minimum weight w_min and an index set Any (N,K) polar sign defined by For this, every minimum weight codeword exists within a unique AS derived by a row vector g_i indexed in a set of information indices having the minimum row weight. This can be represented by [Equation 22].

[0368] [Mathematical Formula 22]

[0369]

[0370] The result of [Mathematical Equation 22] can be proven by the following. Regarding, any codeword It is assumed that... By the result of [Equation 19], it can be shown that the Hamming weight of the codeword c is not smaller than the Hamming weight of the j-th row vector g_j. That is, is. However, The condition of Since this implies, we can see that wt(c) > w_min. The uniqueness of an AS containing the minimum weight codeword is a result naturally derived from the fact that two ASs derived by different preceding rows are coprime.

[0371] FIG. 13 is a diagram illustrating an example of a lower bound of a codeword weight according to an embodiment of the present disclosure. As described above, for any i ∈ [0, N-1], the following holds. (Proposition 2)

[0372]

[0373] That is, the Hamming weight of a combination of the i-th row vector g_i and a subset of row vectors below it (i.e., from i+1 to N-1) is greater than or equal to the Hamming weight of g_i. In other words, the Hamming weight of a row becomes a lower bound on the Hamming weight of any vector obtained by combining it with at least some of the rows below it.

[0374] Figure 13 illustrates the case where g_3 = [1 1 1 1 0 0 0 0] is the i-th row vector g_i. The Hamming weight of g_3 is 4. Assuming any combination of the row vectors below g_3 (g_4, g_5, g_6, g_7), e.g., J⊆[4, 7],

[0375]

[0376] ... holds true. Since the weight of g_3 is 4, at least 4 1 bits are maintained even when combined with rows below it, and the Hamming weight does not decrease further.

[0377] Unless specifically stated otherwise, in the description of an embodiment of the present disclosure, weight may mean Hamming weight. For example, minimum weight may mean minimum Hamming weight.

[0378] FIGS. 14a to 14j are drawings illustrating an example of a lower limit of a codeword weight according to an embodiment of the present disclosure. With reference to FIGS. 14a to 14j, the validity of Proposition 2 described above will be explained more specifically by induction.

[0379] When n=1,2, if we check all possible combinations, we can confirm that the above-described Proposition 2 holds.

[0380] It is assumed that it holds for n-1. is the i-th row vector of the generation matrix G_(n-1).

[0381]

[0382] For n, consider two disjoint cases.

[0383]

[0384] The generation matrix G_n can be written as follows.

[0385]

[0386] In the case of is included in the lower half of the generation matrix G_n, where ( . That is, considering the subvector of g), it can be written as follows.

[0387]

[0388] By applying dimension reduction here Considering this, it can be written as follows based on the assumption for n-1.

[0389]

[0390] In the case of is included in the upper half of the generation matrix G_n, where and Considering ( Partitioning of rows within can be written as follows.

[0391]

[0392] It can be written as follows.

[0393]

[0394] Here, by applying dimensionality reduction Considering this, it can be written as follows.

[0395]

[0396] Here, by applying dimension recovery Considering this, it can be written as follows based on the assumption for n-1.

[0397]

[0398] According to Plotkin construction, it can be written as follows.

[0399]

[0400] Consider the following here.

[0401]

[0402] is a set of index locations where they are both non-zero, and is a set of different index locations. According to this, it can be written as follows.

[0403]

[0404] in other words, is. As described above here. This holds true. Therefore, it is summarized as follows.

[0405]

[0406] Therefore, it can be seen that Proposition 2 is satisfied.

[0407] Construction of minimum weight codewords

[0408] A set of indices defining polar codes of codeword size N Assume that it follows partial order. Then, all row indices Regarding, the corresponding AS The codewords with the minimum Hamming weight within are the row vector g_i of the encoding generation matrix G_n and and It is known that it consists of a combination of rows indexed by [5]. This can be expressed mathematically as follows.

[0409] [Mathematical Formula 23]

[0410]

[0411] Index set in [Equation 23] is defined as a subset of indices that are numerically larger than row index i and dominate i, as follows.

[0412] [Mathematical Formula 24]

[0413]

[0414] and is a set It is a set-valued function. You can refer to [5] for this. That is, a set of indices Polar sign defined by Given, information bits are mapped, and the minimum weight codewords contained in AS C_i, derived by index i having the minimum Hamming weight of the given polar sign's row vector of the corresponding generating matrix, are the index set It is formed based on all subsets of. Therefore, the exact number of minimum weight codewords contained in each AS C_i is It can be seen that.

[0415] row nullification

[0416] (N,K) polar signs Considering, the codeword x∈ For, the set of indices to which information bits are mapped The frozen set that is the complement of Frozen index belonging to The codeword bit x_i in the position cannot have a non-zero value when all codeword bits x_j at the position j>i are 0.

[0417] To derive the above result, the properties of the polar sign generation matrix G_n can be considered. Since the matrix G_n is involutive, that is (Identity matrix), must be a valid encoding input vector for the encoder. Also, G_n is a lower-triangular matrix where all elements of the principal diagonal are non-zero. Therefore, if the codeword bit x_i is 0 for all j>i, the i-th bit u_i of the encoding input vector u is calculated as [Equation 25].

[0418] [Mathematical Formula 25]

[0419]

[0420] In [Equation 25] represents the element at the j-th row and i-th column of matrix G_n. Index i is the frozen index ( Since u_i=0, to guarantee this, x_i must be 0.

[0421] For ease of explanation, the inter-layer bidirectional mapping function is defined in [Equation 26].

[0422] [Mathematical Formula 26]

[0423]

[0424] The mapping functions in [Equation 26] serve to map the indices of encoded input and output vectors between preceding and succeeding layers based on the connection set of each layer. That is, by using the forward function φ_l, it is possible to determine which bit channel of the input vector of the next layer corresponds to the bits of the corresponding layer's output vector (intermediate codeword). As an example, When, of the th bit Is of It is mapped to the nth bit. That is, am.

[0425] Inverse function It operates in the opposite direction to the aforementioned forward function. More specifically, during the rate profiling process of the encoded input vector of a specific layer, it indicates which bit of the output vector received from the previous layer corresponds to the value mapped to the bit channel of the connection set index. As an example, When, of j∈ the th bit is the output vector of this previous layer of It corresponds to the nth bit. That is, am.

[0426] A deep polar code consisting of two layers can be considered. Index of the second layer connection set AS regarding Is Layer 2 encoded input vector It is formed only when both of the following two conditions are satisfied.

[0427] 1 all indices j Regarding, am.

[0428] 2 k Regarding, am. ​

[0429] Since the first condition is always possible when g is an all-zero vector, it is sufficient to check whether the second condition is satisfied while the assumption holds. That is, a Layer 2 linked set index that is frozen at Layer 1. One can consider the Layer 2 input vector bits. is the intermediate code word of the first layer of The nth bit, that is am.

[0430] Output vector of the first layer The index h of In the case of being larger , The second layer input vector bit corresponding to is This is because the intermediate codeword vectors passed from the previous layer are mapped to the connection set of that layer in natural order, Satisfies. Prerequisites Therefore, the second layer input vector Even if the bit value of an index belonging to a Layer 2 information set or connection set greater than i is 1, if the two conditions for the formation of the AS are satisfied, the final codeword is included in C_i. That is, k Regarding, It is reasonable to consider only and is also consistent with encoding methods based on natural order mapping.

[0431] Layer 1 encoding Considering, the transposed polar sign generation matrix is an upper-triangular matrix, and the properties of the sum remain unchanged. Assuming the second condition above, the output vector of the first layer will have the following values ​​depending on the index.

[0432] ​[Mathematical Formula 27]

[0433]

[0434] In [Mathematical Formula 27] am. Layer 1 output vector bit mapped to The value of can be calculated by the following mathematical formula.

[0435] [Mathematical Formula 28]

[0436]

[0437] In [Equation 28] since, It must be, and therefore AS It cannot be formed.

[0438] Next, we consider a 3-layer deep polar code. For index i∈A_3 of the final layer connection set, we examine two different cases depending on the depth of the inner freezing layer.

[0439] a. (Frozen at Layer 2)

[0440] The second layer index corresponding to connection index i A layer 2 frozen index set This is a case belonging to . At this time It is. Layer 2 encoding Considering the formation conditions of and AS C_i, according to [Equation 29] It can be seen that.

[0441] [Mathematical Formula 29]

[0442]

[0443] At this time, Therefore, a prerequisite for AS formation Assuming that, without violating the freeze constraint cannot have a value of 1.

[0444] b. (Frozen at Layer 1)

[0445] Layer 2 index corresponding to i A connection bit and the corresponding Layer 1 index A is the frozen bit set of Layer 1 This is a case belonging to . For the formation of AS C_i It is assumed that the bits of the Layer 2 intermediate codeword (output vector) is the Layer 2 encoded input vector and generation matrix It is expressed as the product of, which is again the encoded bits of the first layer It is related to. Based on this relationship, the freeze bit of the first layer input vector The value of can be shown as [Equation 30].

[0446] [Mathematical Formula 30]

[0447]

[0448] [Mathematical Formula 30] The above freezing index The value of the first layer output vector bit corresponding to It can be derived through [Mathematical Formula 31].

[0449] [Mathematical Formula 31]

[0450]

[0451] In the above [Equation 31], the last equality relationship is due to the assumption that the bit values ​​of the last layer encoded input vectors at indices smaller than i belong to the last layer connection set, which is a condition for forming AS C_i, and are 0. That is, m Regarding, am.

[0452] Next, each bit of the first layer output vector used for the sum of GF(2) in the above [Equation 30] Consider the first layer index ​Regarding, in the second layer All indices smaller than If we consider , the index of the last third layer corresponding to s The maximum value of becomes smaller than i. That is, am. Based on the fact, through [Equation 32] all Regarding, It implies that it is 0.

[0453] [Mathematical Formula 32]

[0454]

[0455] Applying the results derived from [Equation 31] and [Equation 32] to [Equation 30], for the formation of AS To do this, the input vector bits of the first layer According to [Equation 33], it must become 1.

[0456] [Mathematical Formula 33]

[0457]

[0458] In [Equation 33], That ga has a value of 1 means, This contradicts the assumption that... Therefore This cannot be, and the preceding action AS C_i having cannot exist.

[0459] By recursively applying the same procedure to any deep polar code having L layers, the first layer (l <L)에서 동결된 임의의 최종 계층 연결 인덱스 It can be seen that it cannot form the corresponding AS C_i.

[0460] As described above, a codeword with minimum weight is included in a specific AS. Therefore, the number of codewords with minimum weight can be reduced by preventing the formation of an AS that includes the codeword with minimum weight. According to one embodiment of the present disclosure, a method is proposed to prevent such a specific AS from being formed.

[0461] FIG. 15 is a diagram illustrating an example in which AS is generated in a deep polar code to which an embodiment of the present disclosure is applicable. In the example of FIG. 15, information bits (Information bits, ) location and frozen bits(Frozen bits, ) A case where the positions are continuous is exemplified, but this is for convenience of explanation and the present disclosure is not limited thereto. In FIG. 15, {0, 1} means one value of 0 or 1. This applies equally to the description of an embodiment of the present disclosure below.

[0462] FIG. 15 illustrates the last polar code of the deep polar code. For each sub-channel / bit channel (sub-channel index, bit channel index), information bits (Information bits, ) location and frozen bits(Frozen bits, ) This exemplifies a location. Assume information bit indices j, k, l. AS C_j, C_k, C_l are formed when the information bits being input / mapped for information bit indices j, k, l satisfy specific conditions. For example, if the first bit of the three bits to be mapped to information bit indices j, k, l is fixed to 1 (the second and third bits can be 0 or 1, respectively), the corresponding AS C_j is formed; if the first bit of the three bits is fixed to 0 and the second bit to 1 (the third bit can be 0 or 1), the corresponding AS C_k is formed; and if the first and second bits of the three bits are fixed to 0 and the third bit to 1, the corresponding AS C_l is formed. Here, for information bit indices j, k, l, it is assumed that the weight of the corresponding row is the minimum weight d_min = w_min. According to this, AS C_j, C_k, and C_l corresponding to information bit indices j, k, and l can each have a minimum weight codeword.

[0463] It is assumed that the partial order is followed. According to this, all row indices For , the minimum weight codeword included in the corresponding C_i is g_i and and It is a combination of rows indexed by.

[0464]

[0465] Here, is the set of indices that are numerically larger than i and dominate i in partial order.

[0466]

[0467] am. <x>represents the binary support of vector x, is a set It is a set-valued function. Each subset (including the empty set) uniquely contributes to the formation of a minimum-weight codeword. Therefore, the total number of minimum-weight codewords can be expressed as follows.

[0468]

[0469] That is, all possible for each row i Number of subsets of By summing them, the total number of minimum weight codewords can be determined. For convenience, the above description is referred to as Theorem 2.

[0470] FIG. 16 illustrates an example of a method for determining the number of total minimum weight codewords in a deep polar code to which an embodiment of the present disclosure is applicable. Referring to FIG. 16, the generation matrix This is pre-set, It is pre-set to. The row of the generation matrix G_n corresponding to Consider.

[0471] 1. Identify information set rows that have a row weight equal to the minimum weight.

[0472] The Hamming weight is as follows.

[0473]

[0474] Therefore, the minimum weight is 4.

[0475]

[0476] In other words, the two rows g_5 and g_6 are the rows with the minimum weight.

[0477] 2. For each row, according to Theorem 2 ...can be derived. And, Rows within each subset of generate a minimum-weight codeword.

[0478] In the case of, is. Therefore, The number of subsets of . thus, It generates 4 minimum-weight codewords.

[0479] In the case of, is. Therefore, The number of subsets of . It generates 2 minimum-weight codewords.

[0480] FIG. 17 is a diagram illustrating an example of a method for determining the number of total minimum weight codewords in a deep polar code to which an embodiment of the present disclosure is applicable. Details that overlap with the above description are omitted. Referring to FIG. 17, each AS In relation to, The number of subsets of is, respectively is. Therefore, the number of minimum-weight codewords derived by the row {j,k,l} corresponding to the information bit indices j,k,l is as follows.

[0481]

[0482] Since the number of minimum-weight codewords affects the error probability, a method to reduce the number of minimum-weight codewords is required. According to one embodiment of the present disclosure, row nullification may be applied as a method to reduce the number of minimum-weight codewords.

[0483] FIG. 18 is a diagram illustrating the principle of row invalidation according to one embodiment of the present disclosure. FIG. 19 is a diagram illustrating the principle of row invalidation according to one embodiment of the present disclosure. Details that overlap with the above description are omitted. The necessary and sufficient condition for an input vector u to form a minimum-weight codeword within AS C_i corresponding to index i is, Im and is. That is, within the input vector u And, if all bits prior to u_i are 0, a minimum-weight codeword can be formed within AS C_i corresponding to index i.

[0484] For example, if u_j=1 and all bits prior to u_j in the input vector u are 0, a minimum-weight codeword can be formed in C_j. If u_k=1 and all bits prior to u_k in the input vector u are 0, a minimum-weight codeword can be formed in C_k. If u_l=1 and all bits prior to u_l in the input vector u are 0, a minimum-weight codeword can be formed in C_l.

[0485] If these conditions are not satisfied, that is, if u_i=0 or u_j=1 exists at an index smaller than i, the corresponding input vector is included in an AS other than C_i. In other words, by ensuring that these conditions are not satisfied, it is possible to prevent the occurrence of a C_i in which a minimum-weight codeword is formed. That is, by making u_i=0, it is possible to prevent the occurrence of a C_i in which a minimum-weight codeword is formed. In other words, by forcing u_i=0, the corresponding AS C_i can be eliminated.

[0486] In the above example, if u_j is set to 1->0, the formation of a minimum-weight codeword within C_j can be prevented. If u_k is set to 1->0, the formation of a minimum-weight codeword within C_k can be prevented. If u_l is set to 1->0, the formation of a minimum-weight codeword within C_l can be prevented.

[0487] FIG. 20 is a diagram illustrating the principle of row invalidation according to an embodiment of the present disclosure. FIG. 21 is a diagram illustrating the principle of row invalidation according to an embodiment of the present disclosure. FIG. 22 is a diagram illustrating the principle of row invalidation according to an embodiment of the present disclosure. FIG. 23 is a diagram illustrating the principle of row invalidation according to an embodiment of the present disclosure. FIG. 24 is a diagram illustrating the principle of row invalidation according to an embodiment of the present disclosure. In this example, It is assumed that... Details regarding content that overlaps with the above are omitted.

[0488] For sub-channel / bit channel indices s,t,j,k,l, s,t correspond to a minimum weight frozen set row corresponding to d_min. j,k,l correspond to a minimum weight information set row corresponding to d_min. According to one embodiment of the present disclosure, at least some of the sub-channel / bit channel indices corresponding to the minimum weight frozen set row and the sub-channel / bit channel indices corresponding to the minimum weight information set row may be used for a connection bit (A). In this example, s,t,j,k are exemplified as being used for the connection bit. Since a frozen bit is mapped to s,t, it is guaranteed that a corresponding AS C_s, C_t (i.e., an AS forming a minimum row weight codeword) is not formed for s,t as described above. However, since s,t is used for the connection bit in this example, there is no guarantee that a 0 bit is mapped to the sub-channel / bit channel corresponding to s,t. Therefore, in this example, for s,t, a corresponding AS C_s, C_t (i.e., an AS that forms the minimum row weight codeword) may be formed. That is, in this example, s,t,j,k can be understood as corresponding to the minimum weight connected set rows corresponding to d_min, and each row can form an AS. For example, in the previous layer, input bit Output according to If the j-th bit value is 1 and all previous bit values ​​are 0, It can form a minimum-weight codeword within C_j.

[0489] (N,K) polar signs Considering this, for a codeword x∈C, the coded bit (sign bit) x_i at freeze index i∈F cannot be a non-zero value when all sign bits x_j at the position j>i with the larger index are 0. Referring to the generation matrix G_n exemplified in Fig. 22, the value of the elements on the main diagonal of the generation matrix is ​​1. Therefore, the following holds.

[0490]

[0491] In this case, if all x_j=0 (i.e., all coded bits for j>i are 0), then u_i=x_i. Since u_i=0 due to the frozen constraint, x_i also becomes 0. In other words, for i∈F, if x_i=1, then there exists j>i such that j∈I and x_j=1.

[0492] Here, considering the flipped image, the upper-triangular of the generating matrix G_n is transformed into a lower-triangular, and the input bits and the resulting output The bit order of is also changed. However, as described above, for a codeword x∈C, the coded bit (sign bit) x_i at the frozen index i∈F cannot be a non-zero value when all sign bits x_j at the position with the larger index j>i are 0, cannot be the vector of the flipped image, i.e., [{0 or 1}, 1, 0, 0].

[0493] By freezing rows j,k in the inner layer, it is possible to prevent rows j,k from forming an AS. By freezing the connection set rows j,k corresponding to d_min in the inner layer, the minimum-weight codeword generation rows can be effectively removed. That is, and It becomes.

[0494] To summarize, it is as follows: L-layer deep polar code Considers the inner layer (l <L) 내에서 동결된 마지막 계층 연결 비트 It does not form AS, and therefore, does not generate a minimum weight codeword.

[0495] FIG. 25 is a diagram illustrating an example of a deep polar encoding process based on row invalidation according to an embodiment of the present disclosure. In the deep polar encoding process, frozen set Bits corresponding to and information set We assume bits corresponding to . Here, information set It is assumed that the two corresponding rows contribute to the generation of the minimum-weight codeword. In the case of a deep polar code based on row invalidation according to one embodiment of the present disclosure, row invalidation is applied to the two rows that contribute to the generation of the minimum-weight codeword. That is, they are frozen at the inner layer and no longer contribute to the generation of the minimum-weight codeword. Meanwhile, information set Since the 2 bits corresponding to it have been frozen, 2 information bits corresponding to it can be added.

[0496] FIG. 26 is an experimental example regarding the expected performance improvement when using a deep polar code process based on row invalidation according to one embodiment of the present disclosure. The left graph of FIG. 26 shows the number of polar codes that do not use external codewords and the number of codewords having the minimum Hamming weight of the 2-layer deep polar code according to one embodiment of the present disclosure for each (N,K) combination, where the codeword length is N=128 and the length of the information vector not containing external codewords is K∈{15,16,17,18,19,20}. It can be seen that in all (N,K) combinations, the deep polar code has a significantly lower minimum weight codeword compared to the base polar code. The right graph of FIG. 26 shows the performance indicators of concatenated polar codes using different external codewords in three (N,K) combinations: (128, 32), (128, 64), and (128, 80). The X-axis represents the SNR value [dB], and the Y-axis represents the BLER performance measured at each SNR value. In the case of CA Polar, an external codeword generating 11 CRC bits was used, and the length of the CRC bits was not reflected in K. That is, in the case of CA Polar, the length of the information vector containing the external codeword encoded through the polar code is K+11, K∈{32,64,80}. PAC (polarization-adjusted convolutional code) represents a PAC using a rate-1 convolutional code as the external codeword. The rest, excluding this, correspond to a two-layer deep polar code according to an embodiment of the present disclosure designed using a given threshold T and a linkage factor α at (128, 32), (128, 64), and (128, 80), respectively. It is shown that in all three cases, the deep polar code according to an embodiment of the present disclosure can obtain the same BLER performance at a lower SNR value.

[0497] FIG. 27 shows the number of rows that are invalidated in an L-layer deep polar code according to one embodiment of the present disclosure. This illustrates an example of a method for determining [something]. The operation described in FIG. 27 can be understood as the operation of an electronic device performing encoding according to an L-layer deep polar code. The flowchart of FIG. 27 illustrates an exemplary method that can be implemented according to the principles of the present disclosure, and various modifications may be made to the method illustrated in the flowchart. For example, although illustrated as a series of steps, the various steps in each figure may overlap, occur in parallel, occur in a different order, or occur multiple times. In other examples, steps may be omitted or replaced with other steps.

[0498] Input sequence given in 2701 and regarding encoding parameters, l in 2703 <L 인 경우 (즉, 내부-계층인 경우), 2705 로 진행한다. 본 개시의 일 실시예에 따른 동작 2705 에서 For go It may be assigned to. In operation 2707 according to one embodiment of the present disclosure For go It may be assigned to. In operation 2709 according to one embodiment of the present disclosure For It can be set to. In operation 2711 according to one embodiment of the present disclosure, in GF(2). It can be set to. Accordingly, as with 2713 This can be obtained. Referring to 2705 through 2713, the number of input bits encoded in the corresponding loop is This becomes the number of invalidated rows. This exemplifies that it is determined by the sum of the information bits encoded in layers 1 through L-1. In other words, It can be automatically determined based on encoding parameters.

[0499] From 2703 l <L 이 아닌 경우 (즉, 내부-계층이 아닌 경우), 2715 로 진행한다. 본 개시의 일 실시예에 따른 동작 2715 에서, For go It may be assigned to. In another operation 2717 of one embodiment of the present disclosure, For go It may be assigned to. According to one embodiment of the present disclosure, For It can be set to =0. According to one embodiment of the present disclosure, in GF(2) It can be set to.

[0500] The operation exemplified in Fig. 27 can be represented in pseudo-code as follows.

[0501]

[0502] An L-layer deep polar code design algorithm according to one embodiment of the present disclosure is described. Here, L=2 is assumed. The L-layer deep polar code design algorithm may include determining parameters for an L-layer deep polar code according to one embodiment of the present disclosure.

[0503] According to one embodiment, at least one of the following values ​​can be received as input for the design of a two-layer deep polar code.

[0504] - Input: Length N of the codeword of the deep polar code, length K of an information vector that may contain external codeword bits, universal polar code sequence Q, threshold T, and linkage factor α

[0505] - Output: Parameter set of deep polar code D with a 2-layer structure: .

[0506] In the above input values, T and α are both non-negative integers, and in one embodiment, the polar code sequence Q may be an NR polar code sequence (or a polar code sequence reflected in a standard after the NR standard).

[0507] According to one embodiment, the following series of operations of the design algorithm may be performed. Some steps may be omitted based on preset values.

[0508] Step 1. Given universal polar code sequence while adhering to partial order Information index set based on can be formed.

[0509] Step 2. Preliminary polar code minimum Hamming weight It can be calculated. The preliminary polar code is a (N,K) polar code defined based on the information index set I. It could be.

[0510] Step 3. Augmented defined by polar signs the same minimum weight to have quest.

[0511] Step 4. calculate.

[0512] The Hamming weight It can be a set of bit indices corresponding to the row vector. can mean the maximum number of invalidable rows.

[0513] Step 5. The set of rows satisfying Constituting, here ... is satisfied. In the first layer The rows are frozen.

[0514] Step 6. Settings and In the case where it is given in the form of, It can be set to.

[0515] Step 7. Layer 2 connection set including the following 1), 2), and 3). Constitutes:

[0516] 1) Row (invalidated row)

[0517] 2) from The row with the highest confidence level

[0518] 3) Excluding invalidated rows from The row with the lowest confidence level

[0519] Reliability is It can be measured according to.

[0520] Step 8. Set the following.

[0521]

[0522] Based on Create. Here Satisfies. Consists of.

[0523] Step 9. Returns. (In other words, the first layer does not include connection bits.)

[0524] FIG. 28 relates to an L-layer deep polar code design algorithm according to one embodiment of the present disclosure. Here, L=2 is assumed. An operation based on the algorithm described in FIG. 28 can be understood as the operation of an electronic device that performs encoding according to an L-layer deep polar code. The flowchart of FIG. 28 illustrates an exemplary method that can be implemented according to the principles of the present disclosure, and various modifications may be made to the method illustrated in the flowchart. For example, although illustrated as a series of steps, the various steps in each figure may overlap, occur in parallel, occur in a different order, or occur multiple times. In other examples, steps may be omitted or replaced with other steps.

[0525] According to one embodiment, at least one of the following values ​​can be received as input for the design of a two-layer deep polar code.

[0526] - Input: Length N of the codeword of the deep polar code, length K of an information vector that may contain external codeword bits, universal polar code sequence Q, threshold T, and linkage factor α

[0527] In the above input values, T and α are both non-negative integers, and in one embodiment, the polar code sequence Q may be an NR polar code sequence (or a polar code sequence reflected in a standard after the NR standard).

[0528] According to one embodiment, the following series of operations of the design algorithm may be performed. Some steps may be omitted based on preset values.

[0529] In operation 2810 according to one embodiment, an information index set I can be formed based on a given universal polar code sequence Q while adhering to partial order.

[0530] In operation 2820 according to one embodiment, (N,K) polar codes defined based on information index set I Regarding, minimum Hamming weight can be calculated.

[0531] In operation 2830 according to one embodiment, the augmented polar signs To have the same minimum weight, i.e. To satisfy, based on Q person can be identified.

[0532] In operation 2840 according to one embodiment, and When saying, can be calculated.

[0533] In operation 2850 according to one embodiment, satisfying index set of rows Select from to form a subset, and freeze (nullify) these rows in the first layer.

[0534] In operation 2860 according to one embodiment, the first layer intermediate codeword size Set to.

[0535] In operation 2870 according to one embodiment, a second layer connection set including the following 1), 2), and 3) Constitutes:

[0536] 1) from nullified rows

[0537] 2) from The row with the highest confidence level

[0538] 3) Excluding invalidated rows from The row with the lowest confidence level

[0539] In operation 2880 according to one embodiment, the first layer information set The above configured Based on Let it be a set of rows, Set it as.

[0540] In operation 2890 according to one embodiment, Set to.

[0541] The threshold value T used in operation 2850 according to one embodiment may be a parameter that enables the two-layer deep polar code design algorithm according to one embodiment of the present disclosure to efficiently reduce the number of minimum weight codewords of the polar codes that form the basis.

[0542] Referring to the description according to one embodiment of the present disclosure described above, if a row index belonging to the information set I of the base polar code is frozen or nullified in any inner layer of the deep polar code, the index cannot form an AS. Therefore, the information index having the minimum weight for the corresponding row vector, i.e., i∈ Among the indices, the index where the corresponding AS contains the largest number of minimum codewords (i.e., It is reasonable to select and freeze the index with the largest value.

[0543] Each row vector of the N×N polar sign generation matrix G_n The Hamming weight of is the binary vector at the corresponding row index i∈[0,N-1] Hamming weight About It is given as. Therefore, any (N,K) polar sign The minimum Hamming weight of When, i∈ A binary vector of length n with index i satisfying Is It ends up having '1's. Accordingly, the corresponding set The size of Is It becomes lower than.

[0544] Therefore, the threshold value T is greater than or equal to the lower limit, i.e. It is desirable to set it so that this is the case. Accordingly, according to one embodiment of the present disclosure, the threshold value T is It can be set to.

[0545] A set of the K most reliable bit indices within a polar sequence while maintaining partial order It is called [this].

[0546] silver It is called the minimum weight calculated by. Also The Hamming weight It is defined as a set of bit indices corresponding to the row vector.

[0547]

[0548] As described above, frozen in the internal layer The bit indices within do not form an AS and therefore do not contribute to the minimum weight codeword. These rows are said to be nullified.

[0549] should be invalidated Number of bit indices within ... must be equal to the number of input bits encoded in the inner layer up to the L-1 layer.

[0550]

[0551] The number of nullification rows can satisfy the following constraints.

[0552]

[0553] Here, the set S is defined as follows It is a subset of

[0554]

[0555] The threshold value T satisfies the following conditions.

[0556]

[0557] Referring again to Fig. 24, row is u_i=1 and j <i인 모든 j∈ For u_j=0, an affine subspace is formed and a minimum weight codeword is generated. Assuming row i is nullified, this Numerically smaller than this i This means that it includes some bit indices containing information bits. Since deep polarity coding is performed using the transpose of the polar matrix, u_i cannot have a non-zero value while forcing other upper connected rows to zero. Therefore, frozen rows in any inner layer are invalidated, making it impossible to generate minimum weight codewords.

[0558] A polar encoding method according to one embodiment of the present disclosure may include the step of encoding an information bit and one or more internally encoded bits to obtain an encoded bit, wherein the internally encoded bit may be obtained by encoding the information bit and one or more other internally encoded bits using the transpose of a polar matrix. The internally encoded bit may be assigned to a plurality of sub-channels based on the minimum row weight of a segment of a plurality of sub-channels of the polar matrix.

[0559] A polar encoding method according to one embodiment of the present disclosure may include the step of outputting an information bit and an encoded bit obtained from one or more internally encoded bits.

[0560] According to one embodiment of the present disclosure, the total number of information bits to be encoded in the internal layer may not exceed half the number of subchannels to which the internally encoded bits are allocated in the last layer.

[0561] According to one embodiment of the present disclosure, the total number of information bits to be encoded in the inner layer may not exceed the number of bit indices corresponding to the row vectors having the minimum weight among the row vectors of the polar matrix G_N, based on the most reliable set of K row vectors satisfying partial-order constraints but not included in the set.

[0562] According to one embodiment of the present disclosure, the total number of information bits to be encoded in the inner layer is a set It may not exceed the cardinality of.

[0563] According to one embodiment of the present disclosure, the threshold T is It could be more than that. For example, It could be.

[0564] A method performed by a transmission device according to one embodiment of the present disclosure may include, in the encoding process of a concatenated polar code in which a plurality of bits in an encoder input bit sequence to be encoded using a polar code are replaced with an encoder output bit sequence obtained with a smaller polar code, a step of identifying an element of a connection set in an original information set and a step of identifying an element of a connection set in an original frozen set.

[0565] According to one embodiment of the present disclosure, the original information set Identify at least one index in the connection set based on row weight. It can be included in and the freeze bit can be mapped in the internal layer.

[0566] According to one embodiment of the present disclosure, the original information set In the connection set In the step of identifying the index to be included, the information set An information set index with a row weight greater than or equal to the minimum row weight w_min determined by can be selected.

[0567] According to one embodiment of the present disclosure, the original information set In the connection set In the step of identifying the indexes to be included, the number of elements B_1 with the minimum row weight among the information set indexes, i.e. Less than or equal to As many information set indices as there are items can be selected.

[0568] According to one embodiment of the present disclosure, the original information set In the connection set In the step of identifying the index to be included, The entire polar code sequence including Created based on Maximum information set maintaining the minimum row weight is identified, at B_2, the number of elements with the minimum row weight among the indices excluding, i.e. Less than or equal to As many information set indices as there are items can be selected.

[0569] According to one embodiment of the present disclosure, the original information set In the connection set In the step of identifying the index to be included, smaller than the minimum value of B_1 and B_2 As many information set indices as there are items can be selected.

[0570] According to one embodiment of the present disclosure, the original information set In the connection set In the step of identifying an index to be included in the information set index, the index can be identified according to the size of K_i, which is a set of binary vectors obtained by flipping one 0 to 1 or exchanging one 1 with a 0 located in a higher position, in a binary vector of elements with the minimum row weight among the information set indices.

[0571] According to one embodiment of the present disclosure, the original information set In the connection set In the step of identifying indexes to be included, among the indexes of the information collection with the minimum row weight, the set It can be identified among rows where the size is greater than the threshold T.

[0572] According to one embodiment of the present disclosure, the threshold value T can be determined by the minimum weight of the code, w_min, which is determined by the minimum row weight determined by the information bit sequence.

[0573] According to one embodiment of the present disclosure, the threshold value T is It can be selected to satisfy.

[0574] According to one embodiment of the present disclosure, the size N_1 of a connection set can be determined by B_null.

[0575] According to one embodiment of the present disclosure, the size N_1 of a connection set is an integer value α greater than or equal to 1, i.e., α≥1, and N is defined by B_null. It can be determined to satisfy.

[0576] According to one embodiment of the present disclosure, Select at least B_null rows with the highest channel capacity from In including, information bits may be inserted into the index of the internal layer mapped to the included row.

[0577] According to one embodiment of the present disclosure, Select at least B_null rows with the highest channel capacity from In including, the number of rows having the minimum row weight among the included rows is The number of minimum weight rows frozen in the first layer among the elements of may not exceed.

[0578] According to one embodiment of the present disclosure, at The rows with the smallest channel capacity among the rows excluding B_null rows included in It can be included in.

[0579] According to one embodiment of the present disclosure, in a design process for encoding a deep polar code in which a plurality of bits in an information vector are replaced with an intermediate codeword obtained by encoding based on the transpose matrix of a polar code generation matrix of a smaller size using a polar code, the process may include identifying an element of a connection set from an existing information index set of an underlying polar code and identifying an element of a connection set from an existing frozen index set.

[0580] According to one embodiment of the present disclosure, at least one index in an existing information index set of base polar codes is identified based on the Hamming weight of the row vector of the corresponding polar code generation matrix, the selected index is included in a connection set, and a freeze bit can be mapped in an inner layer.

[0581] According to one embodiment of the present disclosure, in identifying and selecting an index to be included in a linkage set from an existing set of information indices of the basis polar code, the index may be selected from a subset of the information set consisting of indices of row vectors having a Hamming weight equal to or greater than the minimum Hamming weight w_min of the basis polar code determined by the information set.

[0582] According to one embodiment of the present disclosure, in identifying an index to be included in a linkage set from an existing information index set of the basis polar code, the parameter B_1 can be calculated as the number of index elements in the information set where the corresponding row vector has a minimum Hamming weight.

[0583] According to one embodiment of the present disclosure, in identifying an index to be included in a linkage set from an existing information index set of the base polar code, an augmented polar code that maintains the minimum Hamming weight of the base polar code is defined based on the same polar code sequence used to form the information set of the base polar code, an extended maximum information set including the information set of the base polar code is identified, and a parameter B_2 may be selected such that it is less than or equal to the number of indices in which the row vector has the minimum Hamming weight among the indices excluding the existing information set from the maximum information set.

[0584] According to one embodiment of the present disclosure, in identifying indices to be included in a connection set from an existing information index set of the basis polar code, B_null values ​​smaller than the minimum value of the set parameter values ​​B_1 and B_2 may be selected.

[0585] According to one embodiment of the present disclosure, in identifying an index to be included in a linkage set from an existing information index set of the basis polar code, the binary vectors obtained by converting one '0' to '1' or exchanging one '1' with a '0' located in a preceding position, wherein among the information set indices, the corresponding row vector is a binary vector of indices having a minimum Hamming weight. It can be identified based on the size of.

[0586] According to one embodiment of the present disclosure, in identifying an index to be included in a linkage set from an existing set of information indices of the basis polar code, among the indices among the information aggregate indices, the index having a minimum Hamming weight for the corresponding row vector, the set Indices whose size is greater than the threshold T can be selected.

[0587] According to one embodiment of the present disclosure, in identifying an index to be included in a connection set from an existing set of information indices of the basis pole code, the threshold value T can be determined by the minimum Hamming weight w_min of the basis pole code.

[0588] According to one embodiment of the present disclosure, in identifying an index to be included in a linkage set from an existing set of information indices of the basis polar code, the threshold value T is the log-2 value of the codeword length N of the basis polar code. and based on the minimum Hamming weight w_min It can be selected to satisfy.

[0589] According to one embodiment of the present disclosure, in identifying an index to be included in a connection set from an existing information index set of the basis polar code, the size of the connection set, i.e., the size N_1 of the output vector of the first layer, can be determined by B_null.

[0590] According to one embodiment of the present disclosure, in identifying an index to be included in a connection set from an existing information index set of the basis polar code, the size of the connection set, i.e., the size N_1 of the output vector of the first layer, is based on an integer value α such that α≥1. It can be set to.

[0591] According to one embodiment of the present disclosure, in identifying an index to be included in a connection set from an existing set of information indices of the base polar code, at least B_null of the most reliable side-channel indices in a subset obtained by excluding the indices of the existing information set from the maximum information set are included in the connection set, and bits of an information vector may be mapped to an index of an internal layer corresponding to a selected row.

[0592] According to one embodiment of the present disclosure, in identifying an index to be included in a linkage set from an existing information index set of the base polar code, among the indexes included in the linkage set from the side-channel index with the highest reliability in the subset from which the indices of the existing information set are excluded from the maximum information set, the number of indices having a minimum Hamming weight for the corresponding row vector may not exceed the number of indices frozen in the first layer among the information set indices corresponding to the row vector having the minimum Hamming weight.

[0593] According to one embodiment of the present disclosure, in identifying indices to be included in a linkage set from an existing set of information indices of the basis polar code, the indices with the smallest reliability among the indices excluded from the existing information set and the linkage set, such as B_null indices, may be additionally included in the information set.

[0594] FIG. 29 is a diagram illustrating an example of the operation of an electronic device according to an embodiment of the present disclosure. The flowchart of FIG. 29 illustrates an exemplary method that can be implemented according to the principles of the present disclosure, and various modifications may be made to the method illustrated in the flowchart. For example, although illustrated as a series of steps, the various steps in each figure may overlap, occur in parallel, occur in a different order, or occur multiple times. In other examples, steps may be omitted or replaced with other steps.

[0595] In operation 2910 according to one embodiment of the present disclosure, the electronic device can identify an input vector for a deep polar code.

[0596] In operation 2920 according to one embodiment of the present disclosure, the electronic device may identify L matrices associated with L layers of the deep polar code. An l-layer input vector for l (2≤l≤L) of the L matrices may include information bits, connection bits, and frozen bits. The information bits of the l-layer input vector may be associated with l of the L parts of the input vector.

[0597] In operation 2930 according to one embodiment of the present disclosure, the electronic device can generate a codeword vector corresponding to the input vector based on the dip polarity code.

[0598] According to one embodiment of the present disclosure, in generating the codeword vector, the connecting bit of the l-th level input vector is associated with the output of the l-1 matrix for the l-1-th level input vector, and the sub-channel index associated with the connecting bit of the l-th level input vector is It includes indices, and among the connection bits of the above l-layer input vector, the above Related to the index A freeze bit can be mapped to the connection bits.

[0599] According to one embodiment of the present disclosure, a set of information indices corresponding to the first layer among the L layers is identified based on a preset polar code sequence Q, and a minimum Hamming weight is identified based on the set of information indices corresponding to the first layer is identified, and the above The indices are the minimum Hamming weights among the row vectors in the l matrix. Corresponding to at least some of the row vectors having, and the minimum Hamming weight among the row vectors in the l matrix The number of row vectors having is It may be less than.

[0600] According to one embodiment of the present disclosure, an information index set corresponding to the first layer and the minimum Hamming weight Based on, a maximum information index set including an information index set corresponding to the first layer and an information index set corresponding to the l layer is identified, and the The maximum value of Is class It is the smaller value among them, is the set of information indices corresponding to the first layer and the minimum Hamming weight It is the number of elements included in the intersection of the set of bit indices of row vectors having, and is the set excluding the elements included in the information index set corresponding to the first layer from the maximum information index set, the information index set corresponding to the first layer, and the minimum Hamming weight It may be the number of elements included in the intersection of the set of bit indices of row vectors having.

[0601] According to one embodiment of the present disclosure, the above The index is the above minimum Hamming weight Among row vectors having It satisfies, and And, is the above-mentioned maximum information index set, and is the binary support of vector x, and is the minimum Hamming weight in the polar sign generation matrix It is a specific row vector having, is in the above polar sign generation matrix It is a specific row vector corresponding to, and And, And, N may be the codeword length corresponding to the above-mentioned deep polar code.

[0602] According to one embodiment of the present disclosure, the set of connection indices associated with the connection bits of the l-layer input vector comprises: the information index set included in the set of information indices corresponding to the first layer. k indices; and the highest reliability included in the set excluding the element of the information index set corresponding to the first layer from the maximum information index set. It includes indices, and among the connection bits of the l-layer input vector, the one with the highest reliability Related to the index Information bits can be mapped to the connection bits.

[0603] According to one embodiment of the present disclosure, in the information index set corresponding to the first layer, the The lowest confidence level excluding the index Includes indexes, can be the codeword length corresponding to the first layer above.

[0604] According to one embodiment of the present disclosure, the size of the set of linked indices is And, It can be an integer.

[0605] According to one embodiment of the present disclosure, an electronic device can transmit a generated codeword vector.

[0606] According to one embodiment of the present disclosure, L=2.

[0607] For more specific details regarding the operation of an electronic device according to one embodiment of the present disclosure described above, refer to the description of various embodiments of the present disclosure described above.

[0608] FIG. 30 is a block diagram of a terminal or user equipment (3000) according to one embodiment of the present disclosure.

[0609] The terminal (3000) is an electronic device capable of wireless communication and may include user equipment (UE), mobile phones, smartphones, tablets, Internet of Things (IoT) devices having various form factors, and can perform wireless communication with a base station through a wireless channel.

[0610] Referring to FIG. 30, the terminal (3000) may include at least one transceiver (3001) (hereinafter, transceiver), at least one processor (3002) (hereinafter, processor), and at least one memory (3003) (hereinafter, memory). The transceiver (3001), processor (3002), and memory (3003) of the terminal (3000) may be operated according to at least one or a combination thereof of the methods corresponding to the embodiments of the present disclosure. However, the components of the terminal (3000) are not limited to the examples of components shown in FIG. 30. In other embodiments, the terminal (3000) may include additional components in addition to the aforementioned components, or some components may be omitted. Also, in some embodiments, any combination of the transceiver (3001), processor (3002), or memory (3003) may be integrated into a single component.

[0611] The transceiver (3001) may be a basic communication circuit or communication circuitry that enables the terminal (3000) to perform wireless communication with a node or entity of a network. For example, the transceiver (3001) may enable the terminal (3000) to transmit and receive signals to and from a base station via cellular wireless communication, or to transmit and receive signals to and from another terminal via cellular wireless communication. For example, the transceiver (3001) may support at least one of various cellular wireless communication technologies including 3G (3rd generation), 4G (4th generation) LTE (long-term evolution), 5G (5th generation) NR (new radio), 6G (6th generation), etc., and the various cellular wireless communication technologies supported by the transceiver (3001) may include all subsequent evolved generations of wireless communication.

[0612] According to one embodiment, the terminal (3000) may include a plurality of transceivers, and for example, when supporting EN-DC (E-UTRA (evolved-universal terrestrial radio access) - NR dual connectivity), it may include a first transceiver supporting 4G LTE wireless communication and a second transceiver supporting 5G NR wireless communication. According to another embodiment, when the terminal (3000) supports NR-DC (NR Dual Connectivity), the terminal (3000) may include a plurality of transceivers supporting 5G NR wireless communication. According to another embodiment, if the terminal (3000) supports short-range wireless communication, the terminal (3000) may separately include a transceiver that supports at least one of a group of wireless communication protocol standards such as those defined by Bluetooth®, wireless LAN or WLAN (wireless local area network) network (including, but not limited to, 802.11ah, 802.11ad, 802.11ay, 802.11ax, 802.11az, 802.11ba and 802.11be).

[0613] According to one embodiment, the transceiver (3001) may include various circuit structures used to transmit and receive signals to and from a base station via a wireless channel. The signals may include control information and data. For example, the transceiver (3001) may be configured to include a radio frequency (RF) transmitter that up-converts and amplifies the frequency of a transmitted signal, and an RF receiver that low-noise amplifies a received signal and down-converts the frequency. The transceiver (3001) may output the signal received via the wireless channel to a processor (3002) and transmit the signal output from the processor (3002) via the wireless channel.

[0614] The processor (3002) can control the overall operation of the terminal (3000) according to an embodiment of the present disclosure. The processor (3002) may be implemented as one or more IC (integrated circuit (or circuitry)) chips and may perform various data processing operations. The processor (3002) may include at least one electrical circuit and may execute instructions (or programs, code, data, etc.) stored in memory (3003) individually, collectively, or in any combination. Additionally, the processor (3002) may include a single-core processor or a multi-core processor, and in a specific implementation, may be composed of a processor assembly including a plurality of processing circuits.

[0615] The processor (3002) is electrically, operatively, or communicatively coupled to the transceiver (3001) so as to control the transceiver (3001).

[0616] The processor (3002) may include at least one processor (or, processing circuitry), and at least one processor may perform the following operations individually, collectively, or in any combination. For example, the processor (3002) may include a communication processor (CP) that controls communication operations and an application processor (AP) that controls the execution of an upper layer (e.g., an application layer). In a specific embodiment, at least one part of the processor (3002) may be included in one chip, and another part of the processor (3002) may be included in a separate chip. Alternatively, at least one processor may be included in other components, e.g., a transceiver (3001) or a memory (3003).

[0617] The processor (3002) may perform, cause, or control the operation of a terminal to perform at least one or a combination of the methods according to the embodiments of the present disclosure. For example, the processor (3002) may control the operation of a terminal to process a downlink signal received from a base station or to generate an uplink signal and transmit it to a base station. To this end, the processor (3002) may control other components of the terminal (3000) to perform various operations by executing computer programs, code, or instructions stored in memory (3003).

[0618] Memory (3003) is a hardware storage device capable of storing information temporarily or permanently and may include one or more storage media. For example, memory (3003) may include a memory assembly comprising one or more storage media. For example, the one or more storage media may include a hard drive, flash memory, permanent memory such as ROM (read-only memory), semipermanent memory such as RAM (random access memory), cache memory, or any combination thereof.

[0619] The memory (3003) can be electrically, operatively, or communically coupled with the processor (3002) and can be accessed by the processor (3002).

[0620] A computer program, code, or instruction that can be executed by a processor (3002) may be stored in the memory (3003). According to one embodiment, the computer program, code, or instruction that can be executed by the processor (3002) may be stored in a single memory device or may be separated and distributed across two or more memory devices. The processor (3002) may perform various functions according to the embodiments of the present disclosure by executing the instruction stored in the memory (3003).

[0621] According to one embodiment of the present disclosure, the operation of the terminal (3000) may be caused to be performed based on at least one processor (or processing circuit) configured to perform the features of the present disclosure individually, collectively, or in any combination based on the execution of instructions (or computer program or code) stored in memory (3003), based on processing circuitry not configured to execute instructions, and / or based on components of a processing circuitry not configured to execute instructions.

[0622] FIG. 31 is a block diagram of a base station (3100) according to one embodiment of the present disclosure.

[0623] The base station (3100) can perform wireless communication with at least one terminal within the area of ​​the base station (3100) through a wireless channel.

[0624] Referring to FIG. 31, a base station (3100) may include at least one transceiver (3101) (hereinafter, transceiver), at least one processor (3102) (hereinafter, processor), and at least one memory (3103) (hereinafter, memory). According to at least one or a combination thereof of methods corresponding to embodiments of the present disclosure, the transceiver (3101), processor (3102), and memory (3103) of the base station (3100) may be operated. However, the components of the base station (3100) are not limited to the examples of components shown in FIG. 31. In other embodiments, the base station (3100) may include additional components in addition to the aforementioned components, or some components may be omitted. Also, in some embodiments, any combination of the transceiver (3101), processor (3102), or memory (3103) may be integrated into a single component.

[0625] The transceiver (3101) may be a communication circuit or communication circuitry that enables the base station (3100) to perform wireless communication with a node or entity of the network. For example, the transceiver (3101) may enable the base station (3100) to transmit and receive signals to and from a terminal (3000) via cellular wireless communication or to transmit and receive signals to and from another network entity via wireless communication. For example, the transceiver (3101) may support various cellular wireless communication technologies including 3G (3rd generation), 4G (4th generation) LTE (long-term evolution), 5G (5th generation) NR (new radio), 6G (6th generation), etc., and the various cellular wireless communication technologies supported by the transceiver (3101) may include all subsequent generations of wireless communication. According to one embodiment, the transceiver (3101) may include various circuit structures used to transmit and receive signals to and from a terminal via a wireless channel. The signals may include control information and data. For example, the transceiver (3101) may be configured to include a radio frequency (RF) transmitter that up-converts and amplifies the frequency of a transmitted signal, and an RF receiver that low-noise amplifies a received signal and down-converts the frequency. The transceiver (3101) may output the signal received via the wireless channel to a processor (3102) and transmit the signal output from the processor (3102) via the wireless channel.

[0626] Meanwhile, according to one embodiment of the present disclosure, a base station (3100) may communicate with an entity or node of a network via wired or wireless communication. For example, the base station (3100) may communicate via wired or wireless communication with an entity or node of an adjacent base station or core network via a backhaul network. Although not shown in the drawings, when the base station (3100) performs wired communication, the base station (3100) may include a separate network interface for wired communication in addition to the transceiver (3101). The network interface may be referred to as network interface circuitry, communication interface circuitry, etc.

[0627] The processor (3102) can control the overall operation of the base station (3100) according to an embodiment of the present disclosure. The processor (3102) may be implemented as one or more IC (integrated circuit or circuitry) chips and may perform various data processing operations. The processor (3102) may include at least one electrical circuit and may execute instructions (or programs, code, data, etc.) stored in memory (3103) individually, collectively, or in any combination. Additionally, the processor (3102) may include a single-core processor or a multi-core processor, and in a specific implementation, may be composed of a processor assembly including a plurality of processing circuits.

[0628] The processor (3102) is electrically, operatively, or communicatively coupled to the transceiver (3101) so as to control the transceiver (3101).

[0629] The processor (3102) may include at least one processor (or processor circuitry), and at least one processor may perform the following operations individually, collectively, or in any combination. In a particular embodiment, at least one part of the processor (3102) may be included in one chip, and another part of the processor (3102) may be included in a separate chip. Alternatively, at least one processor may be included in other components, such as a transceiver (3101) or memory (3103).

[0630] The processor (3102) may perform, cause, or control the operation of a base station to perform at least one or a combination of the methods according to the embodiments of the present disclosure. For example, the processor (3102) may control the operation of a base station to generate a downlink signal and transmit it to a terminal, or to process an uplink signal received from a terminal. Alternatively, the base station may transmit and receive signals with an adjacent base station, transmit a signal received from a terminal to an upper node of the network, or receive a signal from an upper node of the network and transmit it to a terminal. To this end, the processor (3102) may control other components of the base station (3100) to perform various operations by executing computer programs, codes, and instructions stored in memory (3103).

[0631] Memory (3103) is a hardware storage device capable of storing information temporarily or permanently and may include one or more storage media. For example, memory (3103) may include a memory assembly comprising one or more storage media. For example, the one or more storage media may include a hard drive, flash memory, permanent memory such as ROM (read-only memory), semi-permanent memory such as RAM (random access memory), cache memory, or any combination thereof.

[0632] The memory (3103) can be electrically, operatively, or communically coupled with the processor (3102) and can be accessed by the processor (3102).

[0633] A computer program, code, or instruction that can be executed by a processor (3102) may be stored in the memory (3103). According to one embodiment, the computer program, code, or instruction that can be executed by the processor (3102) may be stored in a single memory device or may be separated and distributed among two or more memory devices. The processor (3102) may perform various functions according to the embodiments of the present disclosure by executing the instruction stored in the memory (3103).

[0634] According to one embodiment of the present disclosure, the operation of a base station (3100) may be caused to be performed based on at least one processor (or processing circuit) configured to perform the features of the present disclosure individually, collectively, or in any combination based on the execution of instructions (or computer programs or code) stored in memory (3103), based on processing circuitry not configured to execute instructions, and / or based on components of a processing circuitry not configured to execute instructions.

[0635] A terminal or a base station can perform various communication procedures related to the control plane or user plane by interacting with network entities based on communication through a wireless channel. For example, a terminal can communicate with network entities such as an access and mobility management function (AMF) or a session management function (SMF) through a base station. Alternatively, the base station can perform at least one communication procedure by directly transmitting and receiving signals or relaying them with network entities. The structure of the above-mentioned network entities will be explained in more detail through the drawings below.

[0636] FIG. 32 is a block diagram of a network entity (3200) that performs network functions according to one embodiment of the present disclosure.

[0637] A network entity (3200) may include one or more network functions (NF) that constitute a core network (e.g., 5G (5th generation) core, 5GC) in a communication system, or entities (devices, devices, nodes, or servers, etc.) that perform part of a network function. In this case, multiple NFs may be implemented within a single network entity, or a single NF may be distributed and implemented across multiple network entities. Additionally, when an NF is implemented within a network entity, the NF may be implemented in the form of software, and in such cases, a program for running the NF may be loaded into the memory of the network entity (3200).

[0638] A single NF can be implemented as one or more instances and can operate by being distributed across the same network entity or multiple network entities. Here, the instance is a software unit that logically executes a specific network function and may be separate from physical hardware resources. Additionally, one or more NFs may be implemented as a single network slice to operate in order to satisfy the specifications required by a specific service.

[0639] The above NF may include any one of an access and mobility management function (AMF), a session management function (SMF), a local session management function (L-SMF), a user plane function (UPF), a local user plane function (L-UPF), a policy control function (PCF), unified data management (UDM), a unified data repository (UDR), a network exposure function (NEF), a network repository function (NRF), an application function (AF), a network slice selection function (NSSF), a network data analytics function (NWDAF), a network slice admission control function (NSACF), an authentication server function (AUSF), or a data network (DN).

[0640] Referring to FIG. 32, a network entity (3200) may include at least one network interface (3201), at least one processor (3202) (hereinafter referred to as processor), and at least one memory (3203) (hereinafter referred to as memory). As described above, the NF may be implemented in the form of a physical device such as the network entity (3200), or may be implemented and executed in the form of a virtualized instance. When the NF is implemented in the form of an instance, it may not necessarily include physical components as illustrated in FIG. 32. In such cases, the instance may be composed of one or more logical functional units and may be logically represented.

[0641] According to at least one or a combination thereof of the methods corresponding to the embodiments of the present disclosure, the network interface (3201), processor (3202), and memory (3203) of the network entity (3200) may be operated. However, the components of the network entity (3200) are not limited to the examples of components shown in FIG. 32. In other embodiments, the network entity (3200) may include additional components in addition to the aforementioned components, or some components may be omitted. Also, in one embodiment, the network interface (3201), processor (3202), or memory (3203) may be implemented as a single component.

[0642] The network interface (3201) is a collective term for the transmitting and receiving parts of a network entity and may be a communication circuit for transmitting and receiving signals with a terminal (user equipment, UE), a base station, or other network entities. In this case, the communication circuit may include both a communication circuit for wireless communication and a communication circuit for wired communication. For example, the network interface (3201) may include circuits, logic, hardware, etc. configured to exchange control plane messages or user plane messages with a terminal, a base station, or other core network entities via wireless or wired communication. The network interface (3201) may operate using various protocols (e.g., NAS (Non-Access Stratum) protocol). Depending on the convenience of explanation and technical implementation, the network interface (3201) may be referred to as a communication circuitry, a network interface circuitry, or a communication interface circuitry.

[0643] The processor (3202) may control the overall operation of the network entity (3200) according to an embodiment of the present disclosure. In one embodiment, the processor (3202) may be implemented as one or more IC (integrated circuit or circuitry) chips and may execute various data processing operations. The processor (3202) may include at least one electrical circuit and may execute instructions (or programs, code, data, etc.) stored in memory (3203) individually, collectively, or in any combination. Additionally, the processor (3202) may include a single-core processor or a multi-core processor, and in a specific implementation, may be composed of a processor assembly including a plurality of processing circuits. Additionally, it should be noted that the processor (3202) may not necessarily be composed of physical hardware when the network function (3200) is implemented in an instance form according to another embodiment.

[0644] According to one embodiment, the processor (3202) is electrically, operatively, or communicatively coupled to the network interface (3201) so as to control the network interface (3201).

[0645] The processor (3202) may include at least one processor (or processor circuitry), and at least one processor may perform the following operations individually, collectively, or in any combination. In a particular embodiment, at least one part of the processor (3202) may be included in one chip, and another part of the processor (3202) may be included in a separate chip. Alternatively, at least one processor may be included in other components, such as a network interface (3201) or memory (3203).

[0646] The processor (3202) may perform or control the operation of a network entity (3200) to perform at least one or a combination thereof of the methods according to the embodiments of the present disclosure. For example, the processor (3202) may control the operation of the network entity (3200) to exchange control plane messages or user plane messages with terminals, base stations, or other core network entities via wireless or wired communication using various protocols (e.g., NAS protocols). To this end, the processor (3202) may control other components of the network entity (3200) to perform various operations by executing computer programs, code, or instructions stored in memory (3203).

[0647] Memory (3203) is a hardware storage device capable of storing information temporarily or permanently and may include one or more storage media. For example, memory (3203) may include a memory assembly comprising one or more storage media. For example, the one or more storage media may include a hard drive, flash memory, permanent memory such as ROM (read-only memory), semipermanent memory such as RAM (random access memory), cache memory, or any combination thereof.

[0648] According to one embodiment, the memory (3203) may be electrically, operatively, or communically coupled with the processor (3202) and may be accessed by the processor (3202).

[0649] A computer program, code, or instruction that can be executed by a processor (3202) may be stored in the memory (3203). According to one embodiment, the computer program, code, or instruction that can be executed by the processor (3202) may be stored in a single memory or separated and distributed across two or more memories. The processor (3202) may perform various functions according to the embodiments of the present disclosure by executing the instruction stored in the memory (3203).

[0650] According to one embodiment of the present disclosure, the operation of a network entity (3200) may be caused to be performed based on at least one processor (or processing circuit) configured to perform the features of the present disclosure individually, collectively, or in any combination based on the execution of instructions (or computer program or code) stored in memory (3203), based on a processing circuitry not configured to execute instructions, and / or based on a component of a processing circuitry not configured to execute instructions.

[0651] Meanwhile, although specific embodiments have been described in the detailed description of the present disclosure, it is understood that various modifications are possible within the scope of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the described embodiments, but should be defined by the claims set forth below as well as equivalents thereof.< / x> < / x>

Claims

1. In a method performed by an electronic device, A step of identifying an input vector for a deep polar code; A step of identifying L matrices associated with L layers of the above-described deep polar code, wherein an l-layer input vector for l (2≤l≤L) of the L matrices comprises information bits, connection bits, and frozen bits, and the information bits of the l-layer input vector are associated with l parts of the L parts of the input vector; and The method includes the step of generating a codeword vector corresponding to the input vector based on the above-mentioned deep polar code, In generating the above codeword vector, the connection bits of the above l-layer input vector are associated with the output of the l-1 matrix for the l-1-layer input vector, and The sub-channel index associated with the connection bit of the above l-layer input vector is Includes indexes, Among the connection bits of the above l-layer input vector, the above Related to the index A method in which a freeze bit is mapped to a number of connection bits.

2. In Paragraph 1, Pre-set polar sign sequence Based on this, a set of information indices corresponding to the first layer among the above L layers is identified, and Minimum Hamming weight based on the set of information indices corresponding to the first layer above is identified, The above The indices are the minimum Hamming weights among the row vectors in the l matrix. Corresponding to at least some of the row vectors having, and the minimum Hamming weight among the row vectors in the l matrix The number of row vectors having is Lee Ha-in, method.

3. In Paragraph 2, The set of information indices corresponding to the first layer and the minimum Hamming weight Based on this, a maximum information index set including an information index set corresponding to the first layer and an information index set corresponding to the l layer is identified, and The above The maximum value of Is class It is the smaller value among them, is the set of information indices corresponding to the first layer and the minimum Hamming weight It is the number of elements included in the intersection of the set of bit indices of row vectors having, and is the set excluding the elements included in the information index set corresponding to the first layer from the maximum information index set, the information index set corresponding to the first layer, and the minimum Hamming weight A method that is the number of elements included in the intersection of the set of bit indices of row vectors having.

4. In Paragraph 3, The above The index is the above minimum Hamming weight Among row vectors having It satisfies, and And, is the above-mentioned maximum information index set, and is the binary support of vector x, and is the minimum Hamming weight in the polar sign generation matrix It is a specific row vector having, is in the above polar sign generation matrix It is a specific row vector corresponding to, and And, A method in which N is the codeword length corresponding to the above-mentioned deep polar code.

5. In Paragraph 3, The set of connection indices associated with the connection bits of the above l-layer input vector is: The above included in the set of information indexes corresponding to the first layer above Number of indices; and The highest reliability included in the set excluding the elements of the information index set corresponding to the first layer from the above maximum information index set Includes indexes, Among the connection bits of the above l-layer input vector, the one with the highest reliability Related to the index A method in which information bits are mapped to connection bits.

6. In Paragraph 5, In the set of information indices corresponding to the first layer mentioned above, the The lowest confidence level excluding the index Includes indexes, is a method, which is the codeword length corresponding to the first layer above.

7. In Paragraph 5, The size of the above set of linked indices is And, A method that is an integer.

8. In Paragraph 1, A method further comprising the step of transmitting the above-mentioned codeword vector, wherein L=2.

9. In electronic devices, At least one transceiver; One processor connected to communicate with at least one transceiver; and The electronic device is connected to communicate with at least one processor and is capable of executing individually or in any combination of the at least one processor, such that: Identify the input vector for the deep polar code; Identify L matrices associated with L layers of the above deep polar code, wherein the l-layer input vector for l (2≤l≤L) of the L matrices includes information bits, connection bits, and frozen bits, and the information bits of the l-layer input vector are associated with l parts of the L parts of the input vector; and It includes a memory that stores an instruction to generate a codeword vector corresponding to the input vector based on the above-mentioned deep polar code, and In generating the above codeword vector, the connection bits of the above l-layer input vector are associated with the output of the l-1 matrix for the l-1-layer input vector, and The sub-channel index associated with the connection bit of the above l-layer input vector is Includes indexes, Among the connection bits of the above l-layer input vector, the above Related to the index An electronic device in which a freeze bit is mapped to a number of connection bits.

10. In Paragraph 9, Pre-set polar sign sequence Based on this, a set of information indices corresponding to the first layer among the above L layers is identified, and Minimum Hamming weight based on the set of information indices corresponding to the first layer above is identified, The above The indices are the minimum Hamming weights among the row vectors in the l matrix. Corresponding to at least some of the row vectors having, and the minimum Hamming weight among the row vectors in the l matrix The number of row vectors having is Lee Ha-in, electronic device.

11. In Paragraph 10, The set of information indices corresponding to the first layer and the minimum Hamming weight Based on this, a maximum information index set including an information index set corresponding to the first layer and an information index set corresponding to the l layer is identified, and The above The maximum value of Is class It is the smaller value among them, is the set of information indices corresponding to the first layer and the minimum Hamming weight It is the number of elements included in the intersection of the set of bit indices of row vectors having, and is the set excluding the elements included in the information index set corresponding to the first layer from the maximum information index set, the information index set corresponding to the first layer, and the minimum Hamming weight An electronic device that is the number of elements included in the intersection of the set of bit indices of row vectors having 12. In Paragraph 11, The above The index is the above minimum Hamming weight Among row vectors having It satisfies, and And, is the above-mentioned maximum information index set, and is the binary support of vector x, and is the minimum Hamming weight in the polar sign generation matrix It is a specific row vector having, is in the above polar sign generation matrix It is a specific row vector corresponding to, and And, An electronic device, wherein N is the codeword length corresponding to the above dip polarity code.

13. In Paragraph 11, The set of connection indices associated with the connection bits of the above l-layer input vector is: The above included in the set of information indexes corresponding to the first layer above Number of indices; and The highest reliability included in the set excluding the elements of the information index set corresponding to the first layer from the above maximum information index set Includes indexes, Among the connection bits of the above l-layer input vector, the one with the highest reliability Related to the index An electronic device in which information bits are mapped to connection bits.

14. In Paragraph 13, In the set of information indices corresponding to the first layer mentioned above, the The lowest confidence level excluding the index Includes indexes, An electronic device, which is the codeword length corresponding to the first layer above.

15. In Paragraph 13, The size of the above set of linked indices is And, Electronic device, integer.

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