Transmission chip, transmission method, chip system, optical module and transmission apparatus

Abstract

The present application relates to the technical field of chips. Provided are a transmission chip, a transmission method, a chip system, an optical module and a transmission apparatus. The transmission chip comprises a plurality of receiving ends and a plurality of receiving channels, wherein the plurality of receiving channels include a first receiving channel and a second receiving channel; the first receiving channel comprises a clock input end, and the second receiving channel comprises a clock output end; the plurality of receiving ends are coupled to the plurality of receiving channels in a manner of corresponding to each other on a one-to-one basis; and the clock input end of the first receiving channel is coupled to the clock output end of the second receiving channel. In this way, the start time of a transmission path where the first receiving channel is located can be reduced.

Description

A transmission chip, a transmission method, a chip system, an optical module, and a transmission device.

[0001] This application claims priority to Chinese Patent Application No. 202411588027.7, filed on November 7, 2024, entitled "A transmission chip, transmission method, chip system, optical module and transmission device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a transmission chip, transmission method, chip system, optical module, and transmission device. Background Technology

[0003] High-speed interconnect communication systems can include multiple chips, each chip can include multiple channels (transmitting or receiving channels) and transmission ports (transmitting or receiving ends) coupled to each channel. Channels are used to convert data into a form suitable for transmission or processing, and transmission ports are used to transmit the data. During data transmission, the data flow rate varies, sometimes large and sometimes small. When multiple chips transmit data, these chips can dynamically activate channels. For example, when the data flow rate is large, these chips can activate all channels, thereby increasing interconnect bandwidth; when the data flow rate is small, these chips can activate some channels and deactivate others, thereby reducing power consumption. This maximizes dynamic energy-saving benefits. When the flow rate increases, some previously deactivated channels need to be restarted, and multiple chips transmit data through the restarted channels. During this process, the clock of one chip transmitting data may be out of sync with the clock of another chip receiving the data. After receiving the data, the receiving chip's channel needs to synchronize its clock with the transmitting chip's channel. However, the channel clock synchronization time is long, resulting in a long startup time for the transmission path containing that channel. Summary of the Invention

[0004] This application provides a transmission chip, transmission method, chip system, optical module, and transmission device, which solves the problem of long startup time of transmission paths in the prior art.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a transmission chip is provided, comprising multiple receiving ends and multiple receiving channels, including a first receiving channel and a second receiving channel. The first receiving channel includes a clock input terminal, and the second receiving channel includes a clock output terminal. The multiple receiving ends are coupled one-to-one with the multiple receiving channels. The clock input terminal of the first receiving channel is coupled to the clock output terminal of the second receiving channel.

[0007] In the above technical solution, the clock input terminal of the first receiving channel is coupled to the clock output terminal of the second receiving channel. The first receiving channel can receive clock information from the second receiving channel through its clock input terminal. The first receiving channel can directly receive clock information without needing to process the data through a clock circuit to obtain clock information. Obtaining clock information by processing the data through a clock circuit takes longer than directly receiving clock information. Therefore, this implementation has a shorter startup time. This implementation can reduce the startup time of the path containing the first receiving channel from the 100 microsecond level to the nanosecond level. This can reduce service scenarios with microsecond-level message gaps and meet the requirements of low-power interconnect functions.

[0008] In one possible implementation of the first aspect, both the first and second receiving channels include clock circuits. The clock input of the first receiving channel is coupled to its clock circuit. The clock output of the second receiving channel is coupled to its clock circuit. In this possible implementation, the clock circuit of the second receiving channel can output clock information to the clock circuit coupled to the clock input of the first receiving channel through its clock output. This results in a simpler circuit and faster clock information transmission.

[0009] In one possible implementation of the first aspect, both the first and second receiving channels include buffers. The clock input of the first receiving channel is coupled to its clock circuit via the buffer. The clock output of the second receiving channel is coupled to its clock circuit via the buffer. In this possible implementation, the clock circuit of the second receiving channel can store clock information in the buffer of the second receiving channel. The buffer of the first receiving channel can read clock information from the buffer coupled to the clock output of the second receiving channel via its clock input. The clock circuit of the first receiving channel can read clock information from its buffer. The buffer can store and transmit a larger amount of clock information, allowing the first receiving channel to directly acquire more clock information, resulting in a faster startup time.

[0010] In one possible implementation of the first aspect, the first receiving channel further includes an equalization input terminal, and the second receiving channel further includes an equalization output terminal. The equalization input terminal of the first receiving channel is coupled to the equalization output terminal of the second receiving channel. In the above possible implementation, the equalization input terminal of the first receiving channel is coupled to the equalization output terminal of the second receiving channel. The first receiving channel can receive the equalization information of the second receiving channel through the equalization input terminal. The first receiving channel does not need to process the equalization information through an equalization circuit to obtain the equalization information, but directly receives the equalization information. The time to obtain the equalization information through the equalization circuit is longer than the time to directly receive the equalization information. Therefore, the startup time of this embodiment is shorter.

[0011] In one possible implementation of the first aspect, both the first and second receiving channels include equalization circuits. The equalization input of the first receiving channel is coupled to the equalization circuit of the first receiving channel. The equalization output of the second receiving channel is coupled to the equalization circuit of the second receiving channel. In this possible implementation, the equalization circuit of the second receiving channel can output equalization information to the equalization circuit coupled to the equalization input of the first receiving channel through its equalization output. This results in a simpler circuit and faster transmission speed of the equalization information.

[0012] In one possible implementation of the first aspect, both the first and second receiving channels include buffers. The equalization input of the first receiving channel is coupled to the equalization circuit of the first receiving channel through the buffer. The equalization output of the second receiving channel is coupled to the equalization circuit of the second receiving channel through the buffer. In the above possible implementation, the equalization circuit of the second receiving channel can store equalization information in the buffer of the second receiving channel. The buffer of the first receiving channel can read equalization information from the buffer coupled to the equalization output of the second receiving channel through the equalization input of the first receiving channel. The equalization circuit of the first receiving channel can read equalization information from the buffer of the first receiving channel. The buffer can store and transmit more equalization information, the first receiving channel can directly obtain more equalization information, and the startup time is faster.

[0013] In one possible implementation of the first aspect, a transmission chip is configured to, in response to a start command, control a first receiving channel to input equalization information from the equalization output of a second receiving channel through the equalization input terminal of the first receiving channel. In this possible implementation, the first receiving channel can receive the equalization information from the second receiving channel through the equalization input terminal. The first receiving channel does not need to process the equalization information through an equalization circuit to obtain it; instead, it directly receives the equalization information. The time required to process the equalization information through an equalization circuit is longer than the time required to directly receive the equalization information. Therefore, this implementation has a shorter start-up time.

[0014] In one possible implementation of the first aspect, a transmission chip, in response to a start command, controls a first receiving channel to input clock information from the clock output of a second receiving channel through the clock input terminal of the first receiving channel. The clock information includes frequency information, or the clock information includes both frequency and phase information. In the above possible implementations, when the clock information includes frequency information, the first receiving channel can directly receive the frequency information. The first receiving channel does not need frequency synchronization via a clock circuit, thus reducing the start-up time. The transmission chip and the transmitting chip do not need physical wiring with the master clock, thus reducing costs. The absence of network-wide clock synchronization also reduces the start-up time. When the clock information includes both phase and frequency information, the first receiving channel can directly receive both frequency and phase information. The first receiving channel does not need frequency and phase synchronization via a clock circuit, thus reducing the start-up time. The transmission chip and the transmitting chip do not need physical wiring with the master clock, thus reducing costs. The absence of network-wide clock synchronization also reduces the start-up time. The first receiving channel does not need to transmit clock information between chips, thus eliminating the need to consume bandwidth resources.

[0015] Secondly, a transmission chip is provided, comprising multiple receiving ends and multiple receiving channels, including a first receiving channel, which includes a buffer. The multiple receiving ends are coupled one-to-one with the multiple receiving channels. The transmission chip is used to control the first receiving channel to store clock information in its buffer in response to a shutdown command. The transmission chip is also used to control the first receiving channel to read clock information from its buffer in response to a startup command. The clock information includes frequency information.

[0016] In the above technical solution, the first receiving channel can store clock information in a buffer before shutting down and read the clock information from the buffer after startup. The first receiving channel can directly read the frequency information in the buffer. The first receiving channel does not require frequency synchronization through a clock circuit, thus resulting in a shorter startup time. The transmission chip and the transmitting chip do not require physical wiring with the master clock, thus reducing costs. The absence of network-wide clock synchronization also shortens the startup time. This implementation can reduce the startup time of the path containing the first receiving channel from the 100 microsecond level to the nanosecond level. This can reduce service scenarios with microsecond-level message gaps and meet the requirements of low-power interconnect functionality. Furthermore, when data traffic is low, the first receiving channel can be shut down, or other receiving channels can be shut down. The bandwidth adjustment method is relatively flexible.

[0017] In one possible implementation of the second aspect, the transmission chip is further configured to, in response to a shutdown command, control the first receiving channel to store equalization information in its buffer. The transmission chip is also configured to, in response to a startup command, control the first receiving channel to read equalization information from its buffer. In the above possible implementations, the first receiving channel can store equalization information in its buffer before shutdown and read it from the buffer after startup. The first receiving channel does not need to process the equalization information through an equalization circuit to obtain it; instead, it directly reads the equalization information from the buffer. Since the time required to process the equalization information through the equalization circuit is longer than the time required to directly read the equalization information from the buffer, the startup time of this implementation is shorter. Furthermore, the equalization information of the first receiving channel does not depend on the equalization information of other receiving channels. Even if other receiving channels are shut down, the first receiving channel can still read the equalization information. Therefore, when data traffic is low, it is possible to choose to shut down the first receiving channel or other receiving channels. The bandwidth adjustment method is more flexible.

[0018] In one possible implementation of the first or second aspect, the plurality of receiving channels further includes a second receiving channel. The transmission chip is also configured to receive a shutdown command from a receiving end correspondingly coupled to the first or second receiving channel. In the above possible implementations, the shutdown command can be received via either the first or second receiving channel. Transmitting control information via a data channel saves on control channels. Furthermore, transmitting the startup command simultaneously with data transmission results in faster transmission speed. Therefore, startup time can be further reduced.

[0019] In one possible implementation of the first or second aspect, the transmission chip is used to couple the processor. The transmission chip is also used to receive shutdown instructions from the processor. In the above possible implementations, the processor can receive shutdown instructions, and the processor can centrally schedule the shutdown of the transmission chip's channels. This simplifies the circuitry.

[0020] In one possible implementation of the first or second aspect, the plurality of receiving channels further includes a second receiving channel. The transmission chip is also configured to receive a start command from a receiving end correspondingly coupled to the second receiving channel. In the above possible implementations, the start command can be received through either the first or second receiving channel. Transmitting control information through a data channel saves on control channels. Furthermore, transmitting the start command simultaneously with data transmission results in faster transmission speed. Therefore, start-up time can be further reduced.

[0021] In one possible implementation of the first or second aspect, the transmission chip is used to couple the processor. The transmission chip is also used to receive a startup command from the processor. In the above possible implementations, the processor can receive the startup command, and the processor can centrally schedule the startup of the transmission chip's channels. This simplifies the circuitry.

[0022] In one possible implementation of the first or second aspect, the transmission chip is further configured to receive data through a receiving end correspondingly coupled to the first receiving channel after receiving a start command. In the above possible implementations, the start command can be received first, clock synchronization can be performed according to the start command, and then data can be received, with the synchronized clock signal used to sample the data. Therefore, start-up time can be further reduced.

[0023] Thirdly, a transmission method is provided, applied to a transmission chip. The transmission chip includes multiple receiving ends and multiple receiving channels, including a first receiving channel and a second receiving channel. The first receiving channel includes a clock input terminal, and the second receiving channel includes a clock output terminal. The multiple receiving ends are coupled one-to-one with the multiple receiving channels. The clock input terminal of the first receiving channel is coupled to the clock output terminal of the second receiving channel. The transmission method includes: receiving a start command. In response to the start command, controlling the first receiving channel to input clock information from the clock output terminal of the second receiving channel through the clock input terminal of the first receiving channel. The clock information includes frequency information, or the clock information includes both frequency information and phase information.

[0024] In one possible implementation of the third aspect, the first receiving channel further includes an equalization input terminal, and the second receiving channel further includes an equalization output terminal. The equalization input terminal of the first receiving channel is coupled to the equalization output terminal of the second receiving channel. The transmission method further includes: in response to a start command, controlling the first receiving channel to input equalization information from the equalization output terminal of the second receiving channel through the equalization input terminal of the first receiving channel.

[0025] Fourthly, a transmission method is provided, applied to a transmission chip. The transmission chip includes multiple receiving ends and multiple receiving channels, including a first receiving channel, which includes a buffer. Each receiving end is coupled to one of the multiple receiving channels. The transmission method includes: receiving a shutdown command; responding to the shutdown command, controlling the first receiving channel to store clock information in its buffer; and receiving a startup command; responding to the startup command, controlling the first receiving channel to read clock information from its buffer. The clock information includes frequency information.

[0026] In one possible implementation of the fourth aspect, the transmission method further includes: in response to a shutdown command, controlling the first receiving channel to store equalization information in the buffer of the first receiving channel; and in response to a startup command, controlling the first receiving channel to read equalization information from the buffer of the first receiving channel.

[0027] In one possible implementation of the third or fourth aspect, the plurality of receiving channels further includes a second receiving channel. Receiving a shutdown command includes receiving a shutdown command from a receiving end correspondingly coupled to the first or second receiving channel.

[0028] In one possible implementation of the third or fourth aspect, the transmission chip is used to couple the processor. Receiving a shutdown instruction includes: receiving a shutdown instruction from the processor.

[0029] In one possible implementation of the third or fourth aspect, the plurality of receiving channels further includes a second receiving channel. Receiving a start command includes receiving a start command from a receiving end correspondingly coupled to the second receiving channel.

[0030] In one possible implementation of the third or fourth aspect, the transmission chip is used to couple the processor. Receiving a startup instruction includes: receiving a startup instruction from the processor.

[0031] In one possible implementation of the third or fourth aspect, the transmission method further includes: receiving data through the receiving end corresponding to the first receiving channel after receiving the start command.

[0032] Fifthly, a chip system is provided, comprising a transmitting chip and a transmission chip provided by the first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect. The transmitting chip is used to transmit data with the transmission chip.

[0033] In one possible implementation of the fifth aspect, the transmitting chip sends a start command to the transmitting chip when a recovery command is sent. The recovery command is used to start the transmitting chip.

[0034] Sixthly, an optical module is provided, comprising an optical signal receiver and a transmission chip provided by the first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect. The optical signal receiver is coupled to the transmission chip.

[0035] A seventh aspect provides a transmission device comprising a circuit board and a transmission chip provided by the first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect. The transmission chip is disposed on the circuit board.

[0036] In another aspect, this application provides a computer-readable storage medium storing program code that can be invoked to execute the transmission method provided by the third aspect, any possible implementation of the third aspect, the fourth aspect, or any possible implementation of the fourth aspect.

[0037] In another aspect, this application provides a computer program product that, when run on a computer, causes the computer to perform the transmission method provided by the third aspect, the fourth aspect, any possible implementation of the third aspect, or any possible implementation of the fourth aspect.

[0038] Understandably, any of the transmission methods, systems, optical modules, devices, computer storage media, or computer program products provided above are used in the corresponding transmission chips provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding transmission chips provided above, and will not be repeated here. Attached Figure Description

[0039] Figure 1 is a schematic diagram of a first transmission device provided in an embodiment of this application;

[0040] Figure 2 is a schematic diagram of a second transmission device provided in an embodiment of this application;

[0041] Figure 3 is a schematic diagram of a first transmission chip, a second transmission chip, and a third transmission chip provided in an embodiment of this application;

[0042] Figure 4 is a schematic diagram of phase synchronization provided in an embodiment of this application;

[0043] Figure 5 is a schematic diagram of a second transmission chip provided in an embodiment of this application;

[0044] Figure 6 is a schematic diagram of a receiving channel provided in an embodiment of this application;

[0045] Figure 7 is a schematic diagram of a receiving channel provided in an embodiment of this application;

[0046] Figure 8 is a schematic diagram of a receiving channel provided in an embodiment of this application;

[0047] Figure 9 is a schematic diagram of a transmission method provided in an embodiment of this application;

[0048] Figure 10 is a schematic diagram of a transmission method provided in an embodiment of this application;

[0049] Figure 11 is a schematic diagram of a transmission method provided in an embodiment of this application. Detailed Implementation

[0050] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0051] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0052] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0053] First, the application scenarios of the embodiments of this application will be introduced. The embodiments of this application can be applied to transmission devices with data transmission functions. This transmission device can be an electronic device or a component of an electronic device, such as a chip embedded in the electronic device. The electronic device includes, but is not limited to: switches, mobile phones, tablets, computers, laptops, cameras, wearable devices, vehicle-mounted devices, or terminal devices, etc.

[0054] The following description uses a switch as an example of a transmission device. As shown in Figures 1 and 2, the first transmission device 1000A may include a first transmission chip 1100A, a first circuit board 1200A, a first switching board 1300A, and a first processor 1400A. The first transmission chip 1100A and the first processor 1400A may be disposed on the first circuit board 1200A. The second transmission device 1000B may include a second transmission chip 1100B, a second circuit board 1200B, a second switching board 1300B, and a second processor 1400B. The second transmission chip 1100B and the second processor 1400B may be disposed on the second circuit board 1200B. The first transmission device 1000A can communicate with the second transmission device 1000B.

[0055] The first circuit board 1200A may include multiple pins, such as the pins in Figure 1 and inter-integrated circuit (I2C) bus pins. The first circuit board 1200A can be coupled to the first switching board 1300A through multiple pins. The first transmission chip 1100A may include multiple receive channels, multiple receiver terminals RX, multiple transmit channels, and multiple transmit terminals TX. For example, transmit channels (line transmit, LTX) 11A, 12A, ..., and 1nA for transmitting data to the other side transmission device (e.g., the second transmission device 1000B), receive channels (line receiver, LRX) 21A, 22A, ..., and 2nA for receiving data from the other side transmission device, host receiver (HRX) 31A, 32A, ..., and 3nA for receiving data from the coupled switching board (e.g., the first switching board 1300A), and host transmit channels (host transmit, HTX) 41A, 42A, ..., and 4nA for transmitting data to the coupled switching board.

[0056] The first transmission device 1000A and the second transmission device 1000B can be optical switches with optical transceiver functions, and the first transmission device 1000A and the second transmission device 1000B can be connected by optical fiber. Alternatively, the first transmission device 1000A and the second transmission device 1000B can be electrical switches, and the first transmission device 1000A and the second transmission device 1000B can be coupled by electrical interconnection, such as a data cable. This application does not limit the scope of these embodiments. The following description uses the example of the first transmission device 1000A and the second transmission device 1000B being optical switches.

[0057] The first circuit board 1200A may also include a driver (DRV), such as DRV51A, 52A, ..., and 5nA. The DRV is used to amplify the output current or voltage. The first circuit board 1200A may also include a trans-impedance amplifier (TIA), such as TIA61A, 62A, ..., and 6nA. The TIA is used to convert (or amplify) the input voltage into a voltage output. The first circuit board 1200A may also include a laser diode (LD), such as LD71A, 72A, ..., and 7nA. The LD is used to convert electrical signals into optical signals. The first circuit board 1200A may also include a photo diode (PD), such as PD81A, 82A, ..., and 8nA. The PD is used to convert optical signals into electrical signals. Each of the transmission channels 11A, 12A, ..., and 1nA is coupled to a transmitter TX. Multiple transmitters (TX) corresponding to transmit channels 11A, 12A, ..., and 1nA can be coupled one-to-one with DRV51A, 52A, ..., and 5nA. DRV51A, 52A, ..., and 5nA can be coupled one-to-one with LD71A, 72A, ..., and 7nA. Each receive channel in receive channels 21A, 22A, ..., and 2nA is coupled to one receiver (RX). Multiple receivers (RX) corresponding to receive channels 21A, 22A, ..., and 2nA can be coupled one-to-one with TIA61A, 62A, ..., and 6nA. TIA61A, 62A, ..., and 6nA can be coupled one-to-one with PD81A, 82A, ..., and 8nA. The first processor 1400A can be coupled to the I2C pin and the first transmission chip 1100A. The first transmission chip 1100A and the first processor 1400A can be coupled to multiple DRVs, multiple LDs, multiple TIAs, and multiple PDs. Pins can be coupled to the first transmission chip 1100A. The first processor 1400A can be used to control the operation of the various circuits it is coupled to.

[0058] The second circuit board 1200B may include multiple pins, such as the pin pins and I2C bus pins shown in Figure 2. The second circuit board 1200B can be coupled to the second switching board 1300B via multiple pins. The second transmission chip 1100B may include multiple receive channels, multiple receive terminals RX, multiple transmit channels, and multiple transmit terminals TX. For example, receive channels 11B, 12B, ..., and 1nB are used to receive data from the opposite transmission device (e.g., the first transmission device 1000A); transmit channels 21B, 22B, ..., and 2nB are used to transmit data to the opposite transmission device; transmit channels 31B, 32B, ..., and 3nB are used to transmit data to the coupled switching board (e.g., the second switching board 1300B); and receive channels 41B, 42B, ..., and 4nB are used to receive data from the coupled switching board.

[0059] The second circuit board 1200B may further include TIA51B, 52B, ..., and 5nB. The second circuit board 1200B may further include DRV61B, 62B, ..., and 6nB. The second circuit board 1200B may further include PD71B, 72B, ..., and 7nB. The second circuit board 1200B may further include LD81B, 82B, ..., and 8nB. Each of the receive channels 11B, 12B, ..., and 1nB is coupled to a receiver RX. Multiple receiver RXs corresponding to receive channels 11B, 12B, ..., and 1nB can be coupled one-to-one with TIA51B, 52B, ..., and 5nB. TIA51B, 52B, ..., and 5nB can be coupled one-to-one with PD71B, 72B, ..., and 7nB. Each of the transmit channels 21B, 22B, ..., and 2nB is coupled to a transmitter TX. Multiple transmitters (TX) corresponding to transmission channels 21B, 22B, ..., and 2nB can be coupled one-to-one with DRV61B, 62B, ..., and 6nB. DRV61B, 62B, ..., and 6nB can be coupled one-to-one with LD81B, 82B, ..., and 8nB. The second processor 1400B can be coupled to the pin I2C pin and to the second transmission chip 1100B. The second transmission chip 1100B and the second processor 1400B can be coupled to multiple TIAs, multiple DRVs, multiple PDs, and multiple LDs. The pin can be coupled to the second transmission chip 1100B. The second processor 1400B can be used to control the operation of its coupled circuits.

[0060] The first switching board 1300A can be used to couple the first main chip (not shown in Figure 1). The first main chip can transmit parallel data to the first transmission chip 1100A through the first switching board 1300A. The first transmission chip 1100A can receive parallel data through the receiving terminals RX corresponding to the receiving channels 31A to 3nA, and process this parallel data through the receiving channels 31A to 3nA. The first transmission chip 1100A can transmit this parallel data to the DRV51A to 5nA through the transmitting terminals TX corresponding to the transmitting channels 11A to 1nA. The DRV51A to 5nA can amplify this parallel data and transmit the amplified parallel data to the LD71A to 7nA. The parallel data received by the LD71A to 7nA is an electrical signal. The LD71A to 7nA can convert this electrical signal into an optical signal and transmit the optical signal to the optical fiber. These optical signals are transmitted through the optical fiber to the PD71B to 7nB on the second circuit board 1200B. PD71B-7nB can convert optical signals into current signals and send these current signals to TIA51B-5nB. TIA51B-5nB can convert these current signals into voltage signals, i.e., parallel data. TIA51B-5nB can send the parallel data to the second transmission chip 1100B. The second transmission chip 1100B can receive the parallel data through the receiving terminals RX corresponding to the receiving channels 11B-1nB, and process this parallel data through the receiving channels 11B-1nB. The second transmission chip 1100B can send parallel data to the second switching board 1300B through the transmitting terminals TX corresponding to the transmitting channels 31B-3nB. The second switching board 1300B can be used to couple the second main chip (not shown in Figure 2). The second switching board 1300B can transmit parallel data to the second main chip. In this way, the first main chip can communicate with the second main chip through the first transmission device 1000A and the second transmission device 1000B.

[0061] The structures of the first transmission device 1000A and the second transmission device 1000B shown in the embodiments of this application are merely illustrative. In practice, the first transmission device 1000A and the second transmission device 1000B may include more or fewer devices and connection structures.

[0062] In high-speed interconnected communication systems, traffic flow exhibits tidal and periodic models. During data transmission, data volume varies, sometimes high and sometimes low. Channels can be dynamically activated during data transmission. For example, during data transmission from the first transmission device 1000A to the second transmission device 1000B, when data volume is high, transmission channels 11A-1nA and reception channels 11B-1nB can be activated to increase interconnection bandwidth. When data volume is low, transmission channels 11A and 11B can be activated, while transmission channels 12A-1nA and 12B-1nB can be deactivated, reducing power consumption of both devices. This maximizes dynamic energy savings. When data volume increases, some previously deactivated channels need to be restarted, such as transmission channel 12A and reception channel 12B. The first transmission device 1000A and the second transmission device 1000B then transmit data through these restarted channels. When transmitting channel 12A and receiving channel 12B restart (or due to environmental factors such as temperature changes), the clock for transmitting data via transmitting channel 12A may be inconsistent with the clock for receiving data via receiving channel 12B. After receiving the data, receiving channel 12B needs to synchronize its clock with transmitting channel 12A. Clock synchronization includes frequency synchronization and phase synchronization.

[0063] In one possible implementation, the receiving channel includes a clock circuit that provides a clock signal. The receiving channel can achieve phase and frequency synchronization via the clock circuit. The clock circuit may, for example, include a clock data recovery (CDR) circuit or a time recovery (TR) circuit.

[0064] For example, a clock circuit may include a filter. The purpose of using a filter is to integrate the rapid phase change information and convert it into a relatively slow voltage change to adjust the output frequency of the voltage-controlled oscillator (VCO). The filter can be a loop filter, such as a low-pass filter (LPF). Through repeated phase detection and adjustment, the frequency of the VCO's output signal eventually matches the frequency of the input digital signal, at which point the phase-locked loop (PLL) enters a locked state.

[0065] In this implementation, the receiving channel takes a relatively long time to synchronize phase and frequency using the clock circuit. This results in a longer startup time for the transmission path containing the receiving channel.

[0066] In another possible implementation, both the transmitting-side and receiving-side transmission chips are physically coupled to the master clock, and the transmitting and receiving channels can be frequency synchronized through the clock physical wiring. As shown in Figure 3, taking this embodiment as an example applied to a data center, the data center includes multiple nodes, and each node includes multiple transmission chips. For example, the first transmission chip 1100A, the second transmission chip 1100B, and the third transmission chip 1100C in the data center are physically coupled to the master clock 1003. The first transmission chip 1100A includes a transmitting channel 11A and a receiving channel 21A. The second transmission chip 1100B includes a receiving channel 11B and a transmitting channel 21B. The third transmission chip 1100C includes a transmitting channel 11C and a receiving channel 21C. Transmitting channels 11A and 11C are coupled to the receiving channel 11B via a first optical switch 1001, and the transmitting channel 21B is coupled to the receiving channels 21A and 21C via a second optical switch 1002. The first optical switch 1001 and the second optical switch 1002 can be used to select the receiving channel. When the transmission path between the transmitting channel 11A and the receiving channel 11B is started, the clock signal of the master clock 1003 can be received through physical wiring. Both the transmitting channel 11A and the receiving channel 11B use the frequency of the clock signal of the master clock 1003 to achieve frequency synchronization.

[0067] In one example, based on the physical clock wiring, the receiving channel can achieve phase synchronization via a clock circuit. In this example, the phase synchronization time is relatively long. For frequency synchronization, frequency synchronization via physical clock wiring is faster than frequency synchronization via a clock circuit. Therefore, the overall startup time of this example is shorter. However, this implementation method requires complex physical wiring and is costly to achieve full network node clock synchronization.

[0068] In another example, based on the physical clock wiring, the receiving channel can send phase offset information to the transmitting channel. The transmitting channel can then buffer the phase offset in a phase buffer to achieve phase synchronization. As shown in Figure 4, transmitting channel 11A sends data to receiving channel 11B using a random phase offset 1. Receiving channel 11B obtains phase offset 2 based on the received data using a clock circuit. Receiving channel 11B sends phase offset 2 to transmitting channel 11A. Transmitting channel 11A obtains phase offset 3 based on phase offset 2 using a clock circuit. Transmitting channel 11A buffers phase offset 3 in a phase buffer. When the transmission path between transmitting channel 11A and receiving channel 11B restarts, the transmitting channel uses phase offset 3 to send data, thus achieving phase synchronization. In this example, for frequency synchronization, frequency synchronization via physical clock wiring is faster than frequency synchronization via a clock circuit. Therefore, the startup time of this example is shorter. However, this implementation method requires more complex physical wiring and is more costly to achieve full network node clock synchronization. For phase synchronization, when the transmission path restarts, the transmitting channel can use phase offset 3 in the phase buffer for phase synchronization, resulting in a relatively fast transmission path startup. However, the transmitting channel's phase buffer needs to periodically update the stored phase offset 3, and the receiving channel needs to periodically send phase offset 2 to the transmitting channel. This leads to longer information transmission times between chips and consumes bandwidth resources.

[0069] Based on this, embodiments of this application provide a transmission chip. The receiving channels of this transmission chip can transmit clock information. A restarted receiving channel can use the clock information of an unshutdowned receiving channel, thereby achieving clock synchronization.

[0070] In one possible implementation, the transmission chip includes multiple receivers and multiple receiver channels, including a first receiver channel and a second receiver channel. The first receiver channel includes a clock input terminal, and the second receiver channel includes a clock output terminal.

[0071] Multiple receivers are coupled one-to-one with multiple receiving channels. The clock input of the first receiving channel is coupled to the clock output of the second receiving channel. The transmission chip, in response to a start command, controls the first receiving channel to input clock information from the clock output of the second receiving channel through its clock input.

[0072] The clock information is used for clock synchronization. The clock information may include frequency information, or it may include both frequency and phase information. For example, the clock information may contain a complete clock signal, which includes both frequency and phase information. Alternatively, the clock information may contain a clock code, which may include frequency information (such as frequency offset), or it may include both frequency information (such as frequency offset) and phase information (such as phase offset or phase codeword (pi code)).

[0073] In one example, as shown in Figure 5, the transmission chip is the second transmission chip 1100B in Figure 2. The number of first receiving channels can be one or more. The number of second receiving channels can also be one or more; this embodiment does not limit this. For example, in Figure 5, the first receiving channel may include receiving channels 12B to 1nB. The second receiving channel may include receiving channel 11B. Receiving channel 11B includes a clock output terminal CLK OUT. Receiving channels 12B to 1nB all include a clock input terminal CLK IN. Receiving channels 11B to 1nB all include a clock circuit (not shown in Figure 5).

[0074] When the data flow is high, all receiving channels 11B to 1nB are activated, and a recovery clock is obtained through a clock circuit. This recovery clock can be a synchronized clock signal. When the data flow decreases, receiving channel 11B remains activated, while receiving channels 12B to 1nB are deactivated. When the data flow increases, receiving channels 12B to 1nB restart in response to a start command. At this time, the clock signal of receiving channel 11B is synchronized, while the clock signals of receiving channels 12B to 1nB are not synchronized. Receiving channels 12B to 1nB can each input clock information from the clock output CLK OUT of receiving channel 11B through their respective clock input terminal CLK IN. Receiving channels 12B to 1nB can obtain their recovery clock from this clock information. This is faster than obtaining the recovery clock through a clock circuit.

[0075] In this embodiment, the clock input terminal of the first receiving channel is coupled to the clock output terminal of the second receiving channel. The first receiving channel can receive clock information from the second receiving channel through its clock input terminal.

[0076] The following discussion covers the case where clock information includes frequency information.

[0077] Compared to methods that achieve phase and frequency synchronization via a clock circuit, the first receiving channel does not require frequency synchronization via a clock circuit and can directly receive frequency information. The first receiving channel only needs phase synchronization via a clock circuit. Since frequency synchronization via a clock circuit takes longer than directly receiving frequency information, this implementation has a shorter startup time.

[0078] Compared to methods that achieve phase synchronization via clock circuits and frequency synchronization via physical clock wiring, this implementation also uses clock circuits for phase synchronization. However, for frequency synchronization, the transmission chip and the transmitting chip in this implementation do not require physical wiring with the master clock, resulting in lower costs. It also eliminates the need for network-wide clock synchronization, leading to shorter startup times.

[0079] Compared to phase synchronization achieved through buffered phase offsets and frequency synchronization through physical clock wiring, this implementation eliminates the need for the first receiving channel to send a phase offset to the corresponding transmitting channel for phase synchronization. This saves time on information transmission between chips and avoids consuming bandwidth resources. For frequency synchronization, the transmitting and transmitting chips in this implementation do not require physical wiring with the master clock, resulting in lower costs. Furthermore, it eliminates the need for network-wide clock synchronization, leading to shorter startup times.

[0080] The following discussion covers the case where clock information includes both phase and frequency information.

[0081] Compared to methods that achieve phase and frequency synchronization via clock circuits, the first receiving channel does not require frequency and phase synchronization via clock circuits and can directly receive frequency and phase information. Frequency synchronization via clock circuits takes longer than directly receiving frequency information. Phase synchronization via clock circuits takes longer than directly receiving phase information. Therefore, this implementation has a shorter startup time.

[0082] Compared to methods that achieve phase synchronization via clock circuits and frequency synchronization via physical clock wiring, this implementation eliminates the need for phase synchronization via clock circuits and frequency synchronization via physical wiring with the master clock. Therefore, this implementation has a shorter startup time, lower cost, and eliminates the need for network-wide clock synchronization.

[0083] Compared to phase synchronization achieved through buffered phase offsets and frequency synchronization through physical clock wiring, this implementation eliminates the need for the first receiving channel to send a phase offset to the corresponding transmitting channel for phase synchronization. This saves time on information transmission between chips and avoids consuming bandwidth resources. For frequency synchronization, the transmitting and transmitting chips in this implementation do not require physical wiring with the master clock, resulting in lower costs. Furthermore, it eliminates the need for network-wide clock synchronization, leading to shorter startup times.

[0084] As can be seen, this implementation method has a shorter startup time, reducing the startup time of the path containing the first receiving channel from the 100 microsecond level to the nanosecond level. This reduces the need for microsecond-level message gaps in service scenarios, fulfilling the requirements for low-power interconnect functionality. It also improves system energy efficiency and increases effective bandwidth. Furthermore, it eliminates the need for network-wide clock synchronization.

[0085] In another possible implementation, the first receiving channel may include a clock output terminal, and the second receiving channel may include a clock input terminal. The clock output terminal of the first receiving channel is coupled to the clock input terminal of the second receiving channel. The transmission chip can also be used to control the second receiving channel to input clock information from the clock output terminal of the first receiving channel through the clock input terminal of the second receiving channel.

[0086] In one example, the clock input and clock output of the first receiving channel can be the same terminal. Similarly, the clock input and clock output of the second receiving channel can also be the same terminal.

[0087] In this implementation, the receiving channel, including the clock output, needs to remain active even when data traffic is low. If only the second receiving channel includes a clock output, then the second receiving channel must remain active during the dynamic channel activation process. This prevents flexible selection of which channel to disable. Both the first and second receiving channels include both clock inputs and clock outputs. The first and second receiving channels can transmit clock information to each other, rather than the second receiving channel only outputting clock information to the first receiving channel. When data traffic is low, either the first or second receiving channel can be disabled. This provides greater flexibility in bandwidth adjustment.

[0088] In one possible implementation, environmental factors such as channel restart or temperature changes can also affect channel quality, thus requiring channel equalization. The first receiving channel includes an equalization input, and the second receiving channel includes an equalization output. The equalization input of the first receiving channel is coupled to the equalization output of the second receiving channel. A transmission chip, in response to a start command, controls the first receiving channel to input equalization (EQ) information from the equalization output of the second receiving channel through its equalization input. This equalization information is used for channel equalization.

[0089] In one example, the transmission chip is the second transmission chip 1100B shown in Figure 5 (the equalization input and equalization output terminals are not shown in Figure 5). Receiver channels 11B to 1nB all include equalization circuitry (not shown in Figure 5). The equalization circuitry is used to equalize the data.

[0090] When data traffic is high, all receiving channels 11B to 1nB are active, and equalization information is obtained through the equalization circuit. When data traffic decreases, receiving channel 11B remains active, while receiving channels 12B to 1nB are deactivated. When data traffic increases again, receiving channels 12B to 1nB restart in response to a start command. At this point, receiving channel 11B contains equalization information, while receiving channels 12B to 1nB do not. Receiving channels 12B to 1nB can individually obtain equalization information from the equalization output of receiving channel 11B through their respective equalization input terminals. This is faster than receiving channels 12B to 1nB obtaining equalization information through the equalization circuit.

[0091] In this embodiment, the equalization input terminal of the first receiving channel is coupled to the equalization output terminal of the second receiving channel. The first receiving channel can receive the equalization information from the second receiving channel through the equalization input terminal. The first receiving channel does not need to process the equalization information through an equalization circuit to obtain the equalization information, but directly receives the equalization information. Since the time required to obtain the equalization information through the equalization circuit is longer than the time required to directly receive the equalization information, the startup time of this embodiment is shorter.

[0092] In another possible implementation, the first receiving channel may include an equalization output terminal, and the second receiving channel may include an equalization input terminal. The equalization output terminal of the first receiving channel is coupled to the equalization input terminal of the second receiving channel. The transmission chip can also be used to control the second receiving channel to input equalization information from the equalization output terminal of the first receiving channel through the equalization input terminal of the second receiving channel.

[0093] In one example, the equalization input and equalization output of the first receiving channel can be the same terminal. Similarly, the equalization input and equalization output of the second receiving channel can also be the same terminal.

[0094] The effect of this implementation can be compared with that of an implementation where the first receiving channel includes a clock output terminal and the second receiving channel includes a clock input terminal. That is, when the data traffic is low, either the first receiving channel or the second receiving channel can be turned off. The bandwidth adjustment method is quite flexible. Further details of the embodiments in this application will not be elaborated here.

[0095] In one possible implementation, both the first receiving channel and the second receiving channel include clock circuits. The clock input terminal of the first receiving channel is coupled to the clock circuit of the first receiving channel. The clock output terminal of the second receiving channel is coupled to the clock circuit of the second receiving channel.

[0096] In one possible implementation, both the first receiving channel and the second receiving channel include equalization circuits. The equalization input terminal of the first receiving channel is coupled to the equalization circuit of the first receiving channel. The equalization output terminal of the second receiving channel is coupled to the equalization circuit of the second receiving channel.

[0097] The internal structure of the receiving channel will be illustrated below with reference to Figures 6(a) and 6(b). Taking the second receiving chip 1100B in Figure 2 as an example, the second receiving channel may include receiving channel 11B. The first receiving channel may include receiving channel 12B. Receiving channel 11B may include a first sampling circuit 110B, a first clock circuit 120B, and a first equalization circuit 130B. The coupling method of each circuit can be referred to Figure 6(a). The first sampling circuit 110B is used to couple the receiving terminal RX corresponding to receiving channel 11B. Receiving channel 12B may include a second sampling circuit 210B, a second clock circuit 220B, and a second equalization circuit 230B. The coupling method of each circuit can be referred to Figure 6(b). The second sampling circuit 210B is used to couple the receiving terminal RX corresponding to receiving channel 12B. The first sampling circuit 110B and the second sampling circuit 210B can be sample and hold (SH) circuits.

[0098] The first clock circuit 120B is coupled to both the clock output terminal CLK OUT and the clock input terminal CLK IN of the receiving channel 11B. The second clock circuit 220B is coupled to both the clock output terminal CLK OUT and the clock input terminal CLK IN of the receiving channel 12B. The clock output terminal CLK OUT of the receiving channel 11B is coupled to the clock input terminal CLK IN of the receiving channel 12B. The clock input terminal CLK IN of the receiving channel 11B is coupled to the clock output terminal CLK OUT of the receiving channel 12B. The first equalizer circuit 130B is coupled to both the equalizer output terminal EQ OUT and the equalizer input terminal EQ IN of the receiving channel 11B. The second equalizer circuit 230B is coupled to both the equalizer output terminal EQ OUT and the equalizer input terminal EQ IN of the receiving channel 12B. The equalizer output terminal EQ OUT of the receiving channel 11B is coupled to the equalizer input terminal EQ IN of the receiving channel 12B. The equalizer input terminal EQ IN of the receiving channel 11B is coupled to the equalizer output terminal EQ OUT of the receiving channel 12B.

[0099] The data received by the first sampling circuit 110B from the corresponding receiving terminal RX, and the data received by the second sampling circuit 210B from the corresponding receiving terminal RX, are analog signals. The first sampling circuit 110B and the second sampling circuit 210B are used to sample the input analog signals according to a clock signal to obtain digital signals. The first clock circuit 120B is used to provide a clock signal to the first sampling circuit 110B. The second clock circuit 220B is used to provide a clock signal to the second sampling circuit 210B. The first equalization circuit 130B and the second equalization circuit 230B are used to equalize the digital signals.

[0100] In one example, the second transmission chip 1100B starts working, at which time the data flow is large, and both the receiving channel 11B and the receiving channel 12B are turned on.

[0101] The first sampling circuit 110B receives data, which is a first analog signal, from the corresponding coupled receiving terminal RX. The first clock circuit 120B is used to input a local clock and outputs the local clock to the first sampling circuit 110B. The first sampling circuit 110B samples the first analog signal according to the local clock to obtain a first digital signal. The first sampling circuit 110B outputs the first digital signal to the first clock circuit 120B and the first equalization circuit 130B. The first equalization circuit 130B obtains equalization information based on the first digital signal. The first equalization circuit 130B equalizes the first digital signal according to the equalization information and outputs the equalized first digital signal. The first clock circuit 120B processes the first digital signal to obtain a recovered clock. The first clock circuit 120B outputs the recovered clock to the first sampling circuit 110B. The first sampling circuit 110B samples subsequent input digital signals according to the recovered clock.

[0102] The second sampling circuit 210B receives data, which is a second analog signal, from the corresponding coupled receiving terminal RX. The second clock circuit 220B is used to input a local clock and outputs the local clock to the second sampling circuit 210B. The second sampling circuit 210B samples the second analog signal according to the local clock to obtain a second digital signal. The second sampling circuit 210B outputs the second digital signal to the second clock circuit 220B and the second equalization circuit 230B. The second equalization circuit 230B obtains equalization information from the second digital signal. The second equalization circuit 230B equalizes the second digital signal according to the equalization information and outputs the equalized second digital signal. The second clock circuit 220B processes the second digital signal to obtain a recovered clock. The second clock circuit 220B outputs the recovered clock to the second sampling circuit 210B. The second sampling circuit 210B samples subsequent input digital signals according to the recovered clock.

[0103] As the data flow decreases, receiving channel 11B remains open while receiving channel 12B remains closed. During this process, the first clock circuit 120B of receiving channel 11B contains a recovery clock, and the first equalization circuit 130B contains equalization information.

[0104] As the data flow increases, receiving channel 12B restarts in response to the start command. The first clock circuit 120B outputs a recovery clock to the clock input CLK IN of receiving channel 12B via the clock output CLK OUT of receiving channel 11B. The first equalization circuit 130B outputs equalization information to the equalization input EQ IN of receiving channel 12B via the equalization output EQ OUT of receiving channel 11B.

[0105] The second sampling circuit 210B receives data, which is the third analog signal, from the corresponding coupled receiving terminal RX. The second clock circuit 220B outputs a recovery clock to the second sampling circuit 210B. The second sampling circuit 210B samples the third analog signal according to the recovery clock to obtain the third digital signal. The second sampling circuit 210B outputs the third digital signal to the second equalization circuit 230B. The second equalization circuit 230B equalizes the third digital signal according to the equalization information and outputs the equalized third digital signal.

[0106] As can be seen, after the receiving channel 12B restarts, there is no need to recover the clock based on the digital signal sampled from the local clock. Furthermore, there is no need to obtain equalization information based on the digital signal sampled from the local clock. This saves considerable time.

[0107] In one possible implementation, both the first and second receiving channels include buffers. The clock input of the first receiving channel is coupled to the clock circuit of the first receiving channel through the buffer. The clock output of the second receiving channel is coupled to the clock circuit of the second receiving channel through the buffer.

[0108] In one possible implementation, both the first and second receiving channels include buffers. The equalization input of the first receiving channel is coupled to the equalization circuit of the first receiving channel through the buffer. The equalization output of the second receiving channel is coupled to the equalization circuit of the second receiving channel through the buffer.

[0109] The internal structure of the transmission channel will be illustrated below with reference to Figures 7(a) and 7(b). Taking the second transmission chip 1100B in Figure 2 as an example, the second receiving channel may include receiving channel 11B. The first receiving channel may include receiving channel 12B. Receiving channel 11B may include a first sampling circuit 110B, a first clock circuit 120B, a first equalization circuit 130B, and a first buffer 140B. The coupling method of each circuit can be referred to Figure 7(a). The first sampling circuit 110B is used to couple the receiving terminal RX corresponding to receiving channel 11B. Receiving channel 12B may include a second sampling circuit 210B, a second clock circuit 220B, a second equalization circuit 230B, and a second buffer 240B. The coupling method of each circuit can be referred to Figure 7(b). The second sampling circuit 210B is used to couple the receiving terminal RX corresponding to receiving channel 12B. The first sampling circuit 110B and the second sampling circuit 210B can be sample and hold (SH) circuits.

[0110] The first clock circuit 120B is coupled to the first buffer 140B. The first buffer 140B is coupled to both the clock output terminal CLK OUT and the clock input terminal CLK IN of the receive channel 11B. The second clock circuit 220B is coupled to the second buffer 240B. The second buffer 240B is coupled to both the clock output terminal CLK OUT and the clock input terminal CLK IN of the receive channel 12B. The clock output terminal CLK OUT of the receive channel 11B is coupled to the clock input terminal CLK IN of the receive channel 12B. The clock input terminal CLK IN of the receive channel 11B is coupled to the clock output terminal CLK OUT of the receive channel 12B. The first equalizer circuit 130B is coupled to the first buffer 140B. The first buffer 140B is coupled to both the equalizer output terminal EQ OUT and the equalizer input terminal EQ IN of the receive channel 11B. The second equalizer circuit 230B is coupled to the second buffer 240B. The second buffer 240B is coupled to both the equalizer output terminal EQ OUT and the equalizer input terminal EQ IN of the receive channel 12B. The equalization output terminal EQ OUT of the receiving channel 11B is coupled to the equalization input terminal EQ IN of the receiving channel 12B. The equalization input terminal EQ IN of the receiving channel 11B is coupled to the equalization output terminal EQ OUT of the receiving channel 12B.

[0111] The operating principles of receiving channels 11B and 12B shown in Figures 7(a) and 7(b) can be referenced to those shown in Figures 6(a) and 6(b). Unlike Figures 6(a) and 6(b), the second transmission chip 1100B controls the first clock circuit 120B to store clock information in the first buffer 140B. When the data flow increases, the second transmission chip 1100B controls the second buffer 240B to input clock information from the clock output terminal CLK OUT of the receiving channel 11B, coupled to the first buffer 140B, through the clock input terminal CLK IN of the receiving channel 12B. The second transmission chip 1100B controls the second clock circuit 220B to read clock information from the second buffer 240B. The second transmission chip 1100B controls the first equalization circuit 130B to store equalization information in the first buffer 140B. When the data flow increases, the second transmission chip 1100B controls the second buffer 240B to input equalization information from the first buffer 140B coupled to the equalization output EQ OUT of the receiving channel 11B through the equalization input terminal EQ IN of the receiving channel 12B. The second transmission chip 1100B also controls the second equalization circuit 230B to read equalization information from the second buffer 240B.

[0112] This application also provides a transmission chip. The receiving channel of this transmission chip has a buffer. Before the receiving channel is shut down, clock information is stored in the buffer. After the receiving channel restarts, it retrieves the clock information from the buffer, thereby achieving frequency synchronization.

[0113] In one possible implementation, the transmission chip includes multiple receivers and multiple receiving channels, including a first receiving channel, which includes a buffer. Each receiver is coupled to one of the multiple receiving channels in a one-to-one correspondence. The transmission chip is configured to, in response to a shutdown command, control the first receiving channel to store clock information in its buffer. The transmission chip is also configured to, in response to a startup command, control the first receiving channel to read clock information from its buffer.

[0114] The clock information is used for clock synchronization. The clock information may include frequency information. For example, the clock information may include clock encoding, which may include frequency information (such as frequency offset).

[0115] In one example, the transmission chip is the second transmission chip 1100B shown in Figure 5 (the buffer is not shown in Figure 5). Receive channels 11B to 1nB all include clock circuits (not shown in Figure 5).

[0116] When data traffic is high, all receiving channels 11B to 1nB are active, and a recovery clock is obtained through a clock circuit. The recovery clock can be a synchronized clock signal. When data traffic decreases, receiving channel 11B remains active, while receiving channels 12B to 1nB shut down in response to a shutdown command. Before shutting down, each of receiving channels 12B to 1nB stores its clock information in its respective buffer. When data traffic increases, receiving channels 12B to 1nB restart in response to a startup command. At this time, the clock signals of receiving channels 12B to 1nB are not synchronized. Receiving channels 12B to 1nB can read their clock information from their respective buffers. Receiving channels 12B to 1nB can obtain their recovery clock from this information, which is faster than obtaining the recovery clock through a clock circuit.

[0117] In this embodiment, the first receiving channel can store clock information in a buffer before being turned off, and read the clock information from the buffer after being turned on.

[0118] Compared to methods that achieve phase and frequency synchronization via a clock circuit, the first receiving channel does not require frequency synchronization via a clock circuit and can directly read the buffered frequency information. The first receiving channel only needs phase synchronization via a clock circuit. Since frequency synchronization via a clock circuit takes longer than directly reading the buffered frequency information, this implementation has a shorter startup time.

[0119] Compared to methods that achieve phase synchronization via clock circuits and frequency synchronization via physical clock wiring, this implementation also uses clock circuits for phase synchronization. However, for frequency synchronization, the transmission chip and the transmitting chip in this implementation do not require physical wiring with the master clock, resulting in lower costs. It also eliminates the need for network-wide clock synchronization, leading to shorter startup times.

[0120] Compared to phase synchronization achieved through buffered phase offsets and frequency synchronization through physical clock wiring, this implementation eliminates the need for the first receiving channel to send a phase offset to the corresponding transmitting channel for phase synchronization. This saves time on information transmission between chips and avoids consuming bandwidth resources. For frequency synchronization, the transmitting and transmitting chips in this implementation do not require physical wiring with the master clock, resulting in lower costs. Furthermore, it eliminates the need for network-wide clock synchronization, leading to shorter startup times.

[0121] This implementation reduces the startup time of the first receiving channel from the 100 microsecond level to the nanosecond level. It can reduce service scenarios with microsecond-level message gaps, meeting the requirements for low-power interconnect functionality. It can improve system energy efficiency and increase effective bandwidth. No network-wide clock synchronization is required.

[0122] Furthermore, when data traffic is low, either the first receiving channel or the second receiving channel can be shut down. The bandwidth adjustment method is quite flexible.

[0123] In one possible implementation, the transmission chip is further configured to, in response to a shutdown command, control the first receiving channel to store equalization information in the buffer of the first receiving channel. The transmission chip is also configured to, in response to a startup command, control the first receiving channel to read equalization information from the buffer of the first receiving channel. The equalization information is used for channel equalization.

[0124] In one example, the transmission chip is the second transmission chip 1100B shown in Figure 5. Receive channels 11B to 1nB all include equalization circuitry (not shown in Figure 5). The equalization circuitry is used to equalize the data.

[0125] When data traffic is high, all receiving channels 11B to 1nB are active, obtaining equalization information through the equalization circuit. When data traffic decreases, receiving channel 11B remains active, while receiving channels 12B to 1nB shut down in response to a shutdown command. Before shutting down, each of receiving channels 12B to 1nB stores the equalization information in its respective buffer. When data traffic increases again, receiving channels 12B to 1nB restart in response to a startup command. At this time, receiving channels 12B to 1nB can read the equalization information from their respective buffers. This is faster than receiving channels 12B to 1nB obtaining the equalization information through the equalization circuit.

[0126] In this implementation, the first receiving channel can store equalization information in a buffer before shutting down and read the equalization information from the buffer after restarting. The first receiving channel does not need to process the equalization information through the equalization circuit; instead, it directly reads the equalization information from the buffer. Since processing the equalization information through the equalization circuit takes longer than directly reading the equalization information from the buffer, this implementation has a shorter startup time. Furthermore, the equalization information of the first receiving channel does not depend on the equalization information of the second receiving channel. Even if the second receiving channel is shut down, the first receiving channel can still read the equalization information. Therefore, when data traffic is low, either the first or second receiving channel can be shut down. The bandwidth adjustment method is quite flexible.

[0127] In one possible implementation, the internal structure of the transmission channel will be illustrated below with reference to FIG8. Taking the second transmission chip 1100B in FIG2 as an example, the first receiving channel may include a receiving channel 12B. The receiving channel 12B may include a second sampling circuit 210B, a second clock circuit 220B, a second equalization circuit 230B, and a second buffer 240B. The coupling method of each circuit can be referred to FIG8. The second sampling circuit 210B is used to couple the receiving terminal RX corresponding to the receiving channel 12B. The second clock circuit 220B and the second equalization circuit 230B are both coupled to the second buffer 240B.

[0128] The second sampling circuit 210B receives analog signals from the corresponding receiving end. The second sampling circuit 210B is used to sample the input analog signals according to a clock signal to obtain digital signals. The second clock circuit 220B is used to provide a clock signal to the second sampling circuit 210B. The second equalization circuit 230B is used to equalize the digital signals.

[0129] In one example, the second transmission chip 1100B starts working, at which time the data flow is large and the receiving channel 12B is turned on.

[0130] The second sampling circuit 210B receives data, which is the fourth analog signal, from the corresponding coupled receiving terminal RX. The second clock circuit 220B is used to input a local clock and outputs the local clock to the second sampling circuit 210B. The second sampling circuit 210B samples the fourth analog signal according to the local clock to obtain a fourth digital signal. The second sampling circuit 210B outputs the fourth digital signal to the second clock circuit 220B and the second equalization circuit 230B. The second equalization circuit 230B obtains equalization information from the fourth digital signal. The second equalization circuit 230B equalizes the fourth digital signal according to the equalization information and outputs the equalized fourth digital signal. The second clock circuit 220B processes the fourth digital signal to obtain a recovered clock. The second clock circuit 220B outputs the recovered clock to the second sampling circuit 210B. The second sampling circuit 210B samples subsequent input digital signals according to the recovered clock.

[0131] As the data flow decreases, the receiving channel 12B shuts down in response to the shutdown command. Before shutting down, the second clock circuit 220B stores the clock information in the second buffer 240B, and the second equalization circuit 230B stores the equalization information in the second buffer 240B.

[0132] As the data flow increases, the receiving channel 12B restarts in response to the start command. The second clock circuit 220B reads clock information from the second buffer 240B and obtains the frequency of the recovered clock based on the clock information. The second equalization circuit 230B reads equalization information from the second buffer 240B.

[0133] The second sampling circuit 210B receives data, which is the fifth analog signal, from the corresponding coupled receiving terminal RX. The second clock circuit 220B outputs a clock obtained based on the local clock and frequency information to the second sampling circuit 210B. The second sampling circuit 210B samples the fifth analog signal according to the local clock to obtain the fifth digital signal. The second sampling circuit 210B outputs the fifth digital signal to the second clock circuit 220B and the second equalization circuit 230B. The second equalization circuit 230B equalizes the fifth digital signal according to the equalization information and outputs the equalized fifth digital signal. The second clock circuit 220B quickly obtains the phase of the recovered clock based on the fifth digital signal and the frequency of the recovered clock, thus obtaining the recovered clock. The second clock circuit 220B outputs the recovered clock to the second sampling circuit 210B. The second sampling circuit 210B samples subsequent input digital signals according to the recovered clock.

[0134] As can be seen, after the receiving channel 12B restarts, there is no need to recover the clock frequency from the digital signal sampled by the local clock. Furthermore, there is no need to obtain equalization information from the digital signal sampled by the local clock. This saves considerable time.

[0135] In one possible implementation, the start and stop commands can originate from the switching board corresponding to the transmission chip, or they can originate from the transmission device on the other side that transmits data with the transmission chip. The following description uses the second transmission chip 1100B in Figure 2 as an example.

[0136] In one example, the start and stop commands originate from the second switchboard 1300B correspondingly coupled to the second transmission chip 1100B. The second transmission chip 1100B can receive the stop command from the second processor 1400B. The second processor 1400B can receive the stop command from a pin or an I2C pin. Alternatively, the second transmission chip 1100B can receive the stop command from a pin. Exemplarily, the second transmission chip 1100B can receive the start command from the second processor 1400B. The second processor 1400B can receive the start command from a pin or an I2C pin. Alternatively, the second transmission chip 1100B can receive the start command from a pin.

[0137] In another example, the start and stop commands can originate from the opposite transmission device that transmits data with the second transmission chip 1100B. The second transmission chip 1100B can receive the stop command from the receiving end RX corresponding to the receiving channel 11B or 12B. The second transmission chip 1100B can receive the start command from the receiving end RX corresponding to the receiving channel 12B.

[0138] In this implementation, shutdown and startup instructions can be received by the processor or through a receive channel. The sources of instructions are diverse, and instruction transmission is rapid. Therefore, startup time can be further reduced.

[0139] In one possible implementation, the transmission chip can also be used to receive data through the receiving end corresponding to the first receiving channel after receiving the start command.

[0140] In this implementation, a start command can be received first, clock synchronization can be performed according to the start command, and then data can be received and sampled using the synchronized clock signal. Therefore, start-up time can be further reduced.

[0141] In one possible implementation, the first transmission device 1000A and the second transmission device 1000B can be activated simultaneously. For example, in a chip system comprising the first transmission chip 1100A and the second transmission chip 1100B, the first transmission chip 1100A is used to send a start command to the second transmission chip 1100B when a recovery command is sent. The recovery command is used to activate the first transmission chip 1100A. The recovery command and the start command can be sent by the control circuit in the first transmission chip 1100A.

[0142] In this embodiment, the first transmission device 1000A and the second transmission device 1000B can be started simultaneously, instead of the first transmission device 1000A starting first and the second transmission device 1000B starting later. Therefore, startup time can be further reduced.

[0143] This application also provides an optical module. The optical module may include a PD and the transmission chip described in the chip embodiments above. The optical module may also include a TIA, LD, and DRV. The coupling methods of the PD, TIA, LD, and DRV with the transmission chip can be referred to Figures 1 and 2.

[0144] Based on the transmission device and receiving channel shown in Figures 1, 2, and 5 to 8, this application embodiment also provides a transmission method.

[0145] As shown in Figure 9, the transmission method may include at least one of the following steps:

[0146] S110: The transmission chip receives the start command.

[0147] S120: In response to a start command, the transmission chip controls the first receiving channel to input clock information from the clock output of the second receiving channel through the clock input terminal of the first receiving channel. For example, the clock information includes frequency information, or the clock information includes both frequency information and phase information.

[0148] S130: In response to the start command, the transmission chip controls the first receiving channel to input equalization information from the equalization output of the second receiving channel through the equalization input terminal of the first receiving channel.

[0149] In one possible implementation, as shown in FIG10, S110 may specifically include S111: the transmission chip receives a start command from the receiving end corresponding to the second receiving channel. Alternatively, S110 may specifically include S112: the transmission chip receives a start command from the processor.

[0150] In one possible implementation, as shown in FIG10, the transmission method may further include S131: the transmission chip, in response to a start command, controls the TIA and PD coupled to the first receiving channel to start. Alternatively, the transmission method may further include S132: the transmission chip, in response to a start command, instructs a processor coupled to the transmission chip to control the TIA and PD coupled to the first receiving channel to start.

[0151] As shown in Figure 11, the transmission method may include at least one of the following steps:

[0152] S210: The transmission chip receives the shutdown command.

[0153] S220: In response to the shutdown command, the transmission chip controls the first receiving channel to store clock information in the buffer of the first receiving channel.

[0154] S230: In response to the shutdown command, the transmission chip controls the first receiving channel to store equalization information in the buffer of the first receiving channel.

[0155] S240: The transmission chip receives the start command.

[0156] S250: In response to a start command, the transmission chip controls the first receiving channel to read clock information from its buffer. For example, the clock information includes frequency information.

[0157] S260: In response to the start command, the transmission chip controls the first receiving channel to read equalization information from the buffer of the first receiving channel.

[0158] In one possible implementation, S210 may specifically include: the transmission chip receiving a shutdown command from a receiving end corresponding to the first receiving channel or the second receiving channel. Alternatively, S210 may specifically include: the transmission chip receiving a shutdown command from a processor coupled to the transmission chip.

[0159] In one possible implementation, the transmission method may further include: the transmission chip controlling the TIA and PD coupled to the first receiving channel to shut down in response to a shutdown command. Alternatively, the transmission method may further include: the transmission chip instructing a processor coupled to the transmission chip to control the TIA and PD coupled to the first receiving channel to shut down in response to a shutdown command.

[0160] In one possible implementation, S240 may specifically include: the transmission chip receiving a start command from the receiving end correspondingly coupled to the second receiving channel. Alternatively, S240 may specifically include: the transmission chip receiving a start command from the processor.

[0161] In one possible implementation, the transmission method may further include: the transmission chip controlling the startup of the TIA and PD coupled to the first receiving channel in response to a startup command. Alternatively, the transmission method may further include: the transmission chip instructing a processor coupled to the transmission chip to control the startup of the TIA and PD coupled to the first receiving channel in response to a startup command.

[0162] In one possible implementation, the transmission method may further include: after receiving a start command, the transmission chip receives data through the receiving end corresponding to the first receiving channel.

[0163] The communication process between the first transmission device 1000A and the second transmission device 1000B will be illustrated below with reference to Figures 1 and 2. The transmission chip can be either the first transmission chip 1100A in the first transmission device 1000A or the second transmission chip 1100B in the second transmission device 1000B.

[0164] In one example, the internal structure of the receiving channel of the first transmission device 1000A and the second transmission device 1000B is shown in Figure 6.

[0165] For example, the first switching board 1300A sends a shutdown command to the first processor 1400A via a pin or an I2C pin, and the first processor 1400A sends a shutdown command to the first transmission chip 1100A. Alternatively, the first switching board 1300A sends a shutdown command directly to the first transmission chip 1100A via a pin.

[0166] The first transmission chip 1100A receives a shutdown command and queries the lookup table (LUT) based on the command. The first transmission chip 1100A determines which channels need to be shut down based on the lookup table, such as receive channels 32A-3nA and transmit channels 12A-1nA. The lookup table supports dynamic refreshing, and receive channel 31A and transmit channel 11A remain open.

[0167] The first transmission chip 1100A sends a shutdown command to the second transmission chip 1100B through one of the transmission channels 11A to 1nA.

[0168] The first transmission chip 1100A shuts down the receive channels 32A to 3nA. For example, the first transmission chip 1100A shuts down the receive channels 32A to 3nA via a clock gate or by powering down. The first transmission chip 1100A shuts down the transmit channels 12A to 1nA. The first transmission chip 1100A controls the corresponding DRV52A to 5nA and LD72A to 7nA to shut down; or, the first transmission chip 1100A instructs the first processor 1400A to control the shutdown of DRV52A to 5nA and LD72A to 7nA.

[0169] The second transmission chip 1100B receives a shutdown command through one of the receiving channels 11B to 1nB and queries the task table based on the shutdown command. The second transmission chip 1100B then determines which channels need to be shut down based on the task table, such as receiving channels 12B to 1nB and transmitting channels 32B to 3nB. The task table supports dynamic refreshing, and receiving channel 11B and transmitting channel 31B remain open.

[0170] The method by which the second transmission chip 1100B shuts down the receiving channels 12B-1nB and the transmitting channels 32B-3nB can be referenced from that of the first transmission chip 1100A, and will not be repeated here in this embodiment. The second transmission chip 1100B controls the TIA51B-5nB and PD72B-7nB corresponding to the receiving channels 12B-1nB to shut down; or, the second transmission chip 1100B instructs the second processor 1400B to control the TIA51B-5nB and PD72B-7nB to shut down. Optionally, since the power consumption of PD72B-7nB is relatively low, PD72B-7nB may not need to be shut down.

[0171] For example, the first switching board 1300A sends a boot command to the first processor 1400A via a pin or an I2C pin, and the first processor 1400A sends a boot command to the first transmission chip 1100A. Alternatively, the first switching board 1300A sends a boot command directly to the first transmission chip 1100A via a pin.

[0172] The first transmission chip 1100A receives a start command and queries the task lookup table (LUT) according to the start command. The first transmission chip 1100A determines the channels to be started according to the task lookup table, such as receiving channels 32A~3nA and transmitting channels 12A~1nA. The task lookup table supports dynamic refreshing, and receiving channel 31A and transmitting channel 11A are kept open.

[0173] The first transmission chip 1100A sends a start command to the second transmission chip 1100B through the transmission channel 11A.

[0174] The first transmission chip 1100A starts the receiving channels 32A to 3nA. For example, the first transmission chip 1100A starts the receiving channels 32A to 3nA by removing the clock gate or removing the power-off method. The first transmission chip 1100A starts the transmitting channels 12A to 1nA. The first transmission chip 1100A controls the start of DRV52A to 5nA and LD72A to 7nA corresponding to the transmitting channels 12A to 1nA; or, the first transmission chip 1100A instructs the first processor 1400A to control the start of DRV52A to 5nA and LD72A to 7nA.

[0175] The first transmission chip 1100A, receiving channel 31A, outputs clock information and equalization information to the clock input terminals of receiving channels 32A to 3nA via its clock output terminal. Receiving channels 32A to 3nA operate according to this clock information and equalization information. Alternatively, the first transmission chip 1100A controls receiving channel 31A to output clock information and equalization information to receiving channels 32A to 3nA. Receiving channels 32A to 3nA, based on their respective clock information and equalization information, obtain their respective bathtub curves through methods such as signal-to-noise ratio (SNR) and bit error rate (BER), thereby obtaining the clock information and equalization information for their respective optimal sampling points. Receiving channels 32A to 3nA operate according to the clock information and equalization information of their optimal sampling points.

[0176] The second transmission chip 1100B receives the start command through the receiving channel 11B and queries the task table according to the start command. The second transmission chip 1100B determines the channels to be started according to the task table, such as receiving channels 12B~1nB and transmitting channels 32B~3nB. The task table supports dynamic refreshing, and receiving channel 11B and transmitting channel 31B are kept open.

[0177] The process by which the second transmission chip 1100B starts the receiving channels 12B to 1nB and the transmitting channels 32B to 3nB can be referred to the first transmission chip 1100A, and will not be repeated here in the embodiments of this application. The second transmission chip 1100B controls the start of TIA51B to 5nB and PD72B to 7nB corresponding to the receiving channels 12B to 1nB; or, the second transmission chip 1100B instructs the second processor 1400B to control the start of TIA51B to 5nB and PD72B to 7nB.

[0178] The method by which the second transmission chip 1100B controls the receiving channels 12B to 1nB to acquire clock and equalization information can be referred to that of the first transmission chip 1100A, and will not be repeated here in this embodiment. The receiving channels 12B to 1nB operate according to the acquired clock and equalization information.

[0179] In another example, the internal structure of the receiving channel of the first transmission device 1000A and the second transmission device 1000B is shown in Figure 7.

[0180] For example, the first switching board 1300A sends a shutdown command to the first processor 1400A via a pin or an I2C pin, and the first processor 1400A sends a shutdown command to the first transmission chip 1100A. Alternatively, the first switching board 1300A sends a shutdown command directly to the first transmission chip 1100A via a pin.

[0181] The first transmission chip 1100A receives a shutdown command and queries the task table accordingly. Based on the task table, the first transmission chip 1100A determines which channels need to be shut down, such as receive channels 32A-3nA and transmit channels 12A-1nA. The task table supports dynamic refreshing, and receive channel 31A and transmit channel 11A remain open.

[0182] The first transmission chip 1100A sends a shutdown command to the second transmission chip 1100B through one of the transmission channels 11A to 1nA.

[0183] The first transmission chip 1100A stores the clock information and equalization information of the receiving channels 32A to 3nA into their respective buffers. For example, the clock information may include the frequency offset (ppm pre) at the time before shutdown, and the equalization information may include the equalization coefficient (coef pre) at the time before shutdown.

[0184] The first transmission chip 1100A shuts down the receive channels 32A to 3nA. For example, the first transmission chip 1100A shuts down the receive channels 32A to 3nA via a clock gate or by powering down. The first transmission chip 1100A shuts down the transmit channels 12A to 1nA. The first transmission chip 1100A controls the corresponding DRV52A to 5nA and LD72A to 7nA to shut down; or, the first transmission chip 1100A instructs the first processor 1400A to control the shutdown of DRV52A to 5nA and LD72A to 7nA.

[0185] The second transmission chip 1100B receives a shutdown command through one of the receiving channels 11B to 1nB and queries the task table based on the shutdown command. The second transmission chip 1100B then determines which channels need to be shut down based on the task table, such as receiving channels 12B to 1nB and transmitting channels 32B to 3nB. The task table supports dynamic refreshing, and receiving channel 11B and transmitting channel 31B remain open.

[0186] The method by which the second transmission chip 1100B shuts down the receiving channels 12B-1nB and the transmitting channels 32B-3nB can refer to that of the first transmission chip 1100A, and will not be repeated here in this embodiment. The second transmission chip 1100B controls the TIA51B-5nB and PD72B-7nB corresponding to the receiving channels 12B-1nB to shut down; or, the second transmission chip 1100B instructs the second processor 1400B to control the TIA51B-5nB and PD72B-7nB to shut down. Optionally, since the power consumption of PD72B-7nB is relatively low, PD72B-7nB may not need to be shut down.

[0187] For example, the first switching board 1300A sends a boot command to the first processor 1400A via a pin or an I2C pin, and the first processor 1400A sends a boot command to the first transmission chip 1100A. Alternatively, the first switching board 1300A sends a boot command directly to the first transmission chip 1100A via a pin.

[0188] The first transmission chip 1100A receives a start command and queries the task table accordingly. Based on the task table, the first transmission chip 1100A determines which channels need to be started, such as receiving channels 32A-3nA and transmitting channels 12A-1nA. The task table supports dynamic refreshing, and receiving channel 31A and transmitting channel 11A remain active.

[0189] The first transmission chip 1100A sends a start command to the second transmission chip 1100B through the transmission channel 11A.

[0190] The first transmission chip 1100A starts the receiving channels 32A to 3nA. For example, the first transmission chip 1100A starts the receiving channels 32A to 3nA by removing the clock gate or removing the power-off method. The first transmission chip 1100A starts the transmitting channels 12A to 1nA. The first transmission chip 1100A controls the start of DRV52A to 5nA and LD72A to 7nA corresponding to the transmitting channels 12A to 1nA; or, the first transmission chip 1100A instructs the first processor 1400A to control the start of DRV52A to 5nA and LD72A to 7nA.

[0191] The first transmission chip 1100A controls the receiving channels 32A to 3nA to read the clock information and equalization information from their respective buffers. The receiving channels 32A to 3nA operate according to this clock information and equalization information.

[0192] The second transmission chip 1100B receives the start command through the receiving channel 11B and queries the task table according to the start command. The second transmission chip 1100B determines the channels to be started according to the task table, such as receiving channels 12B~1nB and transmitting channels 32B~3nB. The task table supports dynamic refreshing, and receiving channel 11B and transmitting channel 31B are kept open.

[0193] The process by which the second transmission chip 1100B starts the receiving channels 12B to 1nB and the transmitting channels 32B to 3nB can be referred to the first transmission chip 1100A, and will not be repeated here in this application example. The second transmission chip 1100B controls the start of TIA51B to 5nB and PD72B to 7nB corresponding to the receiving channels 12B to 1nB; or, the second transmission chip 1100B instructs the second processor 1400B to control the start of TIA51B to 5nB and PD72B to 7nB.

[0194] The method by which the second transmission chip 1100B controls the receiving channels 12B to 1nB to acquire clock and equalization information can be referred to that of the first transmission chip 1100A, and will not be repeated here in this embodiment. The receiving channels 12B to 1nB operate according to the acquired clock and equalization information.

[0195] The transmission chip, transmission method, chip system, optical module, and transmission device in this application embodiment can be applied to burst mode clock fast locking scenarios such as data centers, optical switching networks, and passive optical networks (PON).

[0196] This application also provides a computer-readable storage medium storing program code. When the medium is run on a device (e.g., a microcontroller, chip, computer, or processor), the program code can be invoked to execute one or more steps in the above method embodiments.

[0197] Based on this understanding, this application also provides a computer program product containing instructions. The technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or its circuitry to execute all or part of the steps of the methods described in the various embodiments of this application.

[0198] It is understood that the above-mentioned transmission method, chip system, optical module and transmission device can respectively apply the transmission chip in the aforementioned chip embodiment. Since the corresponding functions and effects have been described in detail in the aforementioned transmission chip embodiment, they will not be repeated here.

[0199] The processors involved in the embodiments of this application (such as the first processor 1400A and the second processor 1400B) can be a chip. For example, it can be a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0200] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0201] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0202] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0203] In addition, the circuits in the various embodiments of this application can be integrated into one device, or each circuit can exist physically separately, or two or more circuits can be integrated into one device.

[0204] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0205] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A transmission chip, characterized in that, The transmission chip includes multiple receiving ends and multiple receiving channels, the multiple receiving channels including a first receiving channel and a second receiving channel; The first receiving channel includes a clock input terminal, and the second receiving channel includes a clock output terminal; The plurality of receiving ends are coupled one-to-one with the plurality of receiving channels; The clock input terminal of the first receiving channel is coupled to the clock output terminal of the second receiving channel.

2. The transmission chip according to claim 1, characterized in that, Both the first receiving channel and the second receiving channel include a clock circuit; The clock input terminal of the first receiving channel is coupled to the clock circuit of the first receiving channel; The clock output terminal of the second receiving channel is coupled to the clock circuit of the second receiving channel.

3. The transmission chip according to claim 2, characterized in that, Both the first receiving channel and the second receiving channel include buffers; The clock input terminal of the first receiving channel is coupled to the clock circuit of the first receiving channel through the buffer of the first receiving channel; The clock output terminal of the second receiving channel is coupled to the clock circuit of the second receiving channel through the buffer of the second receiving channel.

4. The transmission chip according to any one of claims 1-3, characterized in that, The first receiving channel further includes an equalization input terminal, and the second receiving channel further includes an equalization output terminal; The equalization input terminal of the first receiving channel is coupled to the equalization output terminal of the second receiving channel.

5. The transmission chip according to claim 4, characterized in that, Both the first receiving channel and the second receiving channel include equalization circuits; The equalization input terminal of the first receiving channel is coupled to the equalization circuit of the first receiving channel. The equalization output terminal of the second receiving channel is coupled to the equalization circuit of the second receiving channel.

6. The transmission chip according to claim 5, characterized in that, Both the first receiving channel and the second receiving channel include buffers; The equalization input terminal of the first receiving channel is coupled to the equalization circuit of the first receiving channel through the buffer of the first receiving channel. The equalization output terminal of the second receiving channel is coupled to the equalization circuit of the second receiving channel through the buffer of the second receiving channel.

7. The transmission chip according to any one of claims 4-6, characterized in that, The transmission chip is configured to respond to a start command by controlling the first receiving channel to input equalization information from the equalization output of the second receiving channel through the equalization input terminal of the first receiving channel.

8. The transmission chip according to any one of claims 1-7, characterized in that, The transmission chip is used to control the first receiving channel to input clock information from the clock output terminal of the second receiving channel through the clock input terminal of the first receiving channel in response to a start command. The clock information includes frequency information, or the clock information includes both frequency information and phase information.

9. A transmission chip, characterized in that, The transmission chip includes multiple receiving ends and multiple receiving channels, the multiple receiving channels including a first receiving channel, and the first receiving channel including a buffer; The plurality of receiving ends are coupled one-to-one with the plurality of receiving channels; The transmission chip is used to control the first receiving channel to store clock information into the buffer of the first receiving channel in response to a shutdown command; The transmission chip is also configured to, in response to a start command, control the first receiving channel to read the clock information from the buffer of the first receiving channel; The clock information includes frequency information.

10. The transmission chip according to claim 9, characterized in that, The transmission chip is also configured to, in response to the shutdown command, control the first receiving channel to store equalization information in the buffer of the first receiving channel; The transmission chip is also configured to, in response to the start command, control the first receiving channel to read the equalization information from the buffer of the first receiving channel.

11. The transmission chip according to claim 9 or 10, characterized in that, The plurality of receiving channels also includes a second receiving channel; The transmission chip is also configured to receive the shutdown command from the receiving end corresponding to the first receiving channel or the second receiving channel.

12. The transmission chip according to claim 9 or 10, characterized in that, The transmission chip is used to couple the processor; The transmission chip is also used to receive the shutdown command from the processor.

13. The transmission chip according to any one of claims 7-12, characterized in that, The plurality of receiving channels also includes a second receiving channel; The transmission chip is also used to receive the start command from the receiving end corresponding to the second receiving channel.

14. The transmission chip according to any one of claims 7-12, characterized in that, The transmission chip is used to couple the processor; The transmission chip is also used to receive the startup command from the processor.

15. The transmission chip according to any one of claims 7-14, characterized in that, The transmission chip is also used to receive data through the receiving end coupled to the first receiving channel after receiving the start command.

16. A transmission method, characterized in that, The transmission method is applied to a transmission chip, which includes multiple receiving ends and multiple receiving channels, including a first receiving channel and a second receiving channel. The first receiving channel includes a clock input terminal, and the second receiving channel includes a clock output terminal; The plurality of receiving ends are coupled one-to-one with the plurality of receiving channels; The clock input terminal of the first receiving channel is coupled to the clock output terminal of the second receiving channel; The transmission method includes: Receive startup command; In response to the start command, the first receiving channel is controlled to input clock information from the clock output of the second receiving channel through the clock input terminal of the first receiving channel; The clock information includes frequency information, or the clock information includes both frequency information and phase information.

17. The transmission method according to claim 16, characterized in that, The first receiving channel further includes an equalization input terminal, and the second receiving channel further includes an equalization output terminal; the equalization input terminal of the first receiving channel is coupled to the equalization output terminal of the second receiving channel. The transmission method further includes: In response to the start command, the first receiving channel is controlled to input equalization information from the equalization output of the second receiving channel through the equalization input terminal of the first receiving channel.

18. A transmission method, characterized in that, The transmission method is applied to a transmission chip, which includes multiple receiving ends and multiple receiving channels. The multiple receiving channels include a first receiving channel, which includes a buffer. The multiple receiving ends are coupled to the multiple receiving channels in a one-to-one correspondence. The transmission method includes: Receive shutdown command; In response to the shutdown command, the first receiving channel is controlled to store clock information in the buffer of the first receiving channel; Receive startup command; In response to the start command, the first receiving channel is controlled to read the clock information from the buffer of the first receiving channel; The clock information includes frequency information.

19. The transmission method according to claim 18, characterized in that, The transmission method further includes: In response to the shutdown command, the first receiving channel is controlled to store equalization information in the buffer of the first receiving channel; In response to the start command, the first receiving channel is controlled to read the equalization information from the buffer of the first receiving channel.

20. The transmission method according to claim 18 or 19, characterized in that, The plurality of receiving channels also includes a second receiving channel; The receiving of the shutdown command includes: The shutdown command is received from the receiving end corresponding to the first receiving channel or the second receiving channel.

21. The transmission method according to claim 18 or 19, characterized in that, The transmission chip is used to couple the processor; receiving the shutdown command includes: The shutdown command is received from the processor.

22. The transmission method according to any one of claims 16-21, characterized in that, The plurality of receiving channels also includes a second receiving channel; The receiving of the start command includes: The start command is received from the receiving end corresponding to the second receiving channel.

23. The transmission method according to any one of claims 16-21, characterized in that, The transmission chip is used to couple the processor; receiving the startup command includes: The startup command is received from the processor.

24. The transmission method according to any one of claims 16-23, characterized in that, The transmission method further includes: After receiving the start command, data is received through the receiving end coupled to the first receiving channel.

25. A chip system, characterized in that, The chip system includes a transmitting chip and a transmission chip as described in any one of claims 1-15; The transmitting chip is used to transmit data with the transmitting chip.

26. The chip system according to claim 25, characterized in that, The transmitting chip is used to send the start command to the transmission chip when sending the recovery command; the recovery command is used to start the transmitting chip.

27. An optical module, characterized in that, The optical module includes an optical signal receiver and a transmission chip as described in any one of claims 1-15; the optical signal receiver is coupled to the transmission chip.

28. A transmission device, characterized in that, The transmission device includes a circuit board and a transmission chip as described in any one of claims 1-15; the transmission chip is disposed on the circuit board.

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