Carrier synchronization method for parallel converters sharing alternating current / direct current bus

Abstract

Disclosed in the present invention is a carrier synchronization method for parallel converters sharing an alternating current / direct current bus. An architecture of one master device, one standby device, and multiple slave devices is used. When the master device operates normally, the master device transmits a synchronization signal, and the standby device and the slave devices receive the synchronization signal. An optical fiber transmitter and an optical fiber receiver are arranged on each device. The carrier synchronization method for multiple parallel converters comprises: in a normal mode, when the carrier count of an EPWM1 register in a master device DSP reaches 0, generating a synchronization signal, and carriers in EPWM2-EPWM6 registers in the master device DSP receiving the synchronization signal internally; routing the synchronizing signal to a GPIO pin via an Output X-BAR register in the master device DSP, then converting the electrical signal into an optical signal via the optical fiber transmitter in the master device, and transmitting the optical signal to the standby device and the slave devices.

Description

A carrier synchronization method for parallel AC / DC bus converters Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a one-master-one-backup-multiple-slave carrier synchronization method for a shared AC / DC bus multi-parallel converter system in energy storage power stations and photovoltaic power stations. Background Technology

[0002] With the continuous development of new energy power generation technologies, converters are increasingly widely used in wind power, photovoltaics, and energy storage. The requirements for converter performance, capacity, reliability, and scalability are also becoming increasingly stringent. Parallel converter technology combines low-cost, standardized converter modules into large-capacity converters, easily meeting the modular design requirements for power electronics integration in power conversion equipment and enabling plug-and-play functionality. However, in high-power parallel systems, converters share a single bus on the DC side and are connected in parallel to the AC bus via inductors on the AC side. The low switching frequency and narrow system bandwidth of the converters, coupled with the inductors' poor suppression of high-frequency harmonics, can lead to inconsistent high-frequency components in the converter output, resulting in high-frequency circulating currents in the parallel system.

[0003] In a parallel system, the DC sides of the converters share the same DC bus, and the AC outputs share the same AC bus connected to the load. When a voltage difference occurs between the converters, this difference will excite the inductors in the parallel branches, thus generating circulating current. Current literature generally classifies circulating current into low-frequency circulating current and high-frequency circulating current. When the modulation waves between modules are inconsistent, the average voltage of the output over one cycle is inconsistent, leading to low-frequency circulating current in the system; when the carrier waves between modules are inconsistent, the average voltage of the output over one cycle is consistent, but the asynchronous switching states of the power devices will cause high-frequency circulating current. Circulating current does not pass through the power grid and load, increasing losses, causing output current distortion, and even damaging power devices.

[0004] There are two main methods for suppressing circulating current: hardware circuit blocking and software algorithm suppression. Hardware blocking involves electrical isolation of the DC or AC side, with each converter using an independent DC source on the DC side or adding a multi-winding transformer on the AC side. This method completely eliminates circulating current by cutting off its path, but it increases system size and cost, hindering modularization and integration. Software suppression methods are lower in cost and can be broadly categorized into converter control strategies and PWM modulation strategies. Converter control strategies typically utilize zero-vector feedforward control to suppress zero-sequence circulating current. PWM modulation strategies include adjusting the zero-vector's duration in SVPWM based on zero-sequence current PI regulation, replacing the zero vector with a non-zero vector, low-frequency circulating current control based on PR control, and space vector modulation algorithms based on interleaved carriers. The aforementioned control strategies have complex algorithms, high control difficulty, and do not synchronize the carrier signal, resulting in less than ideal suppression of high-frequency circulating current in parallel converters. Summary of the Invention

[0005] To address the aforementioned problems in existing technologies, this invention provides a carrier synchronization control method for parallel converters. Addressing the high-frequency circulating current problem caused by asynchronous parallel carriers in converters, it employs a master-slave multi-slave carrier synchronization algorithm. Utilizing fiber optic transmitters and receivers, carrier synchronization is achieved, resulting in high transmission quality and high speed. This method avoids high-frequency circulating currents caused by instantaneous power device switching asynchrony, reduces system losses, and improves system efficiency and stability. The technical solution is as follows:

[0006] A carrier synchronization method for parallel AC / DC converters using a shared AC / DC bus employs a master-slave multi-slave device layout. When the master device is functioning normally, it sends a synchronization signal, which is received by the standby and slave devices. When the master device fails, the standby device sends a synchronization signal, which is received by the master and slave devices, thus achieving carrier synchronization among all parallel converters. Each device is equipped with a fiber optic transmitter and receiver. The carrier synchronization method for multiple parallel converters is as follows: In normal mode, when the carrier count in the EPWM1 ​​register of the master device's DSP reaches 0, a synchronization signal is generated. The carriers in the EPWM2-EPWM6 registers of the master device's DSP internally receive this synchronization signal. This synchronization signal is then routed through the Output X-BAR register of the master device's DSP to a GPIO pin, and then converted from an electrical signal to an optical signal by the fiber optic transmitter in the master device, which is then sent to the standby and slave devices. The fiber optic receivers on the standby and slave devices convert the optical signal back into an electrical signal and input it to their own DSP's GPIO pins, and then through the Input... The X-BAR register input is sent to the EPWM1-EPWM6 registers. After receiving this synchronization signal, the carrier counters of the other PWM waves in the master device DSP, the carrier waves of each PWM wave in the backup device DSP, and the carrier waves of each PWM wave in the slave device DSP start counting upward from 0, thereby achieving carrier phase synchronization of each converter.

[0007] Furthermore, when the master device fails, the backup device DSP detects the period value of the master device's synchronization signal. If the detected actual period value is not within the set range, the pulse detection counter in the backup device DSP program will count once in each control cycle. If the cumulative count reaches the preset limit, a synchronization signal is generated when the carrier count in the EPWM1 ​​register of the backup device DSP reaches 0. The carrier in the EPWM2-EPWM6 registers of the backup device DSP can internally receive the synchronization signal. This synchronization signal is led to the GPIO pin through the Output X-BAR register in the backup device DSP, and then the optical fiber transmitter in the backup device converts the electrical signal into an optical signal and sends it to the master and slave devices. The optical fiber receivers on the master and slave devices convert the optical signal into an electrical signal and input it to the GPIO pin of the DSP, and then input it to the EPWM1-EPWM6 registers through the Input X-BAR register.

[0008] Furthermore, the DSP used in each device is a TMS320F28379D.

[0009] The beneficial effects of this invention are as follows:

[0010] ① Achieve carrier synchronization in multi-converter systems, reducing high-frequency circulating currents and system losses. By combining fiber optic carrier synchronization circuits and carrier synchronization algorithms, carrier synchronization can be effectively achieved in multi-parallel converter systems, avoiding high-frequency circulating current problems caused by asynchronous switching of instantaneous power devices in each converter. This design not only significantly reduces high-frequency circulating currents within the system and the resulting energy losses, but also improves the overall system efficiency and operational stability.

[0011] ② A carrier synchronization algorithm with master-slave switching capability improves system reliability. The carrier synchronization algorithm proposed in this invention, featuring one master, one backup, and multiple slave devices, allows the master device to send a carrier synchronization signal while the backup and slave devices are receiving the signal. When the master device fails, the backup device can promptly take over and send the synchronization signal, ensuring the continuity and reliability of the system's synchronization signal. This design enhances the system's ability to cope with critical equipment failures and strengthens its operational reliability.

[0012] ③ Fiber optic synchronization technology is adopted to improve signal transmission quality and anti-interference capability. Fiber optic transmission has advantages such as fast propagation speed, strong anti-electromagnetic interference capability, long transmission distance and high transmission quality, making the transmission of carrier synchronization signals more stable and reliable, and further improving the system's anti-interference capability and overall performance. Attached Figure Description

[0013] Figure 1 Carrier synchronization flowchart

[0014] Figure 2. Carrier synchronization principle diagram

[0015] Figure 3. Synchronization signal detection flowchart

[0016] Figure 4. Time base counting synchronization diagram

[0017] Figure 5 Simplified model of EPWM register Detailed Implementation

[0018] The carrier synchronization flowchart is shown in Figure 1. It is divided into three types of devices: master, backup, and slave. When the master device is normal, it sends the synchronization signal, and the backup and slave devices receive the synchronization signal. When the master device fails, the backup device sends the synchronization signal, and the master and slave devices receive the synchronization signal. The carrier synchronization principle diagram is shown in Figure 2, and the fault detection flowchart of the master device is shown in Figure 3. This invention uses a DSP as the carrier synchronization signal generator, mainly utilizing the EPWM register in the DSP. Figure 4 shows the internal structure diagram of the time base counter of the EPWM module in the DSP TMS320F28379D. The carrier is generated by counting with the time base counter. This model of DSP has a total of 12 EPWM modules. Each EPWM module can be configured to use or ignore the synchronization input signal. The synchronization input includes external synchronization signals (EXTSYNCIN1, EXTSYNCIN2) and internal synchronization signals. The internal synchronization signal (EPWMxSYNCOUT) can be generated by EPWM1, EPWM4, EPWM7, and EPWM10. As shown in Figure 5, the simplified EPWM model is as follows: Syncln is the synchronization signal input, EN can be selected to receive or block the input synchronization signal, Phase reg is to set the initial phase value, and SyncOut is the synchronization signal output. There are four output modes as follows:

[0019] 1. SyncOut connected to SyncIn --- Outputs the received synchronization input signal

[0020] 2. SyncOut connected to CTR = 0 --- Output is generated when the carrier count reaches zero.

[0021] 3. SyncOut connected to CTR = CMPB --- Output is generated when the carrier count and CMPB register are equal.

[0022] 4. SyncOut connected to X --- No synchronization output signal is generated.

[0023] The specific scheme for achieving carrier synchronization of multiple parallel converters is as follows: Carrier synchronization of multiple parallel converters requires carrier synchronization of the DSPs in the control modules of each converter. This transforms the problem into carrier synchronization of multiple DSPs. In normal mode, one DSP acts as the master device to generate the synchronization signal, one DSP acts as the standby device to receive the synchronization signal, and the other DSPs act as slave devices to receive the synchronization signal. Specifically, the EN setting of the EPWM1-EPWM6 registers of all device DSPs is selected to receive the synchronization signal, the initial value of Phase reg is set to 0, the SyncOut synchronization signal output of the EPWM1 ​​register of the master and standby device DSPs is selected as mode 2, and the SyncOut synchronization signal output of the EPWM2-EPWM6 registers of the master and standby device DSPs, as well as the EPWM1-EPWM6 registers of the slave device DSPs, is selected as mode 1. Thus, in normal mode, the EPWM1 ​​register of the master device DSP acts as the source of the synchronization signal, and the EPWM registers of all other device DSPs act as the source of the synchronization signal. After carrier synchronization begins, a synchronization signal is generated when the carrier count in the EPWM1 ​​register of the master device DSP reaches 0. The carriers in the EPWM2-EPWM6 registers of the master device DSP can internally receive this synchronization signal. This synchronization signal is led to the GPIO pin via the Output X-BAR register in the master device DSP, and then converted from an electrical signal to an optical signal by the fiber optic transmitter in the master device, which is then sent to the standby and slave devices. The fiber optic receivers on the standby and slave devices convert the optical signal back into an electrical signal and input it to the GPIO pin of the DSP, which is then input to its own EPWM1-EPWM6 registers via the Input X-BAR register.

[0024] In fault mode, the EPWM1 ​​register of the standby device DSP serves as the source of the synchronization signal, while the EPWM registers of all other device DSPs serve as the receiving sources. When the master device fails, the standby device DSP detects the period value of the master device's synchronization signal. If the actual period value is outside the set range, the pulse detection counter in the standby device DSP program counts once per control cycle. To prevent signal interference, if the cumulative count reaches five times, a synchronization signal is generated when the carrier count in the EPWM1 ​​register of the standby device DSP reaches 0. The carriers in the EPWM2-EPWM6 registers of the standby device DSP can internally receive the synchronization signal. This synchronization signal is led to the GPIO pin through the Output X-BAR register in the standby device DSP, and then converted from an electrical signal to an optical signal by the fiber optic transmitter in the standby device, and sent to the master and slave devices. The fiber optic receivers on the master and slave devices convert the optical signal back into an electrical signal and input it to the GPIO pin of their own DSPs, and then input it to the EPWM1-EPWM6 registers through the Input X-BAR register.

Claims

1. A carrier synchronization method for parallel AC / DC converters using a shared AC / DC bus, employing a master-slave multi-slave device layout. When the master device is functioning normally, it sends a synchronization signal, which is received by the standby and slave devices. When the master device fails, the standby device sends a synchronization signal, which is received by the master and slave devices, thus achieving carrier synchronization among all parallel converters. Each device is equipped with an optical fiber transmitter and receiver. The carrier synchronization method for multiple parallel converters is as follows: In normal mode, when the carrier count in the EPWM1 ​​register of the master device's DSP reaches 0, a synchronization signal is generated. The carriers in the EPWM2-EPWM6 registers of the master device's DSP internally receive this synchronization signal. This synchronization signal is led to the GPIO pin via the Output X-BAR register of the master device's DSP, and then converted from an electrical signal to an optical signal by the optical fiber transmitter in the master device, which is then sent to the standby and slave devices. The optical fiber receivers on the standby and slave devices convert the optical signal back into an electrical signal and input it to the GPIO pin of their own DSPs, and then through the Input... The X-BAR register input is sent to the EPWM1-EPWM6 registers. After receiving this synchronization signal, the carrier counters of the other PWM waves in the master device DSP, the carrier waves of each PWM wave in the backup device DSP, and the carrier waves of each PWM wave in the slave device DSP start counting upward from 0, thereby achieving carrier phase synchronization of each converter.

2. The carrier synchronization method for shared AC / DC bus parallel converters according to claim 1, characterized in that, When the master device fails, the backup device DSP detects the period value of the master device's synchronization signal. If the detected actual period value is not within the set range, the pulse detection counter in the backup device DSP program will count once in each control cycle. If the cumulative count reaches the preset limit, a synchronization signal is generated when the carrier count in the EPWM1 ​​register of the backup device DSP reaches 0. The carrier in the EPWM2-EPWM6 registers of the backup device DSP can internally receive the synchronization signal. This synchronization signal is led to the GPIO pin through the Output X-BAR register in the backup device DSP, and then the optical fiber transmitter in the backup device converts the electrical signal into an optical signal and sends it to the master and slave devices. The optical fiber receivers on the master and slave devices convert the optical signal into an electrical signal and input it to the GPIO pin of the DSP, and then input it to the EPWM1-EPWM6 registers through the Input X-BAR register.

3. The carrier synchronization method for shared AC / DC bus parallel converters according to claim 1, characterized in that, The DSP used in each device is a TMS320F28379D.

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