Wiring board

Abstract

A wiring board (10) comprises: a core layer (11) having a through hole (14); and build-up layers (12, 13) laminated on both sides of the core layer (11) and having a via hole (15). The through hole (14) includes: first and second through holes (PTH1, PTH2) to which a differential signal is connected; and a third through hole (PTH3) to which a fixed potential is applied. The third through hole (PTH3) overlaps a region sandwiched between external common tangents (ECT1, ECT2) of the first and second through holes (PTH1, PTH2) and is disposed at a position where the distance from the first through hole (PTH1) and the distance from the second through hole (PTH2) are equal.

Description

Wiring board

[0001] The present disclosure relates to a wiring board for mounting a semiconductor integrated circuit device or the like.

[0002] In order to mount a semiconductor integrated circuit device or the like, a wiring board configured to stack one or more relatively thin insulating substrates (referred to as build-up layers) above and below a relatively thick insulating substrate (referred to as a core layer) may be used.

[0003] In such a wiring board, through holes (PTH: Plated Through Hole) are provided in the core layer and via holes are provided in the build-up layer for electrical connection. A semiconductor integrated circuit device or the like mounted on the wiring board and a circuit board or the like on which the wiring board is mounted are electrically connected by conductors provided on the inner surface of the through hole, conductors provided in the via hole, and wirings provided on the surface and inside of the build-up layer.

[0004] Patent Document 1 discloses the configuration of through holes, via holes, and wirings in a wiring board for transmitting differential signals.

[0005] Japanese Patent Application Laid-Open No. 2012-99587

[0006] In Patent Document 1, the through holes provided in the core layer for transmitting differential signals are provided adjacent to each other.

[0007] In recent years, due to the increase in the scale of semiconductor integrated circuit devices, the area and number of layers of the wiring board for mounting them have increased. Therefore, in order to suppress warping occurring in the wiring board, the thickness of the core layer of the wiring board tends to increase.

[0008] When the thickness of the core layer increases, the size of the through hole in the thickness direction increases. As a result, the coupling capacitance between differential signals increases and the differential impedance decreases. Due to this decrease in the differential impedance, impedance mismatch in the transmission path of the differential signal may increase. In this case, signal reflection occurs in the transmission path of the differential signal and signal quality deterioration occurs.

[0009] This disclosure provides a configuration for a wiring board on which semiconductor integrated circuit devices and the like are mounted, which suppresses the reduction of differential impedance in the differential signal transmission path.

[0010] A first aspect of the present disclosure is a wiring board comprising: a core layer having through-holes penetrating in a first direction which is the thickness direction of the wiring board; and build-up layers, one or more layers each laminated on both sides of the core layer in the first direction, each layer having via holes penetrating in the first direction, wherein the through-holes of the core layer include first and second through-holes to which differential signals are connected, and a third through-hole to which a fixed potential is applied, and when viewed in the first direction, the third through-hole overlaps with the region between the first and second through-holes, sandwiched by the common outer tangents of the first and second through-holes, and the distance between the first through-hole and the third through-hole is equal to the distance between the second through-hole and the third through-hole.

[0011] According to this embodiment, the wiring board comprises a core layer having through-holes penetrating in a first direction, and build-up layers laminated on both sides of the core layer and having via holes. The through-holes in the core layer include first and second through-holes to which differential signals are connected, and a third through-hole to which a fixed potential is applied. When viewed in the first direction, the third through-hole overlaps with the region sandwiched between the common outer tangents of the first and second through-holes between the first and second through-holes, and the distance between the first and third through-holes is equal to the distance between the second and third through-holes. This arrangement of the third through-hole weakens the electromagnetic coupling between the first and second through-holes, reducing the coupling capacitance between differential signals. Therefore, a decrease in differential impedance can be suppressed, thereby suppressing impedance mismatch and preventing degradation of the signal quality of the differential signals.

[0012] In a second aspect of the present disclosure, a wiring board comprises a core layer having through-holes penetrating in a first direction perpendicular to the surface of the wiring board, and build-up layers, one or more layers stacked on each side of the core layer in the first direction, each layer having via holes penetrating in the first direction, wherein the through-holes of the core layer include first and second through-holes to which differential signals are connected, and a plurality of third through-holes to which a fixed potential is applied, and when viewed in the first direction, the plurality of third through-holes each overlap with the region between the first and second through-holes, sandwiched by the common outer tangents of the first and second through-holes, and the positional relationship between the first through-hole and the plurality of third through-holes and the positional relationship between the second through-hole and the plurality of third through-holes are line-symmetric or point-symmetric.

[0013] According to this embodiment, the wiring board comprises a core layer having through-holes penetrating in a first direction, and build-up layers laminated on both sides of the core layer and having via holes. The through-holes in the core layer include first and second through-holes to which differential signals are connected, and a plurality of third through-holes to which a fixed potential is applied. When viewed in the first direction, each of the plurality of third through-holes overlaps with the region sandwiched between the common outer tangents of the first and second through-holes between the first and second through-holes, and the positional relationship between the first through-hole and the plurality of third through-holes and the positional relationship between the second through-hole and the plurality of third through-holes are line-symmetric or point-symmetric. This arrangement of the plurality of third through-holes weakens the electromagnetic coupling between the first and second through-holes, and reduces the coupling capacitance between differential signals. Therefore, a decrease in differential impedance can be suppressed, thereby suppressing impedance mismatch and preventing degradation of the signal quality of the differential signals.

[0014] According to this disclosure, it is possible to suppress the decrease in differential impedance in the differential signal transmission path of a wiring board on which semiconductor integrated circuit devices and the like are mounted.

[0015] A cross-sectional view showing the schematic configuration of the wiring board according to the embodiment. A plan view showing the configuration of the multilayer wiring structure in the wiring board. Cross-sectional view of the configuration of Figure 2. (a) to (d) are detailed views of the wiring patterns in each wiring layer of Figure 3. (a) to (c) are examples of the planar arrangement of through-holes and solder balls according to Modification 1. (a) to (d) are examples of the planar arrangement of through-holes and solder balls according to Modification 2.

[0016] The embodiments will be described below with reference to the drawings. In the following description, the thickness direction of the wiring board, in other words, the direction perpendicular to the surface of the wiring board, is referred to as the Z direction (corresponding to the first direction).

[0017] Figure 1 is a cross-sectional view showing the schematic configuration of a wiring board according to an embodiment. As shown in Figure 1, the wiring board 10 is connected to a semiconductor integrated circuit device 20 mounted at the top of the drawing via bumps 21. The bumps 21 are formed by solder, for example, but are not limited to this. The wiring board 10 is also connected to a circuit board (not shown) at the bottom of the drawing via solder balls 22.

[0018] The wiring board 10 comprises a core layer 11 and build-up layers 12 and 13 stacked above and below the core layer. The core layer 11 includes a relatively thick insulating substrate 11a and has through-holes (PTH: Plated Through Hole) 14 that penetrate the insulating substrate 11a in the Z direction. The through-holes 14 have a metal 14a plated on their inner surface and are further filled with resin 14b inside. Note that the through-holes 14 do not necessarily have to be filled with resin, and metal may be filled instead of resin.

[0019] Each of the build-up layers 12 and 13 consists of two layers of insulating substrate 12a, which is thinner than the insulating substrate 11a of the core layer 11. Each layer of the build-up layers 12 and 13 has via holes 15 that penetrate the insulating substrate 12a in the Z direction. The inside of the via holes 15 is filled with metal. In addition, metal wiring 16 is provided on the surface of the build-up layers 12 and 13 and between the layers.

[0020] On the wiring board 10, a multilayer wiring structure is formed by through-holes 14, via holes 15, and metal wiring 16. The semiconductor integrated circuit device 20 located at the top of the diagram of the wiring board 10 and the circuit board located at the bottom of the diagram of the wiring board 10 are connected to each other by the multilayer wiring structure formed on the wiring board 10.

[0021] Figure 2 is a plan view showing the configuration of a multilayer wiring structure for transmitting differential signals on a wiring board 10. In Figure 2, only solder balls, through holes, via holes (on the top layer of the build-up layer), and wiring related to the differential signal transmission path are shown. Figure 3 is a cross-sectional view of the configuration in Figure 2, showing the cross-sectional structure along line Y1-Y1'. Figure 4 is a detailed view of the wiring patterns in the wiring layers (layers A to F) shown in Figure 3, where (a) is layer A, (b) is layers B and E, (c) is layers C and D, and (d) is layer F.

[0022] The solder balls 22A and 22B receive differential signals from the circuit board or output differential signals to the circuit board. The solder balls 22A and 22B are connected to through-holes 14 (denoted as PTH1 and PTH2) in the core layer 11 via via holes 15 and wiring formed in the build-up layer 13 located below the core layer 11. PTH1 and PTH2 of the core layer 11 are further connected to via holes 15 and wiring formed in the build-up layer 12 located above the core layer 11. In Figure 2, the wiring 41A and 41B that transmit differential signals are connected to via holes 15 in the uppermost layer of the build-up layer.

[0023] As shown in Figure 2, in a plan view (when viewed in the Z direction), the centers of PTH1 and solder ball 22A coincide, and the centers of PTH2 and solder ball 22B coincide. A through-hole 14 (let's call it PTH3) with a fixed potential of VSS is placed between PTH1 and PTH2. Note that the fixed potential applied to PTH3 is not limited to VSS. The center of PTH3 lies on the straight line connecting the centers of PTH1 and PTH2, and is equidistant from PTH1 and PTH2. That is, the distance between the centers of PTH3 and PTH1 is equal to the distance between the centers of PTH3 and PTH2.

[0024] The placement of PTH3 weakens the electromagnetic coupling between PTH1 and PTH2, reducing the coupling capacitance between differential signals. This suppresses the decrease in differential impedance, thereby reducing impedance mismatch and preventing degradation of the signal quality of differential signals.

[0025] Furthermore, as shown in Figure 2, through-holes 14 (referred to as PTHX) to which a fixed potential VSS is applied are arranged around PTH1, PTH2, and PTH3. Note that the fixed potential applied to PTHX is not limited to VSS. PTHX reduces crosstalk between the differential signal and its surroundings, suppressing a decrease in signal quality. In addition, PTHX is arranged so that the load capacitance to PTH1 and PTH2 is equal to each other, so as not to disrupt the balance between the differential signals. In Figure 2, PTHX is arranged to the left, right, and above PTH1, and PTHX is arranged to the left, right, and below PTH2. That is, the arrangement of PTHX around PTH1 and the arrangement of PTHX around PTH2 are symmetrical with respect to a straight line in the horizontal direction of the drawing that passes through PTH3.

[0026] Furthermore, as shown in Figure 4, in each wiring layer (layers A to F), ground planes 31, 32, 33, and 34, which are wirings with VSS assigned to them, surround the signal path of the differential signal. This reduces crosstalk between the differential signal and its surroundings, suppressing a degradation of signal quality.

[0027] As described above, according to this embodiment, the wiring board 10 comprises a core layer 11 having through-holes 14 penetrating in the Z direction, and build-up layers 12 and 13 laminated on both sides of the core layer 11 and having via holes 15. The through-holes 14 in the core layer 11 include PTH1 and PTH2 to which differential signals are connected, and PTH3 to which a VSS is applied. When viewed in the Z direction, the center of PTH3 lies on a straight line connecting the centers of PTH1 and PTH2, and is equidistant from PTH1 and PTH2. This arrangement of PTH3 weakens the electromagnetic coupling between PTH1 and PTH2, and reduces the coupling capacitance between differential signals. Therefore, a decrease in differential impedance can be suppressed, thereby suppressing impedance mismatch and preventing degradation of the signal quality of differential signals.

[0028] (Modification 1) Figures 5(a) to 5(c) show examples of the planar arrangement of through-holes and solder balls according to Modification 1.

[0029] In the arrangement shown in Figure 5(a), the positions of PTH1 and PTH2 are shifted to the left of the center of the solder balls 22A and 22B. The position of PTH3 is also shifted to the left by the same amount. In this arrangement as well, similar to the embodiment, the presence of PTH3 weakens the electromagnetic coupling between PTH1 and PTH2, reducing the coupling capacitance between differential signals.

[0030] Furthermore, the arrangement of the PTHX is the same as in the embodiment. Compared to the embodiment, the relationship between the distances of PTH1, PTH2 and PTXX has changed. However, the arrangement of PTH1 and the PTHX around it, and the arrangement of PTH2 and the PTHX around it, are symmetrical with respect to a straight line in the horizontal direction of the drawing that passes through PTH3. That is, as in the embodiment, the PTHX are arranged so that the load capacitance to PTH1 and PTH2 is equal so as not to disrupt the balance between differential signals.

[0031] In the arrangement shown in Figure 5(b), the position of PTH1 is shifted to the left from the center of the solder ball 22A, and the position of PTH2 is shifted to the right from the center of the solder ball 22B. The position of PTH3 is the same as in the embodiment. In this arrangement as well, the presence of PTH3 weakens the electromagnetic coupling between PTH1 and PTH2, reducing the coupling capacitance between differential signals.

[0032] Furthermore, the arrangement of the PTHX is the same as in the embodiment. Compared to the embodiment, the relationship between the distances of PTH1, PTH2 and PTXX has changed. However, the arrangement of PTHX around PTH1 and the arrangement of PTHX around PTH2 are point-symmetric with respect to the center of PTH3. That is, as in the embodiment, the PTHX are arranged so that the load capacitance to PTH1 and PTH2 is equal so as not to disrupt the balance between differential signals.

[0033] In the configuration shown in Figure 5(c), the position of PTH3 is shifted to the left in the drawing. The positions of PTH1 and PTH2 are the same as in the embodiment. PTH3 overlaps with the region enclosed by the common external tangents ECT1 and ECT2 of PTH1 and PTH2. In the configuration shown in Figure 5(c), the degree to which PTH3 weakens the electromagnetic coupling between PTH1 and PTH2 can be reduced compared to the embodiment. As a result, the coupling capacitance between differential signals increases, and the degree to which the reduction of differential impedance is suppressed decreases. In other words, by adjusting the amount by which the position of PTH3 is shifted, the degree to which the reduction of differential impedance is suppressed can be controlled, thereby optimizing the impedance.

[0034] Furthermore, PTH3 has the effect of suppressing the reduction of differential impedance when at least a portion of it overlaps with the region between PTH1 and PTH2, which is enclosed by the common external tangents ECT1 and ECT2 of PTH1 and PTH2. By shifting the position of PTH3 in a direction equidistant from PTH1 and PTH2 within the range where it overlaps with this region, the degree to which the reduction of differential impedance is suppressed can be controlled.

[0035] Furthermore, in the arrangements shown in Figures 5(a) and 5(b), the position of PTH3 may be shifted. In this case as well, the degree to which the reduction of differential impedance is suppressed can be controlled by shifting the position of PTH3 in a direction equidistant from PTH1 and PTH2, within the range that overlaps with the region bounded by the common outer tangents of PTH1 and PTH2.

[0036] In other words, in this modified example, PTH3, to which VSS is provided, overlaps with the region between PTH1 and PTH2, bounded by the common external tangents ECT1 and ECT2 of PTH1 and PTH2, and the distance to PTH1 and the distance to PTH2 are equal. This arrangement of PTH3 weakens the electromagnetic coupling between PTH1 and PTH2, reducing the coupling capacitance between differential signals. Therefore, the decrease in differential impedance can be suppressed, thereby suppressing impedance mismatch and preventing degradation of the signal quality of the differential signals.

[0037] (Modification 2) Figure 6 shows an example of a planar arrangement of through-holes and solder balls according to Modification 2. In Figure 6, an example is shown in which two through-holes 14 (referred to as PTH3 and PTH4) with a fixed potential of VSS are placed between PTH1 and PTH2.

[0038] In Figure 6(a), PTH3 and PTH4 are positioned between PTH1 and PTH2, spaced apart in the horizontal direction of the drawing. PTH3 and PTH4 overlap with the regions between PTH1 and PTH2, respectively, that are bounded by the common external tangents ECT1 and ECT2 of PTH1 and PTH2. The distances between PTH1 and PTH3, PTH1 and PTH4, PTH2 and PTH3, and PTH2 and PTH4 are all equal, and the positional relationship between PTH1 and PTH3 and PTH4, and the positional relationship between PTH2 and PTH3 and PTH4, are symmetrical with respect to the line connecting the centers of PTH3 and PTH4. Even in this arrangement, the presence of PTH3 and PTH4 weakens the electromagnetic coupling between PTH1 and PTH2, and reduces the coupling capacitance between differential signals. Furthermore, by changing the distance between PTH3 and PTH4, the degree to which the electromagnetic coupling between PTH1 and PTH2 is weakened can be adjusted.

[0039] In Figure 6(b), the positions of PTH3 and PTH4 are shifted to the left compared to Figure 6(a). However, PTH3 and PTH4 overlap with the region between PTH1 and PTH2, respectively, which is enclosed by the common external tangents ECT1 and ECT2 of PTH1 and PTH2. In this arrangement as well, the positional relationship between PTH1 and PTH3 and PTH4, and the positional relationship between PTH2 and PTH3 and PTH4, are symmetrical with respect to the line connecting the centers of PTH3 and PTH4. Therefore, the same effect as in the arrangement in Figure 6(a) can be obtained.

[0040] In Figure 6(c), the position of PTH3 is shifted downwards in the drawing, and the position of PTH4 is shifted upwards in the drawing, compared to Figure 6(a). However, PTH3 and PTH4 overlap with the region between PTH1 and PTH2, respectively, which is enclosed by the common outer tangents ECT1 and ECT2 of PTH1 and PTH2. In this arrangement as well, the positional relationship between PTH1 and PTH3 and PTH4, and the positional relationship between PTH2 and PTH3 and PTH4, are point-symmetric with respect to the midpoint of the line connecting the centers of PTH3 and PTH4. Therefore, the same effect as in the arrangement in Figure 6(a) can be obtained.

[0041] In Figure 6(d), PTH3 and PTH4 are positioned such that the distances between PTH1 and PTH3, PTH1 and PTH4, PTH2 and PTH3, and PTH2 and PTH4 are all equal, compared to the arrangement of PTH1 and PTH2 shown in Figure 5(b). However, PTH3 and PTH4 overlap with the region between PTH1 and PTH2, respectively, which is bounded by the common external tangents ECT1 and ECT2 of PTH1 and PTH2. In this arrangement as well, the positional relationship between PTH1 and PTH3 and PTH4, and the positional relationship between PTH2 and PTH3 and PTH4, are point-symmetric with respect to the midpoint of the line connecting the centers of PTH3 and PTH4. The same effect as in Figure 6(a) can be obtained with this arrangement as well.

[0042] That is, in this modified example, the PTH3 and PTH4 to which VSS is applied each overlap with the region sandwiched between the common external tangents ECT1 and ECT2 of PTH1 and PTH2 between PTH1 and PTH2, and the positional relationship between PTH1 and PTH3, PTH4 and the positional relationship between PTH2 and PTH3, PTH4 are line-symmetric or point-symmetric. With such an arrangement of PTH3 and PTH4, the electromagnetic coupling between PTH1 and PTH2 is weakened, and the coupling capacitance between differential signals is reduced. Therefore, a decrease in differential impedance can be suppressed, so impedance mismatch can be suppressed, and deterioration of the signal quality of differential signals can be suppressed.

[0043] In this modified example, an example in which two through-holes 14 to which VSS is applied are arranged between PTH1 and PTH2 has been shown. However, three or more through-holes 14 to which VSS is applied may be arranged between PTH1 and PTH2. In this case, each of the through-holes 14 to which VSS is applied has an overlap with the region sandwiched between the common external tangents of PTH1 and PTH2 between PTH1 and PTH2, and the positional relationship between PTH1 and the through-hole 14 to which VSS is applied and the positional relationship between PTH2 and the through-hole 14 to which VSS is applied may be line-symmetric or point-symmetric.

[0044] Also, in the above-described embodiments and modified examples, through-holes 14 to which VSS is applied are arranged between PTH1 and PTH2. However, the fixed potential applied to the through-holes 14 arranged between PTH1 and PTH2 is not limited to VSS, and may be other potentials.

[0045] Note that a plurality of multilayer wiring structures for differential signal wiring as described above may be formed on the wiring board. In this case, the arrangements of the through-holes 14 may be different from each other according to the required differential impedance for each multilayer wiring structure. For example, each multilayer wiring structure may be arranged as shown in FIG. 6(a), provided that the distances between PTH3 and PTH4 are different from each other.

[0046] This disclosure describes a wiring board on which semiconductor integrated circuit devices and the like are mounted, which can suppress the decrease in differential impedance in the transmission path of differential signals, and is therefore useful, for example, for improving the performance of semiconductor products.

[0047] 10 Wiring board 11 Core layer 12, 13 Build-up layers 14 Through-hole (PTH) 15 Via holes PTH1, PTH2, PTH3, PTH4, PTHX Through-hole ECT1, ECT2 Common external tangent

Claims

1. A wiring board comprising: a core layer having through-holes penetrating in a first direction which is the thickness direction of the wiring board; and build-up layers, one or more layers stacked on each side of the core layer in the first direction, each layer having via holes penetrating in the first direction, wherein the through-holes of the core layer include first and second through-holes to which differential signals are connected, and a third through-hole to which a fixed potential is applied, and when viewed in the first direction, the third through-hole overlaps with the region between the first and second through-holes, sandwiched by the common outer tangents of the first and second through-holes, and the distance between the first through-hole and the third through-hole is equal to the distance between the second through-hole and the third through-hole.

2. The wiring board according to claim 1, wherein the center of the third through-hole lies on a line connecting the centers of the first and second through-holes.

3. A wiring board according to claim 1, comprising a plurality of fourth through-holes located around the first through-hole and to which a fixed potential is applied, and a plurality of fifth through-holes located around the second through-hole and to which a fixed potential is applied, wherein the positional relationship between the first through-hole and the plurality of fourth through-holes and the positional relationship between the second through-hole and the plurality of fifth through-holes are symmetrical with respect to a line or point.

4. A wiring board comprising: a core layer having through-holes penetrating in a first direction perpendicular to the surface of the wiring board; and build-up layers, one or more layers stacked on each side of the core layer in the first direction, each layer having via holes penetrating in the first direction, wherein the through-holes in the core layer include first and second through-holes to which differential signals are connected, and a plurality of third through-holes to which a fixed potential is applied, and when viewed in the first direction, each of the plurality of third through-holes overlaps with the region between the first and second through-holes, sandwiched by the common outer tangents of the first and second through-holes, and the positional relationship between the first through-hole and the plurality of third through-holes and the positional relationship between the second through-hole and the plurality of third through-holes are line-symmetric or point-symmetric.

5. A wiring board according to claim 4, comprising a plurality of fourth through-holes located around the first through-hole and to which a fixed potential is applied, and a plurality of fifth through-holes located around the second through-hole and to which a fixed potential is applied, wherein the positional relationship between the first through-hole and the plurality of fourth through-holes and the positional relationship between the second through-hole and the plurality of fifth through-holes are symmetrical with respect to a line or point.

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