Task allocation device and program

Abstract

Provided is a task allocation device (100) that allocates tasks to logical cores by using SMT, which makes one physical core artificially appear as multiple logical cores. The task allocation device (100) comprises a task management unit (110) that performs task management by, on the basis of the processor idle state of the physical core, shifting and allocating, to logical cores within the same physical core, task groups which have low processing frequency and can sleep for longer than a prescribed time period. A task having a low processing frequency is, for example, a room for which resources are reserved preliminarily, or a room in which no speaking person is present and silence compression is being performed.

Description

Task Allocation Device and Program

[0001] The present invention relates to a task allocation device and a program.

[0002] In the background art, there are a metaverse service system, SMT (Simultaneous Multi Threading) technology, a multi-core CPU, and a CPU power saving function. Hereinafter, the outlines will be described in order. [Metaverse Service System] A metaverse in which users act via avatars in a virtual space has attracted attention. In the metaverse (virtual space), there is a function to create a room among nearby users (such as avatars) in order to perform real-time communication such as audio and video between users located in the vicinity.

[0003] FIG. 14 is a diagram showing a configuration example of the metaverse service system. The metaverse service system 1 shown in FIG. 14 is such that a plurality of users simultaneously participate in a virtual space 2 on the Internet using avatars 3 and freely move within the virtual space 2 with the avatars 3. The avatars 3 participating in the virtual space 2 are attached with identification marks 4, and the identification marks 4 are color-coded for each attribute of the participating users.

[0004] The avatar 3 is a character object that serves as a user's alter ego. The virtual space composed of 2D or 3D includes, in addition to a room for displaying the avatar 3 and a game space where the avatar 3 can be operated, a metaverse space for the purpose of communication with other users, etc.

[0005] Users can perform communication with other users, shopping, video distribution, appreciation meetings of various contents, etc. in the virtual space 2. Users can control so that voice and video calls can be made between nearby users by surrounding and designating (reference numeral aa in FIG. 14) the avatars 3 within the virtual space 2 (arrow bb in FIG. 14). The metaverse service system 1 is realized by a server capable of data communication via a network not shown. The server includes a virtual space control unit 10, a session control unit 11, and a media processing unit 12.

[0006] The virtual space control unit 10 has functions such as avatar position control, avatar profile management, and game scenarios. The session control unit 11 performs session control between the mobile information terminal 5 and personal computer 6 and the media processing unit 12, for example using SIP (Session Initiation Protocol). The media processing unit 12 realizes real-time communication via voice communication, for example using RTP (Real-time Transport Protocol). The media processing unit 12 realizes voice communication by resampling and encoding media data such as voice data and generating RTP packets, etc.

[0007] A mobile information terminal 5 and a personal computer 6 can be connected to the metaverse service system 1. The mobile information terminal 5 and the personal computer 6 can communicate via the network with the session control unit 11 and the media processing unit 12. The session control unit 11 and the media processing unit 12 perform real-time communication control with the mobile information terminal 5 and the personal computer 6.

[0008] The virtual space control unit 10 instructs the session control unit 11 and the media processing unit 12 to create a room so that real-time communication can be performed between nearby users (code cc in Figure 14).

[0009] On the other hand, the CPU (Central Processing Unit) has a function to control the CPU's idle state through hardware control, which is called LPI (Low Power Idle). LPI is also often referred to as CPUidle or C-state, and below, LPI will be explained as C-state (details will be shown later in Figures 17 to 20). When the CPU load decreases, C-state attempts to conserve power by turning off the power to some of the CPU's circuits (Patent Documents 1 and 2).

[0010] Patent Document 1 discloses a task scheduler device that takes C-state into consideration. The task scheduler device described in Patent Document 1 colors the CPU cores into "busy" and "idle" groups in task management, setting shallow C-states for the "busy" CPU cores and deep C-states for the "idle" CPU cores.

[0011] Patent Document 2 discloses a packet forwarding system that takes CPU idle into consideration. In the packet forwarding system described in Patent Document 2, the packet receiving function transitions to a deep C-state when the packet arrival frequency is low, and in order to mitigate the recovery time from the deep C-state, it anticipates packet arrival and performs pre-wake-up.

[0012] Figure 15 is a schematic diagram of the metaverse service system. As shown in Figure 15, the metaverse service system 1 (Figure 14) includes a server 1A. Server 1A has hardware (HW) 20, an OS 30, and room threads (thread for room #1, thread for room #2, thread for room #3, ...) 50 for displaying avatars in the metaverse service program on the user space 40.

[0013] The hardware 20 includes a processor 21 such as a CPU and a NIC (Network Interface Card) 26. The processor 21 has multiple CPU cores #0, CPU core #1, CPU core #2, etc. The NIC 26 is NIC hardware that realizes the NW interface.

[0014] The OS 30 includes a packet forwarding unit 31. The packet forwarding unit 31 includes a packet processing API (Application Programming Interface) and implements packet processing functions when a packet arrives at the NIC 26 and when a packet is forwarded to the NIC 26.

[0015] The room threads (thread for room #1, thread for room #2, thread for room #3, ...) 50 are threads of the program that displays avatars, and a number of room threads are created equal to the number of avatars participating in the metaverse. Figure 15 shows the thread for room #1, thread for room #2, thread for room #3, ..., but in reality, a huge number of room threads are launched based on a vast number of room creation instructions. Each room thread 50 has a session control thread (labeled as session control in Figure 15) 11 for connecting to the session control unit 11 in Figure 14, and a media processing thread (labeled as media processing in Figure 15) 12 for connecting to the media processing unit 12 in Figure 14.

[0016] [SMT Technology] On the other hand, vRAN (virtual Radio Access Network) and AI (Artificial Intelligence) inference technologies heavily utilize CPU computations. For example, applications that perform signal and media processing on the CPU (e.g., vRAN L1 signal processing and Deep Learning) heavily utilize the CPU's SIMD (Single Instruction Multiple Data) instruction set (e.g., Intel SSE / AVX512) ("Intel" is a registered trademark) for high-throughput computation. SIMD instructions use hardware multithreading, which makes one physical core appear as multiple logical cores, to assign a dedicated instruction execution process to each logical core. Conventional technology has been used to ensure equality by allocating a certain amount of CPU time to each process.

[0017] SMT technologies such as Intel Hyper-Threading are techniques that share the arithmetic units of a CPU's microinstructions among logical cores, thereby increasing the utilization rate of those units. However, depending on the type of instruction, the execution of microinstructions within a core can conflict, leading to performance degradation (known as the "Port Contention event"). Specifically, vector arithmetic microinstructions, which are frequently used in vRAN, have a small number of arithmetic units within the core and are therefore prone to conflict.

[0018] [CPU Cores and Intra-Core Performance Counters (PMU / PMC)] This section provides an overview of CPU cores and intra-core performance counters (PMU (Performance Monitoring Unit) / PMC (Performance Monitoring Counter)). Figure 16 is a diagram illustrating the overview of CPU cores and intra-core performance counters (PMU / PMC). Figure 16 shows a CPU core, and the enlarged view of Figure 16 shows an example of a performance counter installed on a logical core. The processor 21, such as the CPU shown in Figure 16, has four physical cores 22 ("four physical cores") and pairs of logical cores 23 residing on the same physical core 22 via SMT. For example, in the processor 21, logical cores 0 and 4 share the same physical core 22. In this case, of the pairs of logical cores 0 and 4 residing on the same physical core 22, logical core 0 is the "front core" of the same physical core 22, and logical core 4 is the "back core" of the same physical core 22. For example, logical cores 3 and 7 share the same physical core 22 (see dashed line ee in Figure 16).

[0019] Many CPUs are equipped with a Programming Unit (PMU) for application optimization and performance measurement. For example, Intel CPUs have 4 to 8 PMCs per logical core, enabling dynamic acquisition of CPU core performance metrics. The PMC can acquire a wide range of data, including internal core behavior (core computation bottleneck, memory access bottleneck, internal instruction type utilization), CPU frequency, and uncore frequency.

[0020] Among CPU performance counters, PMC, which allows for dynamic changes in the data acquired, has a limited number of units per CPU core. Switching is necessary when acquiring more metrics than the number of PMC units available. Furthermore, instruction execution on the target core is required for data acquisition.

[0021] [LPI (Low Power Idle) Hardware Control] The CPU has a function to control the CPU's idle state through hardware control, which is called LPI. LPI is also often called CPUidle or C-state, and below, LPI will be explained as C-state. When the CPU load is low, C-state attempts to conserve power by turning off the power to some of the CPU's circuits.

[0022] Figure 17 is a table illustrating an example of the C-state. Note that the state definition differs depending on the CPU hardware, so Figure 17 is for reference only. As shown in Figure 17, the CPUidle state has grades C0 to C6, and as the time without CPU load increases, it transitions to a deeper sleep state. Deeper sleep states consume less CPU power, but on the other hand, the time required to recover is longer, which can be a problem from the perspective of low latency.

[0023] The definition of C-states varies depending on the CPU hardware. For example, some models lack C4 and C5 states, while others have a state where C1 is followed by C1E. As the state deepens, the power saving effect increases, but the time required to recover from the idle state also increases. Furthermore, the depth to which the CPU idle state transitions is controlled by the CPU hardware and is product-dependent (often not controllable by software such as the kernel).

[0024] Figure 18 is a table showing an example of the maximum values ​​for the transition time to a state (Residency) and the time required to return to the previous state (Wake-up lateny). Figure 18 represents the C-state information for the Intel Xeon CPU E5-26X0 v4 ("Intel" is a registered trademark).

[0025] Figures 19 and 20 are diagrams illustrating the C-state transitions of the CPU core used for calculations. Figure 19 shows the case where the idle time is short, and Figure 20 shows the case where the idle time is long. As shown in Figure 19, when the idle time is short, the CPU core is in a shallow sleep state, and the delay time from task occurrence to recovery is short. However, as shown in Figure 20, when the idle time is long, the CPU core is in a deep sleep state (CPU idle state: grade C6), and the delay time from task occurrence to recovery is prolonged. When the CPU falls into a deep idle state, it takes a long time to recover, which impairs real-time performance.

[0026] Therefore, in task processing systems, measures are taken to disable C-states or to limit the transition to idle states to a limited depth such as C1. In other words, tuning is sometimes performed to prioritize real-time performance at the expense of power efficiency. In conventional task processing systems, once the system fell to a deep C-state, there was nothing to do but wait for it to recover. Therefore, measures were taken to prevent the system from falling to such deep states, even at the expense of power efficiency.

[0027] [Example of internal structure of media processing unit 12 in Figure 14] Figure 21 shows an example of the internal structure of the media processing unit 12 in Figure 14. The same reference numerals are used for the same components as in Figure 16. The processor 21 shown in Figure 21 is a CPU and has, for example, five physical cores 22a to 22e (collectively referred to as physical cores 22). One physical core 22 is used as multiple logical cores by SMT. For example, physical core 22a is shared by logical cores #0 and #1. Logical core #0 is assigned a task for the Room 1 thread (Figure 15) by a task scheduler (not shown) (hereinafter referred to as "assigning the Room 1 thread"), and logical core #1 is assigned the Room 2 thread. Similarly, physical core 22b is assigned the Room 3 thread to logical core #2, and the Room 4 thread to logical core #3. Similarly, for physical cores 22c to 22e, each room's thread is assigned to one of the two logical cores that share the same physical core 22.

[0028] In the following explanation, regarding the notation method for the diagram (Figure 21) showing an example of the internal structure of a CPU core, the upper logical cores #0, #2, #4, #6, and #8 within the processor (CPU) 21 will be referred to as the "front cores" (logical cores 23a) of the same physical core 22, and the lower logical cores #1, #3, #5, #7, and #9 will be referred to as the "back cores" (logical cores 23b) of the same physical core 22. Furthermore, among the logical cores in Figure 21, the shaded logical cores indicate that the task is "busy," and the unshaded logical cores indicate that the task is "free" or "empty" (the definitions of "busy," "free," and "empty" will be described later).

[0029] International Publication No. 2024 / 013831, International Publication No. 2023 / 199519

[0030] When using SMT to utilize a single physical core as multiple logical cores, assigning tasks (threads) such as room media processing to logical cores can result in a mix of busy and idle tasks. This can prevent the physical core from being put to sleep, thus preventing the CPU core from transitioning to a deep C-state. Since a transition to a deep C-state is not possible unless the logical cores associated with the physical core are simultaneously in an idle state, this presents a challenge in that it results in a loss of opportunities for power consumption reduction.

[0031] For example, in the example of the internal structure of the media processing unit 12 shown in Figure 21, at least one of the logical cores associated with the physical cores 22a to 22d, either the "front core" (logical core 23a) or the "back core" (logical core 23b), is assigned a "busy" task. If a busy logical task 23 exists within a physical core 22, that physical core cannot transition to the idle state. That is, as shown by the symbol ff in Figure 21, the physical core cannot sleep and the CPU core cannot transition to a deep C-state (Figures 17 to 20). In Figure 21, of the five physical cores 22a to 22e, only physical core 22e, where idle tasks are assigned to both logical core #8 ("front core") and logical core #9 ("back core"), can transition to the idle state.

[0032] Conventional task processing systems often do not consider SMT (Simultaneous Multitasking) and haphazardly place tasks (threads), resulting in a mix of busy and idle tasks on the CPU core, which hinders the transition of physical cores to an idle state.

[0033] In light of this background, the present invention was made, and its objective is to create more opportunities for the physical core to transition to the processor idle state, thereby improving power efficiency.

[0034] To solve the aforementioned problems, a task assignment device was provided that assigns tasks to logical cores using a function that treats one physical core as multiple logical cores, and is characterized by comprising a task management unit that performs task management by assigning tasks that meet predetermined conditions to other logical cores based on the processor idle state of the physical core.

[0035] According to the present invention, it is possible to create more opportunities for the physical core to transition to the processor idle state, thereby improving power efficiency.

[0036] This is a schematic diagram of a real-time communication control system equipped with a task assignment device according to the first embodiment of the present invention. This is a diagram illustrating an example of a "free" state for the task assignment device according to the first embodiment of the present invention. This is a diagram illustrating an example of a "busy" state for the task assignment device according to the first embodiment of the present invention. This is a diagram showing the task assignment image in the basic operation of the task assignment method of the task assignment device according to the first embodiment of the present invention. This is an operation flowchart showing a task assignment method that realizes the task assignment image of the task assignment device according to the first embodiment of the present invention. This is a diagram showing the task assignment image in the "reassignment when the task changes from free to busy" operation of the task assignment method of the task assignment device according to the first embodiment of the present invention. This is a flowchart showing the operation of "reassignment when the task changes from free to busy" for the task assignment device according to the first embodiment of the present invention. This is a diagram showing the task assignment image in the "reassignment when the task changes from busy to free" operation of the task assignment method of the task assignment device according to the first embodiment of the present invention. This is a flowchart showing the operation of "reassignment when the task changes from busy to free" for the task assignment device according to the first embodiment of the present invention. This is a diagram showing the task assignment image in the "periodic monitoring reassignment" operation of the task assignment method of the task assignment device according to the first embodiment of the present invention. This is a flowchart showing the operation of "periodic monitoring reassignment" for the task assignment device according to the first embodiment of the present invention. This figure shows an example configuration of a metaverse service system equipped with a task assignment device according to a second embodiment of the present invention. This is a flowchart showing the coordinated operation of the task management unit and the virtual space control unit of the task assignment device according to a second embodiment of the present invention. This is a hardware configuration diagram showing an example of a computer that realizes the functions of the task assignment device according to the first and second embodiments of the present invention. This figure shows an example configuration of a metaverse service system. This is a schematic configuration diagram of a metaverse service system. This figure explains the overview of CPU cores and intracore performance counters (PMU / PMC). This figure shows an example of C-state states in a table. This figure shows an example of the maximum values ​​of the time to transition to a state (Residency) and the time required to return (Wake-up lateny) in a table. This is an image diagram of the C-state transition of a CPU core used for calculations when the time without tasks is short.This figure shows an example of the internal structure of the media processing unit of a metaverse service system when there is a long period of no tasks. This figure shows an example of the internal structure of the media processing unit of Figure 14.

[0037] The following describes a task assignment device and the like in an embodiment of the present invention (hereinafter referred to as "this embodiment") with reference to the drawings.

[0038] (First Embodiment) [Overall Configuration] Figure 1 is a schematic diagram of a real-time communication control system equipped with a task assignment device according to the first embodiment of the present invention. The same reference numerals are used for components identical to those in Figure 15. The real-time communication control system of this embodiment is an example applied to the metaverse service system shown in Figure 14. The present invention is not limited to media processing, but also includes session control units for real-time communication and packet forwarding units for real-time communication.

[0039] As shown in Figure 1, the real-time communication control system 1000 includes hardware (HW) 20, an OS 30, and a user space 40, and a task assignment device 100 is provided on the OS 30 and the user space 40. The task assignment device 100 provides an application for communication between multiple users. The task assignment device 100 sets power saving settings for threads related to a room according to the actions of avatars in the room within the application (Figure 12 below).

[0040] The task assignment device 100 has a task management unit 110 and room threads (threads for room #1, room #2, room #3, etc.) 130 (threads for media processing, etc.) on the user space 40, and a processor idle state setting unit 120 on the OS 30. The above threads may also be "processes".

[0041] Hardware 20 includes a processor 21 such as a CPU and a NIC 26. The processor 21 has a plurality of CPU cores #0, CPU core #1, CPU core #2,.... The NIC 26 is NIC hardware that realizes a NW interface. The processor 21 is composed of CPUs. In addition to CPUs, there are accelerators such as GPUs (Graphic Processing Units), FPGAs (Field Programmable Gate Arrays), ASICs (Application Specific Integrated Circuits), and DPUs (Data Processing Units).

[0042] [Task Allocation Device] As shown by the dashed line in FIG. 1, the task allocation device 100 includes a task management unit 110, a processor idle state setting unit 120, and room threads (room #1 thread, room #2 thread, room #3 thread,...) 130 (threads for media processing, etc.).

[0043] <Task Management Unit 110> - The basic function task management unit 110 performs task management that biases and allocates a group of tasks (threads) that are assumed to have a low processing frequency and a long sleepable time based on the CPU idle state of the physical cores of the processor 21 to the logical cores within the same physical core. Specific examples of tasks with a low processing frequency include rooms with preliminary resource reservations and rooms where there is no speaker and are in silent compression.

[0044] The task management unit 110 defines, based on the processor idle state of the physical core, a case where the execution frequency of a task is sparse, the interval during task execution is more than a predetermined value, or the state where no task is allocated continues for more than a predetermined time as a group of tasks with a low processing frequency and a long sleepable time. Also, the task management unit 110 defines a case where the execution frequency of a task is dense, the interval during task execution is less than a predetermined value, or the time when no task is executed is less than a predetermined value as a group of tasks with a high processing frequency and a short sleepable time.

[0045] The "task that satisfies a predetermined condition" described in the claims refers to, for example, a task with a low processing frequency and a sleep time that can be longer than a predetermined time, a task with a high processing frequency and a sleep time that is shorter than a predetermined time, or other tasks in the task group defined above. The "assigning a task to another logical core" described in the claims means, for example, assigning it by shifting to a logical core within the same physical core.

[0046] The task management unit 110 includes a task allocation unit 111 and a CPU idle setting unit 112. When a task to be processed arrives, the task management unit 110 determines whether the task is a task with a high processing frequency and a sleep time that is shorter than a predetermined time (hereinafter referred to as a task with a high processing frequency) from the created room thread or the arrived task. The tasks to be processed include the processing of the speaker's voice data, RTCP (Real-time Transport Protocol Control Protocol) packets, DTX (Discontinuous Transmission) packets, etc. Also, the task management unit 110 is arranged in the user space 40, but it may be arranged in the OS 30 (for example, within the Linux kernel).

[0047] The task allocation unit 111 assigns a task (thread) to a logical core belonging to the physical core to which a task (thread) with a low processing frequency is assigned. The CPU idle setting unit 112 requests the processor idle state setting unit 120 to set the CPU core used by the corresponding task (thread) so that it can transition to a deep idle state.

[0048] - C-state setting for a processor to which a task (thread) with a low processing frequency is assigned. The CPU idle setting unit 112 sets the processor so that the CPU core to which a task (thread) with a low processing frequency is assigned can transition to a deep idle state (C-state).

[0049] - Setting C-states for processors assigned to high-frequency tasks (threads) The CPU idle setting unit 112 configures the processor to limit the number of transitionable idle states (C-states) to a shallow level for CPU cores assigned to high-frequency tasks (threads), according to service requirements.

[0050] - When a task (thread) with low processing frequency is elevated to a task (thread) with high processing frequency due to a change such as a participant in the room starting to speak, the thread status change response task management unit 110 reallocates the task to a physical CPU core that can process high-frequency tasks if there is a physical CPU core available for processing high-frequency tasks ("Reallocation 1").

[0051] When a task (thread) that was processed frequently is demoted to a task (thread) that is processed less frequently due to a change such as a participant in the room finishing speaking, the task management unit 110 reallocates the task to a physical CPU core that processes the less frequently processed task ("Reallocation 2").

[0052] The task management unit 110 periodically monitors the status of tasks (threads), and if there is an imbalance (a mix of busy and idle) in the types of tasks (threads) assigned to physical cores, it reallocates them using the basic function method described above ("Reallocation Method 3").

[0053] The task management unit 110 monitors the status of each room thread 130. The monitoring triggers are: (1) periodic monitoring, (2) when a room thread 130 is started, and (3) when there is a change in the status of a room thread 130. Regarding the status management of the room thread 130, when there is a change in the status of a room thread 130, the room thread 130 may notify the task management unit 110 of the change in status.

[0054] <Processor idle state setting unit 120> The processor idle state setting unit 120 sets the idle state of the CPU core used by the relevant task (thread) so that it can transition to a deep idle state, in accordance with the setting request from the task management unit 110. The processor idle state setting unit 120 basically sets the CPU core used by the room thread 130 so that it can transition to a deep idle state.

[0055] The "deep idle state" described in the claim refers to a predetermined grade when the CPU idle state is defined by a grade. Similarly, the "shallow idle state" also refers to a predetermined grade when it is defined by a grade. For example, LPI (Low Power Idle) hardware control has a function to control the idle state of the CPU by hardware control (Figure 17). LPI is often referred to as CPUidle or C-state, and below, LPI will be described as C-state. The CPU idle state has grades C0 to C6. The "deep idle state" described in the claim refers to a predetermined grade (for example, grade C6).

[0056] The definition of C-states varies depending on the CPU hardware. For example, there are variations such as models that do not have C4 or C5 states, or models where the state after C1 is C1E (Figure 18). Furthermore, the depth to which the CPUidle state transitions is controlled by the CPU hardware and is product-dependent (often not controllable by software such as the kernel).

[0057] <Room Thread 130> Room threads (Thread for Room #1, Thread for Room #2, Thread for Room #3, ...) 130 are program processes that handle media processing exchanged within a room. Media processing exchanged within a room includes signal processing such as SIP for session control processing and avatar processing to display avatars. Room threads 130 are threads for media processing, etc., and here, as many room threads as there are avatars participating in the metaverse are created. Figure 1 shows threads for Room #1, Thread for Room #2, Thread for Room #3, ..., but in reality, a huge number of room threads are launched based on a massive number of room creation instructions.

[0058] [Examples of Definitions of Idle / Busy] Examples of definitions of idle / busy are explained below. "Idle" refers to a state where sufficient CPU idle time can be secured for the CPU cores. Figure 2A is a diagram illustrating an example of "idle". The upper part of Figure 2A shows an example of an "idle" pattern where sufficient CPU idle time can be secured. The symbol 'a' in the upper part of Figure 2A indicates a state where a task is being executed on the CPU. As shown in the upper part of Figure 2A, the execution frequency of tasks is sparse, and there is sufficient time between task executions. In such cases, it is defined as "idle" where sufficient CPU idle time can be secured for the CPU cores.

[0059] The lower section of Figure 2A shows another example of a "free time" pattern where sufficient CPU idle time can be secured. As indicated by the symbol b in the lower section of Figure 2A, even if a task takes a long time to execute, a long period of time follows where no task is assigned. In such cases, we also define this as "free time" where sufficient CPU idle time can be secured for the CPU cores.

[0060] "Busy" refers to a situation where sufficient CPU idle time cannot be secured for the CPU cores. Figure 2B illustrates an example of "busy." The upper part of Figure 2B shows an example of a "busy" pattern where sufficient CPU idle time cannot be secured. As indicated by the symbol c in the upper part of Figure 2B, tasks are constantly running, and there is no time when tasks are not running. In such cases, it is defined as "busy" because sufficient CPU idle time cannot be secured for the CPU cores.

[0061] The lower section of Figure 2B shows another example of a "busy" pattern where sufficient CPU idle time cannot be secured. As indicated by the symbol d in the lower section of Figure 2B, the task execution frequency is high and the intervals between task executions are small. In such cases, we also define it as a "busy" state where sufficient CPU idle time for the CPU cores cannot be secured.

[0062] The operation of the task assignment device 100, configured as described above, will be explained below.

[0063] <Basic Operation of Task Assignment Device 100> Figure 3 is a diagram showing the task assignment image in the basic operation of the task assignment method of the task assignment device 100. The same reference numerals are used for the same components as in Figure 21. The task management unit 110 performs task management by assigning groups of tasks (threads) that are expected to have low processing frequency and long sleep times, based on the CPU idle state of the physical cores of the processor 21, to logical cores within the same physical core.

[0064] As shown in Figure 3, the task management unit 110 assigns a group of tasks (threads for Room 3, Room 4, Room 7, and Room 8) that are expected to have low processing frequency and long sleep times, based on the CPU idle state of the physical cores of the processor 21, to the logical cores within the same physical core. In Figure 3, the task management unit 110 assigns the Room 3 thread "idle" to logical core #2 ("front core") which shares the same physical core 22b, and the Room 4 thread "idle" to logical core #3 ("back core"). It also assigns the Room 7 thread "idle" to logical core #6 ("front core") which shares the same physical core 22d, and the Room 8 thread "idle" to logical core #7 ("back core").

[0065] In other words, the "idle" threads for Room 3 and Room 4 are assigned to logical cores #2 and #3 within the same physical core 22b, while the "idle" threads for Room 7 and Room 8 are assigned to logical cores #6 and #7 within the same physical core 22d. As a result, logical cores #2 and #3, which share the same physical core 22b, are both assigned idle tasks (threads for Room 3 and Room 4), allowing physical core 22b to transition to a CPU idle state. Similarly, logical cores #6 and #7, which share the same physical core 22d, are both assigned idle tasks (threads for Room 7 and Room 8), allowing physical core 22d to transition to a CPU idle state. In this way, by assigning groups of tasks (threads) that are expected to have low processing frequency and long sleep times to logical cores within the same physical core, more opportunities can be created for the physical core to transition to a CPU idle state.

[0066] <Flowchart of the task assignment image in Figure 3> Figure 4 is an operation flowchart showing the task assignment method that realizes the task assignment image in Figure 3. In step S11, the task management unit 110 determines whether or not a room for real-time communication between users has been created, such as when users gather in the vicinity. If a room for real-time communication between users has been created (S11: Yes), the process proceeds to step S13.

[0067] If a room for real-time communication between users is not created (S11: No), in step S12 the task management unit 110 determines whether or not a task to be processed (such as processing speaker voice data, RTCP packets, or DTX packets) has arrived. If a task to be processed has arrived (S13: Yes), the process proceeds to step S13. If no task to be processed has arrived (S13: No), the processing of this flow is terminated.

[0068] Here, tasks (threads) may be assigned separately as C-plane processing and U-plane processing. C-plane processing includes session control processing such as SIP (Session Initiation Protocol). However, session control processing may occur frequently due to session updates such as the addition of users. On the other hand, U-plane processing includes processing of voice data spoken by the user. However, voice data may not be transmitted or received when the user is not speaking due to silent compression.

[0069] Furthermore, tasks (threads) that are expected to be busy due to factors such as the presence of users who frequently participate in discussions in the room, or the presence of multiple users from the friend list, may be assigned to physical cores with high processing frequency.

[0070] Returning to the flow in Figure 4, in step S13, the task management unit 110 determines whether a task is frequently processed or not based on the created room threads and incoming tasks. If immediate determination is not possible, a CPU core is provisionally allocated. In this case, reallocation is performed according to the flow shown in Figures 6, 8, and 10 below.

[0071] In step S14, the task management unit 110 determines whether the processing frequency of the created room threads and the arrived tasks is low. If the processing frequency of the tasks is low (S14: Yes), in step S15, the task assignment unit 111 of the task management unit 110 assigns tasks (threads) to logical cores belonging to physical cores to which low-frequency tasks (threads) are assigned. Specifically, tasks (threads for Room 3, Room 4, Room 7, and Room 8) are assigned to logical cores #2, #3, #6, and #7 labeled "Idle" in Figure 3, respectively.

[0072] In step S16, the CPU idle setting unit 112 of the task management unit 110 requests the processor idle state setting unit 120 to set the CPU core used by the task (thread) to be able to transition to a deep idle state, and then terminates the processing of this flow.

[0073] On the other hand, in step S14, if the task processing frequency is high (S14: No), in step S17, the task assignment unit 111 of the task management unit 110 assigns tasks (threads) to logical cores belonging to physical cores to which high-frequency tasks (threads) are assigned. Specifically, tasks (threads for Room 1, Room 2, Room 5, and Room 6) are assigned to logical cores #0, #1, #4, and #5, which are labeled "Busy" in Figure 3.

[0074] In step S18, the CPU idle setting unit 112 of the task management unit 110 requests the processor idle state setting unit 120 to set a limit on the idle state to which the CPU core used by the task (thread) can transition, according to the service requirements, and then terminates the processing of this flow. Here, if the delay requirement is not strict in the above service requirements, it is not necessary to perform the limit setting.

[0075] Note that the process in step S18 is optional, and this flow may be terminated after the completion of step S17.

[0076] Furthermore, the task assignment device 100 only needs to assign tasks (threads) that are expected to have a low processing frequency and a long sleep time to logical cores within the same physical core. In other words, it is also possible to skip steps S17 and S18. However, by actively assigning tasks (threads) to logical cores belonging to physical cores to which high-frequency tasks (threads) are assigned, the target is clarified, and the effectiveness of this control (control that assigns tasks that are expected to have a low processing frequency and a long sleep time to logical cores within the same physical core) can be enhanced. The basic operation of the task assignment device 100 has been described above.

[0077] The following describes the reallocation of threads to physical CPU cores in response to changes in thread status. Reallocation to physical CPU cores includes (1) "Reallocation when status changes from idle to busy" (Figures 5 and 6), (2) "Reallocation when status changes from busy to idle" (Figures 7 and 8), and (3) "Reallocation for periodic monitoring" (Figures 9 and 10).

[0078] <Reassignment when task changes from idle to busy> Figure 5 shows an image of task assignment in the "reassignment when task changes from idle to busy" operation of the task assignment method of the task assignment device 100. The same reference numerals are used for the same components as in Figure 3. When a task (thread) that was previously processed infrequently is elevated to a task (thread) that is processed infrequently due to a change such as the start of speech by a participant in the room, the task management unit 110 performs task management by reallocating the task to a physical CPU core that is available to process the high-frequency task, if there is a physical CPU core available to process the high-frequency task.

[0079] For example, suppose that the task (thread "idle" for Room 4) on logical core #3 ("background core") within physical core 22b in the task assignment image shown in Figure 3 is elevated to a high-frequency task (thread "busy" for Room 4 in Figure 5) due to a change such as a participant in the room starting to speak. The task assignment unit 111 of the task management unit 110 reassigns the thread "busy" for Room 4 to logical core #7 ("background core") within physical CPU core 22d, which is available to handle the high-frequency task (arrow e in Figure 5).

[0080] As a result, initially, the same physical core 22b had a mix of idle tasks (thread "idle" for Room 3) and busy tasks (thread "busy" for Room 4), and logical cores #2 and #3 associated with physical core 22d could not enter the idle state simultaneously, thus preventing a transition to a deep core C-state. However, with this reallocation, both logical cores #2 and #3 associated with physical core 22b are assigned idle tasks, allowing physical core 22b to transition to the CPU idle state. Note that physical core 22d is unaffected because it originally had a mix of busy tasks (thread "busy" for Room 7) on logical core #6 and idle tasks (thread "idle" for Room 3) on logical core #7, and the situation in which physical core 22d cannot transition to the idle state remains unchanged. In this way, by assigning groups of tasks (threads) that are expected to have low processing frequency and long sleep times to logical cores within the same physical core, it is possible to create more opportunities for the physical core to transition to the CPU idle state.

[0081] <Fluent of "Reassignment when the status changes from idle to busy" in Figure 5> Figure 6 is a flowchart of the operation of "Reassignment when the status changes from idle to busy" in Figure 5. In step S21, the task management unit 110 determines whether a task (thread) that was processed infrequently has been elevated to a task (thread) that is processed infrequently due to a change such as the start of speech by a participant in the room. As a method for detecting a change such as the start of speech by a participant in the room, for example, the determination is made by detecting that media data such as voice is continuously sent by the user. If a task (thread) that was processed infrequently has not been elevated to a task (thread) that is processed infrequently (S21: No), the processing of this flow is terminated.

[0082] If a task (thread) that was previously processed infrequently is elevated to a task (thread) that is processed infrequently (S21: Yes), in step S22, the task management unit 110 determines whether or not there is a physical CPU core available to process the high-frequency task.

[0083] If there is a free physical CPU core for processing high-frequency tasks (S22: Yes), in step S23, the task management unit 110 executes the elevated task (thread) on a logical core within the physical CPU core for processing high-frequency tasks, and terminates the processing of this flow. Specifically, the task (thread for room 4) on logical core #3 within physical core 22b, labeled "Busy" in Figure 5, is reassigned to logical core #7 ("backup core") within physical CPU core 22d, which is free for processing high-frequency tasks (arrow e in Figure 5).

[0084] If, in step S22 above, there are no available physical CPU cores for processing high-frequency tasks (S22: No), then in step S24, the CPU idle setting unit 112 of the task management unit 110 requests the "processor idle state setting unit 120" to set the CPU cores used by the relevant task (thread) to have shallow idle states that it can transition to, according to the service requirements, and terminates the processing of this flow.

[0085] Note that the process in step S24 is optional, and if the delay requirements are not strict, the restriction setting does not need to be performed.

[0086] <"Reassignment when the status changes from busy to idle"> Figure 7 shows an image of task assignment in the "reassignment when the status changes from busy to idle" operation of the task assignment method of the task assignment device 100. The same reference numerals are used for the same components as in Figure 3. The task management unit 110 performs task management in which, when a task (thread) that had a high processing frequency is demoted to a task (thread) with a low processing frequency due to a change such as a participant in the room finishing speaking, it reallocates the low-processing-frequency task to a physical CPU core for processing the low-processing-frequency task.

[0087] For example, in the task assignment image shown in Figure 7, suppose that in the task (thread "busy" for Room 2) on logical core #1 ("background core") within physical core 22a, a task (thread) that was frequently processed is demoted to a task (thread) with a low processing frequency due to a change such as the participants in the room finishing their speech. The task assignment unit 111 of the task management unit 110 reassigns the thread "free" for Room 2 to logical core #3 ("background core") within physical CPU core 22b, which has a free physical CPU core for processing low-frequency tasks (arrow f in Figure 7).

[0088] In this way, demoted tasks are reassigned to logical core #3 ("backup core") within the physical CPU core 22b, which is available to handle low-frequency tasks, and wait on the logical core within the physical CPU core that handles low-frequency tasks. As a result, logical cores #2 and #3 associated with physical core 22b simultaneously enter an idle state, allowing them to transition to a deep core C-state. In other words, since demoted tasks are generally assumed to be in a waiting state, transitioning them to a deep idle state can further reduce power consumption.

[0089] On the other hand, initially, logical core #0, which shares the same physical core 22a, has a mix of busy tasks (threads for Room 1, "busy") and idle tasks (threads for Room 2, "idle"), and logical cores #0 and #1 associated with physical core 22a cannot simultaneously enter an idle state, so it is not possible to transition to a deep core C-state. As described above, even if the idle tasks (threads for Room 2, "idle") of logical core #1, which shares the same physical core 22a, are reassigned to logical core #3 ("background core") within CPU core 22b, physical core 22a cannot be dropped into a deep idle state because logical core #0 has busy tasks (threads for Room 1, "busy"). However, since logical core #1, which shares the same physical core 22a, becomes "empty", it becomes possible to assign any task to this logical core #1 regardless of the processing frequency, thus enabling highly flexible task (thread) assignment.

[0090] In this way, by assigning a group of tasks (threads) that are expected to have low processing frequency and long periods of sleep time to logical cores within the same physical core, it is possible to create more opportunities for the physical core to transition to a CPU idle state.

[0091] <Flowchart of "Reassignment when busy → idle" in Figure 7> Figure 8 is a flowchart of the operation of "Reassignment when busy → idle" in Figure 7. In step S31, the task management unit 110 determines whether a task (thread) that had a high processing frequency has been demoted to a task (thread) with a low processing frequency due to a change such as a participant in the room finishing speaking. As a method for detecting a change such as a participant in the room finishing speaking, for example, the unit determines this by detecting that media data such as voice emitted by the user has stopped. If a task (thread) that had a high processing frequency has not been demoted to a task (thread) with a low processing frequency (S31: No), the processing of this flow is terminated.

[0092] If a task (thread) with a high processing frequency is demoted to a task (thread) with a low processing frequency (S31: Yes), in step S32, the task management unit 110 determines whether the task (thread) has been frequently alternating between idle and busy periods in the most recent single hour. If the task (thread) has been frequently alternating between idle and busy periods in the most recent single hour (S32: Yes), the processing of this flow is terminated to avoid hunting.

[0093] If the task (thread) in question has not been frequently alternating between idle and busy in the most recent single period of time (S32: No), in step S33 the task management unit 110 determines whether or not there is a busy task (thread) in the physical core to which it currently belongs.

[0094] If there is a busy task (thread) in the currently assigned physical core (S33: Yes), in step S34, the task management unit 110 determines whether there is a free physical CPU core for processing low-frequency tasks. If there is no free physical CPU core for processing low-frequency tasks (S34: No), the processing of this flow is terminated.

[0095] If there is a free physical CPU core for processing low-frequency tasks (S34: Yes), in step S35, the task management unit 110 waits for the demoted task (thread) on a logical core within the physical CPU core for processing low-frequency tasks and terminates the processing of this flow. Specifically, the task (thread for Room 2) on logical core #1 within physical core 22a labeled "free" in Figure 7 is designated as the demoted task (thread), and is reassigned to logical core #3 ("backup core") within physical CPU core 22b, which is free for processing low-frequency tasks (arrow f in Figure 7), and waits on a logical core within the physical CPU core for processing low-frequency tasks.

[0096] On the other hand, if, in step S33, there are no "busy" tasks (threads) in the physical core to which the task currently belongs (S33: No), then in step S36, the CPU idle setting unit 112 of the task management unit 110, because there are no "busy" tasks (threads) in the physical core, requests the processor idle state setting unit 120 to set the CPU core used by the relevant task (thread) to transition to a deep idle state, and terminates the processing of this flow.

[0097] <"Reassignment under periodic monitoring"> Figure 9 shows an image of task assignment in the operation of the task assignment method "reassignment under periodic monitoring" of the task assignment device 100. The same reference numerals are used for the same components as in Figure 3. The task management unit 110 periodically monitors the status of tasks (threads), and if there is an imbalance (mixture of busy and idle) in the types of tasks (threads) assigned to physical cores, it performs reassignment according to the <basic operation of the task assignment device 100> (Figures 3 and 4).

[0098] For example, suppose that in the task assignment image shown in Figure 9, the task (thread "free time" for Room 4) on logical core #3 ("background core") within physical core 22b is demoted from a frequently processed task (thread) to a less frequently processed task (thread) due to a change such as the participants in the room finishing their speech. The task assignment unit 111 of the task management unit 110 reassigns the thread "free time" for Room 4 to logical core #7 ("background core") within physical CPU core 22d, which has a free physical CPU core for processing less frequently processed tasks (arrow g in Figure 9).

[0099] In this way, by assigning a group of tasks (threads) that are expected to have low processing frequency and long periods of sleep time to logical cores within the same physical core, it is possible to create more opportunities for the physical core to transition to a CPU idle state.

[0100] <Flowchart of "Reassignment of Periodic Monitoring" in Figure 9> Figure 10 is a flowchart of the operation of "Reassignment of Periodic Monitoring" in Figure 9. In step S41, the task management unit 110 periodically checks the relationship between the physical core (logical core) and the processing frequency of the task (thread) running on the corresponding core.

[0101] In step S42, the task management unit 110 makes the following conditional branching decision ("case") based on the status of the processing frequency of the physical core and the task (thread) ("switch").

[0102] If the "Physical core setting: Status of idle task (thread): Busy" (step S43), in step S44, the CPU idle setting unit 112 of the task management unit 110 requests the processor idle state setting unit 120 to set a limit on the idle state that the CPU core used by the task [thread] can transition to, according to the service requirements, and then terminates the processing of this flow. Note that if the delay requirements are not strict, it is not necessary to perform the limit setting.

[0103] If the "Physical core setting: busy task [thread] status: idle" (step S45), in step S46, the CPU idle setting unit 112 of the task management unit 110 requests the processor idle state setting unit 120 to set the CPU core used by the task (thread) to be able to transition to a deep idle state, and then terminates the processing of this flow.

[0104] If the "Physical core setting: Unspecified task (thread) status: Mixed busy and idle" (step S47), in step S48 the task management unit 110 determines whether or not there are any available physical CPU cores for processing high-frequency tasks.

[0105] If there is a free physical CPU core for processing high-frequency tasks (S48: Yes), in step S49 the task management unit 110 executes the elevated task (thread) on a logical core within the physical CPU core for processing high-frequency tasks, and terminates the processing of this flow. Specifically, the task (thread for room 4) on logical core #3 within physical core 22b, labeled "busy" in Figure 5, is reassigned to logical core #7 ("backup core") within physical CPU core 22d, which is free for processing high-frequency tasks (arrow e in Figure 5).

[0106] If, in step S48, there are no available physical CPU cores for processing high-frequency tasks (S48: No), in step S50, the CPU idle setting unit 112 of the task management unit 110 requests the processor idle state setting unit 120 to set the CPU cores used by the task (thread) to have shallow idle states to which it can transition, according to the service requirements, and terminates the processing of this flow.

[0107] Note that the process in step S50 is optional, and if the delay requirements are not strict, it is not necessary to perform the restriction setting.

[0108] (Second Embodiment) Figure 11 shows an example configuration of a metaverse service system (real-time communication control system) equipped with a task assignment device according to the second embodiment of the present invention. The same reference numerals are used for the same components as in Figure 14. The task assignment device of this embodiment is an example applied to the metaverse service system (real-time communication control system) shown in Figure 14. The present invention is not limited to media processing, but also includes session control units for real-time communication and packet forwarding units for real-time communication.

[0109] The metaverse service system 1000A shown in Figure 11 comprises a virtual space control unit 10, a session control unit 11, and a media processing unit 12A. The virtual space control unit 10 instructs the session control unit 11 and the media processing unit 12A to create rooms so that real-time communication can be established between nearby users. The session control unit 11 and the media processing unit 12A perform real-time communication control between the mobile information terminal 5 and the personal computer 6. In addition to the functions of the media processing unit 12 shown in Figure 14, the media processing unit 12A also includes a task assignment device 100.

[0110] Note that the placement of the task assignment device 100 is an example, and it may be installed outside the media processing unit 12A, for example. In the task assignment device 100 according to the second embodiment, the task management unit 110 (Figure 1) is linked with the status of users (rooms) in the virtual space of the virtual space control unit 10 (bidirectional arrow h in Figure 11). That is, the task management unit 110 (Figure 1) is linked with the virtual space control unit 10 to acquire information about the status of users in a room and the status of the room. Specifically, the task management unit 110 (Figure 1) acquires the status declared by the user (e.g., away from desk) from the virtual space control unit 10, etc., and makes a determination of whether the room is busy or idle according to the user status.

[0111] <Flowchart of the cooperation between the task management unit 110 and the virtual space control unit 10> Figure 12 is a flowchart showing the cooperation between the task management unit 110 and the virtual space control unit 10 of the task assignment device 100 shown in Figure 11. In step S51, the task management unit 110 (Figure 1) cooperates with the virtual space control unit 10 (Figure 11) to acquire information about the status of users in the room and the status of the room (bidirectional arrow h in Figure 11).

[0112] In step S52, the task management unit 110 determines whether the room thread or task is "busy" or "free" based on the acquired information regarding the status of users in the room and the status of the room. Examples of situations where the room thread or task is likely to be "free": - All users participating in the room are "away" or "muted" - All users participating in the room have the "voice call NG" sign displayed - The game scenario status is that the room is in a voice call NG state

[0113] Examples of situations where a room thread or task is likely to be "busy": - Users joining the room have a "Voice call welcome" sign displayed. - There are multiple friends in the room.

[0114] In step S53, the task management unit 110 assigns tasks to CPU cores according to whether they are "busy" or "free," sets the CPU idle setting to the corresponding CPU core, and terminates the processing of this flow.

[0115] [Hardware Configuration] The real-time communication control system 1000 and the metaverse service system 1000A according to the above embodiment are configured by a server such as the metaverse service system shown in Figure 14. When the real-time communication control system 1000 and the metaverse service system 1000A are configured by a server, the server is realized by a computer 900 configured as shown in Figure 13, for example. Figure 13 is a hardware configuration diagram showing an example of a computer 900 that realizes the functions of the task assignment device 100 (Figure 1). The computer 900 has a CPU 901, ROM 902, RAM 903, HDD 904, communication interface (I / F: Interface) 906, input / output interface (I / F) 905, and media interface (I / F) 907.

[0116] The CPU 901 operates based on programs stored in the ROM 902 or HDD 904, and controls each part of the task assignment device 100 shown in Figure 1. The ROM 902 stores boot programs executed by the CPU 901 when the computer 900 starts up, as well as programs that depend on the computer 900's hardware.

[0117] The CPU 901 controls input devices 910, such as a mouse or keyboard, and output devices 911, such as a display, via the input / output interface 905. The CPU 901 acquires data from the input devices 910 and outputs the generated data to the output devices 911 via the input / output interface 905. In addition to the CPU 901, a GPU (Graphics Processing Unit) or the like may also be used as a processor.

[0118] The HDD 904 stores programs executed by the CPU 901 and data used by those programs. The communication I / F 906 receives data from other devices via a communication network (e.g., NW (Network) 920) and outputs it to the CPU 901, and also transmits data generated by the CPU 901 to other devices via the communication network.

[0119] The media interface 907 reads a program or data stored in the recording medium 912 and outputs it to the CPU 901 via the RAM 903. The CPU 901 loads the program related to the desired processing from the recording medium 912 onto the RAM 903 via the media interface 907 and executes the loaded program. The recording medium 912 is an optical recording medium such as a DVD (Digital Versatile Disc) or PD (Phase Change Rewritable Disk), a magneto-optical recording medium such as an MO (Magneto Optical Disk), a magnetic recording medium, or a semiconductor memory.

[0120] For example, when computer 900 functions as a task assignment device 100 configured as one of the devices according to this embodiment, the CPU 901 of computer 900 realizes the function of the task assignment device 100 by executing a program loaded on RAM 903. The HDD 904 stores the data in RAM 903. The CPU 901 reads and executes a program related to the desired processing from the recording medium 912. Alternatively, the CPU 901 may read a program related to the desired processing from another device via a communication network (NW 920).

[0121] [Effects] As described above, the task assignment device 100 (Figure 1) assigns tasks to logical cores using a function that treats one physical core as multiple logical cores (for example, SMT which makes one physical core appear as multiple logical cores). The device includes a task management unit 110 that performs task management by assigning tasks that meet predetermined conditions to other logical cores based on the processor idle state of the physical core (for example, assigning a group of tasks with low processing frequency and sufficient sleep time to logical cores within the same physical core).

[0122] By doing so, the task assignment device 100 (Figure 1) can improve power efficiency by assigning groups of tasks (threads) that are expected to have low processing frequency and long sleep times to logical cores within the same physical core, thereby increasing the opportunities for the physical core to transition to the CPU idle state.

[0123] In the task assignment device 100 (Figure 1), when the task management unit 110 (Figure 1) assigns a group of tasks with low processing frequency and a sleep time of at least 100 to logical cores within the same physical core, it configures the processor so that the core to which the low-frequency task is assigned can transition to a deep idle state.

[0124] For example, specific examples of tasks with low processing frequency include rooms with reserved resources or rooms where there are no speakers and the sound is compressed to silence. By doing so, the task assignment device 100 (Figure 1) can create more opportunities for the physical core to transition to the CPU idle state, thereby improving power saving.

[0125] In the task assignment device 100 (Figure 1), the task management unit 110 (Figure 1) configures the processor to limit the range of idle states that can be transitioned to, according to service requirements, for cores that have been assigned tasks with high processing frequency and a predetermined sleep time or less.

[0126] By doing so, the task assignment device 100 (Figure 1) can extend the sleep time while meeting the delay requirements and media bitrate requirements specified in the service.

[0127] In the task assignment device 100 (Figure 1), when a task that was previously processed infrequently is upgraded to a task with a higher processing frequency, the task management unit 110 (Figure 1) reallocates the task to a physical core that is available to process the high-frequency task if such a core is available.

[0128] By doing so, the task assignment device 100 (Figure 1) actively assigns tasks (threads) to logical cores belonging to physical cores to which high-frequency tasks (threads) are assigned, thereby clarifying the target and making this control (a control that concentrates and assigns groups of tasks that are expected to have low processing frequency and long sleep times to logical cores within the same physical core) more effective.

[0129] In the task assignment device 100 (Figure 1), the task management unit 110 (Figure 1) reallocates tasks that were previously processed frequently to physical cores that process those tasks when those tasks are demoted to tasks with lower processing frequency.

[0130] By doing so, the task assignment device 100 (Figure 1) can further reduce power consumption by transitioning demoted tasks to a deep idle state, as it is generally assumed that the session will often be in a waiting state.

[0131] In the task assignment device 100 (Figure 1), the task management unit 110 (Figure 1) periodically monitors the status of tasks, and if there is an imbalance in the amount of sleep time available for the types of tasks assigned to physical cores, it rearranges the tasks by shifting groups of tasks with low processing frequency and a predetermined amount of sleep time to logical cores within the same physical core, based on the processor idle state of the physical core.

[0132] By doing so, the task assignment device 100 (Figure 1) can periodically monitor the status of tasks and acquire the imbalance in sleep time for the type of task assigned to the physical core, independently of the program trigger, thereby avoiding control failures.

[0133] In the task assignment device 100 (Figure 1), the task management unit 110 (Figure 1) determines the imbalance in the amount of time a room can sleep based on the actions of avatars in a room within an application that facilitates communication among multiple users.

[0134] In this way, the task assignment device 100 (Figure 1) can respond to ever-changing situations by reviewing the assignment of tasks and CPU cores according to the processing frequency of the tasks (for example, by reassigning tasks based on whether or not there is a speaker in the room).

[0135] For example, consider the case where the task assignment device 100 is applied to a real-time communication control system 1000A (metaverse service system). In metaverse use cases, even when real-time communication is not actually taking place between users, rooms are created in advance and processor resources are reserved so that nearby avatars can immediately begin conversing. When rooms are proactively created simply because users pass each other, resources (CPU cores) of the media processing function unit are reserved even when real-time communication is not actually taking place between users. When there is a high density of users on the metaverse, a huge number of room creation instructions will be issued.

[0136] Therefore, when using SMT to use one physical core as multiple logical cores, when assigning tasks (threads) that perform media processing in a room to the logical cores, a situation arises where busy and idle tasks are assigned to the logical cores, and this situation changes moment by moment. As mentioned above, in this case, the physical core cannot be put to sleep, and a transition to a deep core C-state cannot be made. The task management unit 110 (Figure 1) works in cooperation with the virtual space control unit 10 (Figure 11) to acquire information about the status of users in the room and the status of the room, thereby being able to respond to the moment by moment changing situation.

[0137] In the embodiments described above, an example was explained in which a single physical core is made to appear as multiple logical cores using SMT, and tasks are assigned to the logical cores. However, any device that has the function of treating a single physical core as multiple logical cores is acceptable, and is not limited to SMT.

[0138] Furthermore, among the processes described in each of the embodiments and application examples above, all or part of the processes described as being performed automatically can be performed manually, or all or part of the processes described as being performed manually can be performed automatically by known methods. In addition, the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above documents and drawings can be changed at will unless otherwise specified.

[0139] Furthermore, the components of each illustrated device are functionally conceptual and do not necessarily need to be physically configured as shown. In other words, the specific forms of distribution and integration of each device are not limited to those shown, and all or part of them can be functionally or physically distributed and integrated in any unit according to various loads and usage conditions.

[0140] Furthermore, each of the above configurations, functions, processing units, and processing means may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above configurations and functions may be implemented in software that allows the processor to interpret and execute programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC (Integrated Circuit) card, an SD (Secure Digital) card, or an optical disc.

[0141] 2 Metaverse (Virtual Space) 3 Avatar 20 Hardware (HW) 21 Processor 22, 22a-22d Physical Cores 23, 23a, 23b Logical Cores 30 OS 40 User Space 100 Task Assignment Device 110 Task Management Unit 111 Task Assignment Unit 112 CPU Idle Setting Unit 120 Processor Idle State Setting Unit 130 Room Threads (Threads for Media Processing, etc.) 1000 Real-time Communication Control System 1000A Metaverse Service System (Real-time Communication Control System)

Claims

1. A task assignment device that assigns tasks to logical cores using a function that treats one physical core as multiple logical cores, and is characterized by comprising a task management unit that performs task management by assigning tasks that meet predetermined conditions to other logical cores based on the processor idle state of the physical core.

2. The task assignment device according to claim 1, characterized in that when the task management unit assigns a group of tasks with low processing frequency and a predetermined amount of time that can sleep to logical cores within the same physical core, it configures the processor so that the core to which the low-frequency task is assigned can transition to a deep idle state.

3. The task assignment device according to claim 1, characterized in that the task management unit configures the processor to limit the transition to an idle state to a shallow level, according to service requirements, for cores to which tasks with high processing frequency and a predetermined sleep time are assigned.

4. The task assignment device according to claim 1, characterized in that when a task that was previously processed infrequently is upgraded to a task that is processed infrequently, the task management unit reallocates the task to a physical core that is available for processing high-frequency tasks if there is one available for processing high-frequency tasks.

5. The task assignment device according to claim 1, characterized in that when a task with a high processing frequency is demoted to a task with a low processing frequency, the task management unit reallocates the task to a physical core for processing tasks with a low processing frequency.

6. The task management unit periodically monitors the status of tasks, and if there is an imbalance in the amount of sleep time available for the types of tasks assigned to the physical core, it rearranges the tasks by shifting a group of tasks with low processing frequency and a predetermined or longer sleep time to logical cores within the same physical core, based on the processor idle state of the physical core. This is the task assignment device according to claim 1.

7. The task assignment device according to claim 1, characterized in that the task management unit determines the imbalance in the amount of time that a room can sleep in, in accordance with the actions of avatars in a room within an application for communication between multiple users.

8. A program for causing a computer to function as a task assignment device according to any one of claims 1 to 7.

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