Hardware embedded contextual embedding model

The hardware embedded contextual embedding model addresses computation and latency issues in DNNs by integrating the model onto an IC device, enhancing performance and security for edge devices.

WO2026101635A1 Publication Date: 2026-05-15INTEL CORP
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Patent Information

Application Number
PCT/US2025/049204
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-08-18
Filing Date
2025-10-02
Publication Date
2026-05-15

AI Technical Summary

Technical Problem

Existing neural networks for artificial intelligence applications, such as DNNs, face challenges with high computation costs, power consumption, latency, security, and connectivity issues, particularly in edge devices and cloud-based solutions, which are unsuitable for real-time processing and sensitive data handling.

Method used

A hardware embedded contextual embedding model is integrated onto an IC device, encapsulating the model architecture and weights, enabling efficient on-device processing with reduced data movement and power consumption, enhancing performance and security.

Benefits of technology

This approach provides faster, more power-efficient, and scalable processing suitable for edge computing and IoT applications, ensuring real-time computing and improved security by eliminating the need for data transfer and model loading.

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Abstract

An integrated circuit (IC) device may implement a contextual embedding model. The IC device may include a tokenizer unit, embedder unit, layer normalizer unit, dot unit, activator units, and flow control unit. The tokenizer unit may implement a tokenizer in the model and convert text to tokens using the vocabulary of the model. The embedder unit may implement embedders in the model and generate embeddings from the tokens. The layer normalizer unit may implement one or more layer normalizers in the model and compute embedding vectors. The dot unit may implement matrix multiplication and add operations in the encoders and pooler of the model. The activator units may implement activation functions, including tanh function, in the model. The flow control unit may orchestrate the other components of the IC device based on a timing sequence of neural network operations in the model.
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