Data transmission apparatus and method, and chip and data transmission system

Abstract

Provided in the embodiments of the present disclosure are a data transmission apparatus and method, and a chip and a data transmission system. The apparatus comprises: a data-receiving module, which is configured to receive write data packets and flag data packets sent by a main chip, wherein the write data packets originate from a plurality of interconnected devices, and the corresponding flag data packets are provided after the write data packets of the interconnected devices; a storage control module, which is configured to store the write data packets of the interconnected devices into a memory and then store into the memory the corresponding flag data packets after the write data packets; and a processing initiation module, which is configured to cause a processing device to determine, on the basis of the received flag data packets, that all the write data packets of the interconnected devices have been written, such that the processing device initiates processing. The embodiments of the present disclosure prevent latency in processing initiation caused by the processing device performing polling and readflush, and also reduce the bandwidth loss of a central processing unit and interconnect communication.

Description

Data transmission apparatus, method, chip and data transmission system Technical Field

[0001] This disclosure relates to the field of chip interconnect technology, and in particular to a data transmission device, method, chip, and data transmission system. Background Technology

[0002] In large-scale chip systems, each interconnect device sends write data packets to a processing device. After receiving all the write data packets from an interconnect device, the processing device performs processing for that interconnect device. Therefore, the processing device needs to determine the timing of processing.

[0003] Currently, processing devices rely on the interconnectivity of interconnected devices, using polling and read flushing to determine when processing can begin. However, this method makes it impossible for the processing device to accurately determine the processing time, causing processing startup latency. Furthermore, this method results in bandwidth loss for the central processing unit and the interconnect.

[0004] Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a data transmission apparatus, method, chip, and data transmission system to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a data transmission apparatus is provided, applied to a slave chip. The apparatus includes: a data receiving module, configured to receive write data packets and flag data packets sent by a master chip, wherein the write data packets come from multiple interconnect devices, and each interconnect device's write data packet is followed by a corresponding flag data packet; a storage control module, configured to store the write data packets of the interconnect devices into a memory, and then store the flag data packets corresponding to the write data packets into the memory; and a processing start module, configured to instruct a processing device to determine, based on the received flag data packets, that all write data packets of the interconnect devices have been written, and the processing device to start processing.

[0007] According to a second aspect of the present disclosure, a data transmission apparatus is provided, applied to a main chip. The apparatus includes: a data adding module, configured to set a corresponding flag data packet after all write data packets of each interconnected device; and a data sending module, configured to send the write data packets and the flag data packets to a slave chip, causing the slave chip to store the write data packets of each interconnected device into a memory and then store the flag data packets following the write data packets into the memory, causing a processing device to determine that all write data packets of the interconnected devices have been written based on the received flag data packets, and the processing device to start processing.

[0008] According to a third aspect of the present disclosure, a chip is provided, including the data transmission apparatus described in the first or second aspect above.

[0009] According to a fourth aspect of the present disclosure, a data transmission system is provided, comprising an interconnected master chip and a slave chip, the slave chip including the data transmission apparatus described in the first aspect, and the master chip including the data transmission apparatus described in the second aspect.

[0010] According to a fifth aspect of the present disclosure, a data transmission method is provided, applied to a slave chip, the method comprising: receiving write data packets and flag data packets sent by a master chip, the write data packets coming from multiple interconnect devices, and each interconnect device having a corresponding flag data packet following its write data packet; storing the write data packets of each interconnect device into a memory, and then storing the flag data packet following the write data packets into the memory; instructing a processing device to determine, based on the received flag data packets, that all write data packets of the interconnect devices have been written, and initiating processing.

[0011] According to a fifth aspect of the present disclosure, a data transmission method is provided, applied to a master chip, the method comprising: setting a corresponding flag data packet after all write data packets of each interconnected device; sending the write data packets and the flag data packets to a slave chip, causing the slave chip to store the write data packets of each interconnected device into a memory and then store the flag data packets following the write data packets into the memory, causing a processing device to determine, based on the received flag data packets, that all write data packets of the interconnected devices have been written, and the processing device to start processing.

[0012] According to the data transmission scheme provided in this disclosure, the slave chip receives write data packets and flag data packets sent by the master chip. The write data packets originate from multiple interconnect devices, and a flag data packet is set after all write data packets from each interconnect device. The slave chip stores the write data packets from each interconnect device into its memory, and then stores the flag data packets following the write data packets into its memory. The processing device determines that all write data packets from the interconnect device have been written based on the received flag data packets, and then starts processing. This disclosure avoids the processing startup delay caused by polling and read / refresh operations by the processing device, and also reduces bandwidth loss in the central processing unit and interconnect communication. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0014] Figure 1 is a schematic diagram of a data transmission system according to an embodiment of the present disclosure;

[0015] Figure 2 is a schematic diagram of a data transmission system according to another embodiment of the present disclosure;

[0016] Figure 3 is a schematic diagram of a chip according to an embodiment of this disclosure;

[0017] Figure 4 is a schematic diagram of a data transmission device applied to a main chip according to an embodiment of the present disclosure;

[0018] Figure 5 is a schematic diagram of a data transmission device applied to a chip according to another embodiment of the present disclosure;

[0019] Figure 6 is a schematic diagram of a memory applied to a data transmission device from a chip according to yet another embodiment of the present disclosure;

[0020] Figure 7 is a schematic diagram of a processing startup module applied to a data transmission device from a chip according to another embodiment of the present disclosure;

[0021] Figure 8 is a schematic diagram of a data transmission system according to another embodiment of the present disclosure;

[0022] Figure 9 is a flowchart of a data transmission method according to an embodiment of this disclosure;

[0023] Figure 10 is a flowchart of a data transmission method according to another embodiment of this disclosure. Detailed Implementation

[0024] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0025] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0026] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0027] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0028] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0029] First, some of the nouns or terms that appear in the description of the embodiments of this disclosure are to be interpreted as follows.

[0030] PCIe: PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard. Originally named "3GIO", it was proposed by Intel in 2001 to replace the older PCI, PCI-X and AGP bus standards.

[0031] PCIe P2P: Abbreviated as PCI-Express Peer-to-Peer, which means that one interconnected device can directly access another interconnected device.

[0032] The data transmission scheme provided by the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0033] Data transmission system

[0034] Figure 1 illustrates a schematic diagram of a data transmission system 1 applicable to an embodiment of this disclosure. As shown in Figure 1, the data transmission system 1 can be built based on various types of processing devices. The data transmission system 1 can be, for example, an Internet of Things (IoT) processing device system, a system-on-a-chip (SoC), a desktop processing system, or a data center processing system.

[0035] As shown in Figure 1, the data transmission system 1 may include a master chip 10, a slave chip 20, a memory 30, and a processing device 40. The master chip 10 in the data transmission system 1 is used to receive write data packets sent by multiple interconnected devices (not shown in the figure), the slave chip 20 is used to receive write data packets sent by the master chip 10 from multiple interconnected devices, the memory 30 is used to store write data packets provided by multiple interconnected devices, and the processing device 40 is used to process the received write data packets.

[0036] In some cases, memory 30 can be one memory or multiple sub-memories. The memory can be static random access memory or registers.

[0037] In some cases, the data transmission system 1 is applied to one of the following interconnection communications: PCIe P2P, Ethernet, Remote Direct Memory Access (RDMA), and Interlaken. The interconnection device in the data transmission system 1 includes one of the following: PCIe P2P processing device (not shown in the figure), Ethernet processing device (not shown in the figure), Remote Direct Memory Access processing device (not shown in the figure), and Interlaken processing device (not shown in the figure).

[0038] Typically, processing device 40 needs to obtain all write data packets from an interconnect device in order to initiate processing for that interconnect device. In some cases, processing device 40 includes at least one of a central processing unit and a digital processor.

[0039] In addition, the data transmission system 1 may also include storage processing devices, input / output processing devices, etc. The storage processing devices may be hard disks, optical disks, flash memory, or other processing devices used for information storage and retrieval, coupled to the interconnect bus via corresponding interfaces. The display processing devices may be coupled to the interconnect bus via a corresponding graphics card, used for displaying information according to the display signals provided by the interconnect bus.

[0040] The data transmission system 1 may further include a communication processing device, thereby enabling the data transmission system 1 to communicate with a network or other processing device in various ways. The communication processing device may include one or more communication modules, including wireless communication modules adapted to specific wireless communication protocols. For example, the communication processing device may include a WLAN module for implementing WiFi communication conforming to the IEEE 802.11 standard. The communication processing device may include a WWAN module for implementing wireless wide-area communication conforming to cellular or other wireless wide-area protocols. The communication processing device may also include communication modules employing other protocols, such as Bluetooth modules, or other custom-type communication modules. The communication processing device may also be a port for serial data transmission.

[0041] Figure 2 shows a schematic block diagram of another data transmission system 1, which is a PICe P2P interconnect communication system. This disclosure describes an embodiment where the data transmission system 1 includes a processing device 40, and the process of the processing device 40 receiving write data packets sent to it by two interconnected devices (not shown). It should be understood that Figure 2 is only one example of the data transmission system 1 and does not limit the number of processing devices included in the data transmission system 1 or the number of interconnected devices from which the processing device receives write data packets. In other embodiments, the data transmission system 1 may include a greater number of processing devices, and the processing device 40 in the data transmission system 1 may receive write data packets sent by a greater number of interconnected devices.

[0042] As shown in Figure 2, the main chip 10 of the data transmission system 1 receives write data packets 1data, 2data, 3data, and 5data sent by two interconnected devices, namely, write data packets 1data and 3data sent by the first interconnected device, and write data packets 2data and 5data sent by the second interconnected device. The main chip 10 adds a flag data packet 4flag after 1data and 3data sent by the first interconnected device. The main chip 10 adds a flag data packet 6flag after 2data and 5data sent by the second interconnected device.

[0043] In this sequence, the sequence numbers 1, 2, 3, and 5 in 1data, 2data, 3data, and 5data can serve as packet sequence numbers, indicating the order of data packets. However, sequence numbers 1, 2, 3, 4, 5, and 6 do not necessarily serve as packet sequence numbers indicating packet order; they are only used to distinguish different write data packets. Flag 4 can be placed after write data packets 1data and 3data, or after write data packets 3data and 1data. Similarly, flag 6 can be placed after write data packets 2data and 5data, or after write data packets 5data and 2data. Flags 4 and 6 can be the same or different. While sequence numbers 4 and 6 can serve as packet sequence numbers indicating packet order, they do not necessarily serve as packet sequence numbers indicating packet order; they are only used to place them after all write data packets from the interconnected device.

[0044] This disclosure uses only write data packets 1data and 3data sent by the first interconnect device and write data packets 2data and 5data sent by the second interconnect device as examples for illustration. The first interconnect device and / or the second interconnect device may send more than two write data packets, and this disclosure does not limit this.

[0045] The slave chip 20 of the data transmission system 1 receives write data packets and flag data packets 1data, 2data, 3data, 4flag, 5data, and 6flag sent by the master chip 10. The interconnection bus between the slave chip 20 and the master chip 10 ensures that the flag data packet 4flag is located after the write data packets 1data and 3data sent by the first interconnection device, and the flag data packet 6flag is located after the write data packets 2data and 5data sent by the second interconnection device.

[0046] In this embodiment of the present disclosure, the order in which the write data packets sent by the chip 20 to both the first interconnect device and the second interconnect device is not limited. Similarly, this embodiment of the present disclosure does not limit the order of write data packets 1data and 3data sent by the first interconnect device, nor does it limit the order of write data packets 2data and 5data sent by the second interconnect device.

[0047] After the slave chip 20 of the data transmission system 1 stores the write data packets 1data and 3data sent by the first interconnect device into the memory, it also stores the corresponding flag data packet 4flag after the write data packets 1data and 3data into the memory; after the slave chip 20 of the data transmission system 1 stores the write data packets 2data and 5data sent by the second interconnect device into the memory, it also stores the corresponding flag data packet 6flag after the write data packets 2data and 5data into the memory.

[0048] This embodiment of the disclosure only limits the flag data packet 4 (flag) to be stored in memory after writing data packets 1 (data) and 3 (data), and does not limit the order in which data packets 1 (data) and 3 (data) are stored in memory. Similarly, this embodiment of the disclosure only limits the flag data packet 6 (flag) to be stored in memory after writing data packets 2 (data) and 5 (data), and does not limit the order in which data packets 2 (data) and 5 (data) are stored in memory.

[0049] The embodiments of this disclosure do not limit the order in which write data packets and flag data packets of the first interconnect device and the second interconnect device are stored in the memory.

[0050] Those skilled in the art can choose to set the above order as needed, and the embodiments disclosed herein will not be described in detail.

[0051] Since the flag data packet 4flag is stored in the memory after the write data packets 1data and 3data, the processing device 40 reads the write data packets 1data and 3data from the memory and then reads the flag data packet 4flag. Based on the received flag data packet 4flag, the processing device 40 determines that all write data packets 1data and 3data of the first interconnect device have been written, and the processing device 40 starts processing for the first interconnect device.

[0052] Since the flag data packet 6flag is stored in the memory after the write data packets 2data and 5data, the processing device 40 reads the write data packets 2data and 5data from the memory and then reads the flag data packet 6flag. Based on the received flag data packet 6flag, the processing device 40 determines that all write data packets 2data and 5data of the second interconnect device have been written, and the processing device 40 starts processing for the second interconnect device.

[0053] The processing device 40 of this embodiment does not require polling and reading refresh to determine the processing start time, thus reducing the processing start delay and bandwidth loss of the central processing unit and interconnect communication.

[0054] It should be noted that the structure of the data transmission system 1 may vary depending on the motherboard, operating system, and instruction set architecture. While the content of data packets written differs in Ethernet, Remote Direct Memory Access (RDMA), Interlaken, and PICe P2P interconnection systems, they all complete data writing and initiate processing in the form of data packets.

[0055] chip

[0056] Figure 3 shows a schematic block diagram of a chip 10 / 20. As shown in Figure 3, the chip 10 / 20 includes data transmission devices 100 / 200. The data transmission devices 100 / 200 in this embodiment are circuit designs configured to implement different data transmission control operations. The chips 10 / 20 may be multiple chips disposed on the motherboard, or multiple chips included in the same system-on-a-chip; this embodiment does not limit the scope of the present disclosure.

[0057] This embodiment of the disclosure still takes the process of the master chip 10 and slave chip 20 in the PICe P2P interconnection communication system sending write data packets to a processing device 40, and the processing device 40 receiving write data packets sent by the two interconnected devices as an example for description.

[0058] The main chip 10 includes a data transmission device 100, which adds a flag data packet 4 flag after receiving write data packets 1data and 3data sent by the first interconnect device; and adds a flag data packet 6 flag after receiving write data packets 2data and 5data sent by the second interconnect device.

[0059] The slave chip 20 includes a data transmission device 200. The data transmission device 200 ensures that the flag data packet 4 flag sent by the master chip 10 is located after the write data packets 1 data and 3 data sent by the first interconnect device, and that the flag data packet 6 flag is located after the write data packets 2 data and 5 data sent by the second interconnect device, through the interconnect bus between the slave chip 20 and the master chip 10.

[0060] After storing the write data packets 1data and 3data sent by the first interconnecting device into the memory, the data transmission device 200 also stores the corresponding flag data packet 4flag after the write data packets 1data and 3data into the memory; after storing the write data packets 2data and 5data sent by the second interconnecting device into the memory, the data transmission device 200 also stores the corresponding flag data packet 6flag after the write data packets 2data and 5data into the memory.

[0061] Since the flag data packet 4flag is stored in the memory after the write data packets 1data and 3data, the processing device 40 reads the write data packets 1data and 3data from the memory and then reads the flag data packet 4flag. Based on the received flag data packet 4flag, the processing device 40 determines that all write data packets 1data and 3data of the first interconnect device have been written, and the processing device 40 starts processing for the first interconnect device.

[0062] Since the flag data packet 6flag is stored in the memory after the write data packets 2data and 5data, the processing device 40 reads the write data packets 2data and 5data from the memory and then reads the flag data packet 6flag. Based on the received flag data packet 6flag, the processing device 40 determines that all write data packets 2data and 5data of the second interconnect device have been written, and the processing device 40 starts processing for the second interconnect device.

[0063] The processing device 40 of this embodiment does not require polling and reading refresh to determine the processing start time, thus reducing the processing start delay and bandwidth loss of the central processing unit and interconnect communication.

[0064] It should be noted that data transmission device 100 and data transmission device 200 can have different circuit structures. Data transmission device 100 is included when it acts as the master chip during data transmission, while data transmission device 200 is included when it acts as the slave chip. Data transmission device 100 includes circuitry for implementing the operations performed by the master chip during data transmission, and data transmission device 200 includes circuitry for implementing the operations performed by the slave chip during data transmission.

[0065] This disclosure focuses on the data transmission process of the data transmission devices 100 / 200. The internal structure of the data transmission devices 100 and 200 will be described in detail later.

[0066] Data transmission device

[0067] Figure 4 is a schematic diagram of the internal structure of a data transmission device 100 according to an embodiment of the present disclosure. The data transmission device 100 is applied to the main chip 10. As shown in Figure 4, the data transmission device 100 includes a data adding module 110 and a data sending module 130.

[0068] This embodiment of the disclosure still takes the process of the master chip 10 and slave chip 20 in a PCIe P2P interconnect communication system sending write data packets to a processing device 40, and the processing device 40 receiving write data packets sent by the two interconnected devices as an example for description.

[0069] The data adding module 110 can add a flag data packet 4 flag after the write data packets 1data and 3data sent by the first interconnected device; and the data adding module 110 can add a flag data packet 6 flag after the write data packets 2data and 5data sent by the second interconnected device.

[0070] In some embodiments, the flag data packet can be an empty packet or a data packet with any content; this disclosure does not limit this. Those skilled in the art can set the flag data packet as needed; the flag data packet is used to set after all write data packets of the interconnected device.

[0071] The data transmission module 130 sends write data packets and flag data packets 1data, 2data, 3data, 4flag, 5data, and 6flag to the slave chip 20.

[0072] Figure 5 shows a schematic diagram of the internal structure of a data transmission device 200 according to an embodiment of the present disclosure. The data transmission device 200 is applied to a slave chip 20. As shown in Figure 5, the data transmission device 200 includes a data receiving module 210, a storage control module 230, and a processing startup module 250.

[0073] The data receiving module 210 can receive write data packets and flag data packets 1data, 2data, 3data, 4flag, 5data, and 6flag sent by the main chip 10. Flag data packet 4flag follows write data packets 1data and 3data. Flag data packet 6flag follows write data packets 2data and 5data.

[0074] In some embodiments, the data receiving module 210 adjusts the order of write data packets and flag data packets through the reordering buffer (ROB) of the network fabric, placing the flag data packets after all write data packets of the corresponding interconnected device. That is, the order of write data packets and flag data packets is adjusted to 1data, 2data, 3data, 4flag, 5data, 6flag.

[0075] In some embodiments, the data receiving module 210 can also add storage labels to the received write data packets 1data, 2data, 3data, 5data and flag data packets 4data, 6flag, and the storage labels are set according to the number of memory.

[0076] For example, if there are two memory locations, the memory labels can be set to pcie_mstr 1 and pcie_mstr 2.

[0077] The embodiments disclosed herein do not limit the number of memories, and there may be two or more memories. Different memories can be distinguished by memory labels.

[0078] This disclosure embodiment distinguishes different memories by storage labels, realizing multiple storage methods for write data packets and flag data packets, making storage more flexible.

[0079] The storage control module 230 can store the flag data packet 4 after writing data packets 1 and 3, and store the flag data packet 6 after writing data packets 2 and 5.

[0080] In some embodiments, the storage control module 230 is further configured to store the write data packet and the flag data packet following the write data packet into the memory corresponding to the storage label according to the storage label.

[0081] Specifically, if there are two memory locations, store 1-pcie_mstr 1data, 3-pcie_mstr 1data, and 4-pcie_mstr1flag in memory pcie_mstr 1; store 2-pcie_mstr 2data, 5-pcie_mstr 2data, and 6-pcie_mstr 2flag in memory pcie_mstr 2. Alternatively, store 1_1pcie_mstr 1data, 2_1pcie_mstr 1data, 3_1pcie_mstr 1data, 4_1-pcie_mstr 1flag, 5_1-pcie_mstr 1data, and 6_1-pcie_mstr 1flag into memory pcie_mstr 1; and store 1_2pcie_mstr 1data, 2_2pcie_mstr 1data, 3_2pcie_mstr 1data, 4_2-pcie_mstr 1flag, 5_2-pcie_mstr 1data, and 6_2-pcie_mstr 1flag into memory pcie_mstr 2.

[0082] This disclosure only limits the storage of write data packets and flag data packets into the memory corresponding to the storage label. It does not limit how the write data packets and the flag data packets following the write data packets are stored into the memory, or the correspondence between the write data packets, flag data packets and the memory.

[0083] In some embodiments, as shown in FIG6, the memory 30 includes a first sub-memory 301 and a second sub-memory 302. The storage control module 230 is further configured to store write data packets to the first sub-memory 301 and store flag data packets to the second sub-memory 302.

[0084] In this embodiment of the present disclosure, write data packets and flag data packets are stored in a first sub-memory 301 and a second sub-memory 302, respectively, so that the processing device 40 can read the write data packets in the first sub-memory 301. Only after all the write data packets of an interconnect device have been read can the processing device 40 read the flag data packets in the second sub-memory 302.

[0085] Specifically, the first sub-memory 301 is a static random access memory; the second sub-memory 302 is a first register.

[0086] This embodiment of the disclosure stores write data packets through static random access memory and flag data packets through a first register, thereby enabling the storage and retrieval of different data packets.

[0087] In some embodiments, the plurality of interconnect devices include a first interconnect device and a second interconnect device. The storage control module 203 is further configured to store the write data packet of the first interconnect device to the first sub-memory 301, and then store the flag data packet following the write data packet of the first interconnect device to the second sub-memory 302; store the write data packet of the second interconnect device to the first sub-memory 301, and then store the flag data packet following the write data packet of the second interconnect device to the second sub-memory 302.

[0088] In this embodiment, write data packets from interconnected devices are sequentially stored in the first sub-memory 301, thereby enabling the processing device 40 to sequentially read the write data packets from each interconnected device. In this embodiment, flag data packets following the write data packets from interconnected devices are sequentially stored in the second sub-memory 302, thereby enabling the processing device 40 to sequentially read the flag data packets following the write data packets from each interconnected device.

[0089] Referring to Figure 6, the above-mentioned write data packets 1data, 2data, 3data, and 5data, as well as the flag data packets 4flag and 6flag, will still be used as examples for explanation.

[0090] The storage control module 230 stores the write data packets 1data and 3data of the first interconnection device into the first sub-memory 301, and then stores the write data packets 2data and 5data of the second interconnection device into the first sub-memory 301.

[0091] The storage control module 230 stores the flag data packet 4 flag after the write data packet of the first interconnect device into the second sub-memory 302, and then stores the flag data 6 flag after the write data packet of the second interconnect device into the second sub-memory 302.

[0092] The processing startup module 250 can enable the processing device 40 to determine, based on the received flag data packet, that all write data packets of the interconnected device have been written, and the processing device can start processing.

[0093] Since the processing device 40 reads the write data packets 1data and 3data in the first sub-memory 301 and then reads the flag data packet 4flag in the second sub-memory 302, the processing device 40 determines that all write data packets 1data and 3data of the first interconnect device have been written according to the flag data packet 4flag, and the processing device 40 starts processing for the first interconnect device.

[0094] Since the processing device 40 reads the write data packets 2data and 5data in the first sub-memory 301 and then reads the flag data packet 6flag in the second sub-memory 302, the processing device 40 determines that all write data packets 2data and 5data of the second interconnect device have been written according to the flag data packet 6flag, and the processing device 40 starts processing for the second interconnect device.

[0095] The processing device 40 of this embodiment does not require polling and reading refresh to determine the processing start time, thus reducing the processing start delay and bandwidth loss of the central processing unit and interconnect communication.

[0096] In some embodiments, the processing startup module 250 specifically informs the processing device through hardware that it has received the flag data packet, all write data packets of the interconnected device have been written, and the processing device 40 starts processing.

[0097] In some embodiments, referring to FIG7, the processing startup module 250 includes one of the following three notification units.

[0098] The first notification unit 2501 is used to update the second register (not shown in the figure) when the flag data packet is read by the processing device 40, so that the processing device 40 can determine that all write data packets of the interconnected device have been written in order to start processing by accessing the second register.

[0099] Due to the ease of modification of registers, the first notification unit 2501 in this embodiment of the present disclosure enables the processing device 40 to notify the processing device of the receipt of the flag data packet by accessing the second register, which has better general scalability.

[0100] The second notification unit 2502 is used to send a signal to the processing device when the flag data packet is received by the processing device 40, so that the processing device can determine that all write data packets of the interconnected device have been written and start the process.

[0101] The third notification unit 2503 is used to send an interrupt to the central processing device when the flag data packet is received by the processing device 40. The central processing device generates a signal to notify the processing device that all write data packets of the interconnected device have been written to start processing.

[0102] In this embodiment of the present disclosure, the second notification unit 2502 or the third notification unit 2503 can also notify the processing device that it has received the flag data packet and the processing device 40 starts processing.

[0103] The process of data transmission between data transmission device 100 and data transmission device 200 will be described below with reference to the data transmission system shown in Figure 8.

[0104] This embodiment of the disclosure still takes the process of the master chip 10 and slave chip 20 in the PICe P2P interconnection communication system sending write data packets to a processing device 40, and the processing device 40 receiving write data packets sent by the two interconnected devices as an example for description.

[0105] A1. The data adding module 110 of the main chip 10 adds a flag data packet 4 flag after receiving the write data packets 1data and 3data sent by the first interconnect device; and the data adding module 110 adds a flag data packet 6 flag after receiving the write data packets 2data and 5data sent by the second interconnect device.

[0106] A2. The data transmission module 130 of the main chip 10 sends write data packets and flag data packets 1data, 2data, 3data, 4flag, 5data, and 6flag to the slave chip 20.

[0107] A3. Receive write data packets and flag data packets 1data, 2data, 3data, 4flag, 5data, and 6flag from the main chip via the data receiving module 210 of chip 20.

[0108] Specifically, the data receiving module 210 adjusts the order of write data packets and flag data packets to 1data, 2data, 3data, 4flag, 5data, 6flag through the network structure's reordering buffer. Flag data packet 4flag follows write data packets 1data and 3data. Flag data packet 6flag follows write data packets 2data and 5data.

[0109] A4. Storage control module 230 stores the write data packets 1data and 3data of the first interconnect device into the first sub-memory 301, and stores the flag data packet 4flag following the write data packet of the first interconnect device into the second sub-memory 302; storage control module 230 stores the write data packets 2data and 5data of the second interconnect device into the first sub-memory 301, and stores the flag data packet 6flag following the write data packet of the second interconnect device into the second sub-memory 302.

[0110] A5. The processing startup module 250 informs the processing device via hardware that it has received the flag data packet 4 (flag), all write data packets of the first interconnected device have been written, and the processing device 40 starts processing for the first interconnected device; the processing startup module 250 informs the processing device via hardware that it has received the flag data packet 6 (flag), all write data packets of the second interconnected device have been written, and the processing device 40 starts processing for the second interconnected device.

[0111] Specifically, when the hardware informs the processing device that it has received a flag data packet, the second register is updated if the flag data packet is read by the processing device 40. The processing device 40 then accesses the second register to determine that all write data packets of the interconnected device have been written and to start the process.

[0112] Data transmission methods

[0113] Figure 9 shows a flowchart of a data transmission method according to an embodiment of the present disclosure. This data transmission method can be executed by the data transmission device 100 in the above embodiments. As shown in Figure 9, the data transmission method includes the following steps:

[0114] Step 901: Set the corresponding flag data packet after all write data packets of each interconnected device.

[0115] Step 902: Send the write data packet and the flag data packet to the slave chip, so that the slave chip stores the write data packets of each interconnected device into the memory and then stores the flag data packet after the write data packet into the memory. The processing device determines that all write data packets of the interconnected devices have been written based on the received flag data packet, and the processing device starts processing.

[0116] The data transmission scheme provided in this disclosure embodiment receives write data packets and flag data packets sent by the master chip from the slave chip. The write data packets originate from multiple interconnect devices, and a flag data packet is set after all write data packets from each interconnect device. The slave chip stores the write data packets from each interconnect device into its memory, and then stores the flag data packets following the write data packets into its memory. The processing device determines that all write data packets from the interconnect device have been written based on the received flag data packets, and then starts processing. This disclosure embodiment avoids the processing startup delay caused by polling and read / refresh operations by the processing device, and also reduces bandwidth loss in the central processing unit and interconnect communication.

[0117] According to one or more embodiments of this disclosure, the flag data packet includes a packet sequence number, which is used to characterize the order of the flag data packets.

[0118] Figure 10 shows a flowchart of a data transmission method according to another embodiment of the present disclosure, which can be executed by the data transmission device 200 in the above embodiments. As shown in Figure 10, the timestamp synchronization method includes the following steps:

[0119] Step 1001: Receive write data packets and flag data packets sent by the main chip. The write data packets come from multiple interconnected devices, and each interconnected device sets a corresponding flag data packet after its write data packet.

[0120] Step 1002: After storing the write data packets of each interconnected device into the memory, store the flag data packets following the write data packets into the memory.

[0121] Step 1003: The processing device determines that all write data packets of the interconnected device have been written based on the received flag data packets, and the processing device starts processing.

[0122] The data transmission scheme provided in this disclosure embodiment receives write data packets and flag data packets sent by the master chip from the slave chip. The write data packets originate from multiple interconnect devices, and a flag data packet is set after all write data packets from each interconnect device. The slave chip stores the write data packets from each interconnect device into its memory, and then stores the flag data packets following the write data packets into its memory. The processing device determines that all write data packets from the interconnect device have been written based on the received flag data packets, and then starts processing. This disclosure embodiment avoids the processing startup delay caused by polling and read / refresh operations by the processing device, and also reduces bandwidth loss in the central processing unit and interconnect communication.

[0123] According to one or more embodiments of this disclosure, the flag packet is added after all write packets from the main chip to the interconnect device.

[0124] According to one or more embodiments of this disclosure, the flag data packet includes a packet sequence number, which is used to characterize the order of the flag data packets.

[0125] According to one or more embodiments of this disclosure, step 1001 includes: reordering the flag data packet and write data packet through a reordering buffer of the network structure, such that the flag data packet is located after all write data packets of the interconnected device.

[0126] According to one or more embodiments of this disclosure, step 1001 further includes: adding storage labels to the received write data packets and flag data packets, wherein the storage labels are set according to the number of memories.

[0127] According to one or more embodiments of this disclosure, step 1002 further includes: storing the write data packet and the flag data packet following the write data packet into the memory corresponding to the storage label according to the storage label.

[0128] According to one or more embodiments of this disclosure, the memory includes a first sub-memory and a second sub-memory, and the storage control module is further configured to store write data packets to the first sub-memory and store flag data packets to the second sub-memory.

[0129] According to one or more embodiments of this disclosure, the first sub-memory is a static random access memory; the second sub-memory is a first register.

[0130] According to one or more embodiments of this disclosure, a plurality of interconnect devices include a first interconnect device and a second interconnect device. The storage control module is further configured to store a write data packet of the first interconnect device to a first sub-memory, and then store a flag data packet following the write data packet of the first interconnect device to a second sub-memory, store a write data packet of the second interconnect device to the first sub-memory, and then store a flag data packet following the write data packet of the second interconnect device to the second sub-memory.

[0131] According to one or more embodiments of this disclosure, step 1003 includes: having the processing device determine by hardware that a flag data packet has been received, having all write data packets of the interconnected device completed being written, and having the processing device start processing.

[0132] According to one or more embodiments of this disclosure, step 1003 includes: updating a second register when a flag data packet is received by a processing device, causing the processing device to determine, by accessing the second register, that all write data packets of the interconnected device have been written to initiate processing.

[0133] According to one or more embodiments of this disclosure, the interconnect device includes one of: a peripheral component interconnection point-to-point processing device, an Ethernet processing device, a remote memory direct access processing device, and an Interlaken processing device.

[0134] According to one or more embodiments of the present disclosure, the processing device includes at least one of a central processing unit and a digital processor.

[0135] It should be noted that the details of the data transmission method have been described in detail in the data transmission device section of the above embodiments with reference to the structural diagram. For the specific process, please refer to the description in the aforementioned data transmission device embodiments, and will not be repeated here.

[0136] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0137] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0138] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0139] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A data transmission device applied to a chip, the device comprising: The data receiving module is used to receive write data packets and flag data packets sent by the main chip. The write data packets come from multiple interconnected devices, and each write data packet from the interconnected device is followed by a corresponding flag data packet. The storage control module is used to store the write data packet of the interconnected device into the memory and then store the corresponding flag data packet after the write data packet into the memory; The processing startup module is used to instruct the processing device to determine, based on the received flag data packet, that all write data packets of the interconnected device have been written, and the processing device starts the processing.

2. The apparatus of claim 1, wherein, The flag data packet is added by the main chip after all write data packets to the interconnect device.

3. The apparatus of claim 2, wherein, The flag data packet includes a packet sequence number, which is used to characterize the order of the flag data packets.

4. The apparatus of claim 3, wherein, The data receiving module is specifically used to sort the flag data packet and the write data packet through the reordering buffer of the network structure, so that the flag data packet is located after all the write data packets of the interconnected device.

5. The apparatus of claim 4, wherein, The data receiving module is further configured to add storage labels to the received write data packets and flag data packets, wherein the storage labels are set according to the number of memories.

6. The apparatus according to claim 5, wherein the storage control module is further configured to store the write data packet and the flag data packet following the write data packet into a memory corresponding to the storage label according to the storage label.

7. The apparatus of claim 6, wherein, The memory includes a first sub-memory and a second sub-memory. The storage control module is also used to store the write data packet to the first sub-memory and the flag data packet to the second sub-memory.

8. The apparatus of claim 7, wherein, The first sub-memory is a static random access memory; the second sub-memory is a first register.

9. The apparatus of claim 7 or 8, wherein, The plurality of interconnected devices include a first interconnected device and a second interconnected device. The storage control module is further configured to store the write data packet of the first interconnected device to the first sub-memory, and then store the flag data packet following the write data packet of the first interconnected device to the second sub-memory, store the write data packet of the second interconnected device to the first sub-memory, and then store the flag data packet following the write data packet of the second interconnected device to the second sub-memory.

10. The apparatus according to claim 1, wherein the processing startup module is specifically configured to cause the processing device to determine through hardware that the flag data packet has been received, all the write data packets of the interconnected device have been written, and the processing device to start processing.

11. The apparatus according to claim 10, wherein the processing initiation module comprises: The first notification unit is configured to update the second register when the flag data packet is received by the processing device, thereby instructing the processing device to determine, by accessing the second register, that all write data packets of the interconnected device have been written to initiate the process. deal with.

12. The apparatus of claim 1, the interconnect device comprising: One of the following: peripheral component interconnection point-to-point processing device, Ethernet processing device, remote memory direct access processing device, and Interlaken processing device.

13. The apparatus of claim 1, the processing device comprising: At least one of a central processing unit and a digital processor.

14. A data transmission device applied to a main chip, the device comprising: The data addition module is used to set the corresponding flag data packet after all write data packets on each interconnected device. The data transmission module is used to send the write data packet and the flag data packet to the slave chip, so that the slave chip stores the write data packets of each interconnected device into the memory and then stores the flag data packet following the write data packets into the memory, so that the processing device determines that all the write data packets of the interconnected device have been written based on the received flag data packets, and the processing device starts processing.

15. The apparatus of claim 14, wherein, The flag data packet includes a packet sequence number, which is used to characterize the order of the flag data packets.

16. A chip comprising: The data transmission apparatus according to any one of claims 1-15.

17. A data transmission system comprising: Interconnected master and slave chips; The slave chip includes a data transmission device according to any one of claims 1-13, and the master chip includes a data transmission device according to claim 14 or 15.

18. A data transmission method applied to a slave chip, the method comprising: The system receives write data packets and flag data packets sent by the main chip. The write data packets come from multiple interconnected devices, and each of the interconnected devices sets a corresponding flag data packet after its write data packet. After storing the write data packets of each of the interconnected devices into the memory, the flag data packets following the write data packets are then stored into the memory. The processing device determines, based on the received flag data packet, that all write data packets of the interconnected device have been written, and then the processing device starts the process.

19. A data transmission method applied to a main chip, the method comprising: After all write data packets are sent to each interconnected device, a corresponding flag data packet is set. The write data packet and the flag data packet are sent to the slave chip, which then stores the write data packets of each interconnected device into its memory and then stores the flag data packet following the write data packets into its memory. The processing device determines that all the write data packets of the interconnected devices have been written based on the received flag data packets, and the processing device starts processing.

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