Write request processing method, IO proxy module, slave proxy module, and computer system

Abstract

Embodiments of the present disclosure provide a write request processing method, an IO proxy module, a Slave proxy module, and a computer system. The method applied to the IO proxy module comprises: acquiring an IO write request of an IO module; determining cache line override integrity corresponding to a cache line write operation of the IO write request; on the basis of the cache line override integrity of the cache line write operation, sending an exclusive permission request of a cache line corresponding to the cache line write operation; and when the sending sequence of the IO write request arrives, if the exclusive permission of the cache line corresponding to the cache line write operation of the IO write request has been acquired, sending, on the basis of complete write data corresponding to the cache line, a complete write data request corresponding to the cache line write operation, wherein the complete write data request is used for requesting to write the complete write data into the cache line, and the complete write data at least includes write data of the cache line write operation.

Description

Write request handling methods, IO proxy modules, Slave proxy modules, and computer systems.

[0001] This application claims priority to Chinese Patent Application No. 202411615045.X, filed on November 13, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a write request processing method, an IO proxy module, a Slave proxy module, and a computer system. Background Technology

[0003] Master and Slave are a communication mode used in computer systems. The module that initiates the access request is the Master module, and the module that responds to the Master module's access request is the Slave module. The Master module connects to the transmission network through a corresponding Master proxy module, and the Slave module connects to the transmission network through a corresponding Slave proxy module. Thus, the Master proxy module can send the Master module's access request to the transmission network, which in turn sends the access request to the corresponding Slave proxy module. The Slave proxy module then schedules the corresponding Slave module to execute the access request.

[0004] Computer systems need to ensure data consistency, meaning that concurrent access requests should not cause data conflicts or inconsistencies, ensuring that the data read at any given time is up-to-date and accurate. In this context, the I / O (Input / Output) module, as a functional module for data input and output in a computer system, needs to access slave modules such as memory. Specifically, I / O write requests, as access requests issued by the I / O module to write data, present a critical technical problem that needs to be solved by those skilled in the art: how to provide a solution for handling I / O write requests to improve the performance of the computer system's transmission network while ensuring data consistency. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a write request processing method, an IO proxy module, a Slave proxy module, and a computer system to improve the performance of the transmission network while ensuring data consistency.

[0006] To achieve the above objectives, the present disclosure provides the following technical solutions.

[0007] In a first aspect, embodiments of this disclosure provide a write request processing method applied to an IO proxy module, wherein the IO proxy module manages IO write requests for the corresponding IO module using cache lines based on a cache consistency protocol; the method includes:

[0008] Get the IO write requests from the IO module;

[0009] Determine the cache line coverage integrity corresponding to the cache line write operation of the IO write request;

[0010] Based on the cache line coverage integrity of the cache line write operation, an exclusive permission request for the cache line corresponding to the cache line write operation is issued to obtain at least the exclusive permission for the cache line.

[0011] When the order of the IO write requests arrives, if the exclusive access to the cache line corresponding to the cache line write operation of the IO write request has been acquired, then based on the complete write data corresponding to the cache line, a complete write data request corresponding to the cache line write operation is issued; the complete write data request is used to request the writing of the complete write data in the cache line, and the complete write data includes at least the write data of the cache line write operation.

[0012] Secondly, this disclosure provides a write request processing method applied to a Slave proxy module, the method comprising:

[0013] Obtain the exclusive permission request sent by the IO proxy module. The exclusive permission request is at least used to request exclusive permission for a cache line, and the exclusive permission request corresponds to the cache line overwrite integrity of the cache line write operation corresponding to the cache line.

[0014] Feedback the exclusive permission response information corresponding to the exclusive permission request to the IO proxy module;

[0015] Obtain the complete write data request corresponding to the cache line write operation sent by the IO proxy module. The complete write data request is used to request that the complete write data corresponding to the cache line be written in the cache line. The complete write data includes at least the write data of the cache line write operation.

[0016] The corresponding Slave module is scheduled to execute the complete write data request and the response information of the complete write data request is fed back to the IO proxy module.

[0017] Thirdly, embodiments of this disclosure provide an IO proxy module, which connects a corresponding IO module to the transmission network of a computer system. The protocol layer of the IO proxy module is configured with a cache coherence protocol to manage IO write requests of the corresponding IO module using cache lines. The IO proxy module is used for:

[0018] Get the IO write requests from the IO module;

[0019] Determine the cache line coverage integrity corresponding to the cache line write operation of the IO write request;

[0020] Based on the cache line coverage integrity of the cache line write operation, an exclusive permission request for the cache line corresponding to the cache line write operation is issued to obtain at least the exclusive permission for the cache line.

[0021] When the order of the IO write requests arrives, if the exclusive access to the cache line corresponding to the cache line write operation of the IO write request has been acquired, then based on the complete write data corresponding to the cache line, a complete write data request corresponding to the cache line write operation is issued; the complete write data request is used to request the writing of the complete write data in the cache line, and the complete write data includes at least the write data of the cache line write operation.

[0022] Fourthly, embodiments of this disclosure provide a Slave proxy module, which connects a corresponding Slave module to a computer system's transmission network to manage access requests to the Slave module; wherein, the Slave proxy module is used for:

[0023] Obtain the exclusive permission request sent by the IO proxy module. The exclusive permission request is at least used to request exclusive permission for a cache line, and the exclusive permission request corresponds to the cache line overwrite integrity of the cache line write operation corresponding to the cache line.

[0024] Feedback the exclusive permission response information corresponding to the exclusive permission request to the IO proxy module;

[0025] Obtain the complete write data request corresponding to the cache line write operation sent by the IO proxy module. The complete write data request is used to request that the complete write data corresponding to the cache line be written in the cache line. The complete write data includes at least the write data of the cache line write operation.

[0026] The corresponding Slave module is scheduled to execute the complete write data request and the response information of the complete write data request is fed back to the IO proxy module.

[0027] Fifthly, embodiments of this disclosure provide a computer system including multiple functional modules, wherein the functional module that initiates access requests is a Master module, and the functional module that responds to access requests is a Slave module; the Master module includes an IO module, which is connected to the transmission network of the computer system through a corresponding IO proxy module; the Slave module is connected to the transmission network through a corresponding Slave proxy module; wherein the IO proxy module is the IO proxy module as described in the third aspect above, and the Slave proxy module is the Slave proxy module as described in the fourth aspect above.

[0028] In the write request processing method provided in this embodiment, the IO proxy module manages the IO write requests of the corresponding IO module based on the cache consistency protocol and cache lines. When the IO proxy module obtains the IO write request of the IO module, it can determine the cache line coverage integrity corresponding to the cache line write operation of the IO write request, and based on the cache line coverage integrity of the cache line write operation, issue an exclusive permission request for the cache line corresponding to the cache line write operation to at least obtain exclusive permission for the cache line. This ensures that before the IO proxy module performs the write operation on the cache line corresponding to the cache line write operation, other Master proxy modules' access to the cache line will be through the cache line corresponding to the cache line. The query request is fed back to the IO proxy module, which can then respond to the query request based on data consistency requirements to ensure that other Master proxy modules have the latest and most accurate access to the cache line data, thus ensuring data consistency. Furthermore, when the order of IO write requests arrives, if the IO proxy module confirms that it has acquired exclusive access to the cache line corresponding to the cache line write operation of the IO write request, it can issue a complete write data request corresponding to the cache line write operation based on the complete write data corresponding to the cache line, in order to request the writing of complete write data in the cache line. The complete write data includes at least the write data of the cache line write operation, thereby realizing the issuance of the IO write request.

[0029] In the above process, the IO proxy module based on the cache consistency protocol can obtain exclusive access to the cache line corresponding to the write operation of the IO write request, and transfer the order control point (i.e., the order-keeping point) of the data written by the IO write request to the IO proxy module. Therefore, the embodiments of this disclosure can release the order-keeping requirement of the computer system's transmission network for access requests to the IO module, enabling the computer system to adapt to transmission networks with any transmission mechanism, reducing the design limitations of the transmission network, and thereby improving the performance of the transmission network, such as improving the utilization of the transmission network and the throughput of the computer system. Therefore, the embodiments of this disclosure can release the order-keeping requirement of the computer system's transmission network for IO write requests while ensuring the data consistency of the computer system, thereby improving the performance of the transmission network. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0031] Figure 1 is an example diagram of a computer system architecture;

[0032] Figure 2 is an example of continuous write operations on the same Slave module;

[0033] Figure 3A is an example of continuous write operations on different Slave modules;

[0034] Figure 3B is another example of continuous write operations on different Slave modules;

[0035] Figure 4 is a flowchart of a write request processing method provided in an embodiment of this disclosure;

[0036] Figure 5 is an example diagram of the write request processing method provided in an embodiment of this disclosure;

[0037] Figure 6A is another example diagram of the write request processing method provided in the embodiments of this disclosure;

[0038] Figure 6B is another example diagram of the write request processing method provided in the embodiments of this disclosure;

[0039] Figure 7 is another example diagram of the write request processing method provided in the embodiments of this disclosure;

[0040] Figure 8 is another example diagram of the write request processing method provided in the embodiments of this disclosure;

[0041] Figure 9 is yet another example diagram of the write request processing method provided in the embodiments of this disclosure; and

[0042] Figure 10 is another example diagram of the write request processing method provided in the embodiments of this disclosure. Detailed Implementation

[0043] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0044] Computer systems can be configured with various functional modules, such as core complexes, I / O modules, and memory. These modules require data access. The module that initiates the access request is the Master module, and the module that responds to the access request is the Slave module. A computer system can have multiple Master modules and multiple Slave modules. Each Master module connects to the transmission network through a corresponding Master proxy module, which manages the access requests from its corresponding Master module. Each Slave module connects to the transmission network through a corresponding Slave proxy module, which manages the access requests from the transmission network and schedules its corresponding Slave module to execute the access requests. In other words, in a computer system, the access request path is as follows: the Master proxy module sends the access request from its corresponding Master module to the transmission network; the transmission network sends the access request from the Master proxy module to the Slave proxy module; and the Slave proxy module schedules its corresponding Slave module to execute the access request. The transmission network can be, for example, a Data Fabric bus or an on-chip interconnect bus, which are bus networks within the computer system.

[0045] Computer systems can be designed based on multi-core architecture, heterogeneous architecture, system-on-a-chip architecture, etc. For ease of understanding, a multi-core architecture of a computer system is taken as an example. Figure 1 shows an exemplary architectural diagram of a computer system. As shown in Figure 1, a computer system may include:

[0046] Multiple core clusters 110, a core cluster is a functional module containing multiple computing cores, used to handle computing tasks and instruction operations; for example, a computing core can be a processor core, then a core cluster can contain multiple processor cores;

[0047] Multiple core agent modules 111, wherein each core cluster has a corresponding core agent module, and the core cluster connects to the transmission network through the corresponding core agent module, thereby interacting with other functional modules in the computer system;

[0048] Multiple IO modules 120. IO modules are functional modules for data input and output of computer systems, such as PCIE (Peripheral Component Interconnect Express) modules or other peripheral modules of the computer system;

[0049] Multiple IO agent modules 121, wherein each IO module has a corresponding IO agent module, and the IO module connects to the transmission network through the corresponding IO agent module, thereby interacting with other functional modules in the computer system;

[0050] Multiple memory modules (130) are used to store data for the core cluster and I / O module to read and write data. Memory such as DDR (Double Data Rate) memory is used.

[0051] Multiple memory proxy modules 131 are provided, wherein each memory has a corresponding memory proxy module, and the memory is connected to the transmission network through the corresponding memory proxy module, thereby interacting with other functional modules in the computer system.

[0052] The architecture of the aforementioned computer system involves the interaction between the core cluster and memory, and the interaction between the I / O module and memory.

[0053] For example, in the interaction between the core cluster and memory, the core cluster initiates a memory access request (such as a read request or a write request). The core proxy module corresponding to the core cluster sends the access request to the transport network (such as a Data Fabric bus). The transport network then sends the access request to the memory proxy module corresponding to the accessed memory. The memory proxy module schedules the corresponding memory to execute the access request. In the above process, the Master module can be regarded as the core cluster, the Master proxy module can be regarded as the core proxy module, the Slave module can be regarded as the memory, and the Slave proxy module can be regarded as the memory proxy module.

[0054] For example, in the interaction between the IO module and memory, the IO module initiates a memory access request (such as an IO read request or an IO write request). The IO proxy module corresponding to the IO module sends the access request to the transport network (such as a Data Fabric bus). The transport network passes the access request to the memory proxy module corresponding to the accessed memory. The memory proxy module schedules the corresponding memory to execute the access request. In the above process, the Master module can be regarded as the IO module, the Master proxy module can be regarded as the IO proxy module, the Slave module can be regarded as memory, and the Slave proxy module can be regarded as the memory proxy module.

[0055] As can be seen, the functional module that initiates access requests in the computer system is the Master module, including but not limited to the core cluster and IO module; each Master module connects to the transmission network through a corresponding Master proxy module, which includes but is not limited to the core proxy module and IO proxy module; the functional module that responds to access requests in the computer system is the Slave module, including but not limited to memory; each Slave module connects to the transmission network through a corresponding Slave proxy module, which includes but is not limited to the memory proxy module.

[0056] The computer system needs to maintain data consistency when the Master module concurrently accesses the Slave module. This means that concurrent access requests from the Master module to the Slave module should not cause data conflicts or inconsistencies, and the data read at any given time should be the latest and correct. Specifically, when one or more Master modules access data from the Slave module simultaneously, the computer system must ensure that read and write operations do not lead to data conflicts, data overwriting, or the reading of outdated data. Therefore, regardless of which Master module modifies the data in the Slave module, other Master modules should be able to read the latest and most accurate data subsequently.

[0057] As the functional module for data input and output in a computer system, the I / O module must also process I / O write requests (written requests initiated by the I / O module are called I / O write requests) while ensuring data consistency within the computer system. One approach is to ensure the sequential execution of multiple concurrent I / O write requests from the I / O module. Specifically, one or more I / O modules may concurrently initiate multiple I / O write requests to one or more slave modules (such as memory). In this case, the sequential execution of these concurrent I / O write requests must be guaranteed to ensure data consistency within the computer system.

[0058] From the perspective of the computer system as a whole, the sequential execution of I / O write requests is considered as Global Ordering (GO). The computer system can use a global ordering mechanism to ensure that earlier I / O write requests complete first, and subsequent I / O write requests take effect only after that, thus achieving sequential execution of I / O write requests. Here, earlier I / O write requests are those initiated first in time, also known as older I / O write requests; subsequent I / O write requests are those initiated later in time, also known as younger I / O write requests. Specifically, the global ordering mechanism needs to ensure that older I / O write requests execute first. Only after older I / O write requests have completed execution and been synchronized to the computer system are younger I / O write requests visible to other functional modules in the computer system. These other functional modules include those other than those that initiated the younger I / O write requests. For example, if a younger I / O write request is initiated by a certain I / O module, then the other functional modules are other core clusters and their corresponding core proxy modules, other I / O modules and their corresponding I / O proxy modules, etc. In other words, since the I / O write requests of the I / O modules are sent from the I / O proxy module to the memory proxy module through the transmission network, the I / O write requests from the I / O proxy module to the memory proxy module need to be ordered end-to-end.

[0059] To ensure the global ordering of IO write requests in the IO module (i.e., the global ordering of IO write requests in the IO module), one global ordering mechanism is to perform ordering processing of IO write requests on the computer system's transport network. Here, the transport network can be regarded as the transport layer of the computer system, corresponding to the transport path from the Master proxy module to the Slave proxy module.

[0060] To facilitate understanding of the order-preserving processing of IO write requests in the transport network (transport layer), Figure 2 exemplifies an example of consecutive write operations on the same Slave module. Figure 2 uses the Slave module as memory and mainly illustrates the interaction between the IO module, the IO proxy module, and the memory proxy module. As shown in Figure 2, taking four consecutive write operations of the IO module to the same memory as an example, these four consecutive write operations correspond to four consecutive IO write requests, namely IO WriteA1, IO WriteA2, IO WriteA3, and IO WriteA4. Among them, IO WriteA1 is the IO write request with write address A1, IO WriteA2 is the IO write request with write address A2, IO WriteA3 is the IO write request with write address A3, and IO WriteA4 is the IO write request with write address A4. In the example of Figure 2, write addresses A1, A2, A3, and A4 are located in the same memory.

[0061] The four consecutive IO write requests (IO WriteA1, IO WriteA2, IO WriteA3 and IO WriteA4) initiated by the IO module can be transmitted to the corresponding IO proxy module of the IO module;

[0062] The IO proxy module determines the write size of each IO write request, that is, the amount of data in each IO write request. For example, the IO proxy module can determine the write size of IO WriteA1 (represented as IO WriteSizeA1), IO WriteA2 (represented as IO WriteSizeA2), IO WriteA3 (represented as IO WriteSizeA3), and IO WriteA4 (represented as IO WriteSizeA4).

[0063] Because the transport layer implements order-preserving processing for IO write requests (e.g., end-to-end order preservation for IO write requests from the IO proxy module to the memory proxy module), the IO proxy module can directly transmit each IO write request sequentially to the transport network (e.g., the Data Fabric bus). For example, the IO proxy module can directly transmit the four IO write requests, IO WriteA1, IO WriteA2, IO WriteA3, and IO WriteA4, sequentially to the transport network (e.g., the Data Fabric bus).

[0064] Based on the order-preserving processing of the transport layer, the transport network (such as the Data Fabric bus) can enable each IO write request to be transmitted to the memory proxy module in sequence. For example, the transport network can transmit four IO write requests, IO WriteA1, IO WriteA2, IO WriteA3, and IO WriteA4, to the memory proxy module corresponding to the accessed memory in sequence, so that the four IO write requests are delivered to the memory in sequence and executed in sequence, ensuring the global orderliness of continuous write operations to the same memory.

[0065] When the memory completes an I / O write request, the memory proxy module can send back the TgtRsp (Target Response) information of each I / O write request to the I / O proxy module via the transmission network to indicate that the memory has completed the execution of the I / O write request.

[0066] Based on the TgtRsp information of IO write requests obtained by the IO proxy module, if the IO proxy module obtains the TgtRsp information of a certain IO write request, it can confirm that the memory has completed processing the IO write request, and thus send back the corresponding Rsp (Response) information to the IO module; for example, if the IO proxy module confirms that the memory has completed executing IO WriteA1, it can send back RspA1 information to the IO module; if the IO proxy module confirms that the memory has completed executing IO WriteA2, it can send back RspA2 information to the IO module; if the IO proxy module confirms that the memory has completed executing IO WriteA3, it can send back RspA3 information to the IO module; if the IO proxy module confirms that the memory has completed executing IO WriteA4, it can send back RspA4 information to the IO module.

[0067] Furthermore, after the IO proxy module sends the Rsp information of any IO write request back to the IO module, it can also send SrcRsp (Source Response) information back to the memory proxy module through the transmission network, indicating that the IO write request process has been completed.

[0068] However, there may be limitations to preserving the order of I / O write requests in the transport network. For example, while the transport network's preserving process can guarantee that consecutive I / O write requests accessing the same Slave module can be executed sequentially, it may not be able to guarantee the sequential execution of consecutive I / O write requests across multiple Slave modules.

[0069] Specifically, low-order address interleaving (LIO) configuration causes consecutive write operations to be distributed across different slave modules. Taking memory access as an example, LIO is a memory address interleaving configuration that distributes consecutive memory addresses across multiple memory locations to improve the parallelism and speed of data access. Thus, multiple I / O write requests targeting consecutive memory addresses are distributed across different memory locations. Under LIO configuration, if an I / O module performs consecutive write operations on different slave modules, the transport network's order-keeping mechanism cannot guarantee the sequential execution of consecutive I / O write requests initiated by the I / O module. This is because when the transport network sends I / O write requests to the corresponding slave proxy modules of different slave modules, the arrival times of the I / O write requests may differ due to transmission delays or network congestion. This difference in arrival times can lead to consecutive I / O write requests being executed out of order, thereby compromising the data consistency of the computer system. For example, when a transmission network sends consecutive old and young IO write requests to different slave modules, the young IO write requests may arrive at the corresponding slave proxy module first and be scheduled for execution due to better network conditions, while the old IO write requests may arrive at the corresponding slave proxy module later and be scheduled for execution due to transmission delays or network congestion. This disordered order of IO write requests arriving at different slave proxy modules will disrupt the global order and thus affect the data consistency of the computer system.

[0070] Based on this, one solution is to introduce a single-processing mechanism at the Slave level into the IO proxy module. That is, the IO proxy module, at the Slave module level, waits for the previous Slave module to complete all IO write requests before sending the next Slave module's IO write request to the transmission network. Thus, by combining the single-processing mechanism at the Slave level of the IO proxy module with the transmission network's order-preserving processing of IO write requests for the same Slave module, it is ensured that consecutive IO write requests across multiple Slave modules can be executed in sequence, thereby maintaining the global order of IO write requests.

[0071] For ease of understanding, Figure 3A exemplifies a diagram illustrating continuous write operations on different Slave modules. Figure 3A uses Slave modules as memory and primarily illustrates the interaction between the IO module, the IO proxy module, and the memory proxy modules corresponding to multiple memory locations. These multiple memory locations include a first memory and a second memory. The memory proxy module corresponding to the first memory can be the first memory proxy module in Figure 3A, and the memory proxy module corresponding to the second memory can be the second memory proxy module in Figure 3A. Corresponding parts of Figure 3A and Figure 2 can be referenced interchangeably.

[0072] As shown in Figure 3A, based on the low-order address interleaving configuration, the four consecutive IO write requests of the IO module, namely IO WriteA1, IO WriteA2, IO WriteA3, and IO WriteA4, are directed to the second memory and the first memory. Among them, IO WriteA1 and IO WriteA2 are directed to the second memory, and IO WriteA3 and IO WriteA4 are directed to the first memory. In the example of Figure 3A, the consecutive write addresses A1, A2, A3, and A4 are scattered in the second memory and the first memory, with write addresses A1 and A2 located in the second memory and write addresses A3 and A4 located in the first memory.

[0073] The four consecutive IO write requests (IO WriteA1, IO WriteA2, IO WriteA3, and IO WriteA4) initiated by the IO module can be transmitted to the corresponding IO proxy module in sequence. The IO proxy module first sends IO WriteA1 and IO WriteA2 to the transmission network (e.g., Data Fabric bus) in sequence. The transmission network guarantees the order in which IO WriteA1 and IO WriteA2 arrive at the second memory proxy module. That is, for consecutive IO write requests to the same memory, the transmission network can guarantee the sequential execution of IO write requests.

[0074] For IO WriteA3 and IO WriteA4, the IO proxy module cannot directly send IO WriteA3 and IO WriteA4 to the transmission network. If the IO proxy module directly sends IO WriteA3 and IO WriteA4 to the transmission network, due to transmission delays or network congestion, the transmission network cannot guarantee the arrival time of IO WriteA1 and IO WriteA2 at the second memory proxy module, which may arrive at the first memory proxy module before IO WriteA3 and IO WriteA4, potentially disrupting the global ordering.

[0075] Therefore, based on the single-processing mechanism of the IO proxy module with Slave as the granularity, after sending IO WriteA1 and IO WriteA2, the IO proxy module needs to wait for the TgtRsp information fed back by the second memory proxy module through the transmission network; if the IO proxy module obtains the TgtRsp information of IO WriteA1 fed back by the second memory proxy module, it will feed back the RspA1 information to the IO module; if it obtains the TgtRsp information of IO WriteA2 fed back by the second memory proxy module, it will feed back the RspA2 information to the IO module.

[0076] After the IO proxy module obtains the TgtRsp information of IO WriteA1 and IO WriteA2, the IO proxy module can confirm that the second memory has completed the execution of IO WriteA1 and IO WriteA2. Based on the single-processing mechanism with Slave as the granularity, the Master proxy then sends IO WriteA3 and IO WriteA4 to the transmission network (e.g., Data Fabric bus). The transmission network guarantees the order in which IO WriteA3 and IO WriteA4 arrive at the first memory proxy module. That is, for consecutive IO write requests to the same memory, the transmission network can guarantee the sequential execution of IO write requests.

[0077] Then, the IO proxy module obtains the TgtRsp information transmitted by the first memory proxy module through the transmission network. For example, for the processing of IO WriteA3 and IO WriteA4 by the first memory, the TgtRsp information fed back by the first memory proxy module can be, for example, the TgtRsp information of IO WriteA3 and the TgtRsp information of IO WriteA4. Then, the IO proxy module feeds back the RspA3 information and RspA4 information to the IO module respectively, to indicate that the processing of IO WriteA3 and IO WriteA4 is completed.

[0078] It is evident that the order-preserving processing of the transmission network is effective for continuous IO write requests within the same Slave module, but it cannot guarantee the sequential execution of continuous IO write requests across multiple Slave modules. Therefore, an additional single-processing mechanism at the Slave level needs to be introduced in the IO proxy module. Thus, the order-preserving processing of the transmission network has limitations.

[0079] In other words, if the IO proxy module does not introduce a single-processing mechanism at the Slave level, when the IO proxy module attempts to send multiple consecutive IO write requests to different Slave proxy modules through the transport network, relying solely on the order-preserving processing of the transport network may cause sequential errors, leading to data inconsistency problems in the computer system.

[0080] For ease of understanding, based on the example in Figure 3A, Figure 3B exemplifies another example of continuous write operations on different Slave modules. Figure 3B is an example without introducing a single-processing mechanism at the Slave level in the IO proxy module. Combining Figures 3A and 3B, in the example in Figure 3B, the IO proxy module directly transmits the four IO write requests, IO WriteA1, IO WriteA2, IO WriteA3, and IO WriteA4, sequentially and continuously to the transmission network (e.g., Data Fabric bus).

[0081] Due to potential network congestion or transmission delays, the arrival times of IO WriteA1 and IO WriteA2 at the second memory proxy module, and the arrival times of IO WriteA3 and IO WriteA4 at the first memory proxy module, may be inconsistent, leading to a disordered execution order of the actual IO write requests.

[0082] Specifically, as shown in Figure 3B, IO WriteA3 and IO WriteA4 arrive at the first memory proxy module in sequence and are executed by the first memory. Therefore, the first memory processes IO WriteA4 and writes new data (i.e., New A4); as the first memory executes IO WriteA4, the old data (Old A4) is updated to the new data (New A4).

[0083] For IO WriteA1 and IO WriteA2, IO WriteA2 experiences a transmission delay, arriving at the second memory proxy module later than IO WriteA4 arrives at the first memory proxy module. Therefore, when the first memory module executes IO WriteA4 and updates Old A4 to New A4, IO WriteA2 may not have finished executing, or may not even have reached the second memory proxy module. In this situation, if other Master modules and their corresponding Master proxy modules read the Flag data at write address A4, consider IO WriteA4 to have completed successfully, and want to retrieve the data written by the preceding IO write requests (IO WriteA1 to IO WriteA3), since IO WriteA2 has not yet finished executing, the Master proxy modules corresponding to other Master modules will not retrieve the expected new data (New A2) at write address A2, but rather the old data (Old A2), leading to retrieval failure. This results in the computer system reading data that is not the latest data, failing to meet the data consistency requirements of the computer system.

[0084] It should be noted that in the example in Figure 3B, New A2 represents the new data written to address A2. As the second memory executes IO WriteA2, the old data (Old A2) is updated to the new data (New A2). As can be seen from the example in Figure 3B, when the Flag data at address A4 is generated and Old A4 is updated to New A4 (i.e., when IO WriteA4 is completed), the second memory has not yet completed IO WriteA2. That is, Old A2 has not yet been updated to New A2. Therefore, during the period between the completion of IO WriteA4 and the completion of IO WriteA2, other Master modules and the corresponding Master agent modules can read New A4 at address A4, but the data at address A2 is still the old data (Old A2). That is, they cannot obtain the new data (New A2) written by IO WriteA2, which should have been completed before IO WriteA4, resulting in a sequence error and failing to meet the data consistency requirements of the computer system.

[0085] It can be seen that pre-ordering IO write requests from the IO module in the transmission network has limitations. The transmission network cannot guarantee the sequential execution of consecutive IO write requests across multiple Slave modules on its own, requiring the introduction of a single-processing mechanism at the Slave level in the IO proxy module. Furthermore, pre-ordering IO write requests in the transmission network reduces its flexibility and increases its design complexity, thus limiting its performance. Specifically, pre-ordering IO write requests in the transmission network forces it to use a mechanism that transmits IO write requests in order, resulting in a lack of transmission flexibility and limitations on the transmission network design.

[0086] Based on this, the embodiments of this disclosure consider avoiding the order-keeping processing of access requests to IO modules by the transmission network while ensuring the data consistency of the computer system; that is, the solution provided by the embodiments of this disclosure eliminates the order-keeping requirement of the transmission network for access requests to IO modules, thereby freeing up the transmission network of the computer system, enabling the computer system to adapt to transmission networks with any transmission mechanism, reducing the design limitations of the transmission network, and improving the performance of the transmission network.

[0087] As an optional implementation, in order to ensure data consistency of the computer system and improve the performance of the transmission network, the embodiments of this disclosure consider introducing a cache coherence protocol into the IO proxy module. The IO proxy module can manage the IO write requests of the corresponding IO module with cache lines based on the cache coherence protocol.

[0088] Specifically, the IO proxy module can determine the cache line write operation corresponding to the IO write request initiated by the IO module, and acquire exclusive access to the cache line corresponding to the cache line in the Slave module. This ensures that before the IO proxy module issues an IO write request, all accesses to the cache line by other Master proxy modules will be reported back to the IO proxy module through the corresponding query request. Therefore, the IO proxy module can respond to the query request based on data consistency requirements, ensuring that the data access to the cache line by other Master proxy modules is up-to-date and accurate before the IO proxy module issues an IO write request, thus guaranteeing data consistency. Furthermore, when the IO proxy module has acquired exclusive access to the cache line corresponding to the cache line write operation of the IO write request, and the IO write request arrives in the correct order, it issues a request to write the complete cache line corresponding to the IO write request, thereby writing the write data of the IO write request to the Slave module. This ensures data consistency while processing the IO write request of the IO module and releases the computer system's transmission network.

[0089] Based on the above ideas, as an optional implementation, Figure 4 exemplarily shows an optional flowchart of the write request processing method provided by the embodiments of this disclosure. The flowchart in Figure 4 mainly illustrates the scheme for processing IO write requests of the IO module provided by the embodiments of this disclosure from the perspectives of the IO module, the IO proxy module, and the Slave proxy module (such as the memory proxy module). As shown in Figure 4, the process may include the following steps.

[0090] In step S410, the IO module sends an IO write request to the IO agent module.

[0091] In an optional implementation, the IO module can continuously send multiple IO write requests to the IO proxy module, such as multiple concurrent IO write requests, including but not limited to: multiple concurrent IO write requests for the same Slave module, and multiple concurrent IO write requests for different Slave modules (such as multiple IO write requests with contiguous addresses and scattered across different Slave modules).

[0092] In step S411, the IO proxy module obtains the IO write request from the IO module.

[0093] Correspondingly, based on the IO write request sent by the IO module to the IO proxy module, the IO proxy module can obtain the IO write request from the IO module.

[0094] In an optional implementation, the IO proxy module can set up a request queue to store the request information of acquired IO write requests. For example, the IO proxy module can store the acquired IO write request information in the request queue in order. That is, the IO proxy module stores the IO write request information in the request queue according to the order in which it acquired the IO write requests from the IO module. Therefore, the storage order of the IO write request information in the request queue represents the acquisition order of the IO write requests, i.e., the order in which the IO proxy module acquired the IO write requests from the IO module. Furthermore, for the IO proxy module, the order in which the IO write requests are issued (i.e., the order in which the IO proxy module sends the IO write requests to the transport network) corresponds to the acquisition order of the IO write requests. Therefore, when the IO write request information is stored in the request queue of the IO proxy module in the order of acquisition, the storage order of the IO write request information in the request queue is the same as the issuance order of the IO write requests.

[0095] In an optional implementation, the request queue of the IO proxy module can be set in a buffer inside the IO proxy module, so that the IO proxy module can buffer the request information of the acquired IO write requests in order through the request queue in the buffer.

[0096] For example, the request information for an IO write request may include, but is not limited to, the write data (i.e., the data content), the write address (i.e., the address where the write data is written to the Slave module), and the write data size (i.e., the size of the write data).

[0097] In step S412, the IO proxy module determines the cache line coverage integrity corresponding to the cache line write operation of the IO write request.

[0098] In this embodiment, the IO proxy module has cache coherence protocol processing capabilities, enabling it to manage IO write requests for corresponding IO modules at the cache line level based on the cache coherence protocol. That is, for IO write requests from IO modules, the IO proxy module manages them at the cache line granularity. Therefore, when the IO proxy module obtains an IO write request from an IO module (e.g., when the IO proxy module stores the request information of the IO write request in the request queue), it can determine the cache line write operation corresponding to the IO write request. For example, the IO proxy module can parse the request information of the IO write request to determine the corresponding cache line write operation.

[0099] In the IO proxy module, when managing the IO write requests of the IO module with cache lines, the write data operation of the IO write request can be mapped to the corresponding cache line, thereby obtaining the cache line write operation corresponding to the IO write request. That is, the write data of the IO write request is allocated to one or more cache lines, and the data is written with the cache line as the basic operation unit. Thus, the cache line write operation of the IO write request has corresponding write data. That is, the write data of the cache line write operation is: the data content written by the IO write request in the cache line corresponding to the cache line write operation.

[0100] It's important to clarify that an IO write request from the IO module refers to a request from the IO module to write data to an address range (e.g., a memory address range) of the Slave module. This address range can be indicated by the write address of the IO write request. A cache line write operation, on the other hand, maps the IO write request to a specific cache line based on the write address and the size of the write data, and is a write operation with the cache line as the basic unit. Therefore, the relationship between IO write requests and cache line write operations is as follows: an IO write request triggers a cache line write operation, and an IO write request may be decomposed into one or more cache line write operations. The cache line write operation of the IO write request is then used to write the write data of the cache line write operation to the corresponding cache line, thus realizing the data writing of the IO write request.

[0101] It should be further explained that a cache line can be a fixed-size data block in the cacheable space of a slave module, such as memory. For example, the cache line size can be a fixed size such as 64 bytes, depending on the cache line size configuration. This disclosure does not impose any limitations. Data in the cacheable space of a slave module, such as memory, can be loaded into the computer system's system cache (such as the L1 cache, L2 cache, L3 cache, etc. of the core cluster).

[0102] Taking the Slave module as memory as an example, the cacheable space of memory is a memory area that can be used for cache management. Data in this memory area can be loaded into processor caches such as L1 cache, L2 cache, and L3 cache to speed up data access efficiency. Therefore, when the IO proxy module manages the IO write requests of the corresponding IO module using cache lines, the IO proxy module can use the cache line write operation corresponding to the IO write request to write the write data of the cache line write operation in the cacheable space of the Slave module (such as memory), thus realizing the writing of the IO write request data into the Slave module (such as memory).

[0103] When determining the cache line write operation corresponding to an IO write request, the IO proxy module needs to determine the cache line coverage integrity of the cache line write operation. The cache line coverage integrity of a cache line write operation refers to the degree to which the written data of the cache line write operation covers the corresponding cache line. Based on whether the written data of the cache line write operation completely covers the corresponding cache line, the cache line coverage integrity of a cache line write operation is divided into: complete coverage (i.e., completely covering the cache line) and partial coverage (i.e., partially covering the cache line).

[0104] In this context, "complete coverage" means that the size of the write data corresponding to the cache line write operation is equal to the size of the cache line, so that the write data of the cache line write operation completely covers all bytes of the corresponding cache line. For example, if the size of the write data corresponding to the cache line write operation is equal to 64 bytes, the write data of the cache line write operation can be completely written to the corresponding cache line without reading and merging the existing data of the cache line, because the write data of the cache line write operation covers all bytes of the corresponding cache line, and the existing data of the cache line will be overwritten and updated by the write data of the cache line write operation.

[0105] Partial overwriting occurs when the write data in a cache line write operation is smaller than the cache line size, thus failing to cover all bytes of the corresponding cache line, but only covering a portion of the cache line. For example, if the write data in a cache line write operation is less than 64 bytes, the write data cannot be completely written to the corresponding cache line. It is necessary to first read the existing data in the corresponding cache line and merge the write data from the cache line write operation with the existing data corresponding to the uncovered bytes in the cache line.

[0106] For ease of explanation, in this embodiment of the disclosure, a cache line write operation with complete cache line coverage (i.e., completely covering the cache line) is referred to as a complete cache line write operation, and a cache line write operation with partial cache line coverage (i.e., partially covering the cache line) is referred to as a partial cache line write operation. Thus, the cache line write operations in this embodiment of the disclosure are divided into two categories: complete cache line write operations and partial cache line write operations.

[0107] For any IO write request obtained by the IO proxy module, the IO write request may have one or more cache line write operations, and the type of cache line write operations in the IO write request may be a full cache line write operation, or a partial cache line write operation, or a full cache line write operation and a partial cache line write operation.

[0108] In an optional implementation, the cache line write operation of an IO write request can be determined based on the write address and write data size of the IO write request. That is, for any IO write request obtained by the IO proxy module, the IO proxy module can determine the cache line write operation of the IO write request based on the write address and write data size of the IO write request. Specifically, depending on whether the write address of the IO write request is aligned with the cache line boundary and the relationship between the write data size of the IO write request and the cache line size, there can be several different cases for the cache line write operation of the IO write request.

[0109] For example, when the write address of an IO write request is aligned to a cache line boundary, i.e., the write address (e.g., the starting address) of the IO write request is the same as the starting address of a cache line, the cache line write operation of the IO write request includes any of the following:

[0110] If the size of the data written in the IO write request is equal to the size of the cache line, then the IO write request has a complete cache line write operation;

[0111] If the size of the data to be written in the IO write request is less than the size of the cache line, then the IO write request has a partial cache line write operation.

[0112] If the write data size of the IO write request is greater than the cache line size, and the write data size of the IO write request is an integer multiple of the cache line size, then the IO write request has multiple complete cache line write operations corresponding to the number of integer multiples.

[0113] If the write data size of the IO write request is greater than the cache line size, and the write data size of the IO write request is not an integer multiple of the cache line size, then the IO write request has at least one full cache line write operation and one partial cache line write operation.

[0114] For example, when the write address of an IO write request is not aligned with the cache line boundary, the IO write request may involve writing to one cache line or spanning multiple cache lines. Accordingly, the type of cache line write operation of the IO write request may be a partial cache line write operation, or two partial cache line write operations, or a partial cache line write operation and at least one full cache line write operation, or a partial cache line write operation and at least one full cache line write operation and a partial cache line write operation. The specific situations can be referred to the previous description, and will not be elaborated here.

[0115] In step S413, the IO proxy module sends an exclusive permission request for the cache line corresponding to the cache line write operation to the Slave proxy module based on the cache line coverage integrity of the cache line write operation, so as to obtain at least the exclusive permission for the cache line.

[0116] For any IO write request obtained by the IO proxy module, after determining the cache line coverage integrity of the cache line write operation of the IO write request, this embodiment of the disclosure can, based on the cache line coverage integrity of the cache line write operation, send an exclusive permission request for the cache line corresponding to the cache line write operation to the Slave proxy module corresponding to the Slave module targeted by the IO write request (e.g., the memory proxy module corresponding to the memory targeted by the IO write request), so as to at least request and acquire exclusive permission for the cache line corresponding to the cache line write operation. Specifically, an IO write request may have at least one cache line write operation, and each cache line write operation of the IO write request can issue a corresponding exclusive permission request for the cache line based on the corresponding cache line coverage integrity, so as to at least acquire exclusive permission for the corresponding cache line; for example, the exclusive permission for the cache line corresponding to each cache line write operation of the IO write request can be acquired separately through the corresponding exclusive permission request.

[0117] As an optional implementation, the exclusive permission request can indicate the cache line for which exclusive permission is requested. For example, the exclusive permission request can carry the address information of the cache line to identify the location of the cache line for which exclusive permission is requested in the cacheable space of the Slave module, such as memory.

[0118] In an optional implementation, for any cache line write operation of any IO write request (which may be a cache line write operation of one IO write request, or any cache line write operation of multiple cache line write operations of one IO write request), the IO proxy module can issue different exclusive permission requests based on whether the cache line write operation is a complete cache line write operation or a partial cache line write operation, in order to adapt to the specific situation of the cache line write operation.

[0119] Specifically, in an optional implementation, if the cache line write operation is a complete cache line write operation, meaning the cache line overwrite integrity of the cache line write operation is a complete overwrite of the cache line, then the IO proxy module can obtain exclusive access to the cache line corresponding to the cache line write operation without reading the existing data of the cache line, because the existing data of the cache line will be completely overwritten by the write data of the cache line write operation, so there is no need to read the existing data of the cache line. Based on this, if the cache line write operation is a complete cache line write operation, then the IO proxy module can issue a first exclusive access request corresponding to the cache line to the Slave proxy module. The first exclusive access request is used to request exclusive access to the cache line without reading the existing data of the cache line. For ease of explanation, in this embodiment of the disclosure, the exclusive access request that requests exclusive access to the cache line but does not read the existing data of the cache line is referred to as the first exclusive access request.

[0120] For example, the first exclusive access request can be, for instance, an LdToXND (Load To Exclusive No Data) request, where the LdToXND request is used to load a specific memory address as exclusive access, but without transferring the actual data content (No Data), in order to occupy the specific memory address before performing an exclusive write operation, so as to ensure that the subsequent write operation is exclusive.

[0121] In an optional implementation, if the cache line write operation is a partial cache line write operation, that is, the cache line coverage of the cache line write operation is only partially covering the cache line, and the written data of the cache line write operation only covers a portion of the cache line, in order to avoid data conflicts and inconsistencies caused by directly performing partial write operations on the cache line, the IO proxy module needs to obtain exclusive access to the cache line corresponding to the cache line write operation and read the existing data of the cache line.

[0122] Specifically, this embodiment does not support returning partial data in the query response, meaning that only a portion of the cache line cannot be synchronized. This is to avoid data conflicts and inconsistencies caused by different Master modules simultaneously modifying different parts of the same cache line. For example, when a Master proxy module requests exclusive access to or modification of a cache line of a Slave module, the Slave proxy module corresponding to the Slave module sends a query request to the Master proxy module holding a copy of the cache line or the permissions. The query response is the reply to the query request; the Master proxy module holding a copy of the cache line or the permissions returns the current state of the cache line or marks the cache line as invalid. However, if the query response returns partial data (i.e., partial data), it may cause different Master proxy modules in the computer system to modify different parts of the same cache line of the Slave module in parallel, leading to data inconsistencies. Therefore, this embodiment does not support returning partial data in the query response.

[0123] Based on this, when the cache line write operation of the IO module's IO write request is a partial cache line write operation, the IO proxy module can send a second exclusive permission request corresponding to the cache line to the Slave proxy module. This second exclusive permission request is used to request exclusive permission for the cache line and read the existing data in the cache line. Thus, the IO proxy module can possess exclusive permission for the cache line corresponding to the partial cache line write operation and the existing data, allowing it to safely write the data in the corresponding cache line in a partial cache line write operation, and preventing other Master proxy modules from simultaneously modifying the cache line, thereby ensuring data consistency. For ease of explanation, in this embodiment, the exclusive permission request that requests exclusive permission for the cache line and reads the existing data in the cache line is referred to as the second exclusive permission request.

[0124] For example, a second exclusive access request can be an LdDataE (Load Data Exclusive) request. An LdDataE request is used to load data at a specific memory address and mark that memory address as exclusive. Unlike an LdToXND request, an LdDataE request loads and transfers the data content at a specific memory address while requesting exclusive access to that memory address.

[0125] In step S414, the Slave agent module sends back the exclusive permission response information corresponding to the exclusive permission request to the IO agent module.

[0126] After the Slave proxy module receives the exclusive permission request for the cache line sent by the IO proxy module, the exclusive permission request obtained by the Slave proxy module is used at least to request exclusive permission for the cache line, and the exclusive permission request corresponds to the cache line overwrite integrity of the cache line write operation corresponding to the cache line. Therefore, the Slave proxy module can process the exclusive permission request, at least authorize the exclusive permission of the cache line to the IO proxy module, and send back the exclusive permission response information corresponding to the exclusive permission request to the IO proxy module, such as TgtRsp information.

[0127] In an optional implementation, if the exclusive permission request obtained by the Slave proxy module is the first exclusive permission request (e.g., an LdToXND request), since the first exclusive permission request corresponds to a complete cache line write operation, the Slave proxy module can grant the exclusive permission of the cache line indicated by the first exclusive permission request (e.g., an LdToXND request) to the IO proxy module, and send back the exclusive permission response information (e.g., TgtRsp information) corresponding to the first exclusive permission request (e.g., an LdToXND request) to the IO proxy module. At this time, the exclusive permission response information is only used to inform the IO proxy module that it has successfully obtained the exclusive permission of the cache line, and does not carry the existing data of the cache line.

[0128] In an optional implementation, if the exclusive permission request obtained by the Slave proxy module is a second exclusive permission request (e.g., an LdDataE request), since the second exclusive permission request corresponds to a partial cache line write operation, the Slave proxy module can grant the exclusive permission of the cache line indicated by the second exclusive permission request (e.g., an LdDataE request) to the IO proxy module, and send back the exclusive permission response information (e.g., TgtRsp information) corresponding to the second exclusive permission request (e.g., an LdDataE request) to the IO proxy module. At this time, in addition to informing the IO proxy module that it has successfully obtained the exclusive permission of the cache line, the exclusive permission response information also needs to carry the existing data of the cache line so that the IO proxy module can read the existing data of the cache line, so that the write data of the partial cache line write operation of the IO proxy module can be merged with the existing data of the corresponding cache line.

[0129] In a further optional implementation, when processing an exclusive permission request, the Slave proxy module can check the current state of the cache line based on the cache line requesting exclusive permission indicated in the exclusive permission request (such as the address information of the cache line carried in the exclusive permission request). If the current state indicates that the exclusive permission of the cache line is occupied by another Master proxy module, the Slave proxy module can notify the other Master proxy module occupying the cache line to release the permission. If the current state indicates that the exclusive permission of the cache line is not occupied by another Master proxy module, or if the other Master proxy module occupying the cache line has released the permission, the Slave proxy module can confirm that the IO proxy module can successfully acquire the exclusive permission of the cache line. Thus, the Slave proxy module can change the state of the cache line to exclusive and authorize the exclusive permission of the cache line to the IO proxy module. Furthermore, after granting exclusive access to the cache line to the IO proxy module, the Slave proxy module can determine whether the exclusive access response information (such as TgtRsp information) sent back to the IO proxy module carries the existing data of the cache line, depending on whether the exclusive access request is a first exclusive access request (such as an LdToXND request) or a second exclusive access request (such as an LdDataE request).

[0130] In step S415, the IO proxy module obtains the exclusive permission response information corresponding to the exclusive permission request fed back by the Slave proxy module, so as to at least confirm that the exclusive permission for the cache line has been obtained.

[0131] Accordingly, based on the exclusive permission response information corresponding to the exclusive permission request sent by the Slave proxy module to the IO proxy module, the IO proxy module can at least confirm the cache line for which exclusive permission has been acquired. In an optional implementation, when the IO proxy module receives the returned exclusive permission response information, it can match the exclusive permission response information with the issued exclusive permission request to confirm the cache line for which exclusive permission has been acquired.

[0132] For example, when the IO proxy module issues an exclusive permission request, the request can carry a request identifier to uniquely identify the exclusive permission request. Therefore, after the Slave proxy module, based on the address information of the cache line synchronously carried in the exclusive permission request, grants exclusive permission to the IO proxy module for the cache line, it can carry the request identifier of the exclusive permission request in the exclusive permission response information corresponding to the exclusive permission request. That is, the exclusive permission response information can bring back the request identifier of the corresponding exclusive permission request, so that the exclusive permission request and the exclusive permission response information can be matched. Furthermore, the IO proxy module can use the request identifier carried in the exclusive permission response information to uniquely match the issued exclusive permission requests (for example, matching the issued exclusive permission requests with the request identifier carried in the exclusive permission response information in the request table) to confirm the cache line for which exclusive permission has been obtained.

[0133] In a further optional implementation, if the exclusive permission for the cache line corresponding to the cache line write operation of the IO write request has been acquired, the IO proxy module can mark the corresponding permission tag information for the IO write request to indicate that the exclusive permission for the cache line write operation of the IO write request has been acquired; for example, for any IO write request, if the IO proxy module confirms that the exclusive permission response information corresponding to the exclusive permission request for the cache line write operation of the IO write request has been returned, it can mark the corresponding permission tag information for the IO write request.

[0134] For example, the IO proxy module can mark the permission flags of IO write requests in the request queue to indicate that an IO write request in the request queue has acquired exclusive permission for a cache line.

[0135] In a further optional implementation, the IO proxy module can track the status and permissions of cached lines through table entries. For example, the table entries of the IO proxy module can record information such as the address, status, and ongoing operation of the cached line. When the IO proxy module obtains exclusive permission response information, the status of the corresponding cached line in the table entry can be set to exclusive.

[0136] In a further optional implementation, for multiple IO write requests obtained by the IO proxy module (e.g., multiple concurrent IO write requests), the IO proxy module supports obtaining exclusive permissions corresponding to multiple IO write requests in an out-of-order manner. That is, the exclusive permissions for cache lines corresponding to cache line write operations of multiple IO write requests can be obtained in an out-of-order manner, instead of having to obtain the corresponding exclusive permissions for cache lines according to the order in which the IO proxy module obtains multiple IO write requests. For example, the IO proxy module stores the request information of IO write requests in the request queue according to the order in which they were obtained. Thus, the storage order of IO write requests in the request queue corresponds to the order in which they were issued. When storing IO write requests in the request queue, the IO proxy module can issue an exclusive permission request for the corresponding cache line based on the cache line coverage integrity of the cache line write operation of the IO write request. After receiving the corresponding exclusive permission response information, it confirms that the exclusive permission for the cache line write operation of the IO write request has been obtained. In this case, for multiple IO write requests in the request queue that do not have address conflicts, the exclusive permission for the cache lines of multiple IO write requests can be obtained out of order. For example, the exclusive permission response information of multiple IO write requests may be returned to the IO proxy module out of order. The IO proxy module supports obtaining the exclusive permission response information corresponding to multiple IO write requests out of order to support the out-of-order acquisition of exclusive permission for the cache lines of multiple IO write requests.

[0137] It's important to note that since the IO proxy module acquires exclusive access to the cache line corresponding to the write operation of the IO write request, before releasing this exclusive access, any access to the cache line by other Master proxy modules will be relayed to the IO proxy module as a query request from the Slave proxy module. The IO proxy module can then respond to these query requests based on data consistency requirements, ensuring that the data accessed by other Master proxy modules to the cache line is up-to-date and accurate before the IO proxy module executes the write operation, thus guaranteeing data consistency. In other words, all access to the cache line by other Master proxy modules will be queried by the IO proxy module that has exclusive access to the cache line, and the IO proxy module can then inform the IO proxy module of the current correct and complete data through the query response, thereby ensuring data consistency.

[0138] Furthermore, if the exclusive permission response information returned by the Slave proxy module is the same as the exclusive permission response information corresponding to the first exclusive permission request (such as the LdToXND request), then since the cache line write operation corresponding to the cache line that obtained exclusive permission is a complete cache line write operation, the write data of the cache line write operation will completely overwrite the cache line. In this case, on the IO proxy module side, the IO proxy module does not need to perform further data processing, but waits for the IO write requests to arrive in the order of issuance and for the exclusive permission of the cache line to still be maintained before continuing subsequent processing. In other words, for the case where the cache line write operation is a complete cache line write operation, the IO proxy module does not need additional data merging. The write data of the cache line write operation is already the complete write data of the corresponding cache line. The IO proxy module only needs to directly write the write data of the cache line write operation completely into the cache line when the IO write requests arrive in the order of issuance and the exclusive permission of the cache line is still maintained.

[0139] Furthermore, if the exclusive permission response information returned by the Slave proxy module is the same as the exclusive permission response information corresponding to the second exclusive permission request (such as the LdDataE request), the IO proxy module can also read the existing data of the cache line based on the exclusive permission response information. At this time, the cache line write operation corresponding to the cache line for which exclusive permission has been obtained is a partial cache line write operation. The cache line write operation is a partial write to the cache line. Therefore, the IO proxy module needs to merge the write data of the cache line write operation with the existing data of the cache line at the data processing level to obtain the complete write data of the cache line corresponding to the cache line write operation. That is, the complete write data of the cache line at this time includes the write data of the cache line write operation and the part of existing data that has not been overwritten, so that the IO proxy module can write the complete write data of the cache line completely into the cache line when the IO write request arrives in the order it was issued and the exclusive permission of the cache line is still maintained.

[0140] In an optional implementation, the IO proxy module can merge the write data of a partial cache line write operation with the existing data of the corresponding cache line in its internal buffer.

[0141] Furthermore, for cases where a cache line write operation is a partial cache line write operation, after reading the existing data of the corresponding cache line, the IO proxy module can, based on the ByteEnable information of the cache line write operation, write the write data of the cache line write operation to a portion of the cache line's bytes. This overwrites the existing data corresponding to that portion of the bytes, forming the merged data of the cache line, which serves as the complete write data for the corresponding cache line. The ByteEnable information of the cache line write operation indicates the portion of bytes written to the corresponding cache line; that is, the ByteEnable information can locate the range of bytes written to the cache line. Therefore, when merging the write data of the cache line write operation with the existing data of the corresponding cache line, the write data of the cache line write operation is written to the portion of bytes specified by the ByteEnable information in the corresponding cache line. In other words, the ByteEnable information ensures that when merging the write data of a partial cache line write operation with the existing data of the corresponding cache line, the write data of the partial cache line write operation can correctly overwrite the corresponding portion of the bytes in the corresponding cache line, ensuring the accuracy of the data merging and preventing data loss.

[0142] In a further optional implementation, when the cached line write operation is a partial cached line write operation, the IO proxy module cannot discard the ByteEnable information of the cached line write operation, but needs to continue to save the ByteEnable information of the cached line write operation so that the IO proxy module may perform re-data merging in the future; for example, the IO proxy module can save the ByteEnable information of the partial cached line write operation of the IO write request in the request information of the IO write request in the request queue, or save the ByteEnable information of the partial cached line write operation in the Buffer.

[0143] In step S416, when the order of IO write requests arrives, if the exclusive permission for the cache line corresponding to the cache line write operation of the IO write request has been acquired, the IO proxy module issues a complete write data request corresponding to the cache line write operation based on the complete write data corresponding to the cache line.

[0144] The IO write requests obtained by the IO proxy module are issued in order, for example, according to the storage order of IO write requests in the request queue. For any IO write request, when it is the turn of the IO write request to be issued, the IO proxy module can check whether the exclusive permission of the cache line corresponding to the cache line write operation of the IO write request has been acquired (for example, checking whether the IO write request is marked with permission information in the request queue). If the exclusive permission of the cache line corresponding to the cache line write operation of the IO write request has been acquired (for example, detecting that the IO write request is marked with permission information), then the IO proxy module can issue the IO write request by writing the entire cache line. That is, the IO write request is a cache line write operation, writing the complete write data to the cache line corresponding to the cache line write operation of the IO write request, and the complete write data includes the write data of the cache line write operation of the IO write request, so as to realize the write data of the IO write request being written to the Slave module. Therefore, for any IO write request, if the IO write requests arrive in the order they were issued, and the exclusive permission for the cache line corresponding to the cache line write operation has been acquired, the IO proxy module can issue a complete write data request corresponding to the cache line write operation of the IO write request, based on the complete write data in the cache line corresponding to the cache line of the IO write request. This complete write data request writes complete write data into the cache line corresponding to the cache line write operation of the IO write request, and the complete write data includes at least the write data of the cache line write operation of the IO write request. Furthermore, if the IO write request is not marked with permission information when it arrives in the order it was issued, it must wait until the IO write request acquires exclusive permission before issuing the complete write data request corresponding to the cache line write operation based on the complete write data in the cache line.

[0145] As described above, if the cache line write operation of the IO write request is a full cache line write operation, then the complete write data corresponding to the cache line of the cache line write operation is the write data of the cache line write operation. Therefore, the full write data request corresponding to the cache line write operation is used to write the write data of the cache line write operation to the cache line corresponding to the cache line write operation. If the cache line write operation of the IO write request is a partial cache line write operation, then the complete write data corresponding to the cache line of the cache line write operation is merged data, that is, the write data of the cache line write operation is merged with the existing data of the corresponding cache line. Therefore, the full write data request corresponding to the cache line write operation is used to write the merged data of the corresponding cache line to the cache line corresponding to the cache line write operation, and the merged data includes the write data of the cache line write operation.

[0146] In an optional implementation, a full write data request can be, for example, an Evict Data Full request, used to write data completely to the cache line.

[0147] In step S417, the Slave agent module sends a response to the IO agent module regarding the complete write data request.

[0148] After receiving a full write data request (such as an Evict Data Full request) from the IO proxy module, the Slave proxy module can process the full write data request, write the corresponding full write data to the cache line indicated by the full write data request, and send the corresponding response information back to the IO proxy module. The full write data request can carry the address information of the cache line to be written and the full write data to be written; furthermore, the full write data request can also carry a request identifier to identify the full write data request.

[0149] In step S418, the IO proxy module sends the response information of the IO write request back to the IO module.

[0150] After obtaining the response information of the complete write data request from the Slave proxy module, if the IO proxy module confirms that the complete write data request corresponding to the cache line write operation of the IO write request has been completed (e.g., based on the request identifier carried in the response information, matching the completed complete write data request), it can send the corresponding response information (e.g., RSP information) of the IO write request back to the IO module to inform the IO module that the IO write request has been completed.

[0151] Furthermore, when the complete write data request corresponding to the cache line write operation of the IO write request is completed, the IO proxy module can request to release the exclusive rights of the cache line corresponding to the cache line write operation, for example, by sending a request to the Slave proxy module to release the exclusive rights of the corresponding cache line; or, when the Slave proxy module completes the complete write data request corresponding to the cache line write operation, it can also proactively release the exclusive rights of the corresponding cache line and inform the IO proxy module.

[0152] The interaction between the IO proxy module and the Slave proxy module can be carried out through a transmission network. This embodiment of the disclosure does not limit the transmission network. The computer system can adapt to any transmission network, such as a transmission network with any transmission mechanism.

[0153] In the write request processing method provided in this embodiment, the IO proxy module manages the IO write requests of the corresponding IO module based on the cache consistency protocol and cache lines. When the IO proxy module obtains the IO write request of the IO module, it can determine the cache line coverage integrity corresponding to the cache line write operation of the IO write request, and based on the cache line coverage integrity of the cache line write operation, issue an exclusive permission request for the cache line corresponding to the cache line write operation to at least obtain exclusive permission for the cache line. This ensures that before the IO proxy module performs the write operation on the cache line corresponding to the cache line write operation, other Master proxy modules' access to the cache line will be through the cache line corresponding to the cache line. The query request is fed back to the IO proxy module, which can then respond to the query request based on data consistency requirements to ensure that other Master proxy modules have the latest and most accurate access to the cache line data, thus ensuring data consistency. Furthermore, when the order of IO write requests arrives, if the IO proxy module confirms that it has acquired exclusive access to the cache line corresponding to the cache line write operation of the IO write request, it can issue a complete write data request corresponding to the cache line write operation based on the complete write data corresponding to the cache line, in order to request the writing of complete write data in the cache line. The complete write data includes at least the write data of the cache line write operation, thereby realizing the issuance of the IO write request.

[0154] In the above process, the IO proxy module based on the cache consistency protocol can obtain exclusive access to the cache line corresponding to the write operation of the IO write request, and transfer the order control point (i.e., the order-keeping point) of the data written by the IO write request to the IO proxy module. Therefore, the embodiments of this disclosure can release the order-keeping requirement of the computer system's transmission network for access requests to the IO module, enabling the computer system to adapt to transmission networks with any transmission mechanism, reducing the design limitations of the transmission network, and thereby improving the performance of the transmission network, such as improving the utilization of the transmission network and the throughput of the computer system. Therefore, the embodiments of this disclosure can release the order-keeping requirement of the computer system's transmission network for IO write requests while ensuring the data consistency of the computer system, thereby improving the performance of the transmission network.

[0155] To facilitate further understanding, taking the write operation of the IO module to multiple memory locations as an example, Figure 5 exemplifies an example diagram of the write request processing method provided in this embodiment of the present disclosure. Figure 5 mainly illustrates the interaction between the IO module, the IO proxy module, and the memory proxy modules corresponding to the multiple memory locations. The multiple memory locations involve a first memory and a second memory. The memory proxy module corresponding to the first memory is called the first memory proxy module, and the memory proxy module corresponding to the second memory is called the second memory proxy module. In the example of Figure 5, the IO WriteA1 of the IO module targets the first memory; for ease of explanation, IO WriteA1 is referred to as the first IO write request, i.e., the first IO WriteA1, and it is assumed that the first IO WriteA1 has a complete cache line write operation. The IO WriteA2 of the IO module targets the second memory; for ease of explanation, IO WriteA2 is referred to as the second IO write request, i.e., the second IO WriteA2, and it is assumed that the second IO WriteA2 has a partial cache line write operation. As shown in Figure 5, the example process of the write request processing method includes the following steps.

[0156] Step S510: The IO module transmits the first IO WriteA1 to the IO proxy module.

[0157] Step S511: The IO proxy module stores the request information of the first IO WriteA1 in the request queue.

[0158] Step S512: If the IO proxy module detects that the cache line write operation of the first IO WriteA1 is a complete cache line write operation, it sends a first LdToXND request to the first memory proxy module to request exclusive access to the first cache line corresponding to the cache line write operation.

[0159] Figure 5 illustrates this using the cache line write operation of the first IO WriteA1 as an example of a complete cache line write operation. For instance, if the first IO WriteA1 writes a complete 64-byte cache line, the cache line corresponding to the cache line write operation of the first IO WriteA1 is called the first cache line. Thus, when the IO proxy module detects that the first IO WriteA1 has written a complete cache line, it can trigger the LdToXND request (called the first LdToXND request) corresponding to the cache line write operation of the first IO WriteA1 to request exclusive access to the first cache line corresponding to the cache line write operation of the first IO WriteA1, without reading the existing data in the first cache line.

[0160] Step S513: The first memory proxy module feeds back the first TgtRsp information to the IO proxy module.

[0161] After obtaining the first LdToXND request, the first memory proxy module can process the first LdToXND request and return the corresponding TgtRsp information (referred to as the first TgtRsp information) to the IO proxy module to inform the IO proxy module that it has successfully obtained exclusive access to the first cache line.

[0162] In an optional implementation, after receiving the first LdToXND request, the first memory proxy module can check the current state of the first cache line based on the address (e.g., the starting address) of the first cache line carried in the first LdToXND request. If the current state indicates that the permissions of the first cache line are not occupied by other Master proxy modules, or if other Master proxy modules occupying the first cache line have released their permissions, the first memory proxy module can confirm that the IO proxy module has successfully acquired exclusive permissions for the first cache line. Therefore, the first memory proxy module can change the state of the first cache line to exclusive and grant permissions to the IO proxy module. Subsequently, the first memory proxy module returns first TgtRsp information to the IO proxy module. This first TgtRsp information does not carry any existing data in the first cache line; it only informs the IO proxy module that it has successfully acquired exclusive permissions for the first cache line.

[0163] Step S514: The IO proxy module sends the first SrcRsp information to the first memory proxy module.

[0164] In an optional implementation, after the IO proxy module obtains the first TgtRsp information fed back by the first memory proxy module, it can confirm that the IO proxy module has obtained exclusive access to the first cache line by matching the first TgtRsp information with the first LdToXND request. Thus, the table entry maintained by the IO proxy module can record the state of the first cache line as exclusive, and set the permission flag information for the corresponding first IO WriteA1 in the request queue.

[0165] Then, the IO proxy module can send the corresponding SrcRsp information (called the first SrcRsp information) to the first memory proxy module to inform the first memory proxy module that the IO proxy module will prepare to perform write operations related to the first cache line in the future.

[0166] Step S515: The IO proxy module issues IO write requests based on the order of IO write requests in the request queue. When it is the turn of the first IO WriteA1 to issue, if it is checked that the first IO WriteA1 has permission flag information, it sends a first Evict Data Full request to the first memory proxy module based on the write data of the cache line write operation of the first IO WriteA1, so as to request the write data of the cache line write operation to be written in the first cache line.

[0167] The IO proxy module can issue IO write requests sequentially based on the order of IO write requests stored in the request queue. When it is the turn of the first IO WriteA1 to issue, the IO proxy module can confirm that it has obtained exclusive permission for the first cache line written by the first IO WriteA1 based on the permission flag information of the first IO WriteA1 set in the request queue. Therefore, the IO proxy module can send a corresponding Evict Data Full request (called the first Evict Data Full request) to the first memory proxy module based on the write data of the cache line write operation of the first IO WriteA1 (which is the write data of the first IO WriteA1 at this time, corresponding to the complete write data of the first cache line) to request the write data of the cache line write operation of the first IO WriteA1 to be written in the first cache line.

[0168] Step S516: The first memory proxy module sends the first TgtRsp information back to the IO proxy module.

[0169] After receiving the first Evict Data Full request, the first memory proxy module, since the exclusive access to the first cache line has been acquired by the IO proxy module that issued the first Evict Data Full request, allows the execution of the first Evict Data Full request. This schedules the first memory to execute the first Evict Data Full request, writing the corresponding write data to the first cache line indicated by the first Evict Data Full request. Furthermore, the first memory proxy module sends corresponding TgtRsp information (referred to as the first TgtRsp information) back to the IO proxy module to indicate that the execution of the first Evict Data Full request is complete.

[0170] Step S517: The IO proxy module sends the first RSP information back to the IO module.

[0171] Step S518: The IO proxy module sends the first SrcRsp information to the first memory proxy module.

[0172] After receiving the first TgtRsp information, the IO proxy module confirms that the first Evict Data Full request has been completed. Then, it can send back the corresponding Rsp information (called the first Rsp information) to the IO module to indicate that the first IO WriteA1 has completed writing data. Then, the IO proxy module sends back the corresponding first SrcRsp information to the first memory proxy module to indicate that the relevant process of the first IO WriteA1 has been completed.

[0173] Figure 5 further illustrates the processing procedure for the second IO WriteA2, as shown below.

[0174] Step S520: The IO module transmits the second IO WriteA2 to the IO proxy module.

[0175] Step S521: The IO proxy module stores the request information of the second IO WriteA2 in the request queue.

[0176] Step S522: If the IO proxy module detects that the cache line write operation of the second IO WriteA2 is a partial cache line write operation, it sends a second LdDataE request to the second memory proxy module to request exclusive access to the second cache line corresponding to the cache line write operation and to read the existing data of the second cache line.

[0177] Figure 5 illustrates this using the second IO WriteA2 cache line write operation as an example of a partial cache line write operation. For instance, the second IO WriteA2 writes a portion of the bytes in a 64-byte cache line. The cache line corresponding to the second IO WriteA2 cache line write operation is called the second cache line. Thus, when the IO proxy module detects that the second IO WriteA2 is writing a partial cache line, it can trigger the LdDataE request corresponding to the second IO WriteA2 cache line write operation (the LdDataE request for the second IO WriteA2 is called the second LdDataE request) to request exclusive access to the second cache line corresponding to the second IO WriteA2 cache line write operation and read the existing data in the second cache line.

[0178] Step S523: The second memory proxy module feeds back the second TgtRsp information to the IO proxy module.

[0179] After receiving the second LdDataE request, the second memory proxy module can process the second LdDataE request, grant the IO proxy module exclusive access to the second cache line requested by the second LdDataE request, and feed back the data of the second cache line to the IO proxy module through the corresponding TgtRsp information (called the second TgtRsp information). This allows the IO proxy module to be informed that it has successfully obtained exclusive access to the requested second cache line, and enables the IO proxy module to obtain the existing data of the second cache line through the second TgtRsp information.

[0180] Step S524: The IO proxy module merges the write data of the cache line write operation of the second IO WriteA2 with the existing data of the second cache line to obtain the merged data of the second cache line, which is used as the complete write data.

[0181] After obtaining the second TgtRsp information, the IO proxy module can parse the existing data of the second cache line returned by the second memory proxy module. It then merges the write data of the cache line write operation of the second IO WriteA2 (which is now the write data of the second IO WriteA2) with the existing data of the second cache line to obtain the merged data of the second cache line, which serves as the complete write data of the second cache line. For example, the IO proxy module can, within its internal buffer, merge the write data of the cache line write operation with the existing data of the second cache line based on the ByteEnable information of the cache line write operation of the second IO WriteA2, with the write data of the cache line write operation overwriting a portion of the bytes in the second cache line indicated by the ByteEnable information.

[0182] Furthermore, the IO proxy module can set the status of the second cache line to exclusive in the table entry, and set permission flag information for the second IO WriteA2 in the request queue.

[0183] Step S525: The IO proxy module sends the second SrcRsp information to the second memory proxy module.

[0184] Step S526: The IO proxy module issues IO write requests based on the order of IO write requests in the request queue. When it is the turn of the second IO WriteA2 to be issued, if the second IO WriteA2 is checked to have permission flag information, the second Evict Data Full request is sent to the second memory proxy module based on the complete write data of the second cache line to request the complete write data of the second cache line to be written in the second cache line.

[0185] In other words, based on the data merging of the second cache line, the second IO WriteA2 is issued in the form of an Evict Data Full request (called the second Evict Data Full request) corresponding to the merged data of the second cache line (i.e. the complete write data of the second cache line) to write merged data containing the write data of the second IO WriteA2 into the second cache line, so as to realize the execution of the second IO WriteA2.

[0186] Step S527: The second memory proxy module feeds back the second TgtRsp information to the IO proxy module.

[0187] After obtaining the second Evict Data Full request, the second memory proxy module, since the exclusive access to the second cache line has been acquired by the IO proxy module that issued the second Evict Data Full request, allows the execution of the second Evict Data Full request, thereby scheduling the second memory to execute the second Evict Data Full request. Furthermore, the second memory proxy module sends back the corresponding TgtRsp information (referred to as the second TgtRsp information) to the IO proxy module to indicate that the execution of the second Evict Data Full request is complete.

[0188] Step S528: The IO proxy module sends the second RSP information back to the IO module.

[0189] Step S529: The IO proxy module sends the second SrcRsp information to the second memory proxy module.

[0190] After receiving the second TgtRsp information, the IO proxy module sends the corresponding Rsp information (called the second Rsp information) back to the IO module, and the IO proxy module sends the corresponding second SrcRsp information back to the second memory proxy module, indicating that the process related to the second IO WriteA2 has been completed.

[0191] The interaction between the aforementioned IO proxy module and the first memory proxy module and the second memory proxy module can be carried out through a transmission network. This embodiment of the disclosure does not limit the transmission network, and the computer system can adapt to any transmission network, such as a transmission network configured with any transmission mechanism.

[0192] In a further optional implementation, after the IO proxy module obtains exclusive access to the cache line corresponding to the cache line write operation of the IO write request, before issuing the full write data request (e.g., Evict Data Full request) corresponding to the cache line write operation, it may also receive a query request about the cache line from the Slave proxy module. This query request is triggered by other Master proxy modules accessing the cache line, i.e., a query conflict situation before Evict Data Full occurs. Specifically, after the IO proxy module acquires exclusive access to a cache line, before issuing the corresponding Evict Data Full request, the Slave proxy module, based on access requests to the cache line from other Master proxy modules, will check the status of the cache line with the IO proxy module through a polling operation. At this time, the IO proxy module will receive a polling request from the Slave proxy module. To simplify protocol processing, this embodiment supports the IO proxy module setting the status of the cache line to Invalid through the polling response, thereby releasing the exclusive access to the cache line and resetting the process by which the IO proxy module acquires exclusive access to the cache line. This avoids cache line permission conflicts between different modules, ensures that write operations are executed in the correct order, and maintains data consistency.

[0193] In other words, for the example flow in Figure 4, after the IO proxy module obtains exclusive access to the cache line, before issuing the complete write data request corresponding to the cache line write operation, if a query request for the cache line is obtained, the IO proxy module issues the corresponding query response to release the exclusive access to the cache line; and the IO proxy module needs to return to step S413, that is, return based on the cache line coverage integrity of the cache line write operation, and issue the exclusive access request for the cache line corresponding to the cache line write operation, so as to at least obtain the exclusive access to the cache line.

[0194] For ease of understanding, taking the example of the IO proxy module in Figure 5 obtaining exclusive access to the first cache line corresponding to the first IO WriteA1 and obtaining a query request for the first cache line before issuing the first Evict Data Full request, Figure 6A exemplarily shows another example diagram of the write request processing method provided in this embodiment of the disclosure. For simplicity, the content related to Figure 6A and Figure 5 can be referred to accordingly. Specifically, after the IO proxy module obtains exclusive access to the first cache line and before issuing the first Evict Data Full request, the process exemplified in Figure 6A includes the following steps.

[0195] Step S610: The first memory proxy module receives the LdDataE request for the first cache line sent by other Master proxy modules.

[0196] Other Master proxy modules, such as other IO proxy modules or other core cluster proxy modules, can send an LdDataE request for the first cache line to the first memory proxy module to request exclusive access to the first cache line and the existing data. The time when the first memory proxy module receives the LdDataE request for the first cache line from other Master proxy modules is later than the time when the first memory proxy module grants exclusive access to the first cache line to the IO proxy module, but earlier than the time when the first memory proxy module receives the first Evict Data Full request.

[0197] Step S611: The first memory proxy module sends the first query request corresponding to the first cache line to the IO proxy module.

[0198] Since the IO proxy module has already obtained exclusive access to the first cache line through the first LdToXND request, when the first memory proxy module receives an LdDataE request for the first cache line from another Master proxy module, it cannot directly provide exclusive access to the first cache line and return existing data. Therefore, the first memory proxy module can initiate a query request (referred to as the first query request) to the IO proxy module corresponding to the first cache line to inquire about the status of the first cache line and request the IO proxy module to release the exclusive access to the first cache line.

[0199] Step S612: The IO proxy module sends a first query response to the first memory proxy module.

[0200] When the IO proxy module receives the first query request, it has not yet issued the first Evict Data Full request. For example, it may be before the first IO WriteA1 is issued, and therefore the IO proxy module has not yet issued the first Evict Data Full request. At this time, the IO proxy module can respond to the first query request corresponding to the first cache line and set the status of the first cache line to Invalid, indicating that the IO proxy module relinquishes its exclusive rights to the first cache line. Thus, the IO proxy module can send the query response corresponding to the first query request (called the first query response) to the first memory proxy module. The query response may be, for example, query RspToTgt (Query Response To Target), and the first query response indicates that the status of the first cache line is Invalid.

[0201] In other words, after the IO proxy module obtains exclusive access to the cache line, before issuing the complete write data request corresponding to the cache line write operation, if it receives a query request for the cache line, the IO proxy module will issue a corresponding query response to notify that the cache line is in an invalid state, and the IO proxy module releases the exclusive access to the cache line.

[0202] Furthermore, since the IO proxy module obtains the cache line query request before performing Evict Data Full on the cache line, the IO proxy module may not return the complete write data of the cache line to the Slave proxy module when responding to the query. For example, the query response may not carry the data of the cache line. In this case, the query response is only a response indicating that the status of the cache line is invalid, rather than a data response.

[0203] As can be seen, due to the LdDataE requests from other Master agent modules for cached lines and the query requests from Slave agent modules for cached lines, the IO agent module can relinquish its exclusive access to the cached lines. This ensures that before the IO agent module issues an Evict Data Full request, the IO write requests from other Master agent modules for cached lines can be executed in the correct order, thus maintaining data consistency in the computer system.

[0204] Step S613: The first memory agent module sends TgtRsp information to other Master agent modules.

[0205] After receiving the first query response from the IO proxy module, the first memory proxy module can confirm that the IO proxy module has released the exclusive access to the first cache line. Thus, the first memory proxy module can process access requests from other Master proxy modules, such as granting exclusive access to the first cache line to other Master proxy modules and sending corresponding TgtRsp information to them. Since the requests initiated by other Master proxy modules to the first memory proxy module are LdDataE requests, the TgtRsp information sent by the first memory proxy module to other Master proxy modules also carries the existing data of the first cache line.

[0206] Step S614: Other Master agent modules send SrcRsp information to the first memory agent module.

[0207] After other Master agent modules obtain the TgtRsp information of the first memory agent module, it indicates that the other Master agent modules have obtained exclusive access to the first cache line and the existing data. Therefore, the other Master agent modules can send the corresponding SrcRsp information to the first memory agent module.

[0208] Step S615: The IO proxy module resends the first LdToXND request to the first memory proxy module.

[0209] Since the exclusive access of the IO proxy module to the first cache line is interrupted, the IO proxy module needs to re-initiate the first LdToXND request, that is, resend the first LdToXND request to the first memory proxy module to request exclusive access to the first cache line, without reading the existing data in the first cache line.

[0210] Specifically, after the IO proxy module receives the first query request, the status of the first cached line in the IO proxy module's table is changed from exclusive to invalid, meaning the exclusive permission of the first cached line in the table is invalidated. Since the IO proxy module has not yet sent its first Evict Data Full request, it needs to perform write operations on the first cached line to ensure that the first Evict Data Full request can be executed correctly. Therefore, after the first cached line is placed in an invalid state (e.g., after the status of the first cached line in the table is set to Invalid), the IO proxy module can trigger the operation to reacquire the exclusive permission of the first cached line. Consequently, the IO proxy module can resend the first LdToXND request to the first memory proxy module. In other words, the operation of the IO proxy module to acquire the exclusive permission of the first cached line is reset due to the query request.

[0211] In other words, after the IO proxy module acquires exclusive access to the cache line, before issuing the complete write data request corresponding to the cache line write operation, if a query request for the cache line is obtained, the IO proxy module will release the exclusive access to the cache line due to access to the cache line by other Master proxy modules, and the IO proxy module will reacquire the exclusive access to the cache line.

[0212] Step S616: The first memory proxy module feeds back the first TgtRsp information to the IO proxy module.

[0213] After receiving the first LdToXND request, the first memory proxy module can re-grant exclusive access to the first cache line to the IO proxy module and re-feed back the first TgtRsp information.

[0214] In response to the IO proxy module's request for renewed exclusive access to cache lines, the Slave proxy module may re-grant exclusive access to cache lines to the IO proxy module under any of the following circumstances:

[0215] Other Master agent modules have completed their operations on the cache line; the purpose of the query request is to instruct the IO agent module to release control of the cache line so that other Master agent modules can access or modify the data in that cache line; when the Slave agent module receives a response from other Master agents indicating that the cache line operation is complete, the other Master agent modules will release their permissions on the cache line, allowing the Slave agent module to re-grant exclusive permissions to the IO agent module for the cache line.

[0216] If a cache line is in a masterless state and no exclusive rights are held by other Master agent modules after the cache line has been processed, the Slave agent module can re-grant exclusive rights to the IO agent module for the cache line.

[0217] Step S617: The IO proxy module sends the first SrcRsp information to the first memory proxy module.

[0218] The subsequent process in the example of Figure 6A continues to the stage where the IO proxy module in the example of Figure 5 issues the first Evict Data Full request. This will not be elaborated here, but the relevant content can be found in the relevant description in the example section of Figure 5.

[0219] It should be noted that Figure 6A is an example of a complete cache line write operation for the first IO Write A1. When the cache line write operation of the IO write request is a partial cache line write operation, taking the Evict Data Full pre-detection conflict of the second IO Write A2 as an example, Figure 6B exemplarily shows another example of the write request processing method provided in this embodiment. The difference between Figure 6A and Figure 6B is that, in the case of a partial cache line write operation, the IO proxy module needs to reset the exclusive permission to obtain the cache line and reset the process of merging data. Referring to Figures 5 and 6B, the process illustrated in Figure 6B includes the following steps.

[0220] Step S620: The second memory proxy module receives the LdDataE request for the second cache line sent by other Master proxy modules.

[0221] Step S621: The second memory proxy module sends the second query request corresponding to the second cache line to the IO proxy module.

[0222] Since the IO proxy module has obtained exclusive access to the second cache line through the second LdDataE request, when the second memory proxy module receives an LdDataE request for the second cache line from another Master proxy module, the second memory proxy module needs to query the IO proxy module for the status of the second cache line and request the IO proxy module to release the exclusive access.

[0223] Step S622: The IO proxy module sends a second query response to the second memory proxy module.

[0224] When the IO proxy module receives the second query request, it has not yet issued the second Evict Data Full request. For example, the request queue has not yet reached the issuance order of the second IO WriteA2, and therefore the IO proxy module has not yet issued the second Evict Data Full request. At this time, the IO proxy module can respond to the second query request by setting the status of the second cache line to Invalid, indicating that the IO proxy module relinquishes its exclusive rights to the second cache line. For example, the IO proxy module can change the status of the second cache line in the table from Exclusive to Invalid. Therefore, the IO proxy module can send a second query response to the second memory proxy module. The second query response indicates that the status of the second cache line is Invalid, and the second query response is not considered a data response.

[0225] Step S623: The second memory proxy module sends TgtRsp information to other Master proxy modules.

[0226] After receiving the second query response sent by the IO agent module, the second memory agent module can confirm that the IO agent module has released the exclusive rights to the second cache line. Therefore, the second memory agent module can grant the exclusive rights to the second cache line to other Master agent modules and send the corresponding TgtRsp information to other Master agent modules. Since the request initiated by other Master agent modules to the second memory agent module is an LdDataE request, the TgtRsp information also carries the existing data of the second cache line.

[0227] Step S624: Other modules: The Master agent module sends SrcRsp information to the second memory agent module.

[0228] Step S625: The IO proxy module resends the second LdDataE request to the second memory proxy module.

[0229] The IO proxy module can trigger an operation to reacquire exclusive access to the second cache line. Consequently, the IO proxy module can resend the second LdDataE request to the second memory proxy module. Since the cache line write operation of the second IO WriteA2 is a partial cache line write operation, the corresponding exclusive access request is an LdDataE request. In other words, the IO proxy module's operation to acquire exclusive access to the second cache line and the existing data is reset due to the second cache line's query request.

[0230] Step S626: The second memory proxy module feeds back the second TgtRsp information to the IO proxy module.

[0231] Step S627: The IO proxy module merges the write data of the cache line write operation of the second IO WriteA2 with the existing data of the second cache line to obtain the merged data of the second cache line.

[0232] Step S628: The IO proxy module sends the second SrcRsp information to the second memory proxy module.

[0233] The subsequent process in the example of Figure 6B continues to the stage in the example of Figure 5 where the IO proxy module issues the second Evict Data Full request. This will not be elaborated further here; relevant details can be found in the description of the example section in Figure 5. It can be seen that when the cache line write operation corresponding to the query request is a partial cache line write operation, the IO proxy module, in addition to re-acquiring exclusive access to the cache line, also re-performs the process of merging the write data of the cache line write operation with the existing data in the cache line. For example, at this time, it is necessary to use the saved ByteEnable information to perform the data merging again.

[0234] In a further optional implementation, if a polling conflict occurs before Evict Data Full, the IO proxy module needs to check the status of the IO write request based on address matching and mark the IO write request as interrupted. Specifically, the IO proxy module's request buffer temporarily stores incomplete IO write requests. Each IO write request contains a corresponding write address. When the exclusive access of the cache line corresponding to the IO write request is interrupted by the polling and the exclusive access is lost, causing the progress of the IO write request to be forcibly interrupted, the IO proxy module needs to temporarily save the status of the IO write request and mark it as interrupted. Then, after regaining the exclusive access of the cache line, the IO proxy module will match the cache line with the newly acquired exclusive access with the IO write requests in the request buffer to ensure that the processing of the corresponding IO write request can be resumed after the exclusive access of the cache line is restored.

[0235] In a more specific optional implementation, the request buffer of the IO proxy module for buffering IO write requests and the MPQ (Memory Proxy Queue) of the memory proxy module can have the same address matching logic. That is, the request buffer of the IO proxy module needs to add the same address matching processing as the MPQ of the memory proxy module. The MPQ of the memory proxy module is a queue used to process and manage memory requests, used to temporarily store and schedule memory access requests. Thus, when the IO proxy module receives a query request corresponding to a cache line, the IO proxy module can set the status of the cache line at the corresponding address to an invalid state in the table entry. And based on the address matching mechanism, that is, the address matching logic of the request buffer of the IO proxy module (the same as the MPQ of the memory proxy module), the IO proxy module can realize mutual querying between the write address of the IO write request and the status of the corresponding cache line. Thus, when the status of the cache line corresponding to the IO write request becomes invalid, the status of the IO write request is marked as interrupted. When the status of the cache line corresponding to the IO write request is restored to an exclusive state, the continued processing of the corresponding IO write request is resumed.

[0236] In other words, when an Evict Data Full pre-interrogation conflict occurs, the IO proxy module sets the status of the cache line corresponding to the received interrogation request to an invalid state in the table entry, and checks whether there is an incomplete corresponding IO write request in the request buffer according to the address matching mechanism. If there is an incomplete corresponding IO write request, the IO proxy module can set the status of the corresponding IO write request to an interrupted state. Then, after regaining exclusive access to the cache line, the IO proxy module can restore the status of the cache line to an exclusive state in the table entry, and resume the continued processing of the corresponding IO write request according to the address matching mechanism. That is, when the IO write request arrives in the order of issuance, the exclusive access to the cache line for the cache line write operation of the IO write request has been obtained, and a complete write data request corresponding to the cache line write operation is issued.

[0237] It should be further explained that, after the IO proxy module obtains exclusive access to the complete cache line, but before issuing the Evict Data Full request, if the IO proxy module receives a query request for the cache line, it must set the status of the cache line to Invalid and reset the process of obtaining exclusive access to the cache line. Specifically, the following situations may occur:

[0238] After the IO proxy module acquires exclusive access to the cache line, if it does not receive a query request for the cache line before issuing the Evict Data Full request, the IO proxy module can maintain exclusive access to the cache line until the Evict Data Full request is issued. At this time, the IO proxy module does not need to reacquire exclusive access to the cache line.

[0239] Before issuing an Evict Data Full request, the IO proxy module may need to reacquire exclusive access to the cache line. If, after acquiring exclusive access to the cache line, the IO proxy module receives a query request for the cache line before issuing the Evict Data Full request, the IO proxy module needs to reset the process of acquiring exclusive access to the cache line. If, after the IO proxy module reacquires exclusive access to the cache line, it does not receive any further query requests for that cache line until the Evict Data Full request is issued, the IO proxy module can maintain exclusive access to that cache line until the Evict Data Full request is issued.

[0240] Before issuing an Evict Data Full request, the IO proxy module may need to reacquire exclusive access to the cache line multiple times. For example, if the IO proxy module resets the process of acquiring exclusive access to the cache line once, and then receives a query request for the same cache line before issuing an Evict Data Full request, the IO proxy module needs to reset the process of acquiring exclusive access to the cache line again. This process may be repeated multiple times before the IO proxy module issues an Evict Data Full request, meaning the IO proxy module needs to reacquire exclusive access to the cache line multiple times.

[0241] In other words, before issuing an Evict Data Full request, each time the IO agent module receives a query request for a cache line, its exclusive access to that cache line will be invalidated. The IO agent module needs to reset the process of acquiring exclusive access to that cache line in order to regain exclusive access to that cache line until an Evict Data Full request is issued.

[0242] In a further optional implementation, after the IO proxy module issues a full write data request (e.g., an Evict Data Full request) corresponding to the cache line write operation, it may also receive a query request from the Slave proxy module about the cache line. This query request is triggered by other Master proxy modules accessing the cache line, i.e., a query conflict occurs after an Evict Data Full. Specifically, after the IO proxy module issues a full write data request (e.g., an Evict Data Full request) and before receiving the response information from the Slave proxy module regarding the corresponding full write data request (e.g., an Evict Data Full request), the IO proxy module may obtain a query request for a cached line sent by the Slave proxy module. The Slave proxy module issues this query request earlier than the time the full write data request (e.g., an Evict Data Full request) arrives at the Slave proxy module, but later than the time the IO proxy module issues its own full write data request. In this case, the IO proxy module can issue a corresponding query response to release exclusive access to the cached line. The query response carries the complete write data of the cached line, so that the Slave proxy module can provide feedback on the complete write data written by the IO proxy module in the cached line when responding to other Master proxy modules, ensuring data consistency in the computer system.

[0243] Since the time when the full write data request (e.g., the Evict Data Full request) arrives at the Slave proxy module is later than the time when the Slave proxy module issues the query request, the full write data request (e.g., the Evict Data Full request) is interrupted by the query. Therefore, when the IO proxy module subsequently obtains the response information (e.g., TgtRsp information) from the Slave proxy module in response to the query, the IO proxy module can send a response information carrying a Cancel (clear) flag (e.g., SrcRsp information carrying a Cancel flag) to the Slave proxy module to clear the cache line write operation corresponding to the full write data request (e.g., the Evict Data Full request). This is because the full write data of the full write data request (e.g., the Evict Data Full request) is already carried in the query response returned to the Slave proxy module, so there is no need to perform duplicate data operations.

[0244] It is important to note that in the case of a query conflict after an Evict Data Full request, since the IO proxy module has already issued a complete write data request (e.g., an Evict Data Full request), it has already included the complete write data required by the complete write data request (e.g., an Evict Data Full request) in the query response. Therefore, when the IO proxy module issues a query response in the form of a data response, it has indirectly completed the writing of the complete write data of the cache line. Thus, the IO proxy module does not need to reacquire exclusive access to the cache line, and subsequently, based on the TgtRsp information of the Slave proxy module, it can instruct the Slave proxy module to clear the corresponding cache write operation.

[0245] For ease of understanding, taking the example of the IO proxy module in Figure 5 issuing the first Evict Data Full request and obtaining the query request for the first cache line, Figure 7 exemplarily illustrates another example diagram of the write request processing method provided in this embodiment of the present disclosure. For the sake of simplicity, the content related to Figure 7 and Figure 5 can be referred to accordingly. Specifically, after the IO proxy module issues the first Evict Data Full request, the process illustrated in Figure 7 includes the following steps.

[0246] Step S710: The first memory proxy module sends the first query request corresponding to the first cache line to the IO proxy module.

[0247] After the IO proxy module issues the first Evict Data Full request, but before the first Evict Data Full request reaches the first memory proxy module, the first memory proxy module receives LdDataE requests for the first cache line from other Master proxy modules. Thus, other Master proxy modules issue LdDataE requests for the first cache line to the first memory proxy module, triggering the first query request. The time when the LdDataE requests for the first cache line from other Master proxy modules reach the first memory proxy module is later than the time when the IO proxy module issues the first Evict Data Full request, but earlier than the time when the first Evict Data Full request reaches the first memory proxy module. Therefore, since the IO proxy module has not yet received the first Evict Data Full request when it receives the LdDataE requests for the first cache line from other Master proxy modules, the first memory proxy module sends the first query request corresponding to the first cache line to the IO proxy module. That is, the time when the first memory proxy module issues the first query request is earlier than the time when the first Evict Data Full request reaches the first memory proxy module, but later than the time when the IO proxy module issues the first Evict Data Full request.

[0248] Step S711: The IO proxy module sends a first query response to the first memory proxy module, carrying the complete write data of the first cache line.

[0249] When the IO proxy module issues the first Evict Data Full request, the data in the first cache line is marked as globally visible. However, before the first memory proxy module responds to the first Evict Data Full request, other Master proxy modules initiate access requests to the first cache line, requesting to read or modify its data. This causes the IO proxy module to receive the first memory proxy module's first query request for the first cache line. Since the data in the first cache line is globally visible, the IO proxy module (which can be considered the IO request port of the IO module) must respond to the first query request, carrying the complete write data of the first cache line in the first query response, and sending it back to the first memory proxy module. In other words, at this time, the first query response is both a status response and a data response for the cache line. The IO proxy module needs to use the first query response to indicate that the exclusive access to the first cache line has been released, and to carry the complete write data of the first cache line, to ensure data consistency in the computer system.

[0250] Furthermore, since the IO agent module recognizes that the first Evict Data Full request, which is currently in the Victim phase, has been queried, it is necessary to subsequently notify the first memory agent module to mark the Victim transaction corresponding to the first Evict Data Full request as Cancel.

[0251] Step S712: The first memory agent module sends TgtRsp information to other Master agent modules.

[0252] After receiving the first query response from the IO proxy module, the first memory proxy module can confirm that the IO proxy module has released exclusive access to the first cache line. Therefore, the first memory proxy module can grant exclusive access to the first cache line to other Master proxy modules and send corresponding TgtRsp information to them. Since the requests initiated by other Master proxy modules to the first memory proxy module are LdDataE requests, and the first query response also carries the complete write data of the first cache line, the TgtRsp information sent by the first memory proxy module to other Master proxy modules also carries the complete write data of the first cache line. This represents the write data result of the IO proxy module's first Evict Data Full request for the first cache line, thus ensuring the order of IO write requests and consequently ensuring data consistency in the computer system.

[0253] Step S713: Other Master agent modules send SrcRsp information to the first memory agent module.

[0254] Step S714: The first memory proxy module feeds back the first TgtRsp information to the IO proxy module.

[0255] As a data response, the first query response allows the first memory proxy module to send back the first TgtRsp information corresponding to the first cache line to the IO proxy module after completing the operations of other Master proxy modules.

[0256] Step S715: The IO proxy module sends the first RSP information to the IO module.

[0257] Step S716: The IO proxy module sends the first SrcRsp information to the first memory proxy module, and the first SrcRsp information carries a Cancel flag to clear the cache line write operation corresponding to the first Evict Data Full request.

[0258] After the first Evict Data Full request is interrupted by the interrogation, the IO agent module, upon receiving the first TgtRsp information from the first memory agent module, needs to send a SrcRsp message carrying a Cancel flag (i.e., the first SrcRsp message carrying a Cancel flag) to the first memory agent module to notify it to cancel the original Victim operation of the first Evict Data Full request. This ensures that the Victim transaction of the first Evict Data Full request is canceled after being interrupted by the interrogation (because the complete write data of the first Evict Data Full request is already carried in the first interrogation response returned to the first memory agent module), thus avoiding duplicate or unnecessary data operations.

[0259] It should be noted that in the event of a query conflict after Evict Data Full, the above steps involve the management and matching of IO write requests. Therefore, the request queue (REQ queue) must have the function of matching cache line addresses, especially when the Victim operation is interrupted by a query. The IO proxy module needs to match the corresponding Victim transaction in the REQ queue to correctly handle the query conflict. Furthermore, since the Victim transaction requires special handling when a query conflict occurs, and the entire process, from obtaining exclusive rights to confirming TgtRsp information, needs to be tracked in the request queue, the depth of the request queue (REQ queue) needs to be increased to meet high bandwidth requirements.

[0260] In an optional implementation, from the perspective of the Slave proxy module, after sending the exclusive permission response information corresponding to the exclusive permission request back to the IO proxy module, and before obtaining the complete write data request corresponding to the cache line write operation sent by the IO proxy module, if the Slave proxy module obtains access requests for cache lines from other Master proxy modules, it sends a cache line query request to the IO proxy module. Then, the Slave proxy module obtains the corresponding query response from the IO proxy module and processes the access requests from other Master proxy modules. At this point, there are two scenarios:

[0261] In scenario one, if the IO proxy module receives a query request but has not yet issued a complete write data request, the query response indicates that the exclusive access to the cache line has been released and does not carry any data. In this case, the Slave proxy module processes access requests from other Master proxy modules, such as granting exclusive access to the cache line to other Master proxy modules and reporting that there is already data. Furthermore, the Slave proxy module will receive the exclusive access request for the cache line corresponding to the cache line write operation resent by the IO proxy module. Then, the Slave proxy module can re-grant the exclusive access to the cache line to the IO proxy module and re-report the exclusive access response information to the IO proxy module.

[0262] Scenario 2: If the IO proxy module has already issued a full write data request when it receives the query request, the query response indicates that the exclusive access to the cache line has been released and carries the full write data corresponding to the cache line. In this case, the Slave proxy module can process the access requests of other Master proxy modules based on the full write data corresponding to the cache line returned by the query response, and send the response information to the IO proxy module in response to the query response. Then, it receives the response information with a clearing flag sent by the IO proxy module to clear the cache line write operation corresponding to the full write data request.

[0263] In a further optional implementation, the IO write requests obtained by the IO proxy module from the IO module may contain multiple IO write requests with address conflicts, i.e., multiple IO write requests with the same cache line corresponding to cache write operations. Based on this, the IO proxy module needs to introduce a cache line address conflict detection mechanism. For the IO write requests obtained by the IO proxy module, it needs to perform address matching to detect if there are any preceding IO write requests that write to the same cache line that have not been processed. For example, in the request queue, address matching is performed on the IO write requests stored in the request queue to detect if there are any preceding IO write requests that write to the same cache line that have not been processed. If there are multiple IO write requests that write to the same cache line, i.e., multiple IO write requests with the same cache line address, they are considered to have multiple IO write requests with address conflicts. Therefore, for multiple IO write requests with address conflicts, the IO proxy module needs to mark subsequent IO write requests as blocked in the order in which the IO write requests are obtained, until the preceding IO write requests are completed before processing subsequent IO write requests, so that multiple IO write requests with address conflicts can be processed in sequence. For example, for multiple I / O write requests with address conflicts, the exclusive access to the cache line corresponding to the preceding I / O write request is acquired first. When the order of the preceding I / O write requests arrives, the complete write data request corresponding to the cache line write operation of the preceding I / O write request is issued. Then, after the complete write data request corresponding to the cache line write operation of the preceding I / O write request is executed, the subsequent I / O write request can acquire the exclusive access to the corresponding cache line, and so on.

[0264] For ease of understanding, Figure 8 exemplarily illustrates another example diagram of the write request processing method provided in the embodiments of this disclosure. The relevant content of the example in Figure 8 can be referred to the preceding description, and the details will not be elaborated further. In the example in Figure 8, IO WriteA10 and IO WriteA11 are IO write requests with address conflicts, that is, the cache line addresses of IO WriteA10 and IO WriteA11 are the same, and both are examples of complete cache line write operations.

[0265] As shown in Figure 8, the IO proxy module obtains IO WriteA10 and initiates an LdToXND(A10) request to the Slave proxy module, exposing the exclusive permission for the cache line corresponding to IO WriteA10; the Slave proxy module returns TgtRsp(A10) information, confirming that the exclusive permission for the cache line corresponding to IO WriteA10 has been granted to the IO proxy module; after the IO proxy module confirms the exclusive permission for the cache line corresponding to IO WriteA10, the IO proxy module returns SrcRsp(A10) information to the Slave proxy module;

[0266] Before returning SrcRsp(A10) information and issuing an Evict Data Full(A10) request, the IO proxy module obtains the IO WriteA11 sent by the IO module. The IO proxy module detects that the cache line address of IO WriteA11 is the same as that of the preceding IO WriteA10. Since the IO proxy module is still processing IO WriteA10, it triggers an address conflict in the IO write request and marks the subsequent IO WriteA11 as blocked (e.g., by marking IO WriteA11 as blocked in the request queue). This allows it to wait for the preceding IO WriteA10 to finish processing before processing the subsequent IO WriteA11. In other words, by blocking IO WriteA11, the IO proxy module can ensure the order of multiple IO write requests with address conflicts, avoid concurrent modifications to the same cache line, and prevent data inconsistency issues.

[0267] Therefore, the IO proxy module issues an Evict Data Full (A10) request corresponding to IO WriteA10, indicating that the data in the cache line can be written and is globally visible; after the Slave proxy module confirms that the Evict Data Full (A10) request has been executed, it sends TgtRsp (A10) information back to the IO proxy module, and then the IO proxy module sends Rsp (A10) information back to the IO module, and SrcRsp (A10) information back to the Slave proxy module, indicating that the write operation of IO WriteA10 has been completed;

[0268] After the preceding IO WriteA10 is processed, the IO proxy module releases the blocking state of the address conflicting IO WriteA11 and issues the LdToXND(A11) request corresponding to IO WriteA11 to request exclusive access to the cache line. The subsequent processing of IO WriteA11 can be similarly described above and the information with the suffix (A11) in Figure 8, and will not be elaborated here.

[0269] As can be seen, the IO proxy module can ensure the sequential execution of write operations on the same cache line through blocking and queuing. For multiple IO write requests with address conflicts, subsequent IO write requests will only be unblocked and granted processing rights after the preceding IO write request has been completed. Furthermore, to meet the sequential requirement of multiple IO write requests with address conflicts, the request queue of the proxy module needs to have sufficient depth to accommodate blocked IO write requests, thereby ensuring maximum bandwidth utilization and performance.

[0270] As an optional implementation, when the IO module initiates multiple IO write requests, the IO proxy module can store the IO write requests in order in the request queue and attempt to acquire exclusive access to the cache line corresponding to the IO write request. In the absence of address conflicts, the exclusive access to the cache line for multiple IO write requests can be acquired out of order. That is, the exclusive access request is a pre-reservation of the cache line. At this time, the actual data writing has not yet occurred. Therefore, the exclusive access requests for the cache line corresponding to multiple IO write requests can be sent out of order. As long as the IO proxy module acquires the exclusive access to the cache line, it can execute the write operation of the cache line (i.e., issue an Evict Data Full request) in the order of the IO write requests. The embodiments of this disclosure allow out-of-order processing of exclusive access requests, which can accelerate the access acquisition process, avoid delays caused by sequential waiting, and improve parallelism.

[0271] Furthermore, read operations within the same request stream can be processed out of order. Specifically, for multiple read operations within the same request stream, there is no strict dependency between them because read operations do not change the data, so there is no need for strict ordering. In other words, read operations do not modify the data in the cached lines, so they do not cause data consistency issues. Therefore, allowing out-of-order read operations helps to accelerate data reading, improve the parallelism of the transmission network, and thus improve overall performance.

[0272] Furthermore, the cache line write operation corresponding to the Evict Data Full request is a Victim write operation, which evicts the complete write data of the cache line and writes it into memory, making it visible to other Master agent modules. Therefore, the Evict Data Full requests corresponding to the Victim write operation need to be issued in order, that is, according to the order in which the corresponding IO write requests are issued, especially for multiple consecutive IO write requests, to ensure that the order of the finally written data is consistent.

[0273] When the order of IO write requests arrives, an Evict Data Full request needs to be issued accordingly. If the exclusive permission for a cache line is lost or not acquired at this time, the associated subsequent IO write requests need to be blocked until the exclusive permission for the cache line of the current IO write request is successfully acquired. In other words, when the order of IO write requests arrives, if the exclusive permission for the cache line corresponding to the IO write request's cache line write operation is lost or not acquired, the associated subsequent IO write requests need to be blocked until the exclusive permission for the cache line corresponding to the IO write request's cache line write operation is successfully acquired and the corresponding complete write data request is issued.

[0274] For example, when it's the turn of an IO write request to be issued, if the corresponding cache line fails to acquire exclusive access (e.g., is invalidated by a paging operation), the Evict Data Full request corresponding to the IO write request cannot complete the Victim write operation. To ensure order, the IO proxy module needs to block the processing of subsequent IO write requests in the same request stream. That is, it suspends the processing of subsequent IO write requests in the same request stream until the preceding IO write request in the same request stream successfully acquires exclusive access to the corresponding cache line and completes the Evict Data Full request, before resuming the processing of subsequent IO write requests in the same request stream. Here, IO write requests in the same request stream are related and have order requirements; for example, IO write requests in the same request stream may be multiple consecutive IO write requests (e.g., multiple IO write requests with consecutive addresses). In this way, the IO proxy module uses a blocking mechanism to ensure that if a Victim write operation is not completed, subsequent Victim write operations in the same request stream will not overwrite previous data, thus avoiding data order disorder.

[0275] For example, taking multiple consecutive IO write requests as an example, Figure 9 exemplarily shows another example diagram of the write request processing method provided in the embodiments of this disclosure. The relevant content of the example in Figure 9 can be referred to the previous description, and the details will not be elaborated further.

[0276] As shown in Figure 9, the IO module sends multiple consecutive IO WriteA1, IO WriteA2, IO WriteA3, and IO WriteA4 to the IO proxy module. Each IO write request corresponds to a cache line, namely CLA1, CLA2, CLA3, and CLA4. IO WriteA1 and A2 are for the first memory, and IO WriteA3 and A4 are for the second memory. The IO proxy module can store IO WriteA1, IO WriteA2, IO WriteA3, and IO WriteA4 in the request queue. These multiple consecutive IO write requests belong to the same request stream, are interconnected, and must be written to the data in sequence.

[0277] Therefore, the IO proxy module sends the LdDataE(A1) request corresponding to IO WriteA1 and the LdToXND(A2) request corresponding to IO WriteA2 to the first memory proxy module. Here, we take IO WriteA1 writing part of CLA1 as an example and IO WriteA2 writing the complete CLA2 as an example. The IO proxy module sends the LdToXND(A3) request corresponding to IO WriteA3 and the LdDataE(A4) request corresponding to IO WriteA4 to the second memory proxy module. Here, we take IO WriteA3 writing the entire CLA3 as an example and IO WriteA4 writing part of CLA4 as an example.

[0278] Correspondingly, the first memory proxy module feeds back TgtRsp(A1) information and TgtRsp(A2) information to the IO proxy module to respond to the LdDataE(A1) request and LdToXND(A2) request respectively, and then the IO proxy module feeds back the corresponding SrcRsp(A1) information and SrcRsp(A2) information to the first memory proxy module.

[0279] Similarly, the second memory proxy module feeds back TgtRsp(A3) and TgtRsp(A4) information to the IO proxy module to respond to the LdToXND(A3) request and the LdDataE(A4) request respectively, and then the IO proxy module feeds back the corresponding SrcRsp(A3) and SrcRsp(A4) information to the second memory proxy module.

[0280] In the operation of acquiring exclusive permissions, the IO proxy module does not require a strict order. The IO proxy module can issue the above exclusive permission requests corresponding to IO WriteA1, IO WriteA2, IO WriteA3, and IO WriteA4 simultaneously or out of order. Correspondingly, the response information corresponding to the above exclusive permission requests, namely TgtRsp(A1), TgtRsp(A2), TgtRsp(A3), and TgtRsp(A4), can be returned to the IO proxy module in an out-of-order manner.

[0281] When the IO proxy module issues an Evict Data Full request, it must follow the order in which the IO write requests were issued. That is, the IO proxy module issues Evict Data Full requests in sequence, marks the data in the cache line as globally visible, and enters the Victim write phase. For example, the IO proxy module issues Evict Data Full requests (A1), (A2), (A3), and (A4) in sequence. When an Evict Data Full request needs to be issued, if the exclusive access to the cache line corresponding to the Evict Data Full request is lost (e.g., it is invalidated by a query), the IO proxy module needs to pause the processing of subsequent IO write requests in the request stream until the cache line corresponding to the Evict Data Full request regains exclusive access.

[0282] Subsequently, after each Evict Data Full request is executed, the IO proxy module receives the corresponding TgtRsp information, such as TgtRsp(A1), TgtRsp(A2), TgtRsp(A3), and TgtRsp(A4), and sends out the corresponding SrcRsp information, such as SrcRsp(A1), SrcRsp(A2), SrcRsp(A3), and SrcRsp(A4).

[0283] In a further example, to facilitate the illustration of the global order of the solutions provided in the embodiments of this disclosure, FIG10 exemplarily shows another example diagram of the write request processing method provided in the embodiments of this disclosure. The relevant content of FIG10 can be referred to the preceding description, and the details will not be elaborated further.

[0284] As shown in Figure 10, the IO module sends IO WriteA1 and IO WriteA2 to the IO proxy module. Taking the example that both IO WriteA1 and IO WriteA2 have written the entire cache line, although IO WriteA2 arrives at the IO proxy module later than IO WriteA1 in order, because the acquisition of exclusive rights to the cache line can be done out of order, IO WriteA2 may complete the acquisition of exclusive rights to the cache line first. For example, in the example in Figure 9, although the LdToXND(A1) request corresponding to IO WriteA1 is sent before the LdToXND(A2) request corresponding to IO WriteA2, because IO WriteA1 is for the second memory and IO WriteA2 is for the first memory, the delay and out-of-order processing mechanism of the transmission network on the transmission path between the first memory proxy module and the second memory proxy module may cause IO WriteA2 to complete the acquisition of exclusive rights to the cache line earlier than IO WriteA1. That is, the TgtRsp(A2) information is returned to the IO proxy module earlier than the TgtRsp(A1) information. Correspondingly, the IO proxy module sends the SrcRsp(A2) information earlier than the SrcRsp(A1) information.

[0285] Once the IO proxy module obtains exclusive access to the cache lines of IO WriteA1 and IO WriteA2, it must issue the Evict Data Full (A1) request for IO WriteA1 and the Evict Data Full (A2) request for IO WriteA2 in sequence, i.e., the Evict Data Full (A1) request is issued first, and the Evict Data Full (A2) request is issued later. In other words, Victim write operations must strictly adhere to the order to ensure the global consistency of written data and flags. Although the global visibility of IO WriteA1 and IO WriteA2 may be out of order due to the transmission path, the Evict Data Full (A1) request for IO WriteA1 and the Evict Data Full (A2) request for IO WriteA2 must be issued in order.

[0286] Due to transmission path delays, the Evict Data Full (A2) request is executed first, thus achieving global visibility earlier. This means the data written by the Evict Data Full (A2) request is visible before the data written by the Evict Data Full (A1) request. At this point, other Master agent modules may detect that the Flag for IO WriteA2 has been updated and attempt to read the associated data from IO WriteA1. Consequently, other Master agent modules initiate LdDataE (A1) requests to access the cached line written by IO WriteA1. The second memory agent module can then send a corresponding query (A1) request to the IO agent module. Since the IO agent module has already issued the Evict Data Full (A1) request, it will include the complete write data of the cached line written by IO WriteA1 in the corresponding query response information, i.e., the query RspToTgt_Data information. After the complete write data of the cached line written by IO WriteA1 is returned to the second memory agent module via the query response, the IO agent module no longer needs to execute the Evict Data Full (A2) request. The Full(A1) request initiates the scheduled Victim write operation. After receiving the TgtRsp(A1) information from the second memory proxy module, the IO proxy module can send a SrcRsp(A1) message with a Cancel flag, i.e., the SrcRsp_Cancel(A1) message, to the second memory proxy module to cancel the Victim write operation of the Evict Data Full(A1) request. This avoids duplicate writes, optimizes the bandwidth of the computer system, and ensures that the complete write data of the cache line written by IO WriteA1 is correctly obtained, thus guaranteeing global consistency.

[0287] This disclosure introduces a cache consistency protocol at the protocol layer of the IO proxy module and implements ordered processing of IO write requests through a corresponding write request handling scheme. This shifts the order control of data writing from the transport layer to the protocol layer of the IO proxy module, reducing the requirements for order-preserving design in the transmission network. This frees the transmission network of multi-core processors and other computer systems from the strict order control task, thereby releasing the design constraints of the computer system's transmission network and allowing for greater flexibility in its design, supporting more diverse transmission schemes. Therefore, this disclosure can improve the performance of the transmission network while ensuring data consistency in the computer system.

[0288] In a further optional implementation, this disclosure also provides an IO proxy module, which connects the corresponding IO module to the transmission network of the computer system. In this disclosure, the protocol layer of the IO proxy module is equipped with a cache coherence protocol to manage the IO write requests of the corresponding IO module using cache lines based on the cache coherence protocol; wherein, the IO proxy module is used for:

[0289] Get the IO write requests from the IO module;

[0290] Determine the cache line coverage integrity corresponding to the cache line write operation of the IO write request;

[0291] Based on the cache line coverage integrity of the cache line write operation, an exclusive permission request for the cache line corresponding to the cache line write operation is issued to obtain at least the exclusive permission for the cache line.

[0292] When the order of the IO write requests arrives, if the exclusive access to the cache line corresponding to the cache line write operation of the IO write request has been acquired, then based on the complete write data corresponding to the cache line, a complete write data request corresponding to the cache line write operation is issued; the complete write data request is used to request the writing of the complete write data in the cache line, and the complete write data includes at least the write data of the cache line write operation.

[0293] The IO proxy module can be configured to execute the method steps performed by the IO proxy module in the write request processing method provided in the embodiments of this disclosure. The relevant content can be referred to the previous description and will not be elaborated here.

[0294] In a further optional implementation, this disclosure also provides a Slave proxy module, which connects the corresponding Slave module to the transmission network of the computer system to manage access requests for the Slave module; wherein, the Slave proxy module is used for:

[0295] Obtain the exclusive permission request sent by the IO proxy module. The exclusive permission request is at least used to request exclusive permission for a cache line, and the exclusive permission request corresponds to the cache line overwrite integrity of the cache line write operation corresponding to the cache line.

[0296] Feedback the exclusive permission response information corresponding to the exclusive permission request to the IO proxy module;

[0297] Obtain the complete write data request corresponding to the cache line write operation sent by the IO proxy module. The complete write data request is used to request that the complete write data corresponding to the cache line be written in the cache line. The complete write data includes at least the write data of the cache line write operation.

[0298] The corresponding Slave module is scheduled to execute the complete write data request and the response information of the complete write data request is fed back to the IO proxy module.

[0299] The Slave proxy module can be configured to execute the method steps performed by the Slave proxy module in the write request processing method provided in the embodiments of this disclosure. The relevant content can be referred to the previous description and will not be elaborated here.

[0300] In a further optional implementation, this disclosure also provides a computer system including multiple functional modules, wherein the functional module that initiates access requests is a Master module, and the functional module that responds to access requests is a Slave module; for example, the architecture of the computer system can be illustrated in Figure 1; wherein, the Master module includes an IO module, and the IO module is connected to the transmission network of the computer system through a corresponding IO proxy module; the Slave module is connected to the transmission network through a corresponding Slave proxy module; the IO proxy module is the IO proxy module provided in the embodiments of this disclosure described above, and the Slave proxy module is the Slave proxy module provided in the embodiments of this disclosure described above.

[0301] The foregoing describes multiple embodiment schemes provided by the present disclosure. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and made public by the present disclosure.

[0302] While the embodiments disclosed herein are as described above, this disclosure is not limited thereto. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A write request processing method, applied to an IO proxy module, wherein the IO proxy module manages IO write requests for the corresponding IO module using cache lines based on a cache consistency protocol; the method includes: Get the IO write requests from the IO module; Determine the cache line coverage integrity corresponding to the cache line write operation of the IO write request; Based on the cache line coverage integrity of the cache line write operation, an exclusive permission request for the cache line corresponding to the cache line write operation is issued to obtain at least the exclusive permission for the cache line. When the order of the IO write requests arrives, if the exclusive permission of the cache line corresponding to the cache line write operation of the IO write request has been obtained, then based on the complete write data corresponding to the cache line, a complete write data request corresponding to the cache line write operation is issued. The complete write data request is used to request that the complete write data be written to the cache line, and the complete write data includes at least the write data of the cache line write operation.

2. The method according to claim 1, wherein, The cache line write operation is divided into a complete cache line write operation and a partial cache line write operation. The cache line coverage integrity of a complete cache line write operation is to completely cover the cache line, while the cache line coverage integrity of a partial cache line write operation is to partially cover the cache line.

3. The method according to claim 2, wherein, Based on the cache line coverage integrity of the cache line write operation, issuing an exclusive permission request for the cache line corresponding to the cache line write operation, in order to acquire at least exclusive permission for the cache line, includes: If the cache line write operation is a complete cache line write operation, a first exclusive permission request corresponding to the cache line is issued. The first exclusive permission request is used to request exclusive permission for the cache line and does not read the existing data of the cache line. The complete write data corresponding to the cache line is the write data of the cache line write operation.

4. The method according to claim 2, wherein, Based on the cache line coverage integrity of the cache line write operation, issuing an exclusive permission request for the cache line corresponding to the cache line write operation, in order to acquire at least exclusive permission for the cache line, includes: If the cache line write operation is a partial cache line write operation, a second exclusive permission request corresponding to the cache line is issued. The second exclusive permission request is used to request exclusive permission for the cache line and to read the existing data of the cache line.

5. The method according to claim 4, wherein, After reading the existing data in the cached line, the method further includes: The write data of the cache line write operation is merged with the existing data of the cache line to obtain the merged data of the cache line, which serves as the complete write data corresponding to the cache line.

6. The method according to claim 5, wherein, The step of merging the write data of the cache line write operation with the existing data of the cache line to obtain the merged data of the cache line, which serves as the complete write data corresponding to the cache line, includes: Based on the byte enable information of the cache line write operation, the write data of the cache line write operation is written into a portion of the bytes of the cache line to overwrite the existing data corresponding to the portion of the bytes, forming the merged data of the cache line, which serves as the complete write data corresponding to the cache line; wherein, the byte enable information indicates the portion of the bytes; The method further includes: Save the byte enable information.

7. The method according to any one of claims 2-6, wherein, Determining the cache line coverage integrity corresponding to the cache line write operation of the IO write request includes: If the size of the write data corresponding to the write data in the cache line write operation is equal to the size of the cache line, then the cache line write operation is determined to be a complete cache line write operation. If the size of the write data corresponding to the write data in the cache line write operation is less than the cache line size, then the cache line write operation is determined to be a partial cache line write operation.

8. The method according to claim 7, wherein, The IO write request has one or more cache line write operations, and the cache line write operations of the IO write request are determined based on the write address and write data size of the IO write request.

9. The method according to claim 8, wherein, When the write address of the IO write request is aligned to a cache line boundary, the cache line write operation of the IO write request includes any of the following: If the size of the data written in the IO write request is equal to the size of the cache line, then the IO write request has a complete cache line write operation; If the size of the data to be written in the IO write request is less than the size of the cache line, then the IO write request has a partial cache line write operation. If the write data size of the IO write request is greater than the cache line size, and the write data size of the IO write request is an integer multiple of the cache line size, then the IO write request has multiple complete cache line write operations corresponding to the number of integer multiples. If the write data size of the IO write request is greater than the cache line size, and the write data size of the IO write request is not an integer multiple of the cache line size, then the IO write request has at least one full cache line write operation and one partial cache line write operation.

10. The method according to any one of claims 1-9, further comprising: After obtaining exclusive access to the cache line corresponding to the cache line write operation, mark the corresponding permission tag information for the IO write request; The method further includes: When the IO write request arrives in the order it was issued, check whether the IO write request is marked with permission tag information; If the IO write request is marked with permission information, then proceed to the step of issuing a complete write data request corresponding to the cache line write operation based on the complete write data corresponding to the cache line; If the IO write request is not marked with permission information, then wait for the IO write request to acquire the exclusive permission, and then proceed to the step of issuing a complete write data request corresponding to the cache line write operation based on the complete write data corresponding to the cache line.

11. The method according to any one of claims 1-10, wherein, The order in which the IO write requests are issued corresponds to the order in which the IO write requests are acquired. For multiple IO write requests that do not conflict with each other, the multiple IO write requests support acquiring the exclusive access in an out-of-order manner. The method further includes: The request information of the acquired IO write requests is stored in the request queue in order; wherein, the storage order of the IO write requests in the request queue is the order in which they were issued, and the request queue is also marked with permission tag information of the IO write requests, the permission tag information of the IO write requests indicating that the exclusive permission of the cache line corresponding to the cache line write operation of the IO write request has been acquired.

12. The method according to any one of claims 1-11, further comprising: After obtaining exclusive access to the cache line, before issuing a complete write data request corresponding to the write operation of the cache line, if a query request for the cache line is obtained, a corresponding query response is issued to release the exclusive access to the cache line. And, the step of returning to the cache line coverage integrity based on the cache line write operation, issuing an exclusive permission request for the cache line corresponding to the cache line write operation, so as to at least obtain exclusive permission for the cache line.

13. The method of claim 12, further comprising: When a query request for a cache line is received, the status of the cache line corresponding to the query request is set to invalid, and the address matching mechanism is used to check whether there are any corresponding IO write requests that have not yet been completed. If there are any corresponding IO write requests that have not yet been completed, then set the status of the corresponding IO write request to the interrupted state; In addition, after regaining exclusive access to the cache line, the cache line is restored to an exclusive state, and the corresponding IO write request is resumed for further processing according to the address matching mechanism. The address matching mechanism is a request buffer for IO write requests in the IO proxy module, which has the same address matching logic as the memory proxy queue of the memory proxy module.

14. The method according to any one of claims 1-13, further comprising: After issuing the complete write data request corresponding to the cache line write operation, and before receiving the corresponding response information, if a query request for the cache line is obtained, a corresponding query response is issued to release the exclusive rights of the cache line, and the query response carries the complete write data of the cache line. Upon receiving a response message in response to the query, a response message carrying a clear flag is issued to indicate the clearing of the cache line write operation corresponding to the complete write data request.

15. The method according to any one of claims 1-14, further comprising: If there are multiple I / O write requests with address conflicts, the subsequent I / O write requests are marked as blocked in the order in which they are acquired, until the preceding I / O write requests are completed, so that the multiple I / O write requests with address conflicts can be processed in order; where the multiple I / O write requests with address conflicts are multiple I / O write requests with the same cache line address.

16. The method according to any one of claims 1-15, further comprising: When the order of the IO write requests arrives, if the exclusive permission for the cache line corresponding to the cache line write operation of the IO write request is discarded or not acquired, the subsequent IO write requests associated with the IO write request will be blocked until the exclusive permission for the cache line corresponding to the cache line write operation of the IO write request is successfully acquired and the complete write data request is issued.

17. A write request processing method, applied to a Slave proxy module, the method comprising: Obtain the exclusive permission request sent by the IO proxy module. The exclusive permission request is at least used to request exclusive permission for a cache line, and the exclusive permission request corresponds to the cache line overwrite integrity of the cache line write operation corresponding to the cache line. Feedback the exclusive permission response information corresponding to the exclusive permission request to the IO proxy module; Obtain the complete write data request corresponding to the cache line write operation sent by the IO proxy module. The complete write data request is used to request that the complete write data corresponding to the cache line be written in the cache line. The complete write data includes at least the write data of the cache line write operation. The corresponding Slave module is scheduled to execute the complete write data request and the response information of the complete write data request is fed back to the IO proxy module.

18. The method according to claim 17, wherein, The process of obtaining the exclusive permission request sent by the IO proxy module, wherein the exclusive permission request is at least used to request exclusive permission for a cache line, and the exclusive permission request corresponds to the cache line coverage integrity of the cache line write operation corresponding to the cache line, includes: The first exclusive permission request sent by the IO proxy module is obtained. The first exclusive permission request is used to request exclusive permission for the cache line and does not read the existing data of the cache line. The first exclusive permission request corresponds to the cache line write operation being a complete cache line write operation. The step of sending the exclusive permission response information corresponding to the exclusive permission request back to the IO proxy module includes: After granting exclusive access to the cache line to the IO proxy module, the exclusive access response information corresponding to the first exclusive access request is sent back to the IO proxy module to inform the IO proxy module that it has successfully obtained exclusive access to the cache line, and the exclusive access response information does not carry the existing data of the cache line. The complete write data corresponding to the cache line is the write data of the cache line write operation.

19. The method of claim 17, wherein, The process of obtaining the exclusive permission request sent by the IO proxy module, wherein the exclusive permission request is at least used to request exclusive permission for a cache line, and the exclusive permission request corresponds to the cache line coverage integrity of the cache line write operation corresponding to the cache line, includes: The second exclusive permission request sent by the IO proxy module is obtained. The second exclusive permission request is used to request exclusive permission for the cache line and read the existing data of the cache line. The second exclusive permission request corresponds to the cache line write operation being a partial cache line write operation. The step of sending the exclusive permission response information corresponding to the exclusive permission request back to the IO proxy module includes: After granting exclusive access to the cache line to the IO proxy module, the exclusive access response information corresponding to the second exclusive access request is fed back to the IO proxy module, and the exclusive access response information carries the existing data of the cache line. The complete write data corresponding to the cache line is the merged data after merging the write data of the cache line write operation with the existing data of the cache line.

20. The method according to any one of claims 17-19, further comprising: After sending the exclusive permission response information corresponding to the exclusive permission request back to the IO proxy module, and before obtaining the complete write data request corresponding to the cache line write operation sent by the IO proxy module, if an access request for the cache line from other Master proxy modules is obtained, a query request for the cache line is sent to the IO proxy module. Obtain the corresponding query response from the IO proxy module. If the IO proxy module has not yet issued the complete write data request when it receives the query request, the query response indicates that the exclusive access of the cache line has been released and does not carry data. Process the access requests from the other Master proxy modules; In addition, the system receives the exclusive permission request for the cache line corresponding to the cache line write operation resent by the IO proxy module, re-grants the exclusive permission for the cache line to the IO proxy module, and re-feeds the exclusive permission response information to the IO proxy module.

21. The method according to any one of claims 17-20, further comprising: After the IO proxy module issues the complete write data request corresponding to the cache line write operation, and before obtaining the complete write data request corresponding to the cache line write operation sent by the IO proxy module, if an access request for the cache line from another Master proxy module is obtained, a query request for the cache line is sent to the IO proxy module. Obtain the corresponding query response from the IO proxy module. If the IO proxy module has already issued the complete write data request when it receives the query request, the query response indicates that the exclusive permission of the cache line has been released and carries the complete write data corresponding to the cache line. Based on the complete write data corresponding to the cache line, process the access requests of the other Master proxy modules; In addition, after sending the response information for the query response back to the IO proxy module, the system receives the response information carrying the clear flag sent by the IO proxy module to clear the cache line write operation corresponding to the complete write data request.

22. An IO proxy module, wherein, The IO proxy module connects the corresponding IO module to the computer system's transmission network. The protocol layer of the IO proxy module includes a cache consistency protocol to manage IO write requests for the corresponding IO module using cache lines. The IO proxy module is configured as follows: Get the IO write requests from the IO module; Determine the cache line coverage integrity corresponding to the cache line write operation of the IO write request; Based on the cache line coverage integrity of the cache line write operation, an exclusive permission request for the cache line corresponding to the cache line write operation is issued to obtain at least the exclusive permission for the cache line. When the order of the IO write requests arrives, if the exclusive access to the cache line corresponding to the cache line write operation of the IO write request has been acquired, then based on the complete write data corresponding to the cache line, a complete write data request corresponding to the cache line write operation is issued; the complete write data request is used to request the writing of the complete write data in the cache line, and the complete write data includes at least the write data of the cache line write operation.

23. The IO proxy module according to claim 22, wherein, The IO proxy module is used to issue an exclusive permission request for the cache line corresponding to the cache line write operation based on the cache line coverage integrity of the cache line write operation, so as to acquire at least the exclusive permission for the cache line, including: If the cache line write operation is a complete cache line write operation, a first exclusive permission request corresponding to the cache line is issued. The first exclusive permission request is used to request exclusive permission for the cache line and does not read the existing data of the cache line. If the cache line write operation is a partial cache line write operation, a second exclusive permission request corresponding to the cache line is issued. The second exclusive permission request is used to request exclusive permission for the cache line and read the existing data of the cache line. The cache line write operation is divided into a complete cache line write operation and a partial cache line write operation. The cache line coverage integrity of a complete cache line write operation is to completely cover the cache line, while the cache line coverage integrity of a partial cache line write operation is to partially cover the cache line.

24. The IO proxy module according to claim 22 or 23, wherein the IO proxy module is further configured to: After obtaining exclusive access to the cache line, before issuing a complete write data request corresponding to the write operation of the cache line, if a query request for the cache line is obtained, a corresponding query response is issued to release the exclusive access to the cache line. And, the step of returning to the cache line coverage integrity based on the cache line write operation, issuing an exclusive permission request for the cache line corresponding to the cache line write operation, so as to at least obtain exclusive permission for the cache line; And / or, After issuing the complete write data request corresponding to the cache line write operation, and before receiving the corresponding response information, if a query request for the cache line is obtained, a corresponding query response is issued to release the exclusive rights of the cache line, and the query response carries the complete write data of the cache line. In addition, upon receiving a response message for the query response, a response message carrying a clear flag is issued to indicate the clearing of the cache line write operation corresponding to the complete write data request.

25. A slave agent module, wherein, The Slave proxy module connects the corresponding Slave module to the computer system's transmission network to manage access requests for the Slave module; wherein, the Slave proxy module is configured as follows: Obtain the exclusive permission request sent by the IO proxy module. The exclusive permission request is at least used to request exclusive permission for a cache line, and the exclusive permission request corresponds to the cache line overwrite integrity of the cache line write operation corresponding to the cache line. Feedback the exclusive permission response information corresponding to the exclusive permission request to the IO proxy module; Obtain the complete write data request corresponding to the cache line write operation sent by the IO proxy module. The complete write data request is used to request that the complete write data corresponding to the cache line be written in the cache line. The complete write data includes at least the write data of the cache line write operation. The corresponding Slave module is scheduled to execute the complete write data request and the response information of the complete write data request is fed back to the IO proxy module.

26. The Slave proxy module according to claim 25, wherein the Slave proxy module is further configured to: After sending the exclusive permission response information corresponding to the exclusive permission request back to the IO proxy module, and before obtaining the complete write data request corresponding to the cache line write operation sent by the IO proxy module, if an access request for the cache line from other Master proxy modules is obtained, a query request for the cache line is sent to the IO proxy module. Obtain the corresponding query response from the IO proxy module, wherein, If the IO proxy module receives the query request but has not yet issued the complete write data request, the query response indicates that the exclusive access to the cache line has been released and does not carry data. Process the access requests from the other Master proxy modules; In addition, the system receives the exclusive permission request for the cache line corresponding to the cache line write operation resent by the IO proxy module, re-grants the exclusive permission for the cache line to the IO proxy module, and re-feeds the exclusive permission response information to the IO proxy module.

27. The Slave proxy module according to claim 25 or 26, wherein the Slave proxy module is further configured to: After the IO proxy module issues the complete write data request corresponding to the cache line write operation, and before obtaining the complete write data request corresponding to the cache line write operation sent by the IO proxy module, if an access request for the cache line from another Master proxy module is obtained, a query request for the cache line is sent to the IO proxy module. Obtain the corresponding query response from the IO proxy module, wherein, If the IO proxy module has already issued the complete write data request when it receives the query request, the query response indicates that the exclusive permission of the cache line has been released and carries the complete write data corresponding to the cache line. Based on the complete write data corresponding to the cache line, process the access requests of the other Master proxy modules; In addition, after sending the response information for the query response back to the IO proxy module, the system receives the response information carrying the clear flag sent by the IO proxy module to clear the cache line write operation corresponding to the complete write data request.

28. A computer system comprising multiple functional modules, wherein the functional module initiating access requests is a Master module, and the functional module responding to access requests is a Slave module; the Master module includes an I / O module, the I / O module being connected to the computer system's transmission network through a corresponding I / O proxy module; the Slave module being connected to the transmission network through a corresponding Slave proxy module; wherein... The IO proxy module is the IO proxy module as described in any one of claims 22-24, and the Slave proxy module is the Slave proxy module as described in any one of claims 25-27.

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