Gate drive circuit and unit thereof, and display device

Abstract

A gate drive circuit, a gate drive circuit unit, and a display device. A second NMOS transistor (T2) of the gate drive circuit unit is connected to a second negative voltage signal end (VEE2) and a signal output end (Gout), and is used for inputting a second negative voltage signal from the second negative voltage signal end (VEE2) into the signal output end (Gout) under the control of a positive voltage signal provided by a first node (n1). A fourth NMOS transistor (T4) is connected to a third clock signal end (CLK3) and the signal output end (Gout), and is used for inputting a level signal provided by the third clock signal end (CLK3) into the signal output end (Gout) under the control of a high-level potential provided by a third node (n3). The gate drive circuit unit can provide level signals of different potentials, thereby realizing a display effect of the display device.

Description

Gate driving circuit and its unit and display device

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 2024116397185, filed on November 15, 2024, entitled “Gate driving circuit and unit thereof and display device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of display technology, and more particularly to a gate driving circuit, its unit, and a display device. Background Technology

[0004] Compared to traditional liquid crystal display devices, organic light-emitting diode (OLED) display devices have advantages such as faster response speed, better color purity and brightness, higher contrast, and wider viewing angle, and therefore have gradually gained increasing attention from display technology developers.

[0005] Among them, the Gate Driver on Array (GOA) technology integrates the gate switching circuit of the thin film transistor (TFT) on the array substrate of the display device to form a gate driver for the display device.

[0006] Figure 1 shows a gate driving circuit of a related technology. The gate driving circuit is usually composed of multiple cascaded gate driving circuit units, and each gate driving circuit unit is connected to a scan gate line. At the same time, in two cascaded gate driving circuit units, the output signal of the previous gate driving circuit unit serves as the input signal of the next gate driving circuit unit.

[0007] During the operation of an OLED display device, the input signal is converted into an on / off driving signal by the gate driving circuit unit and then applied sequentially to the scanning gate lines of each row of pixels in the OLED display device to select each row of pixels and achieve display refresh.

[0008] As shown in Figure 1, each stage of the gate drive circuit passes down step by step, and the drive signal output by each stage is passed to the AA area in the current row. Therefore, both high and low voltage signals will be passed to the AA area.

[0009] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0010] In view of the problems in the prior art, the purpose of the present invention is to provide a gate driving circuit and its unit and a display device, which overcomes the difficulties of the prior art and can provide a good display effect.

[0011] The first aspect of this disclosure provides a gate driving circuit unit, which includes:

[0012] The first switch module connects the positive voltage signal terminal and the fifth node, and is used to write the positive voltage signal provided by the positive voltage signal terminal to the fifth node under the control of the second clock signal terminal.

[0013] The second switch module is connected to the positive voltage signal terminal and the fourth node. Under the control of the first clock signal terminal, it writes the positive voltage signal provided by the positive voltage signal terminal to the fourth node, wherein the clock signals provided by the first clock signal terminal and the second clock signal terminal have the same period and are out of phase by one line of time.

[0014] A first NMOS transistor and a third capacitor, wherein the first NMOS transistor is connected to the fifth node and the first node, and is used to write the positive voltage signal of the fifth node to the first node under the control of the positive voltage signal provided by the fourth node; the third capacitor is connected to the fifth node and the fourth node, and is used to store the potential of the fourth node and the fifth node.

[0015] The second NMOS transistor and the first capacitor are connected. The second NMOS transistor is connected to the second negative voltage signal terminal and the signal output terminal. Under the control of the positive voltage signal provided by the first node, the second negative voltage signal of the second negative voltage signal terminal is input to the signal output terminal. The first capacitor is connected to the first negative voltage signal terminal and the first node. It is used to store the potential of the first node.

[0016] The third NMOS transistor is connected to the second clock signal terminal and the first node, and is used to write the low potential provided by the second clock signal terminal to the first node under the control of the third node.

[0017] The third switch module is connected to the signal input terminal and the third node. Under the control of the second clock signal terminal, it is used to write a high-level potential provided by the signal input terminal to the third node and to block the connection between the third node and the signal input terminal.

[0018] A fourth NMOS transistor and a second capacitor are provided. The fourth NMOS transistor is connected to the third clock signal terminal and the signal output terminal. Under the control of the high-level potential provided by the third node, it is used to input the level signal provided by the third clock signal terminal to the signal output terminal. The second capacitor is connected to the signal output terminal and the third node. It is used to store the high-level potential provided by the signal input terminal and to maintain the high-level potential of the third node when the third switch module blocks the connection between the third node and the signal input terminal. It controls the third NMOS transistor to write the low-level potential provided by the second clock signal terminal to the first node, triggering the second NMOS transistor to turn off. The clock signals provided by the third clock signal terminal and the first clock signal terminal have the same period and opposite voltage polarities.

[0019] A reset module is connected to the first negative voltage signal terminal and the second node, and is used to provide the first negative voltage signal to the second node under the control of the first clock signal terminal and the first node. The second node is located between the third switch module and the third node.

[0020] In some embodiments, the first switch module includes:

[0021] The fifth NMOS transistor has its gate connected to the second clock signal terminal, its drain connected to the positive voltage signal terminal, and its source connected to the fifth node.

[0022] In some embodiments, the second switch module includes:

[0023] The sixth NMOS transistor has its gate connected to the first clock signal terminal, its drain connected to the positive voltage signal terminal, and its source connected to the fourth node.

[0024] In some embodiments, the gate drive circuit unit further includes:

[0025] The seventh NMOS transistor has its gate connected to the signal input terminal, its drain connected to the first clock signal terminal, and its source connected to the fourth node.

[0026] The seventh NMOS transistor is used to write a low-level signal provided by the first clock signal terminal to the fourth node under the control of the high-level potential provided at the signal input terminal, so that the fourth node is reset after a delay.

[0027] In some embodiments, the third switch module includes:

[0028] The eighth NMOS transistor has its gate connected to the second clock signal terminal, its drain connected to the signal input terminal, and its source connected to the second node.

[0029] In some embodiments, the reset module includes:

[0030] The ninth NMOS transistor has its gate connected to the first clock signal terminal, its drain connected to the first negative voltage signal terminal, and its source connected to the sixth node.

[0031] The tenth NMOS transistor has its gate connected to the first node, its drain connected to the sixth node, and its source connected to the second node.

[0032] The gate drive circuit unit further includes:

[0033] The eleventh NMOS transistor has its gate connected to the positive voltage signal terminal, its drain connected to the second node, and its source connected to the third node. The eleventh NMOS transistor is used to remain on under the control of the positive voltage signal terminal, and to write the high-level potential provided by the signal input terminal and the first negative voltage signal to the third node through the second node with a delay.

[0034] In some embodiments, the second negative voltage signal is higher than the first negative voltage signal, the high-level voltages connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are all equal to the positive voltage signal, the low-level voltages connected to the signal input terminal, the first clock signal terminal, and the second clock signal terminal are all equal to the second negative voltage signal, and the low-level voltage of the third clock signal terminal is equal to the positive voltage signal.

[0035] A second aspect of this disclosure provides a gate driving circuit that includes a plurality of gate driving circuit units according to any of the above embodiments.

[0036] Multiple gate drive circuit units are electrically coupled in a cascaded manner, wherein the signal input terminal of the first-stage gate drive circuit unit is coupled to the start pulse signal, and the signal output terminal of each of the remaining gate drive circuit units, except for the last-stage gate drive circuit unit, is coupled to the signal input terminal of the next-stage gate drive circuit unit.

[0037] In some embodiments, in the cascade chain from the first-stage gate driving circuit unit to the last-stage gate driving circuit unit, the first clock signal terminal and the second clock signal terminal in each of the gate driving circuit units are alternately connected to the first clock signal line and the second clock signal line, and the third clock signal terminal in each of the gate driving circuit units is alternately connected to the third clock signal line and the fourth clock signal line; the clock signals of the third clock signal line and the fourth clock signal line have the same period and opposite voltage polarities.

[0038] A third aspect of this disclosure provides a display device that includes a gate driving circuit according to any of the above embodiments.

[0039] Compared to related technologies, the gate drive circuit unit of this embodiment adds a clock signal terminal and a negative voltage signal terminal. Using the gate drive circuit unit of this embodiment, different potential level signals can be provided to achieve the display effect of the display device.

[0040] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0041] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0042] Figure 1 shows a structural diagram of a gate driver that includes cascaded gate drive circuitry in the related art.

[0043] Figure 2 is a circuit structure diagram of the gate drive circuit unit provided in an embodiment of this disclosure.

[0044] Figure 3 is the equivalent circuit diagram of the gate drive circuit unit shown in Figure 2.

[0045] Figure 4 shows one of the timing waveforms corresponding to the gate drive circuit unit shown in Figure 3.

[0046] Figure 5 is a schematic diagram of the working state of the gate drive circuit unit shown in Figure 3 corresponding to the first time period in Figure 4.

[0047] Figure 6 shows the second timing waveform diagram corresponding to the gate drive circuit unit shown in Figure 3.

[0048] Figure 7 is a schematic diagram of the working state of the gate drive circuit unit shown in Figure 3 corresponding to the second time period in Figure 6.

[0049] Figure 8 shows the third timing waveform diagram corresponding to the gate drive circuit unit shown in Figure 3.

[0050] Figure 9 is a schematic diagram of the working state of the gate drive circuit unit shown in Figure 3 corresponding to the third time period in Figure 8.

[0051] Figure 10 shows the fourth timing waveform diagram corresponding to the gate drive circuit unit shown in Figure 3.

[0052] Figure 11 is a schematic diagram of the working state of the gate drive circuit unit shown in Figure 3 corresponding to the fourth time period in Figure 10.

[0053] Figure 12 shows the fifth timing waveform corresponding to the gate drive circuit unit shown in Figure 3.

[0054] Figure 13 is a schematic diagram of the working state of the gate drive circuit unit shown in Figure 3 corresponding to the fifth time period in Figure 12.

[0055] Figure 14 shows the sixth timing waveform diagram corresponding to the gate drive circuit unit shown in Figure 3.

[0056] Figure 15 is a schematic diagram of the working state of the gate drive circuit unit shown in Figure 3 corresponding to the sixth time period in Figure 14.

[0057] Figure 16 shows a flowchart of the control method for the gate drive circuit unit shown in Figure 2.

[0058] Figure 17 shows another equivalent circuit diagram of the gate drive circuit unit shown in Figure 2.

[0059] Figure 18 shows another equivalent circuit diagram of the gate drive circuit unit shown in Figure 2.

[0060] Figure 19 shows the circuit structure diagram of the gate drive circuit using the gate drive circuit unit shown in Figure 2. Detailed Implementation

[0061] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0062] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0063] Furthermore, the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to define the order of functions performed by these devices, modules or units or their interdependencies.

[0064] As shown in Figure 2, this embodiment of the present disclosure provides a gate driving circuit unit, which includes:

[0065] The first switch module S1 is connected to the positive voltage signal terminal VDD and the fifth node n5, and is used to write the positive voltage signal provided by the positive voltage signal terminal VDD to the fifth node n5 under the control of the second clock signal terminal CLK2.

[0066] The second switch module S2 is connected to the positive voltage signal terminal VDD and the fourth node n4. Under the control of the first clock signal terminal CLK1, it writes the positive voltage signal provided by the positive voltage signal terminal VDD to the fourth node n4, wherein the clock signals provided by the first clock signal terminal CLK1 and the second clock signal terminal CLK2 have the same period and are out of phase by one line of time.

[0067] A first NMOS transistor T1 and a third capacitor C3 are connected. The first NMOS transistor T1 is connected to the fifth node n5 and the first node n1 and is used to write the positive voltage signal of the fifth node n5 to the first node n1 under the control of the positive voltage signal provided by the fourth node n4. The third capacitor C3 is connected to the fifth node n5 and the fourth node n4 and is used to store the potential of the fourth node n4 and the fifth node n5.

[0068] The second NMOS transistor T2 and the first capacitor are connected. The second NMOS transistor T2 is connected to the second negative voltage signal terminal VEE2 and the signal output terminal Gout. Under the control of the positive voltage signal provided by the first node n1, the second negative voltage signal of the second negative voltage signal terminal VEE2 is input to the signal output terminal Gout. The first capacitor C1 is connected to the first negative voltage signal terminal VEE1 and the first node n1. It is used to store the potential of the first node n1.

[0069] The third NMOS transistor T3 is connected to the second clock signal terminal CLK2 and the first node n1, and is used to write the low potential provided by the second clock signal terminal CLK2 to the first node n1 under the control of the third node n3.

[0070] The third switch module S3 is connected to the signal input terminal STV / in and the third node n3. Under the control of the second clock signal terminal CLK2, it is used to write the high-level potential provided by the signal input terminal STV / in to the third node n3, and to block the connection between the third node n3 and the signal input terminal STV / in.

[0071] The fourth NMOS transistor T4 is connected to the third clock signal terminal CLK3 and the signal output terminal Gout. Under the control of the high-level potential provided by the third node n3, it inputs the level signal provided by the third clock signal terminal CLK3 to the signal output terminal Gout. The second capacitor C2 is connected to the signal output terminal Gout and the third node n3. It stores the high-level potential provided by the signal input terminal STV / in and maintains the high-level potential of the third node n3 when the third switch module S3 blocks the connection between the third node n3 and the signal input terminal STV / in. It controls the third NMOS transistor T3 to write the low-level potential provided by the second clock signal terminal CLK2 to the first node n1, triggering the second NMOS transistor T2 to turn off. The clock signals provided by the third clock signal terminal CLK3 and the first clock signal terminal CLK1 have the same period and opposite voltage polarities.

[0072] The reset module Y1 is connected to the first negative voltage signal terminal VEE1 and the second node n2. It is used to provide the first negative voltage signal to the second node n2 under the control of the first clock signal terminal CLK1 and the first node n1. The second node n2 is located between the third switch module S3 and the third node n3.

[0073] The working principle of the gate driving unit in this embodiment is as follows:

[0074] During the power-on phase, the first switch module S1 and the second switch module S2 are controlled to be turned on by the first clock signal terminal CLK1 and the second clock signal terminal CLK2, so that the positive voltage signal provided by the positive voltage signal terminal VDD is written into the first node n1, n1 is pulled high, triggering the second NMOS transistor T2 to be turned on, and the signal output terminal Gout outputs the low-level signal provided by the second low-voltage signal terminal VEE2.

[0075] During the display phase, the first node n1 remains at a high potential, the signal output terminal Gout outputs a low-level signal, and controls the third switch module S3 to turn on and the signal input terminal STV / in to input a high-level signal. The third node n3 is pulled high, triggering the fourth NMOS transistor T4 to turn on, at which point the signal output terminal Gout outputs a low-level signal. Subsequently, when the third switch module S3 turns off, the high potential stored in the second capacitor C2 triggers the third NMOS transistor T3 to turn on, writing the low potential provided by the second clock signal terminal CLK2 to the first node n1. n1 is pulled low to reset, triggering the second NMOS transistor T2 to turn off, while the fourth NMOS transistor T4 remains on, and the signal output terminal Gout outputs the high-level signal provided by the third clock signal terminal CLK3. After this, the power-on phase is repeated to enter the next cycle of the display phase.

[0076] Compared to related technologies, the gate drive circuit unit of this embodiment adds a clock signal terminal and a negative voltage signal terminal. Using the gate drive circuit unit of this embodiment, different potential level signals can be provided to achieve the display effect of the display device.

[0077] As shown in Figure 3, the first switch module S1 includes:

[0078] The fifth NMOS transistor T5 has its gate connected to the second clock signal terminal CLK2, its drain connected to the positive voltage signal terminal VDD, and its source connected to the fifth node n5.

[0079] In this embodiment, when the second clock signal terminal CLK2 provides a high potential, the fifth NMOS transistor T5 is triggered to turn on, and the positive voltage signal provided by the positive voltage signal terminal VDD is written into the fifth node n5. The third capacitor C3 stores the high potential corresponding to the positive voltage signal.

[0080] In this embodiment of the disclosure, the second switch module S2 includes:

[0081] The sixth NMOS transistor T6 has its gate connected to the first clock signal terminal CLK1, its drain connected to the positive voltage signal terminal VDD, and its source connected to the fourth node n4.

[0082] In this embodiment, when CLK1 inputs a high potential, it triggers T6 to conduct, and the fourth node n4 is written with a high potential provided by the positive voltage signal terminal VDD, triggering the first NMOS transistor T1 to conduct to connect the fifth node n5 and the first node n1. At the same time, the third capacitor C3 stores the high potential.

[0083] In one embodiment, the gate drive circuit unit further includes:

[0084] The seventh NMOS transistor T7 has its gate connected to the signal input terminal STV / in, its drain connected to the first clock signal terminal CLK1, and its source connected to the fourth node n4.

[0085] The seventh NMOS transistor T7 is used to write a low-level signal provided by the first clock signal terminal CLK1 to the fourth node n4 under the control of the high-level potential provided by the signal input terminal STV / in, and to perform a delayed reset of the fourth node n4.

[0086] In this embodiment, when STV / in changes from a low potential to a high potential, it triggers the seventh NMOS transistor T7 to turn on. At this time, the first clock signal terminal CLK1 provides a low potential, and the high potential stored in C3 is slowly released until n4 is pulled low to reset.

[0087] In this embodiment of the disclosure, the third switch module S3 includes:

[0088] The eighth NMOS transistor T8 has its gate connected to the second clock signal terminal CLK2, its drain connected to the signal input terminal STV / in, and its source connected to the second node n2.

[0089] In this implementation, STV / in is provided with a high potential, T8 is turned on, n3 is pulled high, T4 is turned on, and Gout outputs the low level provided by the third clock signal terminal CLK3.

[0090] In this embodiment of the disclosure, the reset module Y1 includes:

[0091] The ninth NMOS transistor T9 has its gate connected to the first clock signal terminal CLK1, its drain connected to the first negative voltage signal terminal VEE1, and its source connected to the sixth node n6.

[0092] The tenth NMOS transistor T10 has its gate connected to the first node n1, its drain connected to the sixth node n6, and its source connected to the second node n2.

[0093] In this implementation, when CLK1 provides a high potential and n1 remains at a high potential, T9 and T10 are turned on, n6 and n3 are reset by being written to a low potential provided by VEE1, and T3 and T4 are both turned off.

[0094] In this embodiment of the disclosure, the gate drive circuit unit further includes:

[0095] The eleventh NMOS transistor T11 has its gate connected to the positive voltage signal terminal VDD, its drain connected to the second node n2, and its source connected to the third node n3. The eleventh NMOS transistor T11 is used to remain on under the control of the positive voltage signal terminal VDD and to write the high-level potential of the second node n2 and the first negative voltage signal to the third node n3 with a delay.

[0096] In this implementation, T11 serves to delay the transmission of signals, preventing sudden changes in n3 and ensuring that T4 changes its operating state slowly.

[0097] The working process of the gate drive circuit unit shown in Figure 3 is described below:

[0098] Referring to Figures 4 and 5, in the first time interval t1, STV = 0, CLK1 = 1, CLK2 = 1, CLK3 = 0, where 0 represents a low-level signal and 1 represents a high-level signal;

[0099] When T1, T5, and T6 are turned on, n4, n5, and n1 are pulled high. When T2 is turned on, it inputs a low-level signal provided by VEE1 to Gout. When T8 is turned on, it inputs a low-level potential to n2. At the same time, when T9 and T10 are turned on, VEE1 writes a low potential to n2. When T4 is turned off, C3 stores a high potential.

[0100] As shown in Figures 6 and 7, in the second time period t2, STV = 0, CLK1 = 1, CLK2 = 1, CLK3 = 0;

[0101] T5 is on and T6 is off, C3 keeps n4 at a high potential, T1 is on, n1 is at a high potential, T2 is on, and Gout keeps the output signal low.

[0102] At the same time, STV / in input is at a low level, n2 and n3 remain at a low level, and T4 is cut off.

[0103] T1 and T2 above belong to the power-on phase.

[0104] As shown in Figures 8 and 9, in the third time period t3, STV = 0, CLK1 = 1, CLK2 = 0, and CLK3 = 1.

[0105] When T6 is turned on, n4 remains at a high potential. When T1 is turned on, C3 keeps n5 and n1 at a high potential. When T2 is turned on, Gout outputs a low-level signal.

[0106] T9 and T10 are turned on, n2 is a low-level potential provided by VEE1, and T4 is turned off.

[0107] As shown in Figures 10 and 11, in the fourth time period t4, STV = 1, CLK1 = 0, CLK2 = 1, and CLK3 = 0.

[0108] When T3 is turned on, n2 and n3 are written to a high potential. When T4 is turned on, Gout outputs a low-level signal provided by CLK3.

[0109] When T8 is turned on, n2 and n3 are at high potential. When T2 is turned on, n1 is written to the high potential provided by CLK2. When T2 is turned on, Gout outputs a high-level signal, and C2 stores the high potential of n3.

[0110] At the same time, T7 is turned on, n4 is written with a low level provided by CLK1, and the high level signal stored in C3 is gradually released, eventually making n4 a low potential. During this process, T5 is also turned on under the action of the high potential provided by CLK2, and n5 is a high potential.

[0111] As shown in Figures 12 and 13, in the fifth time period t5, STV = 0, CLK1 = 1, CLK2 = 0, and CLK3 = 1.

[0112] When T8 is off, C2 keeps n3 and n2 at a high potential, T3 and T4 are on, Gout outputs a high-level signal provided by CLK3, and n1 is reset by being written to a low potential provided by CLK2, and T2 is off.

[0113] At the same time, T6 is turned on, n4 is at a high potential and is stored by C3, T1 is turned on, and n1 causes the high potential of n5 stored by C3 to be gradually released.

[0114] As shown in Figures 14 and 15, in the sixth time period t6, STV = 0, CLK1 = 0, CLK2 = 1, and CLK3 = 0.

[0115] When T8 is turned on, n5 is at a high potential, C3 keeps n4 at a high potential, T4 is turned on, n1 becomes at a high potential, T2 is turned on, and Gout outputs a low potential.

[0116] When T8 is turned on, both n2 and n3 become low potential, and T4 is turned off.

[0117] The above t3-t6 is the display phase, and the above display phase is repeated thereafter.

[0118] Specifically, VDD voltage is a positive constant voltage signal, while VEE1 and VEE2 voltages are both negative constant voltage signals. VEE1 voltage is lower than VEE2 voltage, which is characterized by VEE1-VEE2 < Vth_T1 and VEE1-VEE2 < Vth_T.

[0119] The high-level voltages of STV, CLK1, CLK2, and CLK3 signals are all equal to the VDD voltage;

[0120] The low-level voltages of STV, CLK1, and CLK2 signals are all equal to the VEE1 voltage;

[0121] The low-level voltage of the CLK3 signal is equal to the VEE2 voltage.

[0122] Its advantage is that the low-level voltage of node n3 is controlled by STV, and the low-level potential written by n3 is VEE1. When Vth of T1 and T2 is less than 0, VEE1-VEE2<Vth_T1 and Vth_T2, which can ensure that T1 and T2 will not be turned on when they should be turned off.

[0123] Therefore, this disclosure provides a control method for the gate drive circuit unit shown in FIG2, as shown in FIG16, which includes the following steps:

[0124] Step 1610, in the first time period, the first switch module is controlled by the second clock signal terminal to write the positive voltage signal provided by the positive voltage signal terminal to the fifth node, and the second switch module is controlled by the first clock signal terminal to write the positive voltage signal provided by the positive voltage signal terminal to the fourth node, so as to trigger the first NMOS transistor to write the positive voltage signal of the fifth node to the first node, and trigger the second NMOS transistor to input the second negative voltage signal provided by the second negative voltage signal terminal to the signal output terminal, and the signal output terminal outputs a low level signal. At the same time, the third switch module is controlled by the second clock signal terminal to write the low potential signal provided by the signal output terminal to the third node, and the fourth NMOS transistor is turned off.

[0125] Step 1620, Second Time Period: The first switching module is controlled by the second clock signal terminal to write the positive voltage signal provided by the positive voltage signal terminal to the fifth node. Under the action of the positive voltage signal of the fourth node stored in the third capacitor, the second NMOS transistor continues to write the positive voltage signal of the fifth node to the first node, and the signal output terminal continues to output a low-level signal. At the same time, the third switching module is controlled by the second clock signal terminal to write the low-potential signal provided by the signal output terminal to the third node, and the fourth NMOS transistor is turned off.

[0126] Step 1630, in the third time period, the first switch is controlled by the first clock signal terminal to write the positive voltage signal provided by the positive voltage signal terminal to the fourth node, thereby triggering the first NMOS transistor to write the positive voltage signal of the fifth node stored in the third capacitor to the first node. The signal output terminal maintains a low-level output signal. At the same time, under the control of the high potential of the first node and the high potential provided by the first clock signal terminal, the reset module writes the first negative voltage signal provided by the first negative voltage signal terminal to the third node, and the fourth NMOS transistor is turned off.

[0127] Step 1640, fourth time period: The third switch module is controlled by the second clock signal terminal to write a high potential to the second node and the third node, triggering the third NMOS transistor to turn on. The high potential provided by the second clock signal terminal is written to the first node, triggering the second NMOS transistor to turn on. The signal output terminal outputs a low-level signal provided by the second negative voltage signal terminal. At the same time, the high potential of the third node triggers the fourth NMOS transistor to turn on, and the low-level signal provided by the third clock signal terminal is input to the signal output terminal.

[0128] Step 1650, in the fifth time period, the third switch module is controlled by the second clock signal terminal to block the third node from the signal input terminal. The third node maintains the high-level signal of the signal input terminal stored in the second capacitor. The fourth NMOS transistor outputs the high-level potential provided by the third clock signal terminal. At the same time, the high-level signal of the second node triggers the third NMOS transistor to write the low-level potential provided by the second clock signal terminal to the first node to control the second NMOS transistor to turn off. Simultaneously, the second switch module is controlled by the first clock signal terminal to write the positive voltage signal to the fourth node. The third capacitor stores the positive voltage signal of the fourth node.

[0129] Step 1660, in the sixth time period, the third switching module is controlled by the second clock signal terminal to write a low potential provided by the signal input terminal to the third node, triggering the fourth NMOS transistor to turn off. At the same time, the first switching module is controlled to write a high potential to the fifth node. Under the action of the positive voltage signal of the fourth node stored in the third capacitor, the first NMOS transistor writes the high potential of the fifth node to the first node, triggering the second NMOS transistor to input the first negative voltage signal to the signal output terminal, and the signal output terminal outputs a low-level signal.

[0130] In another embodiment of this disclosure, as shown in FIG17, the eleventh NMOS transistor is a dual-gate NMOS transistor, consisting of two NMOS transistors T11a and T11b connected in series and sharing the same gate node. Its advantage is that when one transistor exhibits conductor formation, the other transistor can still function. For example, if the probability of a single transistor failing due to conductor formation is 0.0001, then the probability of both series-connected transistors failing simultaneously is mathematically calculated to be 0.0001² = 10⁻⁸.

[0131] For other transistors, the configuration can be similar to that of the eleventh NMOS transistor, which can be set as a dual-gate transistor.

[0132] In the above embodiment, each transistor is a TFT.

[0133] Referring to another embodiment shown in Figure 18, the second NMOS transistor T2 also has a first back gate structure G1, which is connected to a control electrode. Specifically, the front gate G0 of T2 is connected to the first node n1, and G1 is connected to a control electrode.

[0134] The fourth NMOS transistor T4 also has a second back gate structure G2, which is connected to a control electrode. Specifically, the front gate G3 of T4 is connected to the second node n, and G2 is connected to a control electrode.

[0135] Its advantages are:

[0136] To achieve stronger output capability, T1 and T2 are generally designed with a larger W / L ratio (W is the channel width of the MOS transistor, and L is the channel length of the MOS transistor). This may result in a relatively negative threshold voltage Vth. Setting G1 and G2 can apply a negative back gate voltage to make Vth drift in the positive direction.

[0137] When T1 and T2 are under stress for a long time, Vth may drift positively, making it difficult to output a positive voltage VDD signal. The back gate voltages of G1 and G2 can be set to positive to make Vth of T1 and T2 drift negatively, thus improving the problem of reduced output capability caused by stress.

[0138] This disclosure also provides a gate driving circuit, as shown in FIG19, which includes a plurality of gate driving circuit units of any of the above embodiments.

[0139] Multiple gate drive circuit units are electrically coupled in a cascaded manner, wherein the signal input terminal of the first-stage gate drive circuit unit is coupled to the start pulse signal, and the signal output terminal of each of the remaining gate drive circuit units, except for the last-stage gate drive circuit unit, is coupled to the signal input terminal of the next-stage gate drive circuit unit.

[0140] As shown in Figure 19, this embodiment takes four cascaded gate drive circuit units as an example. The output signal Gout[1] of the first-stage gate drive circuit unit SRC1 is used as the input signal of the second-stage gate drive circuit unit SRC2, the output signal Gout[2] of the second-stage gate drive circuit unit SRC2 is used as the input signal of the third-stage gate drive circuit unit SRC3, and so on. In this way, after a low-level start pulse signal STV is input to the signal input terminal of the first-stage gate drive circuit unit SRC1, a stable output signal can be generated at its first signal output terminal Gout[1]. This output signal of the first signal output terminal Gout[1] is input to the signal input terminal in of the second-stage gate drive circuit unit SRC2. This is repeated to obtain the waveform of the first signal output terminal Gout[1] of the four-stage gate drive circuit unit and the final output of the fourth-stage gate drive circuit unit SRC4, thereby enabling the output of a stable signal.

[0141] As shown in Figure 19, in the cascade chain from the first-stage gate drive circuit unit SRC1 to the last-stage gate drive circuit unit, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 in each gate drive circuit unit are alternately connected to the first clock signal line CKV1 and the second clock signal line CKV2, and the third clock signal terminal CLK3 in each gate drive circuit unit is alternately connected to the third clock signal line CKV3 and the fourth clock signal line CKV4.

[0142] Among them, the clock signals of the third clock signal line CKV3 and the fourth clock signal line CKV4 have the same period but opposite voltage polarities.

[0143] For example, for the first-stage gate drive circuit unit SRC1, its first clock signal terminal CLK1 is connected to the first clock signal line CKV1, its second clock signal terminal CLK2 is connected to the second clock signal line CKV2, and its third clock signal terminal CLK3 is connected to the third clock signal line CKV3; for the second-stage gate drive circuit unit SRC2, its second clock signal terminal CLK2 is connected to the first clock signal line CKV1, its first clock signal terminal CLK1 is connected to the second clock signal line CKV2, and its third clock signal terminal CLK3 is connected to the fourth clock signal line CKV4. The subsequent gate drive circuit units follow the same alternating connection method.

[0144] This embodiment also provides a display device, including the gate driving circuit described above, and sequentially turning on the gate scan lines in the display device line by line using the gate driving circuit units. The display device also includes a drain driving circuit for providing data voltage to the corresponding pixels when the gate scan lines are turned on.

[0145] In one embodiment, the display device can be a variety of electronic display products, specifically including but not limited to at least one of mobile phones, tablet computers, e-book readers, media players, digital cameras, laptops, in-vehicle computers, desktop computers, set-top boxes, smart TVs, and wearable devices. Furthermore, depending on actual needs, the display device may also include other structures such as a touch-sensitive layer, a polarizing film, and a cover plate.

[0146] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A gate driving circuit unit, characterized in that, include: The first switch module is connected to the positive voltage signal terminal and the fifth node, and is used to write the positive voltage signal provided by the positive voltage signal terminal to the fifth node under the control of the second clock signal terminal. The second switch module is connected to the positive voltage signal terminal and the fourth node. Under the control of the first clock signal terminal, it writes the positive voltage signal provided by the positive voltage signal terminal to the fourth node, wherein the clock signals provided by the first clock signal terminal and the second clock signal terminal have the same period and are out of phase by one line of time. A first NMOS transistor and a third capacitor, wherein the first NMOS transistor is connected to the fifth node and the first node, and is used to write the positive voltage signal of the fifth node to the first node under the control of the positive voltage signal provided by the fourth node; the third capacitor is connected to the fifth node and the fourth node, and is used to store the potential of the fourth node and the fifth node. The second NMOS transistor and the first capacitor are connected. The second NMOS transistor is connected to the second negative voltage signal terminal and the signal output terminal. Under the control of the positive voltage signal provided by the first node, the second negative voltage signal of the second negative voltage signal terminal is input to the signal output terminal. The first capacitor is connected to the first negative voltage signal terminal and the first node. It is used to store the potential of the first node. The third NMOS transistor is connected to the second clock signal terminal and the first node, and is used to write the low potential provided by the second clock signal terminal to the first node under the control of the third node. The third switch module is connected to the signal input terminal and the third node. Under the control of the second clock signal terminal, it is used to write a high-level potential provided by the signal input terminal to the third node and to block the connection between the third node and the signal input terminal. A fourth NMOS transistor and a second capacitor are provided. The fourth NMOS transistor is connected to the third clock signal terminal and the signal output terminal. Under the control of the high-level potential provided by the third node, it is used to input the level signal provided by the third clock signal terminal to the signal output terminal. The second capacitor is connected to the signal output terminal and the third node. It is used to store the high-level potential provided by the signal input terminal and to maintain the high-level potential of the third node when the third switch module blocks the connection between the third node and the signal input terminal. It controls the third NMOS transistor to write the low-level potential provided by the second clock signal terminal to the first node, triggering the second NMOS transistor to turn off. The clock signals provided by the third clock signal terminal and the first clock signal terminal have the same period and opposite voltage polarities. The reset module is connected to the first negative voltage signal terminal and the second node, and is used to provide a first negative voltage signal to the second node under the control of the first clock signal terminal and the first node. The second node is located between the third switch module and the third node.

2. The gate drive circuit unit according to claim 1, characterized in that, The first switch module includes: The fifth NMOS transistor has its gate connected to the second clock signal terminal, its drain connected to the positive voltage signal terminal, and its source connected to the fifth node.

3. The gate drive circuit unit according to claim 1, characterized in that, The second switch module includes: The sixth NMOS transistor has its gate connected to the first clock signal terminal, its drain connected to the positive voltage signal terminal, and its source connected to the fourth node.

4. The gate driving circuit unit according to claim 1, characterized in that, The gate drive circuit unit further includes: The seventh NMOS transistor has its gate connected to the signal input terminal, its drain connected to the first clock signal terminal, and its source connected to the fourth node. The seventh NMOS transistor is used to write a low-level signal provided by the first clock signal terminal to the fourth node under the control of the high-level potential provided at the signal input terminal, so that the fourth node is reset after a delay.

5. The gate drive circuit unit according to claim 1, characterized in that, The third switch module includes: The eighth NMOS transistor has its gate connected to the second clock signal terminal, its drain connected to the signal input terminal, and its source connected to the second node.

6. The gate driving circuit unit according to claim 1, characterized in that, The reset module includes: The ninth NMOS transistor has its gate connected to the first clock signal terminal, its drain connected to the first negative voltage signal terminal, and its source connected to the sixth node. The tenth NMOS transistor has its gate connected to the first node, its drain connected to the sixth node, and its source connected to the second node. The gate drive circuit unit further includes: The eleventh NMOS transistor has its gate connected to the positive voltage signal terminal, its drain connected to the second node, and its source connected to the third node. The eleventh NMOS transistor is used to remain on under the control of the positive voltage signal terminal, and to write the high-level potential provided by the signal input terminal and the first negative voltage signal to the third node through the second node with a delay.

7. The gate drive circuit unit according to claim 1, characterized in that, include: The second negative voltage signal is higher than the first negative voltage signal. The high-level voltages connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are all equal to the positive voltage signal. The low-level voltages connected to the signal input terminal, the first clock signal terminal, and the second clock signal terminal are all equal to the second negative voltage signal. The low-level voltage of the third clock signal terminal is equal to the positive voltage signal.

8. A gate driving circuit, characterized in that, Includes the gate drive circuit unit as described in any one of claims 1-6; Multiple gate drive circuit units are electrically coupled in a cascaded manner, wherein the signal input terminal of the first-stage gate drive circuit unit is coupled to the start pulse signal, and the signal output terminal of each of the remaining gate drive circuit units, except for the last-stage gate drive circuit unit, is coupled to the signal input terminal of the next-stage gate drive circuit unit.

9. The gate driving circuit according to claim 8, characterized in that, From the first-stage gate drive circuit unit to the last-stage gate drive circuit unit in the cascaded chain, the first clock signal terminal and the second clock signal terminal in each gate drive circuit unit are alternately connected to the first clock signal line and the second clock signal line, and the third clock signal terminal in each gate drive circuit unit is alternately connected to the third clock signal line and the fourth clock signal line. The third clock signal line has the same clock signal period as the fourth clock signal line, but the voltage polarities are opposite.

10. A display device, characterized in that, Includes the gate drive circuit as described in claim 8 or 9.

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