Circuit design generation method and system by means of grammar-based optimization

Abstract

A computer-implemented method (200) for circuit generation is disclosed, comprising: receiving (202) parameters specifying functionality of a circuit to be designed; optimising (204) one or more circuit designs based on a suitability score that depends at least in part on the suitability of the one or more circuit designs for achieving the specified functionality; wherein the optimising comprises using a grammar based optimisation engine configured to perform a grammar based optimisation in which the one or more circuit designs and any optimisations accord to a selected grammar that describes the structure and / or behaviour of electronic circuits and configured to result in synthesisable circuit components; and the optimising outputs (206) an optimised circuit design.

Description

[0001] M& C Ref: PG451104WO

[0002] 1

[0003] CIRCUIT GENERATION SYSTEM AND METHOD

[0004] Field of Invention

[0005] The present disclosure relates to generating and modifying circuits, particularly to a computer implemented system and method for use in generating and modifying electrical circuits. Background

[0006] Generating electrical circuits is a skilled, slow, and costly process, with minor errors in design being extremely costly to fix. To assist designers, there are a wide range of electronic design automation (EDA) tools available, depending on the type of circuit and the preferred approach. For digital designs, to make the task tractable, specialised hardware description languages (HDLs) are used to design circuits, which are heavily tested in simulators before being committed to hardware to minimise the costs associated with mistakes at the design stage. For example, candidate circuits described in HDL that pass initial functional testing also need to be “verified” to ensure they can be manufactured, which is another time-consuming step. Despite the wide range of electronic design automation tools available, designing, testing, and fabricating electrical circuits can be prohibitively expensive. Furthermore, the process of designing such circuits relies largely on engineers fully understanding the problem for which the circuit is being created.

[0007] Circuit design-oriented scripting tools such Cadence SKILL address part of this gap. Unlike HDLs, which specify what a circuit should do, SKILL is a Lisp-based scripting language used within the Cadence Virtuoso environment to define how a circuit is constructed. It can instantiate devices and schematic structures, size devices, generate parameterised cells, and interact directly with simulation tools such as Spectre. In this way, HDL-based behavioural descriptions can be complemented by SKILL-driven schematic and layout generation, helping to bridge the gap between abstract circuit intent and its physical realisation.

[0008] However, improvements in tools for circuit generation would be beneficial, such as but not limited to improvements in efficiency of the generation process, the quality of the generated circuits, increasing the degree of automation, reducing the size and / or power consumption of the generated circuits, improving the ease of manufacturing, and / or the like.

[0009] It is an object of the invention to provide a method of designing or generating circuits that is easier and more efficient. Another object of the invention is to provide a method of designing M& C Ref: PG451104WO

[0010] 2

[0011] and generating circuits that is not only easier and more efficient, but also capable of producing highly sophisticated chips with minimal manual intervention.

[0012] Summary

[0013] According to a first aspect of the present invention, there is provided a computer-implemented method for circuit generation, comprising: receiving parameters specifying functionality of a circuit to be designed; optimising one or more circuit designs based on a suitability score that depends at least in part on the suitability of the one or more circuit designs for achieving the specified functionality; wherein the optimising comprises using a grammar based optimisation engine configured to perform a grammar based optimisation in which the one or more circuit designs and any optimisations accord to a selected grammar that describes the structure and / or behaviour of electronic circuits and is configured to result in synthesisable circuit components; and the optimising outputs an optimised circuit design.

[0014] In this way, using a grammar-based approach, circuit designs can be generated that are coherent and described in a complete way that increases the likelihood that generated circuits behave as expected once committed to hardware. This is because rules of the grammar can prevent the generation of designs having components that are connected impermissibly, or designs having components whose connections are incompletely described, which can lead to the unintended generation of latches or other circuit features that affect circuit performance and functionality. This grammar-based optimisation approach has been found to be effective at generating complex circuits based on minimal input from users, enabling less-skilled users to generate effective circuit designs and enabling higher-skilled users to generate effective circuits more efficiently.

[0015] The selected grammar is configured to result in synthesisable (i.e., manufacturable) circuit components (and hence circuit designs). This can be achieved by only including manufacturable components in the selected grammar. In other words, circuit components that are useful for performing simulations or modelling but are not manufacturable in practice are excluded from the selected grammar. Generating circuits in this way means that a separate “verification” step is not needed to check the optimal circuit designs can be built, because the composition of the selected grammar already ensures that generated circuits are manufacturable. This allows a time-consuming step in the process of manufacturing circuits to be avoided completely. The term “synthesisable” can also refer to formalising a high-level circuit design into a corresponding design of logic gates or fine-grain hardware (e.g., insilicon). However, in this context, the “synthesisable circuits” refers to being able to physically create a copy of the generated circuit (i.e., manufacture the circuit or suitably configure a M& C Ref: PG451104WO

[0016] 3

[0017] programmable logic device, such as a FPGA, ASIC or other device that is reconfigurable at the hardware level).

[0018] The circuits may be generated at an electronic circuit element or component level, e.g. at a transistor or other component level. Preferably, the selected grammar comprises a plurality of electronic circuit elements. The plurality of circuit elements may be combined with one another to form a circuit design, each electronic circuit element comprising either a single circuit component or a combination of circuit components. A subset of the plurality of electronic circuit elements may comprise predefined combinations of circuit components. The electronic circuit elements may comprise one or more transistors, which may comprise NMOS and / or PMOS transistors, or other active components. The electronic circuit elements may comprise one or more passive components, such as resistors. In this way, useful functionality can be “seeded” in the selected grammar, so that useful circuit modules can be incorporated easily into optimised designs. This helps the method to converge onto a solution more quickly. The predefined combinations of circuit components can have any suitable predefined function. The method can include receiving predefined combinations of circuit components from the user, which allows the user to provide circuit sections or modules they anticipate will be useful for achieving the intended functionality of the circuit to be designed. In some examples, the circuit of the circuit design may be a digital circuit. In examples where the circuit is a digital circuit, the electronic circuit elements may comprise or consist of one or more transistors, which may comprise NMOS and / or PMOS transistors. In some examples, the circuit of the circuit design may be an analogue circuit. In examples where the circuit is an analogue circuit, the electronic circuit elements may comprise or consist of: one or more transistors, one or more other active components and / or one or more passive components, such as resistors. The optimising may comprise optimising a topology of the circuit, which may comprise selecting electronic circuit elements and / or the electrical connections and / or interconnections between the electronic circuit elements. In examples where the circuit is a digital circuit, the optimising may comprise or consist of optimising the topology of the circuit. The optimising may comprise optimising properties of the electronic circuit elements, which may comprise optimising properties, such as physical and / or electrical properties, of the electronic circuit elements, such as size, e.g. length, width and / or height of the electronic circuit elements. In examples where the circuit is an analogue circuit, the optimizing may comprise or consist of optimising the topology of the circuit and the properties of the electronic circuit components, which may be optimized simultaneously and / or within the same optimization.

[0019] Preferably, each of the one or more circuit designs comprises a combination of electronic circuit elements of the plurality of electronic circuit elements, and the optimising includes M& C Ref: PG451104WO

[0020] 4

[0021] generating variants of the one or more circuit designs by: combining subsets of electronic circuit elements from two or more previously generated circuit designs, or replacing one or more elements of a previously generated circuit design with one or more different electronic circuit elements, to form a new circuit design. Additionally or alternatively, the optimising may include generating variants of the one or more circuit designs by varying one or more properties of one or more electrical circuit elements of a previously generated circuit design. In this way, candidate circuit designs can be generated using previously generated designs. The variants can be generated using any suitable technique, such as grammatical evolution, which is particularly efficient at generating variant designs. Previously generated circuit designs may be selected for generating variants preferentially according to the suitability score of the previously generated circuit designs. For instance, previously generated circuit designs having a better suitability score may be selected preferentially over previously generated circuit designs having a worse suitability score. The previous designs with the best suitability score can be more likely to be selected, or, alternatively, a predetermined number or proportion of the previously generated circuit designs having the best suitability scores can be selected to form the new circuit designs.

[0022] Preferably, the selected grammar comprises one or more rules prohibiting the combination of two or more particular electronic circuit elements in a circuit design, or a particular manner of connecting two circuit designs, to avoid or prevent generating non-functioning circuit designs. In this way, it can be ensured that only coherent circuit designs are generated. The rules can include an explicit rule that prohibits two components to be connected (or connected in a particular way). Alternatively, the rules can be implicit by only allowing selected combinations of components included in the selected grammar, whereby non-selected combinations are effectively prohibited.

[0023] Preferably, at least one of the subset of the plurality of electronic circuit elements comprises a combination of circuit components that is configured to act as (i.e., be or provide) one or more of: a signal filter, such as a finite impulse response filter, a high-pass filter or a low-pass filter, or an adder, a multiplier, a flip-flop, switch, a multiplexer, a multiplier, a delay element, a logic gate or other logic element, or a register. The combination of circuit components can be configured to provide any other suitable circuit module or component. The circuit may be a sensor circuit or a logic gate or other logic element. The logic gate or other logic element may be or comprise an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate or the like. The circuit may be an analogue circuit and the electronic circuit elements may comprise or consist of analogue elements, which may comprise active and / or passive elements, such as transistors, resistors and / or the like. The circuit may be a digital circuit and the electronic M& C Ref: PG451104WO

[0024] 5

[0025] circuit elements may comprise or consist of digital elements, such as transistors. The circuit may be a mixed circuit that comprises both digital and analogue circuit components.

[0026] Preferably, the one or more circuit designs comprise components of a hardware description language expressed in a formal grammar. The formal grammar can be an attribute grammar, a Backus-Naur Form (BNF) grammar, or any other suitable formal grammar. BNF grammars, or grammars based on BNF, are useful when exact descriptions are required, and therefore provide a particularly effective grammar for the purposes of circuit generation. The hardware description language can be of any suitable kind, such as Verilog, VHDL, System Verlilog, or the like. The use of a hardware description language expressed in a formal grammar enables optimised circuit designs to accord precisely to the rules of the hardware description language, so that optimised circuits behave as expected during testing and simulation.

[0027] In examples, a scripting language such as Cadence SKILL can be used to implement more advanced functionality. For example, by combining HDL-based behavioural descriptions with SKILL-driven automation for schematic and layout generation, the approach described herein can accelerate the entire design cycle from concept to manufacturable silicon, reduce human error, and make the process more scalable. Although scripting languages such as Cadence SKILL are general-purpose, in the present workflow they may be used as a formalised circuit description language, effectively serving a role analogous to a hardware description language at the transistor level. Attribute grammars may be used to ensure that all generated SKILL code is both syntactically and semantically valid, so that each individual represents a legal circuit topology that can be instantiated and simulated directly within a simulator or layout suite such as Cadence Virtuoso / Spectre.

[0028] Preferably, the optimising comprises simulating iteratively a behaviour of the one or more circuit designs. The optimising may further comprise, during one or more earlier cycles of simulating iteratively, using a first simulation model, and, during one or more later cycles of simulating iteratively, using a second simulation model that is different from the first simulation model. In this way, different aspects of the circuit designs can be optimised. The first and second simulation models can be different simulation engines or environments. Alternatively, the first and second simulation models can use the same simulation environment or engine, but with different settings configured to test a different aspect, or the same aspect in more detail, of the circuit designs. In other examples, any other number of simulation models can be used in different cycles.

[0029] Preferably, the first simulation model is configured to provide less information (or less accurate information) about a simulated circuit but to execute more quickly compared to the second simulation model and the second simulation model is configured to provide more information, M& C Ref: PG451104WO

[0030] 6

[0031] or more accurate information, about a simulated circuit but to execute less quickly compared to the first simulation model. In this way, the method can execute more efficiently because during earlier cycles, circuit designs may not be able to perform the basic functionality set out in the received parameters, such that simulating their behaviour to a high level of accuracy or detail would not be a worthwhile use of computing resources. During later cycles, the optimisation will generally progress the designs until one or several have been found that achieve the basic functionality set out in the received parameters. At this stage, a betterquality simulation will provide information that is more useful and worthwhile obtaining.

[0032] Preferably, the first simulation model is configured to perform a functional simulation that simulates a behaviour of a simulated circuit, and the second simulation model is configured to perform a gate-level simulation that simulates a behaviour of the simulated circuit after the circuit has been converted to a corresponding circuit of logic gates. In this way, the circuit designs can be optimised according to different simulation models that simulate different aspects of the circuits behaviour. By optimising using a variety of simulation models, the circuit designs can be tested and optimised as completely as possible, so that the designs behave as expected once committed to hardware. Further, using a variety of simulation models enables automatic performance of all testing stages that a manually designed circuit would be subjected to, further reducing the level of skill required to generate a useful circuit design. In one example, the second simulation model is a gate level timing simulator.

[0033] A plurality of different simulation models can be used in different cycles or iterations. Each simulation model can be configured to perform one of: functional testing; Post Synthesis Static Timing Analysis (STA); Gate Level Functional Simulation; Post Fitting STA, which may be carried out after each of the circuit designs has been processed by a fitter; and a Gate Level Timing Simulation. The particular simulation models used can be any suitable model known in the art, such as ModelSim and Questa (from Siemens), Incisive Enterprise Simulator (from Cadence), Xilinx Simulator (XSIM) etc. and synthesis tools such as Synopsys Design Compiler NXT, Cadence Genus, Siemens Precision RTL, or the like.

[0034] Preferably, the optimising comprises simulating iteratively a behaviour of the one or more circuit designs, and, during one or more cycles of simulating iteratively, the one or more circuits are optimised using less than all of the received parameters. In this way, during the earlier cycles, only a subset of the received parameters are used to perform the optimisation so that the optimisation can begin to converge on a solution more easily because the method is not attempting to optimise all variables simultaneously. During later cycles of simulating iteratively, a larger subset or all of the received parameters may be used to optimise towards a more “complete” solution. M& C Ref: PG451104WO

[0035] 7

[0036] Preferably, the optimising is performed using a grammar-based machine learning tool. In one example, the optimising is performed using a grammar-based genetic programming tool or technique, such as grammatical evolution. Grammatical evolution has been found to be particularly efficient at optimising circuit designs. However, in other embodiments, any other suitable machine learning tool can also be used.

[0037] Preferably, the method further comprises manufacturing a circuit according to the optimised one or more circuit designs. The manufactured circuit can be in any suitable form. For example, the manufactured circuit can be in the form of a FPGA or other programmable logic device, an ASIC chip, or any other kind of integrated circuit. The manufactured circuit may be a digital circuit or an analogue circuit or a mixed circuit. The manufacturing can be carried out using any suitable circuit manufacturing process known in the industry, which can include steps such as etching, ion implantation, diffusion, oxide layer growth, patterning, and the like. Preferably, receiving parameters specifying functionality of a circuit to be designed comprises receiving, from a user, testbench parameters specifying functionality of a circuit to be designed, the testbench parameters comprising sets of one or more input parameters and corresponding sets of one or more output parameters. The parameters specifying functionality of a circuit to be designed, e.g. the testbench parameters, may comprise one or more performance specifications, which may comprise at least one or each of: gain, bandwidth, power consumption, delay, noise and / or the like. In this way, the expected outputs corresponding to specific inputs can be designed and the circuit designs can be optimised on this basis. Each set of one or more input parameters and corresponding output parameters can define a particular test case or scenario, such that the sets of testbench parameters can define how the circuit to be designed should behave in various scenarios. This allows the behaviour of the circuit to be described more completely by a user. The testbench parameters can be provided in any suitable form, such as a truth table, a matrix, or any other form known in the art. The input and output parameters can include one or more ideal input signals and one or more corresponding ideal output signals, respectively, for the circuit to be designed. Preferably, at least one of the one or more output parameters corresponds to a functionality of the circuit to be designed. For example, the one or more of the output parameters may include a particular output signal to be generated in response to a particular input signal or signals. For example, the one or more of the output parameters may comprise the output parameters associated with combinations of inputs so as to operate as a logic gate, such as an AND, OR, NAND, NOR orXOR gate. In another example, the input signals are electrical signals output by a sensor, and the output signals are signals indicative of the value of a property measured by the sensor, or a property derived therefrom. M& C Ref: PG451104WO

[0038] 8

[0039] Preferably, receiving parameters specifying functionality of a circuit to be designed comprises receiving one or more performance parameters specifying a performance of the circuit to be designed. In this way, the circuit designs can be optimised based on performance as well as functionality. The performance parameters can be any suitable variable describing an attribute of the circuit to be designed.

[0040] Preferably, the one or more performance parameters specify one or more of: a threshold power consumption, a threshold circuit area, a threshold processing speed, a threshold latency, a threshold throughput, ora threshold component cost. The performance parameters can also define or relate to one or more of: power consumption or dissipation, propagation or other delay, clock frequency (including any of clock latency, jitter and skew), circuit area (i.e., minimum area of the components of the circuit on a chip once manufactured), processing speed, latency (i.e. how long is it permissible to wait between providing inputs in the input parameters to achieve the output parameters), a throughput, total component cost and / or the like.

[0041] Preferably, the optimising comprises simulating a behaviour of each of the one or more circuit designs and determining a suitability score for each circuit design using one or more fitness functions that quantify the extent to which sets of output parameters in the received parameters are achieved when each of the one or more circuits are provided with corresponding inputs of the received parameters. In this way, the suitability score can be used to test the circuit designs against the received parameters, so that circuits can be optimised accordingly. The fitness functions can be any suitable kind of function known in the art and could be prepared by persons skilled in the art according to the circumstances of the circuit to be designed. The fitness functions may be or comprise multi-objective fitness functions, e.g. comprising multiple objective criteria, which may balance trade-offs or competing objectives. The objective criteria may comprise criteria of one or two or more of: correctness, total circuit area, number of transistors or other circuit components, amount or rate of errors, power consumption, gain, delay, lag, linearity, skew, sensitivity, and / or the like. The suitability score can be a collection of outputs of the fitness functions. Alternatively, the suitability score can be the outputs of the fitness functions combined into one or more values using a suitable formula. For example, when the circuit is a digital circuit, the objective criteria may comprise criteria of one or more of: correctness, total circuit area, amount or rate of errors, power consumption and / or average power. In examples, where the circuit is an analogue circuit, the objective criteria may comprise criteria of one or more of: correctness, area, error rate, power consumption, average power, sensitivity, linearity, and / or static power. M& C Ref: PG451104WO

[0042] 9

[0043] Preferably, the optimising comprises: subsequently, determining, based on the suitability scores, that a condition is not met by any of the one or more circuit designs; generating iteratively, sets of variants of circuit designs, and simulating iteratively a behaviour of each circuit design in each set of variants to determine a suitability score for each circuit design using the one or more fitness functions; wherein each set of variants is generated by modifying a corresponding previous set of circuit designs, such that previous circuit designs having higher suitability scores are more likely to be selected to generate a subsequent set of variants; wherein the generating iteratively and simulating iteratively are repeated until a final set of variants is generated and determined, based on corresponding suitability scores, to include one or more circuit designs that meet the condition. The modifying of the corresponding previous set of circuit designs may comprise modifying the topology of the previous circuit and / or the parameters of electrical circuit components of the circuit, such as resistor size. In examples where the circuit is a digital circuit, the modifying of the corresponding previous set of circuit designs may comprise or consist of modifying the topology of the previous circuit. In examples where the circuit is an analogue circuit, the modifying of the corresponding previous set of circuit designs may comprise or consist of modifying both the topology of the previous circuit and the parameters of electrical circuit components of the circuit, such as resistor size. The condition can be whether some or all of a minimum functionality and performance defined in received parameters is achieved one or more of the circuit designs. This provides one particular manner of performing the optimisation. However, in other examples, other optimisation techniques could be employed that use the selected grammar to generate coherent circuits.

[0044] According to a further aspect of the present invention, there is also provided a computer system comprising: one or more processors; and a memory storing executable instructions that, once executed by the one or more processors, cause the one or more processors to perform steps comprising: receiving parameters specifying functionality of a circuit to be designed; optimising one or more circuit designs based on a suitability score that depends at least in part on the suitability of the one or more circuit designs for achieving the specified functionality; wherein the optimising comprises using a grammar based optimisation engine configured to perform a grammar based optimisation in which the one or more circuit designs and any optimisations accord to a selected grammar that describes the structure and / or behaviour of electronic circuits and is configured to result in synthesisable circuit components; and the optimising outputs an optimised circuit design. M& C Ref: PG451104WO

[0045] 10

[0046] According to a further aspect of the present invention, there is also provided a computer program product which, when executed by one or more processors, causes the one or more processors to perform the method of the first aspect of the invention.

[0047] According to a further aspect of the present invention, there is also provided a non-transitory computer readable medium storing instructions which, when executed by a processor, cause the processor to perform steps comprising: receiving parameters specifying functionality of a circuit to be designed; optimising one or more circuit designs based on a suitability score that depends at least in part on the suitability of the one or more circuit designs for achieving the specified functionality; wherein the optimising comprises using a grammar based optimisation engine configured to perform a grammar based optimisation in which the one or more circuit designs and any optimisations accord to a selected grammar that describes the structure and / or behaviour of electronic circuits and is configured to result in synthesisable circuit components; and the optimising outputs an optimised circuit design.

[0048] According to a second aspect of the invention, there is provided a computer-implemented method of designing a circuit, comprising: receiving, from a user, testbench parameters specifying intended functionality of a circuit to be designed, the testbench parameters comprising sets of one or more input parameters and corresponding sets of one or more output parameters; generating, using a subset of a grammar of circuit components, the subset of the grammar corresponding to manufacturable circuit components, an initial set of circuit designs in a hardware description language; simulating a behaviour of each circuit design of the initial set of circuit designs and determining a suitability score for each circuit design using one or more fitness functions that quantify the extent to which the sets of output parameters are achieved when each initial circuit is provided with inputs corresponding to the respective sets of input parameters; determining, based on the suitability scores, that a condition is not met by any of the circuit designs in the initial set of circuit designs; generating iteratively, sets of variants of circuit designs, and simulating iteratively a behaviour of each circuit design in each set of variants to determine a suitability score for each circuit design using the one or more fitness functions; wherein each set of variants is generated probabilistically by modifying a corresponding previous set of circuit design, such that previous circuit designs having higher suitability scores are more likely to be selected to generate a subsequent set of variants; wherein the generating iteratively and simulating iteratively are repeated until a final set of variants is generated and determined, based on corresponding suitability scores, to include one or more circuit designs that meet the condition; and outputting the one or more circuit designs to a user. M& C Ref: PG451104WO

[0049] 11

[0050] According to a further aspect of the present invention, there is also provided a computer system comprising: one or more processors; and a memory storing executable instructions that, once executed by the one or more processors, cause the one or more processors to perform steps comprising: receiving, from a user, testbench parameters specifying intended functionality of a circuit to be designed, the testbench parameters comprising sets of one or more input parameters and corresponding sets of one or more output parameters; generating, using a subset of a grammar of circuit components, the subset of the grammar corresponding to manufacturable circuit components, an initial set of circuit designs in a hardware description language; simulating a behaviour of each circuit design of the initial set of circuit designs and determining a suitability score for each circuit design using one or more fitness functions that quantify the extent to which the sets of output parameters are achieved when each initial circuit is provided with inputs corresponding to the respective sets of input parameters; determining, based on the suitability scores, that a condition is not met by any of the circuit designs in the initial set of circuit designs; generating iteratively, sets of variants of circuit designs, and simulating iteratively a behaviour of each circuit design in each set of variants to determine a suitability score for each circuit design using the one or more fitness functions; wherein each set of variants is generated probabilistically by modifying a corresponding previous set of circuit design, such that previous circuit designs having higher suitability scores are more likely to be selected to generate a subsequent set of variants; wherein the generating iteratively and simulating iteratively are repeated until a final set of variants is generated and determined, based on corresponding suitability scores, to include one or more circuit designs that meet the condition; and outputting the one or more circuit designs to a user.

[0051] According to a further aspect of the present invention, there is also provided a computer program product which, when executed by one or more processors, causes the one or more processors to perform the method of the second aspect of the invention.

[0052] According to the second aspect of the present invention, there is also provided a non-transitory computer readable medium storing instructions which, when executed by a processor, cause the processor to perform steps comprising: receiving, from a user, testbench parameters specifying intended functionality of a circuit to be designed, the testbench parameters comprising sets of one or more input parameters and corresponding sets of one or more output parameters; generating, using a subset of a grammar of circuit components, the subset of the grammar corresponding to manufacturable circuit components, an initial set of circuit designs in a hardware description language; simulating a behaviour of each circuit design of the initial set of circuit designs and determining a suitability score for each circuit design using one or more fitness functions that quantify the extent to which the sets of output parameters are M& C Ref: PG451104WO

[0053] 12

[0054] achieved when each initial circuit is provided with inputs corresponding to the respective sets of input parameters; determining, based on the suitability scores, that a condition is not met by any of the circuit designs in the initial set of circuit designs; generating iteratively, sets of variants of circuit designs, and simulating iteratively a behaviour of each circuit design in each set of variants to determine a suitability score for each circuit design using the one or more fitness functions; wherein each set of variants is generated probabilistically by modifying a corresponding previous set of circuit design, such that previous circuit designs having higher suitability scores are more likely to be selected to generate a subsequent set of variants; wherein the generating iteratively and simulating iteratively are repeated until a final set of variants is generated and determined, based on corresponding suitability scores, to include one or more circuit designs that meet the condition; and outputting the one or more circuit designs to a user.

[0055] Any of the features of the first aspect of the invention described above can also be implemented or applied to the second aspect of the invention.

[0056] The individual features and / or combinations of features defined above in accordance with any aspect of the present invention or below in relation to any specific embodiment of the invention may be utilised, either separately and individually, alone or in combination with any other defined feature, in any other aspect or embodiment of the invention.

[0057] Furthermore, the present invention is intended to cover apparatus configured to perform any feature described herein in relation to a method and / or a method of using or producing, using or manufacturing any apparatus feature described herein.

[0058] Description of the Drawings

[0059] Various examples of the present disclosure will now be described by way of example, and with reference to the accompanying drawings, of which:

[0060] Figure 1 is a schematic diagram of a system according to an embodiment of the invention;

[0061] Figure 2A is a flowchart of a circuit generation method according to an embodiment of the invention;

[0062] Figure 2B is a flowchart of a circuit generation method according to an embodiment of the invention;

[0063] Figure 3A is a schematic diagram of a portion of testbench parameters usable in embodiments of the invention; M& C Ref: PG451104WO

[0064] 13

[0065] Figure 3B is a schematic diagram of a portion of testbench parameters usable in embodiments of the invention;

[0066] Figure 4 is a flowchart of a circuit generation method according to an embodiment of the invention;

[0067] Figure 5 is a flowchart of a circuit generation method;

[0068] Figure 6 is a flowchart of a circuit generation method according to an embodiment of the invention;

[0069] Figure 7A shows two graphs of generated circuit designs plotted as a function of their effectiveness as measured by fitness functions after 5 generations (left) and 15 generations (right) of circuit designs;

[0070] Figure 7B shows two graphs of generated circuit designs plotted as a function of their effectiveness as measured by fitness functions after 40 generations (left) and 200 generations (right) of circuit designs;

[0071] Figure 8 shows a photographic image of an ASIC chip (right) designed and produced according to an embodiment of the invention;

[0072] Figure 9 shows a schematic control diagram of a first FPGA and a second FPGA used for prototyping in an embodiment of the invention;

[0073] Figure 10 shows a schematic control diagram of the second FPGA used in an embodiment of the invention;

[0074] Figure 11 is a flowchart illustrating a method of generating an analogue circuit;

[0075] Figure 12 is a schematic of a process for generating a topology and optionally also component properties of a circuit;

[0076] Figures 13 to 15 show values of performance metrics in the form of circuit error, transistor count (area) and power consumption with iteration (generation cycle) achieved for example digital circuits in the form of NAND and NOR gates generated using the method of Figures 2 and 12; and

[0077] Figure 16 shows responses of digital circuits in the form of NAND and NOR gates created using the method of Figures 2 and 12 against the values of inputs A & B.

[0078] Detailed Description of the Drawings

[0079] 1. Systems and methods of the invention. M& C Ref: PG451104WO

[0080] 14

[0081] Figure 1 shows a schematic diagram of a system 1 according to an embodiment of the invention.

[0082] The system 1 comprises a computer 2 comprising one or more processors 4 and a memory 6 storing executable instructions 8 that can be executed to perform methods of the invention, such as the methods 100, 200 discussed below. A network interface 10 is provided in this example for communicating with other devices over a network, such as the internet. Input peripherals 12 and output peripherals 14 are provided in this example for receiving and providing information from or to a user, respectively.

[0083] The memory 6 stores various components used to perform methods of the invention, however such components can also be stored remotely in other examples. The memory 6 stores simulation models 16 for simulating various behaviours of circuits. Examples described herein use grammar based optimisation techniques that allow circuit optimisations to be carried out according to a grammar that can be used to guide the optimisation. A particularly beneficial example of a suitable grammar based approach is Grammatical Evolution (GE). In this case, a grammar model 18 is also stored to provide a model and design space for generating candidate circuit designs. The grammar model 16 comprises a set of elements where each element comprises a hardware description language element that defines a single circuit component or a particular combination of circuit components, and rules for combining the elements to form a manufacturable circuit. The memory 6 also comprises circuit designs 20 to be tested by the simulation models 16, and testbench parameters 22 received from a user, e.g. through the input peripherals 12 or through the network interface 10. The memory 6 also stores fitness functions 24, simulation results 26, and weightings 28. The various functions of the components stored in the memory 6 are described in more detail below with reference to Figure 2 and the method 100.

[0084] In this example, the system 1 is provided as a single computer 2. However, methods of the invention, such as the method 100 described below, can also be performed by several computers in a distributed fashion across a network. For instance, the computer 2 may send initially generated circuit designs 20 to a remote device 11 for simulation over the network interface 10. The remote device 11 may then send results of the simulation back to the computer 2 as necessary. In another example, the computer 2 may act as a server computer that receives user inputs (such as the testbench parameters 22) over a network and outputs final circuit designs back to the user over the network. It would be appreciated that other steps of the methods described herein can be performed similarly using one or more remote devices. M& C Ref: PG451104WO

[0085] 15

[0086] Figures 2A and 2B show a flowchart of a method 100 according to an embodiment of the invention. The method 100 can be performed by executing the instructions 8 stored in the memory 6 of the computer 2, however any suitable computing device can also perform the method in other examples. Equally, the invention can also be embodied as a computer program product that implements the method 100 when executed by a computer.

[0087] The method 100 begins at step 102, at which the user provides the testbench parameters 22 as an input. The testbench parameters 22 comprise sets of input parameters each having a corresponding set of output parameters that define the intended functionality of the circuit the user intends to design. That is, the test bench parameters specify what the circuit should do. Generally, the input parameters include one or more sets of inputs to be provided to the circuit and each corresponding set of output parameters can include the intended output or outputs of the circuit in response to the corresponding set of input parameters.

[0088] Figure 3A and 3B show schematic representations of exemplary testbench parameters 22. It will be appreciated that the testbench parameters are typically implemented as statements that include, amongst others, statements specifying inputs to be applied and desired outputs. In this example, a circuit 21, i.e., a circuit to be designed (analogous to a device under test (DUT) in a conventional testbench setup), has three inputs (e.g., input signals that could be provided on input pins or connections), inputs A, B and C, and two outputs (e.g., output signals that could be provided on output pins or connections), D and E. A first set of input parameters 30 is provided in the testbench parameters 22, comprising input signals for each input: input signal 1-A, input signal 1-B, and input signal 1-C, each to be provided to a corresponding input of the circuit 21. A corresponding set of output parameters 32 includes desired output signals for each output D, E: output signal 1-D and output signal 1-E. The input signals 1-A to 1-C and the output signals 1-D and 1-E may comprise time varying signals, binary values, or a mixture thereof. Thus, the input parameters 30 and corresponding output parameters 32 provide a scenario that sets out how the circuit 21 should behave in response to certain inputs. The testbench parameters 22 can include a second scenario defined by different input parameters 34 and corresponding output parameters 36, each with their own sets of input signals (2-A, 2-B, and 2-C) and output signals (2-D and 2-E). This allows the behaviour of the circuit 21 to be defined more completely.

[0089] Figures 3A and 3B show two pairs of input and output parameters for the circuit 21; however, it would be appreciated that a much greater number of pairs may be provided in practice. As such, although two scenarios (i.e. two sets of inputs and corresponding outputs) are discussed simply for illustration, the present disclosure is not limited to this and in practice any number of scenarios could be provided, as depending on the application, a circuit may have to perform M& C Ref: PG451104WO

[0090] 16

[0091] different operations in relation to different inputs or scenarios. Similarly, it would be appreciated that other circuits to be designed may have different numbers of input and output connections, such as only one input and only one output connection. As such, the present disclosure is not limited to the scenarios shown in Figures 3A and 3B and other testbench parameters are envisaged.

[0092] The testbench parameters 22 may also include other information, such as a desired performance of the circuit to be designed. For instance, the testbench parameters 22 may include one or more thresholds or other criteria that need to be met by the circuit, such as but not limited to one or more or any of: power consumption or dissipation, propagation or other delay, clock frequency (including any of clock latency, jitter and skew), circuit area (i.e., minimum area of the components of the circuit on a chip once manufactured), processing speed, latency (i.e., how long is it permissible to wait between providing inputs in the input parameters to achieve the output parameters), a throughput, total component cost and / or the like. Further examples include propagation delay, clock frequency (including clock latency, jitter, and skew), etc., of the desired circuit. Any of the above can be specified in the testbench parameters 22 or, alternatively, can be specified indirectly using the fitness functions 24, described in more detail below. Any other suitable parameters can be provided in the testbench parameters 22 in other examples.

[0093] The testbench parameters 22 may be provided in any suitable format as known in the art, for instance as lines of code such as VHDL, Verilog, System Verlilog or other code, a list of statements, a table or matrix of values with specific columns or rows corresponding to inputs, outputs, or performance characteristics, or the like. The testbench parameters 22 may be provided directly to the computer 2 by a user using the input peripherals 12 or alternatively may be provided to the computer 2 over a network.

[0094] In step 104, an initial set (also referred to herein as a “generation”) of circuit designs 20 are generated using the grammar model 18.

[0095] As discussed above, the grammar model 18 comprises a set of elements that correspond to one or more circuit components (such as an adder, multiplier, flip-flop, multiplexer, filter, or more complex components), or combinations of such circuit components. In this example, each element is a code expression that corresponds to one or more specific components of a HDL, for later conversion into HDL or a synthesised gate-level circuit. In other embodiments, the elements of the grammar model 18 may be expressed directly in HDL, or in any other suitable format. M& C Ref: PG451104WO

[0096] 17

[0097] The grammar model 18 also comprises rules defining how the components of each element may be connected with one another. The rules can define permitted combinations of components and permitted ways of connecting components. The components and combinations can include those that are actually synthesisable (i.e. those that can be manufactured and work together) and those that are not. There is a key difference between synthesisable circuits and simulatable circuits. Unsynthesisable components and combinations of components allow circuit designers extra freedom to explore the impact of various design choices. However, simply because a circuit can be simulated doesn’t necessarily mean that it can be successfully synthesised. This is because simulation can include non-synthesizable constructs that behave correctly in a software environment but cannot be mapped to actual hardware components, and timing issues or resource constraints might not be fully accounted for in the simulation process. Further, missing conditions or incomplete logic definitions in the HDL code can lead to the unintended generation of latches during the synthesis process, which in turn potentially creates issues such as timing problems, debugging challenges, and / or non-portable designs.

[0098] Only a small subset of constructs in a HDL tend to be synthesisable due to an historic focus on providing simulatable circuits, because prior simulation is necessary to design digital circuits in a cost-effective way. This has led to the converse challenge that not all simulated designs can be manufactured. The present invention employs a hybrid automated approach that can employ various simulation models to maximise pre-prototype testing while ensuring only coherent, manufacturable circuit designs are generated.

[0099] The grammar model 18 provides a complete syntax for combining circuit components together. In examples of the present disclosure, the grammar that is selected (e.g. selected as a subset of a complete grammar) for use in the grammar model 18 is limited to only elements of grammar (e.g. circuit components or combinations of circuit components) that are synthesisable. For synthesisable elements of the grammar model 18, the generated circuits are necessarily arranged in a manufacturable way that will function as a circuit. For instance, the grammar 18 may prohibit the connection of components in a way that would form short-circuits or latches, would give rise to timing problems, or otherwise lead to undesirable outcomes in generated designs.

[0100] In a simplified example, a first element of the grammar model may correspond to component A of the HDL language, a second component may correspond to component B of the HDL language, a third element may correspond to a component C of the HDL language, a fourth element may correspond to components A and B of the HDL language connected in a configuration D, and a fifth element may correspond to components A and B of the HDL M& C Ref: PG451104WO

[0101] 18

[0102] language connected in a configuration E that is different from configuration D. Continuing this example, the rules of the grammar model 18 may define that a circuit can comprise two or more of any of the first to fifth elements, except for the first element and the third element, which may not be provided in the same circuit. This means that circuit designs can be generated automatically, using a variety of combinations of elements in the grammar model 18, while ensuring that the resultant circuits have a minimum degree of functionality.

[0103] In one example, the grammar model 18 comprises a plurality of elements in the form of a list of HDL indications of circuit components (or combinations thereof) expressed in an exactly defined notation such as Backus-Naur form (BNF), which is a particularly useful notation for when exact descriptions are required. Each circuit and each element can be represented by a “symbol” of BNF, expressed below between angular brackets <>, and each circuit can be represented by one of many possible combination of symbols. In the following simplified example of a portion of the grammar model 18, “|” indicates a possible choice,

[0104]

[0105] and means that the symbol on the left is defined by, or can be replaced by, the expression on the right.

[0106] 1) <circuit>:: = <first element> <second element> | <first element> <fourth element> | <first element> <fifth element> |... | < (N-l ) th element> < Nth element>

[0107] 2) <fourth element>:: = <first element> <second element> Connected in manner C>

[0108] 3) <first element>:: = < HDL component A>

[0109] 4) <second element>:: = < HDL component B>...

[0110] The first line 1) defines that a candidate circuit design can be composed of a large plurality of possible element combinations for N elements. The second line 2) explains that the fourth element is equivalent to the first and second elements connected in a particular manner C. The third and fourth lines 3), 4), explain that the first and second elements correspond to a particular component in a HDL language and may be the most granular definition in the grammar model 18. In practice, it would be appreciated that circuit designs may comprise combinations of more than two elements of the grammar model 18 and the grammar model 18 may comprise many more than five elements.

[0111] In general, HDLs can define circuit components that are not manufacturable in practice but make simulating performance of circuits described in HDL easier or quicker. The grammar model 18 of the present invention only utilises a subset of components of the HDL language that are known to be manufacturable. Thus, the grammar model 18 can be considered as a M& C Ref: PG451104WO

[0112] 19

[0113] subset of a wider grammar of a HDL that contains only manufacturable circuit components. Whether a given component is manufacturable may be indicated by an attribute of each component of the HDL language, for example. The attributes indicating whether each component is manufacturable I synthesisable or not can be set based on previous experience, testing, modelling or simulation, manufacture or other successful use, or any other suitable technique.

[0114] Using only a subset of manufacturable components in a syntactically complete grammar ensures that generated circuit designs are both manufacturable and connected in a way that does not generate unexpected circuit features, such as latches. This addresses a problem with known approaches to providing computer-generated circuit designs, in which generated circuits may include components not connected properly, or such that connections between components are incompletely defined, resulting in unintended circuit features, such as latches. The approach of the present invention also avoids a problematic scenario wherein non-manufacturable HDL components in initial designs are used to speed up initial simulations and later it transpires that a seemingly equivalent set of manufacturable HDL components behaves differently in practice.

[0115] As mentioned previously, some of the elements of the grammar model 18 comprise a plurality of components connected together, which may be referred to as “composite elements” for brevity. A subset of the composite elements in the grammar model 18 can correspond to circuit modules known to provide a particular function. For example, composite elements may comprise an arrangement of components that provide: a filter (e.g. a high pass filter, a low pass filter, a finite impulse filter, or the like), an adder, multiplier, delay element, a register, or any other suitable circuit module known in the art. A user may be able to input customised circuit modules into the grammar model 18 in order to seed the generated circuit designs with modules that are expected to be useful for fulfilling the desired function. For example, the user may be able to input, as a prior step, lines of code describing a particular form of a basic finite impulse filter as an element of the grammar, which typically comprises at least a few specific components connected in a particular way. The grammar model 18 may have constraints so that the element is connected in a sensible way. This allows the method 100 to converge on a final circuit design more quickly, because useful circuit subsections are built into the grammar model 18.

[0116] Returning to step 104, an initial set (or “generation”) of circuit designs 20 are generated using the grammar model 18. The set of circuit designs can be referred to as candidate solutions, or individuals, that represent potential solutions to the problem of how to achieve required outputs and / or other goals (e.g. minimising or providing required values of propagation delay, M& C Ref: PG451104WO

[0117] 20

[0118] power dissipation, clock frequency, including clock latency, jitter, and skew, and / or the like) specified in the testbench parameters. In one example, this can be performed by randomly combining elements together, up to a predefined maximum number of elements or components in each circuit, to form a set of candidate circuit designs 20. The number of circuit designs 20 generated in the first generation can be varied, e.g. according to how quickly the user would like the method 100 to be completed, how difficult it is to find an acceptable solution, and so on. In one example, the initial set of circuit designs 20 may comprise 1000, 10,000, or 1,000,000 circuit designs 20, but the present disclosure is not limited to any specific number.

[0119] Once the initial set of circuit designs 20 has been generated using the grammar model 18, each circuit design may be converted to suitable HDL code (e.g., using the most granular parts of the grammar model 18 illustrated by steps 3) and 4) above). This allows generated circuit designs to be interpreted and tested by simulation models. Any suitable HDL language known in the art may be used, such as Verilog, SystemVerilog, VHDL or the like.

[0120] In step 106, the behaviour of each circuit design in the set of initial circuit designs is simulated. The simulation can be performed using any suitable simulation model known in the art, such as ModelSim and Questa (from Siemens), Incisive Enterprise Simulator (from Cadence), Xilinx Simulator (XSIM) etc. and synthesis tools such as Synopsys Design Compiler NXT, Cadence Genus, or Siemens Precision RTL.

[0121] At this stage, the simulation is preferably a high-level functional simulation configured to test the basic functionality of each candidate circuit with respect to the testbench parameters 22 quickly. The high-level functional simulation may provide less information about the circuit designs 20 but execute faster than other simulation models. This is useful because initial circuit designs are likely to perform poorly, such that more detailed simulation models are unlikely to provide useful information early on in the process. The simulation can be performed using a simulation model 16 stored in the memory 6 or, alternatively, could be performed remotely by a remote server after the initial set of circuit designs have been passed to the server.

[0122] The simulation results 26 of each simulation may be stored in the memory 6 for later reference. At step 108, the suitability of each of the generated circuit designs 20 is evaluated using one or more fitness functions 24 to generate suitability scores for each circuit design. The fitness functions 24 generally provide formulas or metrics for scoring how well a generated circuit design achieves the functionality (e.g. the desired outputs, any performance characteristics, physical characteristics, etc.) defined by the testbench parameters 22. This is useful because M& C Ref: PG451104WO

[0123] 21

[0124] initially generated designs are highly unlikely to achieve all of the user’s intended functionality, meaning that a gradual scale for assessing the designs is needed in order to select the most promising candidate designs.

[0125] In this example, the fitness functions 24 receive at least a portion of the testbench parameters 22 as an input, for instance to check how closely simulated output signals resemble intended output signals defined in the testbench parameters 22.

[0126] For example, the testbench could implement a truth table of all possible inputs and desired corresponding outputs could be used. It would then compare the output of the circuit under test with the desired output for either all combinations of inputs, or, in some cases, a portion of them. A portion may be desirable where either there are too many inputs to exhaustively test or where the time required to test each is too long because the circuit is complex and requires much time to test.

[0127] The fitness functions 24 can be provided by the user at step 108 or as a prior step of the method 100. Alternatively, the memory 6 could store pre-built fitness functions that are generally useful in certain scenarios, and the user can be prompted to select from the pre-built fitness functions or a certain fitness function can be used by default. The simulation results 26 may be used to test retroactively each circuit design against the fitness functions 24. Alternatively, the fitness functions can be applied during the simulation, such that steps 106 and 108 occur approximately at the same time.

[0128] The form of the fitness functions 24 may vary depending on the type of circuit to be designed. Two exemplary fitness functions used to evaluate candidate designs for a finite impulse filter, fi and f2, are:

[0129] ^ZF=i((p; - ti))

[0130] = NRMSEN

[0131]

[0132] f2= 1 — PearsonCorrelation(p, t)

[0133] where n is the number of training cases, p is a vector of predictions, t is the target vector, and max is the maximum possible root mean square error (a measure of how poorly a candidate design filters a signal). A perfect circuit would score zero on both functions, and the lower the score, the better the result. Other examples can use any other suitable formula and may include a single fitness function or more than two fitness functions. Persons skilled in the art would be capable of preparing an appropriate set of fitness functions. M& C Ref: PG451104WO

[0134] 22

[0135] The outputs from each fitness function may be combined together to determine a single suitability score that summarises the overall performance of a candidate design, e.g. using a formula. Alternatively, a suitability score for each circuit can be represented by a collection of the outputs of each fitness function, e.g., as a vector of values, such as (fi, f2).

[0136] Once the fitness functions 24 have been applied to each of the initial circuit designs, weightings 28 for each of the circuit designs may be set based at least in part on the determined suitability scores. The weightings 28 can be normalised values corresponding to each candidate circuit that determines the probability that a given candidate design will be selected for modification to form subsequent sets or generations of candidate designs. Other factors can also be used to adjust the weightings 28, such as the associated performance, cost, or size of a circuit design. Alternatively, such factors may be assessed by the fitness functions 24, such that a separate adjustment of the weightings 28 is not necessary. Setting weightings 28 may not be required in other embodiments that use suitability scores directly to adjust probabilities of a circuit being selected for subsequent generations of circuit designs. At step 110, a check is performed to determine whether any of the candidate designs meet a condition, which in this example is whether the functionality set out in the testbench parameters 22 is achieved, or at least achieved to a set or pre-set. This check may be performed by checking the outputs of the fitness functions (or a suitability score derived from those outputs) against a threshold or other criterion, in one example. In other examples, other termination conditions for the iterative process could be used. For example, the iterative process described herein may be performed a set number of times or for a set duration and the candidate design identified during that process that best meets the functionality set out in the testbench parameters 22 is selected as an output. Other termination conditions could be used, such as a rate of change of the suitability score or fitness function between iterations or between a given number of iterations being below a threshold amount, or the like.

[0137] Given that the initial set of circuit designs is predominantly selected randomly, the initial set of designs is highly unlikely to contain a working solution. Therefore, for the initial set or sets of candidate designs, this check may be skipped. In this example, the initial check 110 is performed and the initial designs are determined not to provide the functionality set out in the testbench parameters 22, e.g. the functionality set out in the testbench parameters 22 is not achieved or not achieved to the required extent or any other termination condition has not been met.

[0138] It should be noted that the method 100 repeats steps 110 to 118 iteratively. Thus, the method 100 later returns to step 110 in subsequent iterations to check whether subsequently generated sets of circuit designs have the desired functionality. M& C Ref: PG451104WO

[0139] 23

[0140] At step 112, a new set of circuit designs is generated, using the grammar model 18, based on the previous set of circuit designs. At this stage, the previous set of designs is the initial set of circuit designs generated in step 104. However, the method 100 will later return to step 112 in subsequent iterations of steps 110 to 118, in which case a new set of circuit designs will be generated based on the circuit designs generated during the most recent previous iteration of step 112. In this way, the designs can be optimised iteratively.

[0141] There are various options for generating variations in the designs. For example, the new set of circuit designs can be generated firstly by probabilistically selecting designs in the previous set for modification. The weighting 28 (and thus the suitability score) corresponding to each of the previous circuit designs define the likelihood that they will be selected at this stage, so that the best-performing designs are most likely to be selected for modification. A subset of the previous (in this case, initial) circuit designs are selected and can be modified by, either: randomly replacing one or more elements in the selected design with one or more different elements of the grammar model 18, or copying a whole or part of a different design in the subset and combining this with the selected design. Other ways of modifying the designs can also be implemented, such as by changing the way one or more elements are connected or arranged in the design. Once this has been completed, a new set of candidate designs has been generated. The new set may contain the same number of designs as the initial set, in this case 1000, or alternatively a different number of designs, which may be selected according to the current iteration of step 112.

[0142] The generation of new circuit designs in step 112 using the grammar model 18 can be performed using any suitable genetic programming technique. In this example, step 112 is performed using the techniques used in grammatical evolution, which has been found to be particularly efficient.

[0143] In other embodiments, circuit designs may not be selected probabilistically. For instance, a subset of the designs corresponding to a predefined number of the best performing designs may be selected.

[0144] Once the new set of circuit designs has been generated using the grammar model 18, each of the new circuit designs is converted to a corresponding HDL model (which can be embodied by HDL code) so that the circuit design can be tested by a simulation model. During later iterations, a different simulation model may be selected that simulates behaviour of a “lower-level” version of the circuit designs that does not use HDL,.e.g. the circuit designs expressed as logic gates or in-silicon. In this case, at step 112, the new set of circuit designs can be converted to an alternative appropriate code representation. M& C Ref: PG451104WO

[0145] 24

[0146] If, previously, the check at step 110 reveals that the testbench parameters 22 were achieved by the previous set of designs, then step 112 may be skipped for the current iteration to avoid unnecessarily altering designs found to satisfy the testbench parameters 22.

[0147] In step 114, a simulation model 16 is selected based on whether the testbench parameters 22 were determined to be achieved in step 110. In general, the simulation model 16 used and the type of simulation performed (functional, post-synthesis static timing analysis, gate level functional simulation, gate level timing, etc) can differ in different iterations.

[0148] Specifically, a first simulation model (e.g., configured to provide functional simulation) may be used for the initial sets of circuit designs 20 until the check at step 110 determines that the testbench parameters 22 have been achieved by the candidate circuits in the current set. Thereafter, a second, different simulation model may be used for testing candidate designs in greater detail, or for testing a different aspect of the candidate designs, such as circuit timing. New generations of designs can be generated in the manner of step 112 described above until the testbench parameters 22 are also achieved according to the simulations performed by the second model. In the same way, third, fourth, or any number of additional simulation models can be used until one or more circuit designs are generated and found to satisfy the testbench parameters 22 when assessed using all of the models. Additionally or alternatively, different fitness functions can be used, with one or more first fitness functions being used for optimisation initially followed by optimisation according to a second set of one or more fitness functions that comprises one or more different fitness functions. For example, the iterative process 110-118 can be used to optimise according to one or more first requirements (which may be specified in the testbench parameters) represented in the first fitness functions, and then after certain termination criteria are met, switching to the second set of fitness functions that represent at least one different criterion.

[0149] Therefore, at step 114, the same simulation model as was used to simulate the previous set of circuit designs is selected, unless the check at step 110 reveals that the testbench parameters 22 were achieved by the previous set of designs. It would be appreciated that the selection can be implicit. That is, a simulation model can be “selected” by not changing the model used to test the previous set of circuit designs.

[0150] In step 116, the behaviour of the new set of designs is simulated using the simulation model selected in step 114, as described above in step 106.

[0151] In step 118, suitability scores are determined for the circuit designs in the current set. Weightings 28 may be assigned to each circuit design based on the corresponding suitability score. The suitability scores generated for each circuit will generally differ from those M& C Ref: PG451104WO

[0152] 25

[0153] calculated in step 108 because the new generation of circuit designs are modified with respect to the initial set of circuit designs. The suitability scores for each generation should be at least marginally improved with respect to the previous generation because the most successful subset of candidate designs (as measured using the fitness functions 24) are generally used as the foundation for each next generation of designs. Over many iterations, the sets of generated circuits gradually improve until a set is found to contain at least one circuit functioning as intended. The suitability scores therefore provide a metric for performing optimisation of the designs.

[0154] In step 120, the method 100 returns to step 110 to perform a subsequent iterations of steps 110-118.

[0155] In this example, new sets of candidate circuit designs (and corresponding HDL models) are iteratively generated and simulated in this manner, using a first functional simulation model, until the check at an iteration of step 110 reveals that the testbench parameters 22 are achieved by at least one circuit design in the set.

[0156] At this point, the method 100 skips to step 114 (as indicated by the dashed arrow on the left of Figure 2A), at which a new simulation model is selected. The “new” simulation model can be new in the sense of a completely different simulation model, simulation environment, or simulation engine. Alternatively, the “new” simulation model can be the same model environment or engine as selected previously, but with different settings that allows different aspects of circuit behaviour to be tested (or the same aspects to be tested in more detail). As described previously, the new simulation model can be a simulation model configured to provide more information but which takes longer to execute. Using a less granular model at early iterations of steps 110-118 can significantly improve the performance of the method 100. In this example embodiment, four different testing stages are implemented, where different simulation models are used at each of the first three stages of testing and a physical prototype is tested during a fourth stage. Figure 6, discussed further below, shows a flowchart of an alternative method based on three stages (functional simulation, timing simulation, and hardware verification).

[0157] Returning to the example method 100, at a first stage of testing, a first functional simulation model is used as described above to test the basic functionality of generated circuit designs. The first functional simulation model is configured to provide quick results but less information or a less accurate simulation, to improve performance of the method 100 during the first stage. The first functional simulation model is used until the check performed at step 110 is passed. M& C Ref: PG451104WO

[0158] 26

[0159] For example, the first functional simulation may be based only on optimising against a subset of the output parameters or other requirements specified in the testbench parameters.

[0160] Next, during a second stage performed in lateriterations of steps 110-118, a second functional simulation model that also tests the functionality of circuit designs is used. The second functional simulation model can provide a more accurate and / or more detailed simulation, which could reveal that one or more circuit designs that seemed previously to satisfy the testbench parameters 22 (or to satisfy the subset of testbench parameters) do not in fact satisfy the testbench parameters 22 (e.g. including any additional testbench parameters) or that the optimisation against the testbench parameters could be improved. The second functional simulation model is used in subsequent iterations of steps 110-118 until the check performed at an iteration of step 110 reveals that one or more circuit designs satisfy the testbench parameters 22.

[0161] At a third stage of testing performed in later still iterations, a third simulation model is used. The third simulation model is configured to perform a timing simulation, for instance to assess how quickly the generated circuit designs achieve the outputs specified by the testbench parameters 22 when provided with corresponding inputs. If the tested circuits achieve the intended outputs of the testbench parameters 22 but perform too slowly, for instance, then it can be determined that further iterations are required.

[0162] During the third stage of testing, step 112 may involve an additional step of “synthesising” the generated circuits into a form comprised of specific logic gates. This can be performed using any suitable tool and technique as known in the art.

[0163] In this example embodiment, three batches of iterations of steps 110-118 are completed for the three different stages of testing described above. In general, the method 100 can use any number of stages of testing based on different simulation models, as known in the art, in which case further batches of iterations of steps 110-118 can be performed. For instance, the method 100 can be performed using only a single simulation model, in which case only a single batch of iterations of steps 110-118 may be performed.

[0164] Preferably, however, a plurality of different simulation models are used at different at different iterations of steps 110-118, in order to ensure the generated circuit designs behave as predictably as possible once committed to hardware. In particular, method 100 can include one or more, or all, of the following stages of simulation and testing, which can be performed in the order mentioned: functional testing (at the HDL level), and, after synthesis has been performed: Post Synthesis Static Timing Analysis (STA) and Gate Level Functional Simulation. Subsequently, after circuit designs have been passed to a fitter (sometimes M& C Ref: PG451104WO

[0165] 27

[0166] known as a “place and route”, where the components and wires from the synthesised designs are placed in silicon): Post Fitting STA, which, similar to the Post Synthesis STA extracts the worst-case delays, and a Gate Level Timing Simulation, which verifies that an otherwise functionally correct simulation won't operate incorrectly due to timing issues such as missing or improperly applied timing constraints or, as is most likely, through routing and buffering issues.

[0167] Additionally, between different iterations of steps 110-118 using the same simulation model, less than all of the thresholds or parameters in the testbench parameters 22 may be used to generate the suitability score for each circuit in the method 100. During later iterations also using the same simulation model, a larger subset, or all of, the parameters in the testbench parameters 22 may be assessed by the fitness function. In other words, the number of variables defined in the testbench parameters 22 used to optimise the circuit designs can increase as further optimisation iterations are completed. This can help the method 100 to converge on circuit designs more quickly because the method 100 is not trying to optimise for all variables in the testbench parameters 22 at once. In one example, a specified maximum circuit size and cost (merely as examples) in the testbench parameters 22 may be ignored during earlier iterations and introduced during later iterations. This would help the method 100 converge on a solution that satisfies the remaining parameters (such as circuit power consumption and processing speed) first. Overall, this can improve the performance of the method 100.

[0168] Once the first, second and third stages of testing have been completed, i.e. when one or more circuits pass a check at step 110 during the third stage, the method 100 can proceed to step 122.

[0169] At step 122 a final set of circuit designs is output to the user. The final set of circuit designs can be a subset of the final set of circuit designs generated in steps 110-118 found to satisfy the testbench parameters performed in all stages of testing.

[0170] In this example, the method 100 involves generating about 200 generations (“sets”) of circuit designs across the three stages of testing. However, fewer or more generations can be generated in other embodiments.

[0171] The final set of circuit designs may generally contain a plurality of circuit designs that meet the criteria specified by the user. The final circuit designs can be analysed and sorted according to different metrics to make it easier for the user to select a particular design. For instance, the designs may be sortable by area size, component cost, speed, or any other suitable metric, to provide a range of solutions to meet the needs of different circumstances. M& C Ref: PG451104WO

[0172] 28

[0173] Advantageously, the syntactically complete grammar model 18 together with the use of a grammar model 18 based only on synthesisable components means that each of the final set of circuit designs is guaranteed to be manufacturable. This avoids a further verification step that is time consuming and would otherwise be necessary to ensure that seemingly final circuit designs can be manufactured in practice.

[0174] The final designs can be output to the user in any suitable format known in the art. In the event the method 100 is performed by the computer 2 acting as a server, the final design or set of designs may be forwarded to the user through a network such as the internet.

[0175] In some examples, the method 100 can end at step 122. In this example, the method proceeds to optional step 124.

[0176] In examples, the final design can be used to create instructions for configuring a hardware level reconfigurable device such as a field programmable gate array, ASIC or other hardware programmable logic device (PLD) in order to implement the final design. In examples, the final design or set of designs can be broken down into process stages associated with different manufacturing steps required to manufacture a circuit according to the final design, such as diffusion, ion implantation, oxide layer growth, patterning, etch, and the like. Manufacturing instructions can be created for each process stage for manufacturing a circuit or part of a circuit according to the final design.

[0177] In step 124, one or more prototypes can be made, for example using a field programmable gate array (FPGA) or other programmable logic device, and be subject to further testing as known in the art. One example of how this can be performed is described further below with respect to Figures 9 and 10, in which a first FPGA is used to provide inputs to a second FPGA that is configured according to a generated circuit design. This arrangement can be useful to provide an additional tier of testing and verification of the final circuit design, with the final circuit design being implemented in the second FPGA and the inputs provided by, and the outputs received and optionally analysed for performance by, the first FPGA.

[0178] Optionally, equivalence testing is performed on the prototype, as known in the art.

[0179] In step 126, which is also optional, one or more of the final set of circuit designs are manufactured. The manufactured circuits are manufactured more efficiently because the circuits can be computer-generated both reliably and to a high degree of complexity in a manner that avoids time-consuming verification steps.

[0180] In step 128, which is also optional, the manufactured circuits can be subject to physical testing. For example, the manufactured circuits can be tested to check that they do in fact provide the M& C Ref: PG451104WO

[0181] 29

[0182] output functionality intended and at the level of performance intended. Optionally, if the manufactured circuits are determined not to provide the intended functionality or performance, the method 100 can return to the second or third stage of testing, respectively, or any other stage of testing, so that the designs can be refined further.

[0183] Figure 4 shows a flowchart of a computer-implemented method 200 of circuit generation (i.e., “circuit design”) according to an embodiment of the invention. The method 200 can be implemented using the system 1 as described above with reference to Figure 1, or in a distributed fashion. The method 200 can be implemented as a computer program product. The method 100 described above is a specific example of the more general method 200. Features and steps of the method 100 described above can therefore generally be applied in the method 200.

[0184] In step 202, parameters specifying functionality of a circuit to be designed are received. The parameters can correspond to the testbench parameters 22 described above. Alternatively, the parameters can be of any suitable kind and format that specify how a circuit to be designed is to behave. In one example, step 202 can be performed in the manner of step 101 of the method 100.

[0185] In step 204, one or more circuit designs are optimised based on a (respective) suitability score that depends at least in part on the suitability of the (respective) one or more circuit designs for achieving the specified functionality. Specifically, the optimising involves using a grammar based optimisation engine configured to perform a grammar based optimisation in which the one or more circuit designs and any optimisations accord to a selected grammar that describes the structure and / or behaviour of electronic circuits and is configured to result in synthesisable circuit components.

[0186] The selected grammar can be configured to result in synthesisable circuits by containing circuit elements that can be manufactured in practice only (i.e., by not including circuit elements that can be simulated but cannot be manufactured). Alternatively, or in addition, the selected grammar may contain rules prohibiting the combination of certain circuit components and / or rules specifying how components should be connected, so that stray or incomplete connections are necessarily avoided during the optimisation process. The selected grammar can correspond to the grammar model 18 described above or any other suitable grammar configured to result in synthesisable circuits.

[0187] The grammar based optimisation can be performed in any suitable manner, for instance using genetic programming (such as grammatical evolution) to generate sets of candidate circuit designs that are modified versions of a preceding generated set. One or more simulators can M& C Ref: PG451104WO

[0188] 30

[0189] be used to simulate behaviours of the one or more circuits and generate suitability scores based on the simulated behaviour. The suitability scores may be calculated using the received parameters and one or more functions (such as the fitness functions 24 discussed above). In one example, the optimisation can be performed using the iterative approach of steps 104-118 described above. However, any other optimisation technique known in the art that can be employed.

[0190] In any case, the optimisation is performed using a grammar in order to prevent the generation of circuits that are not manufacturable in practice, or are generated with an incomplete definition that results in an unexpected change in behaviour of the circuit once it is manufactured. This significantly speeds up the time required to manufacture a circuit because hardware verification (verifying a circuit can be manufactured) happens inherently, rather than as a separate (usually time consuming) step.

[0191] In step 208, an optimised circuit design is output from the optimisation of the previous step. The optimised circuit design can be provided as one of several optimised designs determined to exhibit or achieve the functionality specified in the received parameters. The circuit design can be provided in any suitable format.

[0192] 2. Further Background and Specific Example

[0193] The following section describes further background to the invention and a specific example of the method performed to generate and manufacture a design for an application specific integrated circuit (ASIC).

[0194] Problem of the invention

[0195] Many industries rely on digital circuits in some way. These can vary from embedded devices using ARM, RISC-V or low-powered Intel / AMD processors to those using low-volume FPGAs. Designing, testing, and fabricating these can be prohibitively expensive, and HDL code is challenging to use and debug. More recently, high level synthesis (HLS) tools have been used, enabling engineers to write code in higher-level languages such as C, C++ or MATLAB, which are subsequently translated into an HDL. Regardless of whether HDL or HLS to HDL conversion is used, the circuit design relies almost wholly on engineers fully understanding the problem for which the circuit is being created. To summarize, there is currently no fully automated tool for generating digital circuits, which are crucial to many industries. M& C Ref: PG451104WO

[0196] 31

[0197] With a few exceptions, in general, modern circuits are not created from logic gates, rather from HDLs, with the relationship between gate- and HDL-level being analogous to that between Assembler and high-level programming language. HDLs have been around since the 1960s, but really began to gain popularity in the eighties as VLSI (very large-scale integration) ICs became increasingly available. The complexity of their design demanded sophisticated languages to describe circuits, and the CAD flow in Figure 5 became the standard approach. Figure 5 shows a typical computer aided design (CAD) flow for circuit design. The “functional simulation”, “gate level functional simulation” I post synthesis static timing analysis (STA) are simulations and timing while “synthesis” and “fitter” are steps performed by standard tools in the industry. Failure at any of the simulations or analyses results in redesign.

[0198] With reference to Figure 5, first, a circuit model is designed using an HDL and subjected to a functional test to determine if the circuit behaves as expected. Due to the prohibitive costs of mistakes in circuit design, particularly for ASICs, simulator technology in the IC world is very sophisticated; in fact, the common approach is to use an HDL for both the circuit being simulated and to write test routines for the simulator. Testing is such an important part of this world that the majority of time spent by design teams is in testing and verification. In some cases, the designer will perform formal verification while constructing the program (i.e., the HDL model of the circuit); this takes the form of formal assertions that help describe what the circuit should do, e.g. if Property A holds then Property B must also hold. While formal verification doesn't always provide complete testing coverage it can, when it can be used, provide a good first test and sits in front of the functional test.

[0199] Failure at this point requires redesign, and this continues until all tests have been satisfied, at which point the design is compiled into a netlist, which is essentially a set of logic primitives such as AND, OR, NOT, flip-flops, etc. This step, which is analogous to compilation in the software world, is known as synthesis. Two more tests are then applied to the netlist. The first, Post Synthesis Static Timing Analysis (STA), extracts the worst-case delays based on the circuit topology; if these delays are unacceptable, then redesign is required. The second, the Gate Level Functional Simulation, performs what is essentially another functional simulation, but which yields different information from the first. They differ because of how much lower the level is; that is, it is possible that behaviour described in the initial design is too complex to be realised in gates.

[0200] Once the design team is satisfied that the circuit is functionally correct, it is then passed to a Fitter, which performs what is sometimes known as a “place and route”, where the components and wires from the netlist are placed in silicon. Two more timing tests are performed on this circuit, the Post Fitting STA which, similar to the Post Synthesis STA extracts the worst-case M& C Ref: PG451104WO

[0201] 32

[0202] delays, and a Gate Level Timing Simulation, which verifies that an otherwise functionally correct simulation won't operate incorrectly due to timing issues such as missing or improperly applied timing constraints or, as is most likely, through routing and buffering issues.

[0203] Any problems highlighted at this step may be corrected either by using the Fitter to create a different layout, or, possibly, by modifying the design and going back to the Synthesis step. After successfully passing all simulated tests, a FPGA is programmed and configured as a prototype, translating the designed circuit into Logic Equivalents (LEs) and interconnected wires within the physical silicon of the FPGA. Subsequently, final equivalence testing is conducted to verify that the hardware operates correctly. Once the designer confirms satisfaction with the FPGA's output, the netlist along with the design constraint files are forwarded to the foundry and packaging vendor for the fabrication of the ASIC.

[0204] A fully automated system for digital circuit design is proposed herein, which can be referred to as Automatic Design of Digital Circuits (ADDC). The ADDC techniques proposed can include a combination of Machine Learning (ML) and standard silicon simulation tools, providing a fully automated general circuit synthesis tool. Users needs only to provide test benches that specify what the circuit should do, and ADDC automatically generates a physical circuit that performs the task.

[0205] Examples of ADDC disclosed herein use grammar based techniques that can be used to guide the circuit optimisation to correct solutions, particularly Grammatical Evolution (GE), a powerful automatic programming technique. The inventors have used its capability to utilize ML and create a silicon chip design, which has been fabricated. The chip was prototyped on an FPGA board and later fabricated using 65 nm technology. The functional testing and verification of the fabricated chip is described briefly below.

[0206] As discussed, examples of ADDC disclosed herein operate on grammar based techniques, particularly Grammatical Evolution (GE), a form of ML, and can automatically generate software from high-level descriptions, often in the form of test cases resembling regression tests. GE generates candidate solutions, referred to as individuals, which represent potential solutions to an outlined problem. These individuals undergo testing and scoring via a 'fitness function' that assesses their performance based on how effectively they address the test cases. Through iterative refinement, individuals are continuously improved until one emerges that effectively solves all test cases while meeting additional constraints such as size and speed.

[0207] Examples of the present disclosure use a version of GE to automatically generate, test and implement HDL models in hardware, using HDLs, such as Verilog, SystemVerilog and VHDL, M& C Ref: PG451104WO

[0208] 33

[0209] the three most popular HDLs. Examples of target hardware include both FPGAs and ASICs as well as other programmable logic devices (PLDs). The ADDC proposed in examples plugs into, and re-purposes, parts of the traditional CAD flow, using existing, industry standard circuit simulators such as ModelSim and Questa (from Siemens), Incisive Enterprise Simulator (from Cadence), Xilinx Simulator (XSIM) etc. and synthesis tools such as Synopsys Design Compiler NXT, Cadence Genus, Siemens Precision RTL etc.

[0210] Figure 6 shows a flowchart of a method according to an embodiment of the invention, i.e. according to ADDC. The following steps of Figure 6 are steps that can be completed using existing, industry-standard tools and methods: “functional simulation”, “formal verification (possibly)”, “synthesis”, “timing simulation”, and “commit to hardware”. The following components or steps of Figure 6 represent aspects specific to the embodiment of the invention, i.e., part of ADDC: “initialise population”, “create HDL model”, “grammar database”, “create variants of programs”. The method of Figure 6 corresponds to a specific implementation of the method 100 or 200 as described above.

[0211] The fitness function comprises a testbench, the standard CAD method for determining whether a circuit is functionally correct and can also incorporate other constraints. These constraints can include propagation delay, power dissipation, clock frequency (including clock latency, jitter, and skew), etc., of the desired circuit. The output can be a Pareto set (selection) of circuits, each of which satisfies the constraints while offering different trade-offs, e.g. power versus speed, etc.

[0212] A significant inherent feature of the present approach is that verification explicitly occurs within the design generation, eliminating a separate verification step after design. This offers design teams enhanced productivity, as typical verification time costs are more than 60% of the design team’s total time. All testing can be done with the same industry-standard tools that are common in the art, providing backwards compatibility.

[0213] Specific Example - ASIC

[0214] To show the effectiveness of the techniques disclosed herein, ADDC as described herein has been used to create a silicon chip, known as an Application Specific Integrated Circuit (ASIC). The chip is relatively simple (and described below), but has been designed end-to-end in a computer-generated manner using embodiments of the invention. The ASIC described below has been successfully tested.

[0215] The example chip is a Finite Impulse Response (FIR) filter. It was evolved from scratch using the open-source Icarus simulation tool before being synthesised using the Cadence Genus tool. FIR filters are commonly used tools in digital signal processing as they can remove noise M& C Ref: PG451104WO

[0216] 34

[0217] from signals; they are often used in audio processing and telecommunications and have recently seen an uptick in use in ML, specifically for feature extraction and data preprocessing.

[0218] The fitness function in this example was the ability of the circuit to successfully filter a noisy signal, which was measured in two ways, fi and f2:

[0219] - 1 / (n)2

[0220] f = NRMSE =

[0221]

[0222] i max

[0223] f2= 1 — PearsonCorrelation(p, t)

[0224] where n is the number of training cases, p is the vector of predictions, t is the target vector, and max is the maximum possible root mean square error (a measure of how poorly an individual filtered the signal). A perfect circuit would score zero on both functions. In this example, generating the optimised circuit took around 3 hours.

[0225] Figures 7A and 7B show graphs illustrating a collection of generated FIR filter circuits for different numbers of generations (i.e., sets of circuit designs). Each axis represents an output of one of the fitness functions f1, f2, such that dots closer to the origin represent better solutions (or at least solutions with satisfy the fitness functions to a greater extent). Dots of the same colour or pattern represent solutions on the same Pareto front. Each generation represents a single iteration of refinement.

[0226] As shown by the left graph in Figure 7A, after 5 generations, two circuit designs are found. However, as shown by the right graph, after 15 generations of circuit designs have been generated, simulated and tested, many more candidate solutions were found. The left and right graphs of Figure 7B show the number of solutions found after 40 and 200 sets of circuit designs, respectively, had been generated, simulated and tested.

[0227] The fabricated ASIC chip is shown in Figure 8 (right) next to a 50 cent (Euro) coin for comparison (left).

[0228] The evolved (i.e., generated) FIR filter was synthesised on Cadence Genus with 65 nm technology. The synthesised report in Table 1, which shows the chip area, power, and delay comparison with an ideal process but with different voltage and temperature corners, showing the trade-off between power and delay. The maximum and minimum power consumptions are recorded as 21.3 mW at BC and 13.9 mW at WCL, respectively. The maximum and minimum delay recorded are 8303 pS at WCL and 1542 pS at LT, respectively.

[0229] BC LT TO WC WCL M& C Ref: PG451104WO

[0230] 35

[0231] Temperature (Celsius) 0° -40° 25° 125° -40°

[0232] Core Voltage (Volts) 1.32 1.32 1.2 1.08 1.08

[0233] IO Voltage (Volts) 2.75 2.75 2.5 2.25 2.25

[0234] Area (Cell count) 6562 6570 6568 6513 6514 Total Power (in Milliwatt) 21.30 21.00 17.60 14.40 13.90 Datapath Delay (in Pico Second) 1691 1542 5180 7986 8303

[0235] Table 1: Area, power and delay analysis of the evolved FIR ASIC at different corners of TSMC 65nm Technology. BC: Best Case, LT: Low Temperature Best Case, TC: Typical Case, WC: Worst Case, WCL: Worst Case Low Temperature ( -40C).

[0236] The synthesised filter's PnR (place and route) was performed using the Cadence Innovus tool. PnR in chip design involves optimising the physical layout of components and interconnections on a chip to meet performance, power, and area constraints. Power / rail analyses were performed at the post-floor planning and the post-route stages. Detailed signoff Static Timing Analysis (STA) and Gate Level Simulation (GLS) were also performed before fabrication. To ensure that the fabricated design produces the expected outcomes and meets all fabrication requirements, the following steps were performed:

[0237] 1. Static Timing Analysis (STA): Xilinx Design Constraint (XDC) and Synopsys Design Constraint (SDC) files are prepared to ensure the fabricated design meets all timing requirements. The clock signal is generated at a 50 MHz frequency with the desired clock uncertainty, rise and fall delay, and clock latency. The reset signal is set as the ideal network, and the remaining inputs and all outputs are constrained with the desired input and output delays.

[0238] 2. Design Prototyping on AMD Xilinx FPGA Boards: FPGAs are an evolution of Programmable Logic Devices (PLDs), which are reconfigurable circuits. The distinguishing factors between variants of PLDs and FPGAs are typically their internal architecture, interfaces to external sources, and complexity. Two Xilinx Artix-7 FPGA boards are used to test the evolved FIR filter's functionality. The FIR filter core is implemented on the ‘slave’ FPGA board, whereas inputs and outputs are provided / collected by the ‘master’ FPGA board using a Serial Peripheral Interface (SPI). Coordinates of a distorted sinusoidal wave are transmitted through SPI as input from the ‘master’ to the ‘slave’. Later, the same ‘slave’ architecture is implemented on ASIC using TSMC 65 nm technology. M& C Ref: PG451104WO

[0239] 36

[0240] Figure 9 shows SPI interfacing between the “master” and “slave” FPGAs. Figure 10 shows a schematic diagram of the internal architecture of the “slave” FPGA.

[0241] The 'slave' architecture consists of five input signals ('resetEX', 'sck', 'ss', 'mosi', and 'inEX') and two output signals ('miso' and 'outEX'), four of which are standard SPI signals ('sck', 'ss', 'mosi', and 'miso'). The 'sck' and 'ss' signals are the clock signal and slave select signals generated by the 'master,' respectively, 'mosi' carries eight coefficients of 8 bits each, and 'miso' transfers the filtered output bits generated by the FIR filter. 'inEX' is a 10-bit bus that provides inputs to the FIR filter, and 'outEX' is a 22-bit bus that carries the outputs generated by the filter, 'miso' and 'outEX' are used for the same purpose — to accumulate the output bits — but the only difference is the former does it serially, and the latter does it in parallel.

[0242] As mentioned earlier, the ‘master’ and the ‘slave’ are connected using SPI as shown in Figure 9. The coordinates of the distorted sinusoidal wave are pre-loaded in a single port ROM (IP) of the ‘master’ which are transported to the ‘slave’ through the ‘inEX’ bus. The distorted sinusoidal wave is generated using MATLAB.

[0243] The coefficients for the FIR filter are collected from the user through the 'sw0'-'sw7' signals and transmitted to the 'slave' through the 'mosi' signal serially. The 'master' is responsible for generating the signals 'sck' and 'ss' based on the required logic. It is also responsible for accumulating the output bits coming from the 'slave' through the 'miso' signal. Finally, the accumulated 'miso' bits are represented in integer form using eight 7-segment blocks available on the 'master' FPGA board.

[0244] 3. Gate-Level Simulation (GLS): GLS is a post-synthesis simulation that ensures that the output of the design at a higher level of abstraction matches the output of the gate-level netlist. Only the source file gets replaced, whereas the test bench parameters remain the same. Library-specific Verilog / VHDL files are also essential to run the GLS. TSMC 65 nm technology libraries (.v files) were used to run the GLS.

[0245] 3. Other aspects:

[0246] Multi Objective Optimization of Silicon

[0247] The invention uses “Multi-objective optimization” (MOO) to evolve circuits. In the specific example described above, MOO was used to balance between error (minimize) and correlation (maximise). However, various factors can also be used. These factors could include: minimize power consumption; minimize real estate (of silicon) usage; optimize speed of device; minimize latency by implementing functions directly in hardware, bypassing the need for software execution; maximize throughput by efficiently utilizing hardware resources M& C Ref: PG451104WO

[0248] 37

[0249] and optimizing data paths; minimize cost of components, for example, hard core CPUs on FPGAs.

[0250] This will enable the invention to be used to create suites or even libraries of different hardware designs / options for the same problem.

[0251] Incorporating Useful Components

[0252] Some human knowledge was captured prior to evolving the solution. Specifically, the general structure of the FIR filter in terms of delay element (D flip-flop), multiplier and adder were added to the grammar model as useful composite elements of the model. In other examples, the grammar model can include: useful IP blocks; details of on-chip functionality such as RAM, processors, etc., as these are often present on FPGAs; known useful hardware and data structures for the particular circuit being generated. The ability to include likely components as part of the grammar allows the optimisation to better reach likely optimal results.

[0253] Full integration into the EDA flow

[0254] Figure 5 shows the standard EDA flow. The invention could be seamlessly integrated with the Program Design / Functional Simulation / Synthesis / Gate Level Functional Simulation flow, fully automating the process.

[0255] Automatic hardware acceleration

[0256] The system has been designed to generate digital circuits for ASICs. However, the system can easily be adopted to perform hardware acceleration in FPGAs by integrating with software IDEs (Integrated Development Environments), by enabling programmers to dispatch software modules for hardware acceleration even though they have no expertise with silicon design. Natural Language Design

[0257] Due to the structured nature of the system, some examples of the present disclosure could integrate Natural Language Processing (NLP) and Large Language Models (LLMs) to create an interactive system where end-users can specify reguirements using natural language in an iterative way, where the system will reguest more information as reguired.

[0258] Expansion to Analogue Circuits

[0259] Certain of the specific examples above refer to generation of digital circuits but the present disclosure is not limited to this and, surprisingly, it has been found that the above technigues can also be applied to generating analogue circuits. M& C Ref: PG451104WO

[0260] 38

[0261] Analogue and digital IC design, though often part of the same chip, differ fundamentally in their objectives and methodologies. Digital design operates on discrete binary signals, emphasizing logical correctness, clock timing, and scalability, typically through automated flows using Hardware Description Languages (HDLs). Analogue design, on the other hand, deals with continuous-time signals and relies heavily on the subtle control of electrical parameters, such as gain, noise, linearity, and power. These differences become especially pronounced at the transistor level, where analogue design involves crafting current mirrors, biasing networks, and amplifiers with fine-grained control. In contrast, digital design focuses on optimizing standard cells, Static Random Access Memory (SRAM) bit-cells, and critical timing paths. As such, there are core differences between digital and analogue circuit design and there is no expectation that techniques for generating digital circuits will automatically always be similarly useful in generating analogue circuit designs.

[0262] Transistor-level IC design provides deep visibility and control, allowing designers to directly manipulate circuit behaviour based on semiconductor physics and layout interactions. This low-level approach is indispensable in analogue blocks, where performance often hinges on subtle effects such as mismatch, parasitics, and temperature sensitivity. In digital domains, transistor-level design, though less commonly used for full systems, is crucial for high-speed data paths, low-power cells, or where synthesis tools fall short. The ability to custom-tailor these critical elements enables superior performance and power efficiency, often beyond what is possible through HDL-based design alone.

[0263] Figure 11 illustrates an overall analogue or mixed circuit design process.

[0264] At step 1105, the requirements for a circuit are input. This step comprises defining performance specifications such as gain, bandwidth, power, delay, and noise. These performance specifications guide the selection of appropriate circuit topologies. At steps 1110 and 1115 the process continues with system behavioural simulation and defining functional blocks and specifications.

[0265] The block indicated by dashed lines at 1120 involves iteratively adjusting the topology of the circuit and the properties of the circuit components, such as sizing of resistors, to produce an optimal design.

[0266] Once the circuit topology and the properties of the circuit components have been determined, then steps 1125 are performed to realise the designed circuit, such as generating a layout drawing, performing a design rule check (DRC), performing a layout vs schematic (LVC) step, extracting the layout, doing post-layout simulation and evaluation, process, voltage and temperature (PVT) analysis, and / or the like. M& C Ref: PG451104WO

[0267] 39

[0268] An automated optimization of the topology and circuit component properties (i.e. step 1120) of the analogue circuit is performed using an evolutionary technique, such as Grammatical Evolution (GE), as illustrated in Figure 12, and as discussed above. This technique uses a grammar that dictates valid structures of solutions. A fitness function is used to assess how well the generated topology and circuit component properties meet the input circuit requirements (from step 1105). The process is a component I transistor level design process. The grammar 1200 is supplied to an optimization engine 1205 that, in examples, can be a Grammatical Evolution (GE) engine. The grammar 1200 is an attribute grammar used to incorporate semantic constraints, enabling context-aware synthesis of valid circuit topologies and circuit component properties. The grammar 1200 and / or optimization engine 1205 are optionally configured such that only synthesisable circuits are considered and generated, as described above. The grammar 1200 has semantic information embedded directly in the grammar 1200. This allows the system not only to ensure syntactic correctness, but also to enforce design constraints such as node reuse, connectivity integrity, and naming consistency.

[0269] In one possible example, the grammar 1200 can be configured for dynamic variable initialisation. Variables that are updated dynamically are initialized using an equality operator to ensure consistent naming and reuse. The grammar contains at least one or each of: a start symbol, production rules that define how non-terminal symbols are expanded into terminals and other non-terminals, terminals such as signal lines (A, B), Ground, VDD, etc., and nonterminals that are symbols used to structure the grammar. The grammar also contains attribute functions that guide both initialisation and dynamic phenotype construction.

[0270] The optimization engine 1205 is computer implemented and configured to implement an evolutionary algorithm, which in this specific example is an attribute grammar driven grammatical evolution algorithm.

[0271] In this grammatical evolution algorithm, each candidate solution begins as a binary genotype composed of codons. These codons are decoded using the user-defined attribute grammar 1200 to produce a syntactically valid program or model 1210 (such as a SKILL model) representing a complete candidate electrical circuit. The generated program or model 1210 representing the candidate electrical circuit is automatically instantiated as a schematic in a IC circuit design tool 1215 such as Cadence Virtuoso, where the circuit components are connected according to the evolved topology (and the circuit component properties such as device sizing in the case of analogue circuits) for the candidate electrical circuit, as determined by the optimization engine 1205. A custom testbench or other simulator functionality 1220 is then used to simulate the circuit, e.g. using the Spectre simulator. Simulation outputs 1225, M& C Ref: PG451104WO

[0272] 40

[0273] including waveforms and key performance metrics, are extracted and evaluated 1230, and the results are used to compute the fitness of each candidate. In the present example, a multiobjective fitness function that takes into account multiple objectives (which may be competing or trade-offs), such as optimising for metrics such as correctness or other measure of error rate, transistor count or other measure of area, power consumption, gain, delay, linearity, and / or the like. The process is then repeated over a number of iterations until a stop condition is met (e.g. until the value of the fitness function is better than a threshold, or until a certain number of iterations or time has elapsed, etc.). The best candidate circuit at the end of the process is selected as the output. That candidate circuit can then be implemented based on the output, e.g. in a physical circuit or using a hardware level programmable logic device such as an FPGA, ASIC or the like.

[0274] The benefits of the above process have been illustrated by designing simple digital circuits, including a NAND logic gate and an OR logic gate and a simple analogue circuit in the form of a temperature sensor circuit.

[0275] Figures 13 to 16 give the results for example NAND and NOR circuits generated using the optimization engine (e.g. Grammatical Evolution (GE) engine) 1205 from Figure 12 (and the method of Figures 2A and 2B). The circuit performance has been determined for different interpretation thresholds for logic levels, namely 90-10% and 70-30%. These thresholds define voltage bounds used to distinguish logical high and low signals. For example, with a 1 V supply, the 90-10% threshold treats any signal above 900 mV as logic T and any signal below 100 mV as logic ‘O’. Values in between are classified as undefined and penalised accordingly during evaluation.

[0276] From these, it can be seen that the errors produced by the candidates circuits quickly drop to zero within 5 iterations. Similarly, the transistor count (used as a metric of circuit area) of the candidate circuits quickly drops to low values within 5 iterations. The power consumption of the candidate circuits reduces to a low value in a range from 5 to 25 iterations. The logic responses from the final circuits shown in Figure 16 indicates that the final electrical circuits generated provide the appropriate outputs for a given pair of inputs A, B.

[0277] Tables 1 and 2 below provide a performance comparison of the above approach (as explained in relation to Figures 2A, 2B and 12) with some alternative comparative approaches. These tables provide performance metrics for a NAND gate (table 1) and a NOR gate (table 2) designed using the approach of Figures 2A, 2B and 12 against corresponding NAND and NOR gates designed using comparative approaches. In this, the comparative approaches include: the Complementary Metal-Oxide-Semiconductor (CMOS) approach described in Semiconductor, F. CMOS, the ideal logic family, nota de aplicacion 1983; the Gate Diffusion M& C Ref: PG451104WO

[0278] 41

[0279] Input (GDI) described in Morgenshtein, A.; Fish, A., Wagner, I. A, Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits, IEEE transactions on very large scale integration (VLSI) systems 2003, 10, 566-581; and Transmission Gate Logic (TG) described in Milovanovic, D. P.; Litovski, V. B. Fault models of CMOS transmission gate, International journal of electronics 1991, 71, 675-683. The evolved designs are those generated using the approach of Figures 2A, 2B and 12 with logic levels 90-10% and 70-30%.

[0280] From these, it can be seen that the circuits generated according to the evolved designs, at both threshold levels, demonstrated 100% functional correctness. Notably, the evolved design NAND and NOR circuits outperformed their conventional counterparts across all evaluated parameters, with the exception of propagation delay in the GDI-based design. Given the well- known trade-off between power consumption and delay, a comparison based on the Power- Delay Product (PDP) is also assessed. In this metric as well, the evolved circuits showed a clear advantage over the comparative approaches.

[0281] NAND CMOS TG GDI Evolved (90-10%) Evolved (70-30%) No of Transistors 4 8 4 3.3 Average Power (W) 12.66 n 29.99 n 14.05 n 9.201 n 8.99 n Delay (s) 121.6 p 127.4 p 92.32 p < J< p PDP (WsorJ) 1.539 a 3.821 a 1.2”“.; 1.137 a 0.822 a

[0282]

[0283] n (nano):10-9; p (pico):10-12; f (femto):10-15; a (atto):10-18

[0284] Table 1: Performance Comparison of an Evolved Digital Circuit Design of a NAND gate against Comparative Techniques

[0285] NOR CMOS TG GDI Evolved (90-10%) EvoNed (70-30%) No of Transistor 4 8 4 3 3 Average Power (W) 6.934 n 24.24 n 5.834 n 5.834 n Delay (s) 154.7 p 117.9 p 83.18 p 137.9 p 137,9 p PDP (Ws or J) 1.073 a 2.858 a 012 a 0.805 a 0.805 a

[0286]

[0287] n (nano):10“9; p (pico):10“12; f (femto):10“i:i; a (atto): 10

[0288]

[0289] Table 2: Performance Comparison of an Evolved Digital Circuit Design of a NOR gate against Comparative Techniques

[0290] Whilst the logic gate examples given above relate to design of digital circuits, the performance of the approach of Figures 2A, 2B and 12 applied to an example analogue circuit in the form of a temperature sensor circuit is shown in Table 3 below. Whilst the digital circuits assessed in Tables 1 and 2 were generated by applying the grammatical evolution engine 1120 to the topology of the circuits only, the analogue circuit assessed in Table 3 was generated by M& C Ref: PG451104WO

[0291] 42

[0292] applying the grammatical evolution engine 1120 to the topology and to the properties of the circuit components (such as the size of circuit components such as resistors) of the circuits. The comparative circuit is an existing “gold standard” circuit.

[0293] Temperature Sensor Gold Circuit Evolved Best Fit Ir Sensitivity (V / °C) 1.18 m 1.3 in INL (V) 6.94 m 2.40S m Nominal Temp Static Power (W) 15.6 p 4.524 u Area (m2) 184 p 149.8 f No. of Transistor 5 2 No. of Resistor 2 0

[0294]

[0295] n (nano):10-9; p (pico):10-12; f (femto):10-15; a (atto):10-18

[0296] Table 3: Performance Comparison of an Evolved Digital Circuit Design of a NAND gate against Comparative Techniques

[0297] From these results it can be seen that the best fit evolved design of temperature circuit outperforms the existing “gold standard” design over every metric, including sensitivity, linearity (INL), static power at nominal temperature, area, no. of transistors and no. of resistors. As such, whilst some adaptations are preferably made to the grammatical evolution engine (i.e. applying the grammatical evolution approach to both circuit topology and circuit component parameters such as component size, rather than to circuit topology only as in the case of the digital circuit generation, it can be seen that the above techniques are surprisingly as applicable to analogue and mixed circuit design as they are to digital circuit design. Another difference between the application of the above techniques to analogue circuits to the application to digital circuits is that the multi-objective fitness functions are different. For digital circuit design, a fitness-function that includes at least one or each of: error rate or other metric of circuit errors, transistor count ort other metric representative of area and / or average power consumption is used. For analogue circuit design, a fitness-function that includes at least one or each of: sensitivity, total circuit area, linearity, and / or static power consumption is used. Recap

[0298] A key aspect of this invention is the ability to create synthesizable circuits. There has been a significant amount of prior work that simulatable circuits, that is, circuits which can be tested in a simulator, but a successful simulation does not guarantee that the circuit can be synthesized in silicon. This is because simulation can include non-synthesizable constructs that behave correctly in a software environment but cannot be mapped to actual hardware components, and timing issues or resource constraints might not be fully accounted for in the M& C Ref: PG451104WO

[0299] 43

[0300] simulation process. Moreover, missing conditions or incomplete logic can lead to the unintended generation of latches during the synthesis process, which in turn creates timing problems, debugging challenges, and non-portable designs.

[0301] Synthesizable circuits can be created by default because the grammar utilized in the Grammatical Evolution (GE) engine is explicitly designed to generate individuals (circuits) using synthesizable constructs only. This approach ensures that the search process is inherently limited to hardware-compatible constructs, avoiding issues related to missing conditions or incomplete logic definitions. As a result, every generated circuit is optimized and ready for direct implementation. Beneficially, and surprisingly, Grammatical Evolution and similar approaches have been found to be effective in simulation of not only digital circuits but also analogue circuits, albeit with slightly differing implementations.

[0302] In some examples, the generation of digital circuits comprises logic synthesis, which is the process of converting high-level Hardware Descriptions Language (HDL) code (typically in Verilog or VHDL) into a gate-level representation. This step translates abstract logic and behaviour into a network of logic gates (AND, OR, NOT, etc.) and digital components that can be physically implemented on a chip. The goal is to optimize the design for performance, power, and area while ensuring it meets functional requirements. Logic synthesis bridges the gap between high-level design and physical implementation in digital circuit design. IN many cases, digital circuits can be generated by using the GE engine (or similar grammatical approach) to optimise the digital circuit topology only.

[0303] Certain HDL constructs are non-synthesizable — useful for simulation but not translatable into hardware. This complexity underscores the need for skilled engineers in IC design. In the ADDC project, Grammatical Evolution (GE), a machine learning technique, is used to generate synthesizable HDL code. The best circuit is selected based on its fitness score. To validate that GE-generated designs are hardware-implementable, one of the evolved circuits is prototyped on the AMD Xilinx Nexys-A7 FPGA board, then fabricated as a chip (ASIC) using 65 nm technology.

[0304] In some examples, the generation of analogue circuits comprises using the Grammatical Evolution (GE) engine to optimise both the topology of the circuit and parameters (such as size) or some or all of the circuit components (such as resistors or the like), which may be done simultaneously and / or within the same simulation. As illustrative examples, SKILL (or other suitable scripting language)-driven automation can be used for schematic and layout generation, and attribute grammars may be used to ensure that all generated circuit design and / or SKILL code is both syntactically and semantically valid, so that each individual represents a legal circuit topology that can be instantiated and simulated directly within a M& C Ref: PG451104WO

[0305] 44

[0306] simulator or layout suite. In some cases, multi-objective fitness functions can be used to allow for simultaneous optimization for a plurality of objectives (which may be competing), such as two or more of: correctness, total circuit area, number of transistors or other circuit components, amount or rate of errors, power consumption, average power, static power, gain, delay, lag, linearity, skew, sensitivity, and / or the like.

[0307] The specific examples described above in relation to the figures are only examples of how the present concepts could be implemented and the present disclosure is not limited to these narrow examples but variations are possible within the scope of the claims.

Claims

M& C Ref: PG451104WO45Claims1. A computer-implemented method for circuit generation, comprising:receiving parameters specifying functionality of a circuit to be designed;optimising one or more circuit designs based on a suitability score that depends at least in part on the suitability of the one or more circuit designs for achieving the specified functionality; whereinthe optimising comprises using a grammar based optimisation engine configured to perform a grammar based optimisation in which the oneor more circuit designs and any optimisations accord to a selected grammarthat describes the structure and / or behaviour of electronic circuits and configured to result in synthesisable circuit components; andthe optimising outputs an optimised circuit design.

2. The computer-implemented method of claim 1, wherein the circuit is an analogue circuit and the optimising comprises optimising both a circuit topology and one or more properties of circuit components of the circuit.

3. The computer-implemented method of claim 2, wherein the one or more properties comprises a size of at least one of the circuit components of the circuit.

4. The computer-implemented method of claim 1, wherein the circuit is a digital circuit and the optimising is a transistor level optimisation that comprises optimising a circuit topology.

5. The computer-implemented method of any preceding claim, wherein the selected grammar comprises a plurality of electronic circuit elements that can be combined with one another to form a circuit design, each electronic circuit element comprising either a single circuit component or a combination of circuit components, and wherein a subset of the plurality of electronic circuit elements comprises predefined combinations of circuit components; optionally wherein each of the one or more circuit designs comprises a combination of electronic circuit elements of the plurality of electronic circuit elements, and wherein the optimising includes generating variants of the one or more circuit designs by: combining subsets of electronic circuit elements from two or more previously generated circuit designs, or replacing one or more elements of aM& C Ref: PG451104WO46previously generated circuit design with one or more different electronic circuit elements, to form a new circuit design.

6. The computer-implemented method of claim 5, wherein the selected grammar comprises one or more rules prohibiting the combination of two or more particular electronic circuit elements in a circuit design to avoid generating non-functioning circuit designs.

7. The computer-implemented method of any of the preceding claims, wherein the one or more circuit designs comprise components of a hardware description language expressed in a formal grammar.

8. The computer-implemented method of any of the preceding claims, wherein the optimising comprises simulating iteratively a behaviour of the one or more circuit designs, and wherein, during one or more earlier cycles of simulating iteratively, a first simulation model is used, and, during one or more later cycles of simulating iteratively, a second simulation model is used that different from the first simulation model; optionally wherein the first simulation model is configured to provide less information about a simulated circuit but to execute more quickly compared to the second simulation model and the second simulation model is configured to provide more information, or more accurate information, about a simulated circuit but to execute less quickly compared to the first simulation model; or optionally wherein the first simulation model is configured to perform a functional simulation that simulates a behaviour of a simulated circuit, and wherein the second simulation model is configured to perform a gate-level simulation that simulates a behaviour of the simulated circuit after the circuit has been converted to a corresponding circuit of logic gates.

9. The computer-implemented method of any of the preceding claims, wherein the optimising comprises simulating iteratively a behaviour of the one or more circuit designs, and wherein, during one or more cycles of simulating iteratively, the one or more circuits are optimised using less than all of the received parameters.

10. The computer-implemented method of any of the preceding claims, wherein the optimising is performed using a grammar-based machine learning tool or wherein theM& C Ref: PG451104WO47method further comprises manufacturing a circuit according to the optimised one or more circuit designs.

11. The computer-implemented method of any of the preceding claims, wherein receiving parameters specifying functionality of a circuit to be designed comprises receiving, from a user, testbench parameters specifying functionality of a circuit to be designed, the testbench parameters comprising sets of one or more input parameters and corresponding sets of one or more output parameters, optionally wherein at least one of the one or more output parameters corresponds to a functionality of the circuit to be designed.

12. The computer-implemented method of any of the preceding claims, wherein receiving parameters specifying functionality of a circuit to be designed comprises receiving one or more performance parameters specifying a performance of the circuit to be designed.

13. The computer-implemented method of claim 12, wherein the one or more performance parameters specify one or more of: a threshold power consumption, a threshold circuit area, a threshold processing speed, a threshold latency, a threshold throughput, or a threshold component cost.

14. The computer-implemented method of any of the preceding claims, wherein the optimising comprises:simulating a behaviour of each one or more circuit designs and determining a suitability score for each circuit design using one or more fitness functions that quantify the extent to which sets of output parameters in the received parameters are achieved when each of the one or more circuits are provided with corresponding inputs of the received parameters, optionally wherein the optimising comprises:subsequently, determining, based on the suitability scores, that a condition is not met by any of the one or more circuit designs;generating iteratively, sets of variants of circuit designs, and simulating iteratively a behaviour of each circuit design in each set of variants to determine a suitability score for each circuit design using the one or more fitness functions;M& C Ref: PG451104WO48wherein each set of variants is generated by modifying a corresponding previous set of circuit designs, such that previous circuit designs having higher suitability scores are more likely to be selected to generate a subsequent set of variants; andwherein the generating iteratively and simulating iteratively are repeated until a final set of variants is generated and determined, based on corresponding suitability scores, to include one or more circuit designs that meet the condition.

15. The computer-implemented method of any of claim 15, wherein the one or more fitness functions comprises a multi-objective fitness function, and the objectives reflected in the fitness function include objectives based on at least two of: amount or rate of errors, accuracy, power consumption, total circuit area, number of transistors and / or other circuit components,16. A computer system comprising:one or more processors; anda memory storing executable instructions that, once executed by theone or more processors, cause the one or more processors to perform steps comprising:receiving parameters specifying functionality of a circuit to be designed;optimising one or more circuit designs based on a suitability score that depends at least in part on the suitability of the one or more circuit designs for achieving the specified functionality; whereinthe optimising comprises using a grammar based optimisation engine configured to perform a grammar based optimisation in which the oneor more circuit designs and any optimisations accord to a selected grammar that describes the structure and / or behaviour of electronic circuits and configured to result in synthesisable circuit components; andthe optimising outputs an optimised circuit design.

17. A computer program product which, when executed by one or more processors, causes the one or more processors to perform the method of claim 1.M& C Ref: PG451104WO4918. A non-transitory computer readable medium storing instructions which, when executed by a processor, cause the processor to perform steps comprising:receiving parameters specifying functionality of a circuit to be designed;optimising one or more circuit designs based on a suitability score that depends at least in part on the suitability of the one or more circuit designs for achieving the specified functionality; whereinthe optimising comprises using a grammar based optimisation engine configured to perform a grammar based optimisation in which the one or more circuit designs and any optimisations accord to a selected grammar that describes the structure and / or behaviour of electronic circuits and configured to result in synthesisable circuit components; andthe optimising outputs an optimised circuit design.

19. A computer-implemented method of designing a circuit, comprising:receiving, from a user, testbench parameters specifying intended functionality of a circuit to be designed, the testbench parameters comprising sets of one or more input parameters and corresponding sets of one or more output parameters;generating, using a subset of a grammar of circuit components, the subset of the grammar corresponding to manufacturable circuit components, an initial set of circuit designs in a hardware description language;simulating a behaviour of each circuit design of the initial set of circuit designs and determining a suitability score for each circuit design using one or more fitness functions that quantify the extent to which the sets of output parameters are achieved when each initial circuit is provided with inputs corresponding to the respective sets of input parameters;determining, based on the suitability scores, that a condition is not met by any of the circuit designs in the initial set of circuit designs;generating iteratively, sets of variants of circuit designs, and simulating iteratively a behaviour of each circuit design in each set of variants to determine a suitability score for each circuit design using the one or more fitness functions;wherein each set of variants is generated probabilistically by modifying a corresponding previous set of circuit design, such that previousM& C Ref: PG451104WO50circuit designs having higher suitability scores are more likely to be selected to generate a subsequent set of variants;wherein the generating iteratively and simulating iteratively are repeated until a final set of variants is generated and determined, based on corresponding suitability scores, to include one or more circuit designs that meet the condition; andoutputting the one or more circuit designs to a user.

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