Display device

Abstract

The present invention provides a novel display device. The first element layer is provided with a signal conversion circuit, a storage circuit, a processor circuit, and a display drive circuit. The second element layer is provided with a pixel circuit electrically connected to a monitor line, and a signal readout circuit electrically connected to the signal conversion circuit via a monitor current line. The signal readout circuit has a function of transmitting a current flowing through the pixel circuit to the monitor current line via the monitor line. The signal conversion circuit has a function of converting the amount of current flowing through the monitor current line into a digital signal. The storage circuit has a function of storing the digital signal. The processor circuit has a function of correcting the data voltage supplied from the display drive circuit to the pixel circuit in accordance with the digital signal.

Description

Display device

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods.

[0003] In recent years, higher definition of display devices has been demanded. As devices that require high-definition display devices, for example, there are devices for virtual reality (VR: Virtual Reality), augmented reality (AR: Augmented Reality), substitutional reality (SR: Substitutional Reality), or mixed reality (MR: Mixed Reality), and they have been actively developed in recent years. VR, AR, SR, and MR are also collectively called xR.

[0004] In display devices used in devices for xR, miniaturization is required in addition to higher definition. Examples of display devices for xR include light-emitting devices having light-emitting elements such as organic EL (Electro Luminescence) elements and light-emitting diodes (LED: Light Emitting Diode).

[0005] For display devices used in devices for xR, configurations that are multifunctional in addition to higher definition and miniaturization have been proposed. For example, in Patent Document 1 and Patent Document 2, in addition to configurations related to image display such as pixel circuits and display driving circuits, functional circuits having functions for performing arithmetic processing such as image processing are provided integrally with configurations such as pixel circuits and display driving circuits.

[0006] International Publication No. 2022 / 118141 International Publication No. 2022 / 118151

[0007] Display devices used for xR (extended rayography) have small pixel sizes per pixel. Therefore, it can be difficult to increase the number of transistors in the pixel circuit. When the number of transistors in the pixel circuit is small, it can be difficult for the transistor that controls the amount of current flowing to the display element (driver transistor) to control other transistors in the pixel circuit and correct variations in the electrical characteristics of the drive transistor (internal correction operation).

[0008] Furthermore, to compensate for variations in the electrical characteristics of the drive transistors, there is an operation (external correction operation) that monitors the current flowing through the drive transistors outside the pixel circuit and corrects the data voltage supplied to the drive transistors according to the monitored current value. In the external correction operation, the current value is converted into a digital signal to correct the data voltage. However, because the pixel size of display devices used in xR equipment is small, the current to be monitored becomes small, and external correction operation may become difficult.

[0009] Furthermore, external correction operation requires a memory circuit to store a digital signal corresponding to the read current value. However, providing a separate memory circuit from the display unit may lead to an increase in the size of the display device and manufacturing costs. Similarly, providing various circuits for reading the signals necessary for external correction operation separately from the display unit may also lead to an increase in the size of the display device and manufacturing costs.

[0010] One aspect of the present invention aims to provide a display device with excellent display quality. Alternatively, one aspect of the present invention aims to provide a miniaturized display device. Alternatively, one aspect of the present invention aims to provide a display device with excellent convenience. Alternatively, one aspect of the present invention aims to provide a novel display device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0012] One aspect of the present invention is a display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor having a semiconductor layer with a channel formation region made of silicon, the second element layer has a second transistor, the second transistor having a semiconductor layer with a channel formation region made of oxide semiconductor, the first element layer is provided with a signal conversion circuit, a memory circuit, a processor circuit, and a display driving circuit, the second element layer is provided with a pixel circuit electrically connected to a monitor line and a signal readout circuit electrically connected to the signal conversion circuit via a monitor current line, the signal readout circuit has the function of transmitting the current flowing through the pixel circuit via the monitor line to the monitor current line, the signal conversion circuit has the function of converting the amount of analog current flowing through the monitor current line into digital correction data, the memory circuit has the function of storing the correction data, and the processor circuit has the function of correcting the data voltage supplied from the display driving circuit to the pixel circuit according to the correction data.

[0013] In one embodiment of the present invention, a display device is preferred in which the pixel circuit includes a light-emitting element and a transistor that supplies a current to the light-emitting element according to the data voltage, and the current flowing through the monitor line is the current flowing through the transistor.

[0014] In one embodiment of the present invention, a display device is preferred in which the signal conversion circuit includes an integrating circuit that converts the amount of current flowing through a monitor current line into an analog voltage value, and an analog-to-digital conversion circuit that converts the voltage value into digital correction data.

[0015] In one embodiment of the present invention, a display device is preferred in which the monitor lines are arranged in a direction parallel to the surfaces of the first element layer and the second element layer, and the monitor current lines have portions arranged in a direction perpendicular to the surfaces of the first element layer and the second element layer.

[0016] In one embodiment of the present invention, a display device is preferred which has a third element layer having a second transistor, the third element layer being provided between a first element layer and a second element layer, and the third element layer having a memory circuit.

[0017] In one embodiment of the present invention, the oxide semiconductor is preferably indium oxide, and this is used in the display device.

[0018] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings.

[0019] One aspect of the present invention can provide a display device with excellent display quality. Alternatively, one aspect of the present invention can provide a miniaturized display device. Alternatively, one aspect of the present invention can provide a display device with excellent convenience. Alternatively, one aspect of the present invention can provide a novel display device.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0021] Figure 1A is a schematic diagram illustrating an example of the configuration of a display device, and Figure 1B is a block diagram illustrating an example of the configuration of a display device. Figure 2 is a schematic diagram illustrating an example of the configuration of a display device. Figure 3A is a block diagram illustrating an example of the configuration of a display device, and Figure 3B is a schematic diagram illustrating an example of the configuration of a display device. Figures 4A, 4B, 4C, and 4D are circuit diagrams illustrating an example of the configuration of a display device. Figures 5A, 5B, 5C, and 5D are circuit diagrams illustrating an example of the configuration of a display device. Figures 6A, 6B, 6C, and 6D are circuit diagrams illustrating an example of the configuration of a display device. Figures 7A and 7B are timing charts illustrating an example of the configuration of a display device, and Figure 7C is a circuit diagram illustrating an example of the configuration of a display device. Figure 8A is a timing chart illustrating an example of the configuration of a display device, and Figure 8B is a circuit diagram illustrating an example of the configuration of a display device. Figures 9A and 9B are circuit diagrams illustrating an example of the configuration of a display device. Figures 10A and 10B are circuit diagrams illustrating an example of the configuration of a display device. Figures 11A, 11B, and 11C are schematic diagrams illustrating an example of the configuration of a display device. Figure 12A is a schematic diagram illustrating an example of the configuration of a display device, and Figure 12B is a block diagram illustrating an example of the configuration of a display device. Figure 13 is a schematic diagram illustrating an example of the configuration of a display device. Figures 14A, 14B, 14C, and 14D are circuit diagrams illustrating an example of the configuration of a display device. Figures 15A and 15B are schematic diagrams illustrating an example of the configuration of a display device. Figure 16 is a schematic cross-sectional diagram illustrating an example of the configuration of a display device. Figure 17 is a schematic cross-sectional diagram illustrating an example of the configuration of a display device. Figure 18 is a schematic cross-sectional diagram illustrating an example of the configuration of a display device. Figure 19 is a schematic cross-sectional diagram illustrating an example of the configuration of a display device. Figures 20A, 20B, 20C, 20D, and 20E are schematic diagrams illustrating an example of electronic equipment.

[0022] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different forms, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0023] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0024] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "A", "b", "_1", "[n]", or "[m,n]". Also, when describing something common to multiple elements that have been given identifying numerals, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0025] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state in an n-channel transistor is defined as the voltage V between the gate and source. ｇｓ The threshold voltage V ｔｈ Lower than (in p-channel transistors, V ｔｈ This refers to a state that is higher than [a certain value].

[0026] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. For example, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0027] In this specification and in the drawings, the X, Y, and Z directions may be defined to explain the arrangement of each element. The X, Y, and Z directions are perpendicular or approximately perpendicular to each other. In this specification, the X direction is referred to as the row direction, the Y direction as the column direction, and the Z direction as the vertical direction.

[0028] (Embodiment 1) A display device according to one aspect of the present invention will be described.

[0029] <Example of Display Device Configuration> Figures 1A and 2 are perspective views of a display device 100 according to one aspect of the present invention. Figure 1B is a block diagram illustrating the configuration of the display device 100. The display device 100 comprises an element layer 20, an element layer 30 on the element layer 20, and a sealing substrate 40 on the element layer 30. In Figure 2, the element layer 20, the element layer 30, and the sealing substrate 40 are shown separated to make the configuration of the display device 100 easier to understand.

[0030] The element layer 20 includes, for example, a processor circuit 21, a display driving circuit 22, a signal conversion circuit 23, a memory circuit 71, and a terminal section 29.

[0031] Each circuit in the element layer 20 is composed of Si CMOS transistors, for example, transistors (Si transistors) in which the semiconductor layer in the channel formation region is silicon. The element layer 20 is an element layer having Si transistors. By composing multiple circuits such as the processor circuit 21, the display driving circuit 22, the signal conversion circuit 23, and the memory circuit 71 with Si transistors, each circuit for which a high degree of integration is desirable can be provided in the element layer 20.

[0032] Furthermore, by making the element layer 20 an element layer having Si transistors, it can be configured to have various functional circuits such as sensor circuits, communication circuits, and control circuits. Also, by arranging the display drive circuit 22, processor circuit 21, signal conversion circuit 23, and memory circuit 71 on the same layer, the processor circuit 21, signal conversion circuit 23, and memory circuit 71 can be arranged in the area of ​​the element layer 20 where the display drive circuit 22 is not located. This increases the freedom of layout, such as distributing the processor circuit 21, signal conversion circuit 23, and memory circuit 71 on the element layer 20.

[0033] For Si transistors, using highly crystalline silicon, particularly single-crystal silicon or polycrystalline silicon, is preferable because it allows for high field-effect mobility and enables faster operation.

[0034] The element layer 30 is provided on top of the element layer 20. The element layer 30 includes, for example, a display unit 31 and a signal readout circuit unit 25. As shown in Figure 1A, a sealing substrate 40 is provided on the element layer 30.

[0035] The element layer 30 on which the display unit 31 is provided is a semiconductor layer having a channel formation region, and the semiconductor layer having an oxide semiconductor transistor (OS transistor). With this configuration, the display unit 31 having the OS transistor can be laminated with the element layer 20.

[0036] OS transistors have the characteristic of having a very low off-current. Therefore, when OS transistors are used, especially in pixel circuits, the written data can be retained for a long period of time.

[0037] Examples of metal oxides used in OS transistors include indium oxide (also called In oxide or indium oxide), gallium oxide (Ga oxide), and zinc oxide (also called Zn oxide or zinc oxide). In addition, In-Zn oxide can be used as the metal oxide used in OS transistors. Furthermore, it is preferable that the metal oxide contains two or three elements selected from indium, element M, and zinc. Element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, it is preferable that element M is one or more elements selected from aluminum, gallium, yttrium, and tin.

[0038] Furthermore, when indium oxide is used as the metal oxide applied to an OS transistor, using highly crystallinity, preferably single-crystal indium oxide, allows for an OS transistor that possesses excellent off-current characteristics as well as excellent on-current characteristics. In addition, transistors with indium oxide in the semiconductor layer have smaller hysteresis in the Id-Vg characteristic (drain current characteristics with respect to gate voltage) and better electrical characteristics compared to transistors with low-temperature polysilicon in the semiconductor layer, making them suitable for current flow during external correction operations.

[0039] Furthermore, the display section 31 of the element layer 30 has a light-emitting element. The luminescence brightness of the light-emitting element is controlled by the current flowing through the transistors of the pixel circuit 51. The light-emitting element can be considered as part of the pixel circuit 51.

[0040] Next, the various configurations of the element layer 20 and the element layer 30, as shown in Figures 1A, 1B, and 2, will be described.

[0041] The display unit 31 provided on the element layer 30 has a plurality of pixel circuits 51. The pixel circuits 51 of the display unit 31 have an OS transistor configuration. The pixel circuits 51 correspond to the pixel circuits of sub-pixels (sub-pixels) for color display. Details of the pixel circuits 51 and light-emitting elements will be described later.

[0042] Each sub-pixel controls the amount of light emitted, whether red, green, or blue. The colors of light controlled by each of the three sub-pixels are not limited to a combination of red (R), green (G), and blue (B); they can also be cyan (C), magenta (M), and yellow (Y). Furthermore, the areas of the three sub-pixels do not have to be the same. If the luminous efficiency and reliability differ depending on the emitted color, the area of ​​the sub-pixels can be varied for each emitted color.

[0043] The signal readout circuit section 25 provided in the element layer 30 has the function of selectively outputting the current flowing through the pixel circuit 51. Specifically, it has the function of transmitting the current flowing within the pixel circuit 51 to the wiring connected to the signal conversion circuit (hereinafter sometimes referred to as the monitor current line) via the wiring connected to the pixel circuit 51 (hereinafter sometimes referred to as the monitor line). The signal readout circuit section 25 has a signal readout circuit 26 that transmits the current flowing through the monitor line of each row to the monitor current line. Details of the signal readout circuit 26 will be described later.

[0044] The signal conversion circuit 23 provided in the element layer 20 has the function of converting the amount of analog current flowing through the monitor current line into correction data of digital value. Specifically, it has an integrating circuit that converts the amount of analog current flowing through the monitor current line into an analog voltage value, and an analog-to-digital conversion circuit that converts the analog voltage value into correction data of digital value. Details of the signal conversion circuit 23 will be described later.

[0045] The memory circuit 71 provided in the element layer 20 has the function of storing correction data obtained by the signal conversion circuit 23. The correction data stored in the memory circuit 71 corresponds to the data acquired for each pixel circuit 51 of the display unit 31. For example, this includes data corresponding to the current flowing through the drive transistor of the pixel circuit 51, and data corresponding to the current flowing through the light-emitting element of the pixel circuit 51.

[0046] The memory circuit 71 includes multiple memory cells. Various types of memory devices can be used as the memory circuit 71. For example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), Phase-Change Memory (PCM), Resistive Random Access Memory (ReRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Memory (FeRAM), Antiferroelectric Memory, etc. can be used.

[0047] The processor circuit 21 provided in the element layer 20 is connected to the memory circuit 71 of the element layer 20 and has the function of executing processing based on the program and correction data held in the memory circuit 71. The memory circuit 71 holds a program for correcting image data and correction data for correcting image data. The processor circuit 21 corrects the image data input via the terminal section 29 based on the program for correcting image data and the correction data for correcting image data. The processor circuit 21 has the function of correcting the data voltage supplied from the display drive circuit 22 to the pixel circuit of the display section 31 according to the corrected image data.

[0048] The processor circuit 21 can correct the image data supplied to the display device 100 by performing calculations based on correction data corresponding to the current flowing through the drive transistors acquired for each pixel circuit of the display unit 31. Preferably, the magnitude of each current flowing through the pixel circuit 51 corresponds to the data voltage applied to the pixel circuit 51, but this changes according to variations in the electrical characteristics of the drive transistors. Therefore, by periodically applying a voltage based on a correction signal (correction signal) to the pixel circuit 51 and measuring the current corresponding to that voltage, the processor circuit 21 can correct the image data by referring to the correction data based on the magnitude of that current, thereby enabling a display in which the amount of current for each pixel circuit 51 due to variations in the electrical characteristics of the drive transistors is corrected.

[0049] Since the measurement of the current using the correction signal is performed for each pixel circuit 51, the measurement takes time. Therefore, it is preferable to configure the device to periodically update the correction data during times when the display device 100 is not used on a daily basis, such as at night.

[0050] The display driving circuit 22, provided in the element layer 20, is connected to the display unit 31 provided in the element layer 30. The display driving circuit 22 includes, for example, a gate line driving circuit 32 and a source line driving circuit 33. The gate line driving circuit 32 is a circuit that drives the gate lines connected to the pixel circuits 51 of the display unit 31. The gate lines are wiring to which scanning signals are supplied, and are sometimes simply referred to as wiring. The source line driving circuit 33 is a circuit that drives the source lines connected to the pixel circuits 51 of the display unit 31. The source line driving circuit 33 includes a digital-to-analog conversion circuit that outputs a data voltage corresponding to the corrected image data, an amplifier circuit that amplifies the data voltage and outputs it to the source line, etc. The source line is wiring to which a voltage for performing external correction operations is supplied in addition to the data voltage.

[0051] Flexible printed circuits (FPCs) and the like are connected to the terminal portion 29. The diagram shows an example where the element layer 30 and the sealing substrate 40 are not formed in the area overlapping with the terminal portion 29, but the terminal portion 29 can also be formed in the element layer 30.

[0052] FIG. 3A is a schematic diagram for explaining an external correction operation in a display device according to an aspect of the present invention. FIG. 3B is a schematic diagram showing the connection of each circuit included in the element layer 20 and the element layer 30 provided on top of the element layer 20. In the schematic diagram shown in FIG. 3A, the X direction, the Y direction, and the Z direction are defined to explain the arrangement of each element constituting the display device 100. For example, in the schematic diagram shown in FIG. 3B, it can be said that the element layer 20 and the element layer 30 are provided so as to overlap in the Z direction (vertical direction).

[0053] The pixel circuit 51 shown in FIG. 3A includes a light-emitting element and a driving transistor that supplies a current corresponding to the data voltage V ＤＡＴＡ to the light-emitting element. The data voltage V ＤＡＴＡ is a voltage supplied from a source line driving circuit via a source line SL connected to the pixel circuit 51. The source line SL may simply be referred to as a wiring. In the external correction operation, a voltage by a correction signal V ＭＯＮＩ is applied to the driving transistor to read out the current (monitor current I ＭＯＮＩ ) flowing through the driving transistor to the outside of the pixel circuit 51, the read current is converted and stored as correction data D Ｃ , and the data voltage V Ｃ supplied to the driving transistor is corrected according to the correction data D ＤＡＴＡ .

[0054] In FIG. 3A, a correction signal V ＭＯＮＩ is supplied to the source line SL, and the state of operating so that the monitor current I ＭＯＮＩ flowing through the driving transistor included in the pixel circuit 51 flows through the monitor line ML is illustrated. The correction signal V ＭＯＮＩ is a signal supplied from a source line driving circuit via the source line SL. The monitor current I ＭＯＮＩ is transmitted to the signal readout circuit unit 25 via the monitor line ML.

[0055] The signal readout circuit section 25 has a signal readout circuit 26 connected to the monitor line ML. In Figure 3A, one signal readout circuit 26 is shown for one pixel circuit 51, but it is also possible to have one signal readout circuit 26 for multiple pixel circuits 51. Since the signal readout circuit 26 is provided corresponding to the pixel circuit of each row, the signal readout circuit section 25 can be made smaller.

[0056] The signal readout circuit 26 is connected to the pixel circuit 51 via the monitor line ML and to the signal conversion circuit 23 via the monitor current line MOL. During external correction operation, the signal readout circuit 26 receives the monitor current I flowing through the monitor line ML. ＭＯＮＩ It has the function of selectively transmitting the current to the monitor current line MOL. The signal readout circuit 26 also has the function of supplying a constant potential V0 to the pixel circuit 51 via the monitor line ML during normal operation (the operation of supplying current to the light-emitting element based on the data voltage and lighting up the light-emitting element).

[0057] As shown in Figure 3B, the monitor line ML is arranged in a direction parallel to the surfaces of the stacked element layers 20 and 30. As shown in Figure 3B, the monitor current line MOL has a portion that extends in a direction perpendicular to the surfaces of the stacked element layers 20 and 30 (Z direction in the figure). This configuration allows the signal readout circuit 26 provided in the element layer 30 to be arranged in a separate area from the display unit 31 provided in the element layer 30. Furthermore, the connection between the signal conversion circuit 23 of the element layer 20 and the signal readout circuit 26 of the element layer 30 can be efficiently made over a short distance. As a result, the wiring resistance in the monitor current line MOL can be reduced, and the monitor current I ＭＯＮＩ It can operate even when the current is small.

[0058] The signal conversion circuit 23, as an example, controls the monitor current I flowing through the monitor current line MOL. ＭＯＮＩ An integrating circuit 27 converts the magnitude (current) into an analog voltage value (analog voltage value), and digital correction data D is generated based on the analog voltage value. Ｃ It includes an analog-to-digital conversion circuit 28 that has the function of converting to a certain format.

[0059] As described above, the memory circuit 71 stores the correction data D Ｃ It has a function to store the correction data D. The processor circuit 21 also has a function to store the correction data D. Ｃ It has a function to correct the image data supplied to the display device 100 accordingly. Based on the corrected image data, the processor circuit 21 supplies the data voltage V from the source line drive circuit 33 to the pixel circuit 51. ＤＡＴＡ This can be corrected.

[0060] Since the connection between the processor circuit 21 and the memory circuit 71 is made via wiring within the same element layer 20, it is not affected by the bus width limitations that would occur if it were made via external circuitry. As a result, the data transfer rate for correction data between the processor circuit 21 and the memory circuit 71 can be increased. Similarly, the connection between the processor circuit 21 and the source line drive circuit 33 is made via wiring within the same element layer 20. Therefore, the data transfer rate for corrected image data between the processor circuit 21 and the source line drive circuit 33 can be increased.

[0061] Since the processor circuit 21 is capable of general-purpose arithmetic processing, it can perform functions other than correcting image data using correction data. For example, it can perform functions such as correcting the output voltage in the amplifier circuit 35 and switching the drive frequency in the display drive circuit 22.

[0062] The source line drive circuit 33, for example, outputs a data voltage V according to the corrected image data. ＤＡＴＡ A digital-to-analog conversion circuit 34 outputs a data voltage V. ＤＡＴＡ The system includes an amplifier circuit 35 that outputs to a source line SL. As shown in Figure 3B, the source line SL has a portion that extends perpendicularly (in the Z direction) to the surface of the stacked element layers 20 and 30. This configuration allows for efficient connection of the amplifier circuit 35 in the element layer 20 and the pixel circuit 51 in the element layer 30 over a short distance. As a result, the wiring resistance in the source line SL can be reduced, and the data voltage V ＤＡＴＡ This allows for reduced power consumption when supplying power.

[0063] In one aspect of the present invention, a display device has a pixel circuit capable of reading out the current necessary for external correction operation, in addition to the operation of displaying data according to the data voltage (normal operation). Furthermore, in one aspect of the present invention, a display device has a signal readout circuit that selectively reads out the current output by the pixel circuit, a signal conversion circuit that converts the amount of current output by the pixel circuit into correction data for the digital signal, and a storage circuit that stores the correction data. The processor circuit can correct the input image data based on the correction data stored in the storage circuit and correct the data voltage output by the source line drive circuit of the display drive circuit.

[0064] In a display device according to one aspect of the present invention, the above-described circuits are provided on stacked element layers, and a series of processes, either normal operation or external correction operation, are performed. The current flowing through the pixel circuit to store the correction data necessary for the external correction operation is stored as correction data in a storage circuit via a signal readout circuit and a signal conversion circuit located close to the pixel circuit, and the processor circuit can perform correction of the image data. The corrected image data can be used to correct the pixel-by-pixel variation in the magnitude of the current flowing through the light-emitting elements according to the image data by correcting the data voltage output from the display drive circuit to the pixel circuit.

[0065] Therefore, even when the transistor size of the pixel circuit is small and the current flowing through the pixel circuit required for correction operation (monitor current) is small, correction data can be obtained. In addition, since the wiring connecting each circuit can be shortened, the power consumption required for charging and discharging the wiring is reduced, and the display device can be made smaller.

[0066] <Example of Pixel Circuit Configuration> Figures 4A to 5D show an example of a pixel circuit configuration applicable to a pixel circuit 51 that can perform external correction operation, and a light-emitting element connected to the pixel circuit 51. In the following description, the light-emitting element is not limited to an organic EL element, but can also be a self-emissive light-emitting element such as an LED, microLED, QLED (Quantum-dot Light Emitting Diode), or semiconductor laser.

[0067] In this specification, the term "element" may sometimes be replaced with "device." For example, display elements and light-emitting elements can be replaced with display devices and light-emitting devices, respectively.

[0068] The pixel circuit 51A shown in Figure 4A includes transistors 55A, 55B, 55C, and capacitor 56. Figure 4A also illustrates a light-emitting element 61 connected to the pixel circuit 51A. Furthermore, Figure 4A shows the source line SL, gate line GL1, monitor line ML, power line ANO, and power line VCOM.

[0069] In Figures 4A to 5D, the gate lines GL (gate lines GL1 to GL4) are wires that supply signals to control the conduction or non-conduction state between the source and drain of the transistors in each pixel circuit applicable to the pixel circuit 51. The power lines ANO and VCOM are wires that provide a potential to supply current to the light-emitting element 61 in accordance with the data voltage written to the pixel circuit.

[0070] Transistor 55A is provided between the gate electrode of transistor 55B and the source line SL, which functions as the source line, and its conduction or non-conduction state is controlled based on the potential of the gate line GL1. Transistor 55C is provided between the monitor line ML and the source electrode of transistor 55B, and its conduction or non-conduction state is controlled based on the potential of the gate line GL2 (or gate line GL1). Capacitor 56 is provided to maintain the voltage between the gate and source of transistor 55B.

[0071] This allows the intensity (brightness) of the light emitted by the light-emitting element 61 to be controlled according to the data voltage applied to the gate of transistor 55B. In other words, transistor 55B can function as a driving transistor. Furthermore, the constant potential (V0) of the monitor line ML provided via transistor 55C can suppress variations in the gate-source potential of transistor 55B. In addition, a current used for generating correction data can be output from the monitor line ML. More specifically, the monitor line ML can function as wiring that outputs the current flowing through transistor 55B to the outside of the pixel circuit 51.

[0072] Transistor 55A has its gate connected to gate line GL1, one of its source and drain connected to source line SL, and the other connected to the gate of transistor 55B and one electrode of capacitor 56. Transistor 55B has one of its source and drain connected to power line ANO, and the other connected to the anode of light-emitting element 61. Transistor 55C has its gate connected to gate line GL1, one of its source and drain connected to the anode of light-emitting element 61, and the other connected to monitor line ML. Capacitor 56 has its other electrode connected to the anode of light-emitting element 61. Light-emitting element 61 has its cathode connected to power line VCOM. The anode and cathode of light-emitting element 61 can be swapped as needed by changing the magnitude of the supplied potential.

[0073] The pixel circuit 51B shown in Figure 4B is an example in which transistors 55A to 55C of the pixel circuit 51A are replaced with transistors having a pair of gates. This increases the current that the transistors can supply. In this example, transistors having a pair of gates are used for all transistors, but this is not the only option. Alternatively, transistors having a pair of gates, and where these gates are connected to different wirings, may be used. For example, reliability can be improved by using transistor 55B in which one of the gates is connected to the source, as shown in the pixel circuit 51B_S in Figure 6A.

[0074] The pixel circuit 51C shown in Figure 4C is an example where, in the pixel circuit 51A described above, transistors 55A and 55C are connected to different gate lines (gate line GL1 and gate line GL2). Similarly, the pixel circuit 51D shown in Figure 4D is an example where, in the pixel circuit 51B described above, transistors 55A and 55C are connected to different gate lines (gate line GL1 and gate line GL2). Such pixel circuits are suitable for operations where transistors 55A and 55C are simultaneously in a conductive state, or switched to a conductive state at different timings. Furthermore, the pixel circuit 51D shown in Figure 4D can be made more reliable by using a transistor 55B in which one of the gates and the source are connected, as shown in the pixel circuit 51D_S illustrated in Figure 6B.

[0075] The pixel circuit 51E shown in Figure 5A is configured by adding a transistor 55D to the above-mentioned pixel circuit 51C. The pixel circuit 51E also has three gate lines (gate line GL1, gate line GL2, and gate line GL3) connected to it. The gate of transistor 55D is connected to gate line GL3, and one of its source and drain is connected to the other source or drain of transistor 55B and one source or drain of transistor 55C, while the other is connected to the anode of the light-emitting element 61.

[0076] By making transistor 55D non-conductive, the current flowing to the light-emitting element 61 can be forcibly interrupted regardless of the state of transistors 55A and 55B. Such a pixel circuit is suitable when using a display method that alternates between display periods and off periods. In Figure 5A, a configuration is shown in which transistor 55D, which forcibly interrupts the current flowing to the light-emitting element 61, is placed between transistor 55B and the light-emitting element 61, but it can be placed anywhere on the path between power line ANO and power line VCOM. For example, it is also possible to place it between power line ANO and transistor 55B.

[0077] The pixel circuit 51F shown in Figure 5B is an example in which transistors 55A to 55D of the pixel circuit 51E are replaced with transistors having a pair of gates. This increases the current that the transistors can supply. In this example, transistors having a pair of gates are used for all transistors, but this is not the only option. Alternatively, transistors having a pair of gates, and where these gates are connected to different wirings, may be used. For example, reliability can be improved by using transistor 55B, in which one of the gates is connected to the source, as shown in the pixel circuit 51F_S in Figure 6C.

[0078] The pixel circuit 51G shown in Figure 5C is an example in which a transistor 55E and a capacitor 56B are added to the above-mentioned pixel circuit 51E. The pixel circuit 51G is also connected to four gate lines (gate line GL1, gate line GL2, gate line GL3, and gate line GL4). The gate of transistor 55E is connected to gate line GL3, one of its source and drain is connected to gate line GL4, and the other is connected to the gate of transistor 55D and one electrode of capacitor 56B. The other electrode of capacitor 56B is connected to the other source or drain of transistor 55D.

[0079] The pixel circuit 51H shown in Figure 5D is an example in which transistors 55A to 55E of the pixel circuit 51G are replaced with transistors having a pair of gates. This increases the current that the transistors can supply. In this example, transistors having a pair of gates are used for all transistors, but this is not the only option. Alternatively, transistors having a pair of gates, and where these gates are connected to different wirings, may be used. For example, reliability can be improved by using transistor 55B, in which one of the gates is connected to the source, as shown in the pixel circuit 51H_S in Figure 6D.

[0080] Figures 4A to 5D above show an example of a circuit configuration in which external correction operation can be performed using only an n-channel type OS transistor. Therefore, it can be applied to the pixel circuit 51 of the display unit 31 in the element layer 30.

[0081] In the pixel circuits 51A to 51H applicable to the pixel circuit 51 of the display unit 31, the operation of controlling the transistors of the pixel circuit to maintain a voltage corresponding to the threshold voltage of the drive transistor (internal correction operation) is not performed, thus the number of transistors in the pixel circuit can be reduced. Therefore, it is possible to create a pixel circuit suitable for display devices with small pixel sizes.

[0082] Furthermore, in the pixel circuits 51A to 51H applicable to the pixel circuit 51 of the display unit 31, OS transistors can be applied as described above. OS transistors have a very small off-current. Therefore, by lowering the frequency of the clock signal for driving the source line drive circuit and the gate line drive circuit, the refresh frequency when displaying a still image on the display unit 31 can be reduced. In this specification, the technique for reducing the refresh frequency described above may be called "idling stop drive" or "IDS drive". In the display device 100, the power consumption required to drive the display unit 31 can be reduced by applying IDS drive.

[0083] As an example of the operation of the pixel circuit described above, the normal operation and external correction operation of the pixel circuit 51G shown in Figure 5C will be explained. Note that the normal operation and external correction operation of the pixel circuit 51G shown in Figure 5C are also applicable to other pixel circuits, such as the pixel circuit 51H shown in Figure 5D.

[0084] Figure 7A shows a timing chart to explain the normal operation of the pixel circuit 51G shown in Figure 5C. Figure 7A shows the changes in the potential of the gate lines GL1, GL2, GL3, GL4 and the source line SL.

[0085] The normal operation shown in Figure 7A proceeds through periods T11, T12, T13, and T14, and the data voltage V ＤＡＴＡ Data current I corresponding to the current I ＤＡＴＡThe operation is performed to supply power to the light-emitting element 61. During normal operation, the source line SL is the data voltage V ＤＡＴＡ A constant potential V0 is supplied to the pixel circuit 51 via the monitor line ML. Furthermore, for ease of understanding, the signals of the gate lines GL1, GL2, GL3, and GL4 will be described as operating by switching between two logic states: H level and L level. The H level (or L level) potentials for different gate line signals may be the same or different. The H level is the potential at which the gate line GL causes the transistor connected to its gate to conduct (turn on). The L level is the potential at which the gate line GL causes the transistor connected to its gate to deconduct (turn off).

[0086] Period T11 is the period before the initialization operation of the pixel circuit 51G. During period T11, gate lines GL1, GL2, and GL3 are set to the L level, and gate line GL4 is set to the H level. Gate line GL2 is switched to the H level before transitioning to period T12. With this configuration, transistor 55D can be more reliably made non-conductive during period T12, thereby reducing the current flowing between power line ANO and power line VCOM.

[0087] Period T12 is the initialization period. During period T12, gate lines GL2 and GL3 are switched to the H level, and gate line GL4 is switched to the L level. This operation causes transistors 55C and 55E to become conductive, and transistor 55D to become non-conductive. The source side of transistor 55B (the other side of the source and drain) is initialized to the constant potential V0 of the monitor line ML.

[0088] During period T12, it is preferable to keep the gate line GL4 at the H level, as shown in Figure 7B. With this configuration, transistor 55D becomes conductive. In this case, the constant potential V0 of the monitor line ML is set to be below the potential of the power line VCOM or the threshold voltage of the light-emitting element 61 (the voltage at which current begins to flow), so that no current flows to the light-emitting element 61. With this configuration, the source potential of transistor 55D can be initialized. Therefore, it is possible to make the boosting operation described later more reliable.

[0089] During period T13, the data voltage V to the pixel circuit 51G is... ＤＡＴＡ This is the period for supplying (writing) data. During period T13, the gate line GL1 is switched to the H level. This operation causes transistor 55A to become conductive. Data voltage V ＤＡＴＡ This is supplied to the gate of transistor 55B, and the voltage between the gate and source of transistor 55B (gate-source), i.e., the data voltage V ＤＡＴＡ A current corresponding to the potential difference between the constant potential V0 and transistor 55B flows through transistor 55B. During period T13, transistor 55D is in a non-conductive state, so no current flows through the light-emitting element 61.

[0090] During period T14, the data voltage V ＤＡＴＡ Data current I corresponding to the current I ＤＡＴＡ This is the operation of supplying power to the light-emitting element 61. Figure 7C shows the data voltage V that flows during period T14. ＤＡＴＡ Data current I corresponding to the current I ＤＡＴＡ This is a circuit diagram explaining the circuit. In Figure 7C, transistors marked with an "X" over the circuit symbol are non-conducting transistors, while transistors without an "X" are conducting transistors.

[0091] During period T14, gate line GL4 is switched to the H level, and gate lines GL1 and GL2 are switched to the L level. This operation causes transistors 55A and 55C to become non-conductive. Gate line GL3 is also switched to the L level after transitioning to period T14. This configuration makes it possible to more reliably set the gate of transistor 55D to the H level and make transistor 55E non-conductive.

[0092] Data current I in transistor 55B ＤＡＴＡ When the current is flowing and transistor 55D is in a conducting state, the potential of the source of transistor 55D, i.e., node N, is ＥＬ The potential rises. By making transistor 55E non-conductive, the gate of transistor 55D becomes floating, and the voltage across capacitor 56B is maintained. Therefore, node N ＥＬAs the potential of the 55D rises, the potential of the gate of transistor 55D also rises (boosting). Therefore, transistor 55D can be more reliably turned on. In the case of pixel circuits with small pixel sizes, the breakdown voltage of the transistors is low, making it difficult to apply a large voltage in advance as a scanning signal. By boosting, as in the configuration of pixel circuit 51G, the potential of the gate of transistor 55D can be increased, and the desired operation can be achieved without increasing the amplitude voltage of the scanning signal.

[0093] Figure 8A shows a timing chart to explain the external correction operation in the pixel circuit 51G shown in Figure 5C. In Figure 8A, as in Figure 7A, the changes in the potential of the gate lines GL1, GL2, GL3, GL4 and the source line SL are shown.

[0094] The external correction operation shown in Figure 8A proceeds through periods T21, T22, and T23 to generate the correction signal V ＭＯＮＩ Monitor current I corresponding to the current I ＭＯＮＩ The operation involves sending a correction signal V to the monitor line ML. During the external correction operation period, the voltage of the correction signal V fluctuates in stages. ＭＯＮＩ The current is supplied, and the monitor line ML is configured to allow current to flow between it and the power line ANO. Specifically, the monitor line ML and the monitor current line MOL are configured to be connected.

[0095] Period T21 is the period before the current monitoring operation of the pixel circuit 51G. During period T21, gate lines GL1, GL2, and GL4 are set to the L level, and gate line GL3 is set to the H level. Transistor 55E is in a conducting state, while the other transistors are in a non-conducting state.

[0096] Period T22 is the period of current monitoring operation of the pixel circuit 51G, that is, the period during which the magnitude of the current flowing when the gate potential of the drive transistor, transistor 55B, is varied is measured. During period T22, gate lines GL1 and GL2 are switched to the H level. Transistors 55A and 55C are switched to a conductive state, and a correction signal V is sent to transistor 55B. ＭＯＮＩ Monitor current I corresponding to the current I ＭＯＮＩ A current flows. Monitor current I ＭＯＮＩThis flows to the monitor line ML via transistor 55C. Figure 8B shows the correction signal V in period T22, similar to Figure 7C. ＭＯＮＩ Monitor current I corresponding to the current I ＭＯＮＩ This is a circuit diagram explaining the circuit.

[0097] Note: Correction signal V ＭＯＮＩ During period T22, the voltage is switched in stages to change the magnitude of the current flowing through transistor 55B. The voltage that is switched in stages is the data voltage V ＤＡＴＡ It is preferable to switch between multiple voltages depending on the data voltage V. ＤＡＴＡ Since the current that flows when the power is supplied to the pixel circuit 51 can be estimated in advance, the corrected data voltage V ＤＡＴＡ This makes it easier to correct the current based on [the specified factor].

[0098] Period T23 is the period after the current monitoring operation of the pixel circuit 51G. During period T23, gate lines GL1 and GL2 are switched to the L level. Transistor 55E becomes conductive, while the other transistors become non-conductive.

[0099] In the external correction operation in the pixel circuit 51G shown in Figure 5C described above, the current flowing through the drive transistor (transistor 55B) is monitored and read out to generate correction data. However, other configurations are also possible. Specifically, components other than the drive transistor in the pixel circuit 51G, such as the light-emitting element 61, can also be monitored.

[0100] When monitoring the light-emitting element 61, the configuration is such that the voltage of the monitor line ML for supplying current to the light-emitting element 61 is switched by supplying currents of progressively different magnitudes to the light-emitting element 61. The monitor line ML can read out voltage values ​​corresponding to the current-voltage characteristics of the light-emitting element 61 (the current that flows when a voltage is applied). By storing the voltage values ​​for supplying progressively changed currents to the light-emitting element 61 as correction data in the memory circuit 71 via the signal conversion circuit 23, it is possible to estimate correction data corresponding to the variation in the current-voltage characteristics of the light-emitting element 61.

[0101] As described above, the pixel circuit of the display device 100 according to one aspect of the present invention can be a pixel circuit capable of reading out the current necessary for external correction operation, in addition to the operation of displaying according to the data voltage (normal operation).

[0102] <Example of Signal Readout Circuit Configuration> As described above, in one embodiment of the present invention, the signal readout circuit section 25 has a signal readout circuit 26. Figures 9A and 9B are circuit diagrams illustrating signal readout circuits 26A and 26B applicable to the signal readout circuit 26 of the signal readout circuit section 25.

[0103] The signal readout circuit 26A shown in Figure 9A has switches SW11 and SW21. Switches SW11 and SW21 provided in the element layer 30 can be replaced with OS transistors. In Figure 9A, when the monitor line ML is set to a constant potential V0 as in normal operation, switch SW11 is turned ON and switch SW12 is turned OFF. Also, as in external correction operation, the monitor current I ＭＯＮＩ To supply current to the monitor current line MOL, turn switch SW11 OFF and switch SW12 ON.

[0104] The signal readout circuit 26B shown in Figure 9B includes a multiplexer MUX that switches the connections between multiple monitor lines ML1 to ML3 and one monitor current line MOL, and a switch SW21 that provides a constant potential V0 to each monitor line ML1 to ML3. OS transistors can be used for the switch SW21 and multiplexer MUX provided in the element layer 30. In Figure 9B, when the monitor lines ML1 to ML3 are set to a constant potential V0 as in normal operation, the switch SW21 is turned ON and the multiplexer MUX is turned OFF. Also, as in external correction operation, the monitor current I ＭＯＮＩ When the current is to flow through the monitor current line MOL, switch SW21 is turned off, and the multiplexer MUX switches the connection between one of the monitor lines ML1 to ML3 and the monitor current line MOL. Since multiple monitor lines ML can be assigned to one monitor current line MOL, the number of signal readout circuits 26 can be reduced.

[0105] <Example of Signal Conversion Circuit Configuration> Figures 10A and 10B are circuit diagrams illustrating an example of a configuration applicable to the signal conversion circuit 23 described above. As described above, in one embodiment of the present invention, the signal conversion circuit 23 includes an integration circuit 27 and an analog-to-digital conversion circuit 28.

[0106] Figure 10A shows an integrating circuit 27A applicable to the integrating circuit 27, a switch SW32 and capacitor C32 that hold an analog voltage, and an analog-to-digital conversion circuit 28. The integrating circuit 27A has an operational amplifier 45A that constitutes a differential amplifier circuit, a switch SW31, and a capacitor C31. A reference voltage line VL and a monitor current line MOL are connected to the operational amplifier 45A. With this configuration, an analog voltage corresponding to the magnitude of the current in the monitor current line MOL is held and supplied to the analog-to-digital conversion circuit 28, which then receives a digital signal D ＯＵＴ This can be output as correction data.

[0107] The analog-to-digital conversion circuit 28 can employ any one of the following methods: flash type, delta-sigma type, pipeline type, integral type, successive approximation type, etc.

[0108] Figure 10B also shows an integrating circuit 27B applicable to the integrating circuit 27, a switch SW32 and capacitor C32 that hold the analog voltage, and an analog-to-digital conversion circuit 28. The integrating circuit 27B has an operational amplifier 45B with three input terminals, a switch SW31, and a capacitor C31, and multiple monitor current lines MOL_A, MOL_B, and MOL_C are connected to the operational amplifier 45B. With this configuration, multiple inputs are averaged, making it possible to create a configuration that is less susceptible to noise.

[0109] <Example of Display Driving Circuit Configuration> Figure 11A is a schematic diagram illustrating the connection relationship between the display driving circuit 22 and the display unit 31. As described above, in one embodiment of the present invention, since the display driving circuit 22 and the display unit 31 are provided on different layers, the display unit 31 can be configured to be provided on the display driving circuit 22.

[0110] The display drive circuit 22 includes a gate line drive circuit 32 and a source line drive circuit 33. The gate line drive circuit 32 is a circuit that drives the gate lines connected to the pixel circuit 51. The source line drive circuit 33 is a circuit that drives the source lines connected to the pixel circuit 51. The gate line drive circuit 32 is connected to the pixel circuit 51 of the display unit 31 located above it via the gate line GL. The source line drive circuit 33 is connected to the pixel circuit 51 of the display unit 31 located above it via the source line SL.

[0111] In the display drive circuit 22, the gate line drive circuit 32 and the source line drive circuit 33 are each provided in a vertically elongated (or horizontally elongated) rectangular shape. In this case, in the element layer 20, it is preferable that the processor circuit 21 be arranged to fill the area in the display drive circuit 22 where the gate line drive circuit 32 and the source line drive circuit 33 are not provided, as shown in Figure 11B. With this configuration, the processor circuit 21 and the display drive circuit 22 can be efficiently arranged in the element layer 20 without separating the areas in which the processor circuit 21 and the display drive circuit 22 are provided.

[0112] The schematic diagram shown in Figure 11C is an example of a configuration in which multiple sets of the display unit 31, gate line drive circuit 32, and source line drive circuit 33 shown in Figure 11A are arranged side by side. The display unit 31, gate line drive circuit 32, and source line drive circuit 33 are each arranged in a matrix of m rows and n columns (where m and n are integers of 1 or more). In this specification, the section in the first row and first column is referred to as display unit 31[1,1], and the section in the m row and n column is referred to as display unit 31[m,n]. Display units 31[1,1] to display units 31[m,n] can be combined to form a display unit 31. Note that display units 31[1,1] to display units 31[m,n] may each be referred to as sub-display units. The display unit 31 can display one image by combining multiple sub-display units. Figure 11C shows the case where m is 4 and n is 4. The display unit 31 is divided into 16 sections. Each of the divided display units 31[1,1] to 31[m,n] has a gate line drive circuit 32 connected to the gate line GL and a source line drive circuit 33 connected to the source line SL.

[0113] By placing the display unit 31 and the display drive circuit 22 in an overlapping area, the connection distance (wiring length) between the pixel circuit 51 and the gate line drive circuit 32 and source line drive circuit 33 can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. Power consumption can also be reduced. Furthermore, miniaturization and weight reduction can be achieved.

[0114] Furthermore, the display unit 31 has a configuration in which each of the display units 31[1,1] to 31[m,n] has a gate line drive circuit 32 and a source line drive circuit 33. Therefore, the display unit 31 can rewrite the image for each of the display units 31[1,1] to 31[m,n]. For example, it is possible to rewrite the image data only in the sections of the display unit 31 where a change has occurred, and retain the image data in the sections where no change has occurred, thereby reducing power consumption. For example, it is possible to make the number of image rewrites per unit time of the image data in one of the sub-display units of the display unit 31[1,1] to 31[m,n] less than the number of image rewrites per unit time of the image data in the other sub-display units, thereby reducing power consumption.

[0115] Furthermore, the display device 100 allows for individual setting of the drive frequency (frame frequency, frame rate, or refresh rate, etc.) for each display unit 31[1,1] to 31[m,n] during image display. Therefore, by combining this with eye tracking, it becomes possible to apply foveated rendering, a type of rendering that varies the frame rate for each region according to the user's gaze. As a result, a configuration can be achieved that outputs images with excellent display quality at a low load.

[0116] Furthermore, high-speed rewriting can be achieved by performing the image data rewriting, which is done for each divided display unit 31, simultaneously on all divided display units.

[0117] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0118] (Embodiment 2) This embodiment describes a modified configuration of a display device according to one aspect of the present invention. In this embodiment, repeated descriptions of components that are denoted by the same reference numerals as in the above embodiment may be omitted.

[0119] Figures 12A and 13 are perspective views of a display device 100A according to one aspect of the present invention. Figure 12B is a block diagram illustrating the configuration of the display device 100A. The display device 100A comprises an element layer 20, an element layer 30A on the element layer 20, an element layer 30B on the element layer 30A, and a sealing substrate 40 on the element layer 30B. The element layer 30A also includes a memory circuit 71. In Figure 13, the element layer 20, element layer 30A, element layer 30B, and sealing substrate 40 are shown separated to make the configuration of the display device 100A easier to understand.

[0120] The description of the element layer 20 corresponds to the configuration in which the memory circuit 71 in the above embodiment 1 is omitted. As an example, the element layer 20 is provided with a signal conversion circuit 23, a processor circuit 21, a display drive circuit 22 having a gate line drive circuit 32 and a source line drive circuit 33, and a terminal section 29.

[0121] The memory circuit 71 provided on the element layer 30A includes a plurality of memory cells 72. In the configuration of the display device 100A, the processor circuit 21 and the memory circuit 71 are provided on separate layers, the element layer 20 and the element layer 30A, respectively. The memory cells 72 in the memory circuit 71 and the pixel circuit 51 in the display unit 31 can both be configured to have OS transistors.

[0122] The memory circuit 71 having an OS transistor can be fitted with either NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory) or DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).

[0123] NOSRAM refers to memory where the memory cells are 2-transistor (2T) or 3-transistor (3T) gain cells, and the access transistors are OS transistors. OS transistors have extremely low leakage current, which is the current flowing between the source and drain when off. NOSRAM allows for non-destructive reading of the stored data without damaging it.

[0124] DOSRAM refers to RAM with a 1T (transistor) 1C (capacitance) type memory cell. Like NOSRAM, DOSRAM is a memory that utilizes the low off-current of the OS transistor.

[0125] NOSRAM and DOSRAM are types of memory devices that use OS transistors.

[0126] The memory cell 72 of the memory circuit 71 and the pixel circuit 51 of the display unit 31 are configured to have OS transistors. This configuration allows for the superimposed arrangement of element layer 30A and element layer 30B on the element layer 20. By superimposing the memory circuit 71 and the display unit 31, it is possible to increase the memory capacity of the memory circuit 71, increase the display area of ​​the display unit 31, and so on.

[0127] The memory circuit 71 connected to the processor circuit 21 can also be used as a memory circuit for saving (backing up) the program or data used in the processor circuit 21. By combining a memory circuit using an OS transistor and a processor circuit in this way, a normally-off CPU (also called a "Noff-CPU") can be realized. A Noff-CPU is an integrated circuit that includes normally-off type transistors that are in a non-conductive state (also called an off state) even when the gate voltage is 0V.

[0128] The Noff-CPU can stop supplying power to circuits within the Noff-CPU that are not in operation, putting those circuits into a standby state. When power is cut off and the circuit is in standby mode, no power is consumed. Therefore, the Noff-CPU can minimize power consumption. Furthermore, the Noff-CPU can retain information necessary for operation, such as settings, for a long period of time even when the power supply is cut off. To recover from standby mode, it is only necessary to resume power supply to the circuit in question, and there is no need to rewrite settings or other information. For example, high-speed recovery from standby mode is possible. In this way, the Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0129] As described above, a display device 100A according to one aspect of the present invention has a configuration in which an element layer having a display unit 31, an element layer having a memory circuit 71, and an element layer having a display drive circuit 22 and a processor circuit 21 are stacked. By stacking the layers on which each circuit is provided, the display device 100A can be made smaller. In addition, since the display drive circuit 22 can be placed on top of the display unit 31, the area of ​​the display unit 31 can be increased. Therefore, the resolution of the display unit 31 can be increased, and the display quality of the display device 100A can be improved.

[0130] Next, an example configuration of a memory cell 72 having an OS transistor will be described with reference to Figures 14A to 14D. The memory cell 72 corresponds to a memory cell in the memory circuit 71. The memory cells 72A to 72D that are applicable to the memory cell 72 shown in Figures 14A to 14D are all memory cells using OS transistors. Figures 14A and 14B can be broadly classified as memory cells applicable to NOSRAM, and Figures 14C and 14D as memory cells applicable to DOSRAM.

[0131] The memory cell 72A shown in Figure 14A is a two-transistor (2T) gain cell. The memory cell 72A has transistors MW1 and MR1 and a capacitor CS1. Transistor MW1 is a writing transistor, and transistor MR1 is a reading transistor. The back gates of transistors MW1 and MR1 are connected to wiring BGL.

[0132] Since the readout transistor is configured with an OS transistor, the memory cell 72A does not consume power to retain data. Therefore, the memory cell 72A is a low-power memory cell capable of retaining data for a long period of time, and the memory circuit 71 can be used as a non-volatile memory device.

[0133] The memory cell 72B shown in Figure 14B is a 3T type gain cell and has transistors MW2, MR2, MS2, and capacitor CS2. Transistors MW2, MR2, and MS2 are the write transistor, read transistor, and select transistor, respectively. The back gates of transistors MW2, MR2, and MS2 are connected to wiring BGL. The memory cell 72B is connected to word lines RWL, WWL, bit lines RBL, WBL, capacitance line CDL, and power line PL2. For example, the ground voltage (low-level power supply voltage) is input to the capacitance line CDL and power line PL2.

[0134] In the gain cell shown above, a bit line that serves both as a read bit line RBL and a write bit line WBL may be provided.

[0135] Figures 14C and 14D show examples of 1T1C (capacitance) type memory cells. The memory cell 72C shown in Figure 14C is connected to the word line WL, bit line BL, capacitance line CDL, and wiring BGL. The memory cell 72C has a transistor MW3 and a capacitor CS3. The back gate of transistor MW3 is connected to wiring BGL. The memory cell 72D shown in Figure 14D illustrates the configuration of a ferroelectric memory using a capacitor FE1 having a ferroelectric material in the capacitor CS3. For example, HfZrO is used as the ferroelectric material. Ｘ You can use it.

[0136] As described above, the display device 100A of this embodiment has a configuration in which an element layer having a memory circuit 71 is stacked on an element layer having a processor circuit 21. Therefore, the layout area for arranging the memory circuit 71 can be increased, and thus the memory capacity can be increased. This makes it possible to correct correction data of large amounts in a display device with a large number of pixels.

[0137] Furthermore, the display device 100A can be miniaturized by stacking layers on which each circuit is provided. Also, by stacking the element layer having the memory circuit 71 and the element layer having the processor circuit 21, the wiring connecting them can be shortened. As a result, wiring resistance and parasitic capacitance are reduced, and the operating speed of the processor circuit 21 can be increased. In addition, the power consumption of the display device 100A is reduced.

[0138] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0139] (Embodiment 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer as described in Embodiment 1 and a crystalline indium oxide film will be described.

[0140] <Oxide Semiconductor Layer> In one aspect of the present invention, the oxide semiconductor layer preferably has a crystalline metal oxide. Examples of structures of the crystalline metal oxide include CAAC (c-axis aligned crystal) structure, polycrystalline (Poly-crystal) structure, microcrystalline structure, and nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect level density in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor using the oxide semiconductor layer in one aspect of the present invention can be improved, and the reliability of a memory device on which the transistor is mounted can be improved.

[0141] In one aspect of the present invention, the oxide semiconductor layer preferably has a metal oxide having a CAAC structure. A CAAC structure is a crystalline structure in which a plurality of microcrystals (typically a plurality of microcrystals having a hexagonal crystal structure) are oriented along the c axis, and in the a-b plane, the plurality of microcrystals are linked together without orientation. Furthermore, when a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in layers in the crystalline portion. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having a layered crystalline portion.

[0142] The crystallinity of an oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for the analysis.

[0143] The crystallinity of the semiconductor material in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more amorphous semiconductors (semiconductors with an amorphous structure), single-crystal semiconductors (semiconductors with a single-crystal structure), or semiconductors with crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in part). The crystallinity of the oxide semiconductor layer may suppress the degradation of transistor characteristics.

[0144] Examples of metal oxides that can be found in an oxide semiconductor layer according to one aspect of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one aspect of the present invention preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Element M is a metal or metalloid element with a high bond energy with oxygen, for example, a metal or metalloid element with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M present in the metal oxide is gallium, the metal oxide according to one aspect of the present invention preferably has one or more selected from indium, gallium, and zinc. In this specification, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification may include metalloid elements.

[0145] Examples of metal oxides according to one aspect of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium tungsten oxide (In-W oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also written as IGTO), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, Indium aluminum zinc oxide (also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (also written as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. can be used. Alternatively, silicon-containing indium tin oxide (also called ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0146] <Indium Oxide Film> In one embodiment of the present invention, a crystalline indium oxide film can be used as the oxide semiconductor layer.

[0147] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0148] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0149] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0150] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0151] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0152] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0153] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10１９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0154] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0155] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0156] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0157] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0158] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0159] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0160] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0161] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0162] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0163] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0164] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0165] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0166] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0167] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0168] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0169] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0170] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0171] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0172] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O４ type structure or Yb ２ Fe ３ O ７ As an example of a crystal having a type structure, IGZO etc. may be mentioned.

[0173] This embodiment can be appropriately combined with other embodiments. Also, in this specification, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined.

[0174] (Embodiment 4) In this embodiment, a configuration example of a display module to which a display device according to an aspect of the present invention can be applied will be described.

[0175] The display device of this embodiment can be a high-definition display panel. For example, the display device according to an aspect of the present invention can be used for a display unit of an information terminal device (wearable device) such as a wristwatch type and a bracelet type, a VR device such as a head-mounted display, and a display unit of a wearable device that can be worn on the head such as a glasses type AR device.

[0176] [Display module] FIG. 15A shows a perspective view of a display module 980. The display module 980 has a display device 200A and an FPC 990. Note that the display panel included in the display module 980 is not limited to the display device 200A, and may be the display device 200B described later.

[0177] The display module 980 has a substrate 991 and a substrate 992. The display module 980 has a display unit 981. The display unit 981 is an area for displaying an image.

[0178] FIG. 15B shows a perspective view schematically showing the configuration on the substrate 991 side. On the substrate 991, a circuit unit 982, a display unit 983 on the circuit unit 982, and a pixel unit 984 on the display unit 983 are laminated. Also, a terminal unit 985 for connecting to the FPC 990 is provided in a portion that does not overlap with the pixel unit 984 on the substrate 991. The terminal unit 985 and the circuit unit 982 are connected by a wiring unit 986 composed of a plurality of wirings.

[0179] The layer having the circuit section 982 can be fitted with the circuits of each configuration of the element layer 20 described in Embodiment 1, etc. The layer having the display section 983 can be fitted with the pixel circuit 983a as well as the circuits of the element layer 30 described in Embodiment 1, etc. Furthermore, by appropriately increasing the number of layers on which elements are provided, the memory circuit of the element layer 30A described in Embodiment 1, etc. can be fitted.

[0180] The pixel section 984 has a plurality of pixels 984a arranged periodically. An enlarged view of one pixel 984a is shown on the right side of Figure 15B. The pixel 984a has a light-emitting element 410R that emits red light, a light-emitting element 410G that emits green light, and a light-emitting element 410B that emits blue light.

[0181] The display unit 983 has a plurality of periodically arranged pixel circuits 983a. Each pixel circuit 983a is a circuit that controls the light emission of three light-emitting elements in one pixel 984a. Each pixel circuit 983a can be configured to have three circuits that control the light emission of one light-emitting element.

[0182] The circuit section 982 has circuits for driving each pixel circuit 983a of the display section 983. For example, it has one or both of a gate line drive circuit and a source line drive circuit. In addition, it has calculation circuits, memory circuits, etc.

[0183] The FPC990 functions as wiring for supplying video signals and power supply voltage, etc., to the circuit section 982 from an external source. An IC may also be mounted on the FPC990.

[0184] The display module 980 can be configured such that a layer having a display unit 983 and a layer having a circuit unit 982 are stacked below the pixel unit 984, thereby making the aperture ratio (effective display area ratio) of the display unit 981 extremely high. Furthermore, it is possible to arrange the pixels 984a at an extremely high density, making the resolution of the display unit 981 extremely high.

[0185] Because such a display module 980 is extremely high-resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration where the display part of the display module 980 is viewed through lenses, the display module 980 has an extremely high-resolution display part 981, so even when the display part is magnified with lenses, pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 980 is not limited to this, and can be suitably used in electronic devices having relatively small display parts. For example, it can be suitably used in the display part of wearable electronic devices such as wristwatches.

[0186] [Display device 200A] The display device 200A shown in Figure 16 has a configuration in which a transistor 810 with a channel formed on a substrate 801 and a transistor 820 containing a metal oxide on a semiconductor layer in which the channel is formed are stacked.

[0187] The substrate 801 corresponds to the substrate 991 in Figures 15A and 15B.

[0188] The transistor 810 is a transistor having a channel-forming region in the substrate 801. The substrate 801 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 810 comprises a portion of the substrate 801, a conductive layer 811, a low-resistance region 812, an insulating layer 813, and an insulating layer 814. The conductive layer 811 functions as a gate electrode. The insulating layer 813 is located between the substrate 801 and the conductive layer 811 and functions as a gate insulating layer. The low-resistance region 812 is a region of the substrate 801 doped with impurities and functions as either a source or a drain. The insulating layer 814 is provided covering the side surface of the conductive layer 811.

[0189] Furthermore, an element isolation layer 815 is provided between two adjacent transistors 810 so as to be embedded in the substrate 801.

[0190] An insulating layer 961 is provided covering the transistor 810, and a conductive layer 951 is provided on the insulating layer 961. An insulating layer 962 is provided covering the conductive layer 951, and a conductive layer 952 is provided on the insulating layer 962. The conductive layer 951 and the conductive layer 952 each function as wiring. An insulating layer 963 and an insulating layer 832 are provided covering the conductive layer 952, and a transistor 820 is provided on the insulating layer 832.

[0191] Transistor 820 is an OS transistor in which a metal oxide (also called an oxide semiconductor) is applied to the semiconductor layer where the channel is formed.

[0192] The transistor 820 has a semiconductor layer 821, an insulating layer 823, a conductive layer 824, a pair of conductive layers 825, an insulating layer 826, and a conductive layer 827.

[0193] An insulating layer 832 is provided on the insulating layer 963. The insulating layer 832 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 963 to the transistor 820, and prevents oxygen from detaching from the semiconductor layer 821 to the insulating layer 832. As the insulating layer 832, for example, a film that is less susceptible to hydrogen or oxygen diffusion than a silicon oxide film can be used, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0194] A conductive layer 827 is provided on an insulating layer 832, and an insulating layer 826 is provided covering the conductive layer 827. The conductive layer 827 functions as the first gate electrode of the transistor 820, and a part of the insulating layer 826 functions as the first gate insulating layer. It is preferable to use an oxide insulating film, such as a silicon oxide film, for at least the portion of the insulating layer 826 that is in contact with the semiconductor layer 821. It is preferable that the upper surface of the insulating layer 826 is flattened.

[0195] The semiconductor layer 821 is provided on the insulating layer 826. Preferably, the semiconductor layer 821 has a metal oxide (also called an oxide semiconductor) film that exhibits semiconductor properties. A pair of conductive layers 825 are provided in contact with the semiconductor layer 821 and function as a source electrode and a drain electrode.

[0196] An insulating layer 828 is provided covering the top and side surfaces of a pair of conductive layers 825, as well as the side surfaces of the semiconductor layer 821, and an insulating layer 964 is provided on the insulating layer 828. The insulating layer 828 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the semiconductor layer 821 from the insulating layer 964, etc., and to prevent oxygen from detaching from the semiconductor layer 821. An insulating film similar to that of the insulating layer 832 can be used as the insulating layer 828.

[0197] The insulating layer 828 and the insulating layer 964 are provided with openings that reach the semiconductor layer 821. An insulating layer 823 in contact with the upper surface of the semiconductor layer 821 and a conductive layer 824 are embedded inside these openings. The conductive layer 824 functions as a second gate electrode, and the insulating layer 823 functions as a second gate insulating layer.

[0198] The upper surfaces of the conductive layer 824, the insulating layer 823, and the insulating layer 964 are flattened so that their heights are the same or approximately the same, and the insulating layer 829 and insulating layer 965 are provided covering them.

[0199] Insulating layers 964 and 965 function as interlayer insulating layers. Insulating layer 829 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the transistor 820 from insulating layer 965, etc. As insulating layer 829, an insulating film similar to that used for insulating layers 828 and 832 can be used.

[0200] A plug 974, which connects to one of the pair of conductive layers 825, is provided so as to be embedded in the insulating layer 965, insulating layer 829, and insulating layer 964. Here, it is preferable that the plug 974 is configured such that the sides of the openings of the insulating layer 965, insulating layer 829, insulating layer 964, and insulating layer 828, and a portion of the upper surface of the conductive layer 825, are covered with the conductive layer. In this case, it is preferable to use a conductive material that does not easily allow hydrogen and oxygen to diffuse as the conductive layer covering the plug 974.

[0201] Furthermore, a capacitor 840 is provided on the insulating layer 965. The capacitor 840 and the transistor 820 are connected by a plug 974.

[0202] Transistor 820 can be used as a transistor constituting a pixel circuit. Transistor 810 can also be used as a transistor constituting a pixel circuit, or as a transistor constituting a drive circuit (gate line drive circuit, source line drive circuit) for driving the pixel circuit. Furthermore, transistors 810 and 820 can be used as transistors constituting various circuits such as memory cells.

[0203] The capacitor 840 has a conductive layer 941, a conductive layer 945, and an insulating layer 943 located between them. The conductive layer 941 functions as one electrode of the capacitor 840, the conductive layer 945 functions as the other electrode of the capacitor 840, and the insulating layer 943 functions as the dielectric of the capacitor 840.

[0204] The conductive layer 941 is provided on the insulating layer 961 and embedded in the insulating layer 954. The conductive layer 941 is connected to either the source or drain of the transistor 810 by a plug 971 embedded in the insulating layer 961. The insulating layer 943 is provided covering the conductive layer 941. The conductive layer 945 is provided in the region that overlaps with the conductive layer 941 via the insulating layer 943.

[0205] An insulating layer 955a is provided covering the capacitance 840, an insulating layer 955b is provided on top of the insulating layer 955a, and an insulating layer 955c is provided on top of the insulating layer 955b.

[0206] Insulating layers 955a, 955b, and 955c can each preferably be made of inorganic insulating films. For example, it is preferable to use silicon oxide films for insulating layers 955a and 955c, and silicon nitride films for insulating layer 955b. This allows insulating layer 955b to function as an etching protective film. In this embodiment, an example is shown in which a part of insulating layer 955c is etched and a recess is formed, but the insulating layer 955c does not necessarily have to have a recess.

[0207] A light-emitting element 410R, a light-emitting element 410G, and a light-emitting element 410B are provided on the insulating layer 955c.

[0208] The display device 200A has different light-emitting elements for each light-emitting color, resulting in minimal change in chromaticity between low-brightness and high-brightness illumination. Furthermore, because the organic layers 412R, 412G, and 412B are spaced apart, crosstalk between adjacent sub-pixels can be suppressed even in high-resolution display panels. Therefore, a display panel with high resolution and high display quality can be realized.

[0209] An insulating layer 425, a resin layer 426, and a layer 428 are provided in the region between adjacent light-emitting elements.

[0210] The pixel electrodes 411R, 411G, and 411B of the light-emitting element are connected to either the source or drain of the transistor 810 by plugs 956 embedded in insulating layers 955a, 955b, and 955c, a conductive layer 941 embedded in insulating layer 954, and plugs 971 embedded in insulating layer 961. The height of the upper surface of insulating layer 955c and the height of the upper surface of plug 956 are equal or approximately equal. Various conductive materials can be used for the plugs. Note that the pixel electrodes 411R, 411G, and 411B are sometimes collectively referred to as the pixel electrode 411.

[0211] Furthermore, a protective layer 421 is provided on the light-emitting elements 410R, 410G, and 410B via a common electrode 413 and a common layer 414. The substrate 470 is bonded to the protective layer 421 by an adhesive layer 471.

[0212] There is no insulating layer covering the upper edge of the pixel electrode 411 between two adjacent pixel electrodes 411. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made.

[0213] This configuration allows for the formation of not only pixel circuits but also drive circuits directly beneath the light-emitting elements, making it possible to miniaturize the display panel compared to cases where the drive circuits are located around the display area.

[0214] [Display Device 200B] The display device 200B shown in Figure 17 has a configuration in which a transistor 820A containing a metal oxide in the semiconductor layer where the channel is formed and a transistor 820B containing a metal oxide in the semiconductor layer where the channel is formed are stacked. With this configuration, transistors with different compositions of constituent elements in the metal oxide of the semiconductor layer can be used. Therefore, a display device can be made using OS transistors with different transistor characteristics. For example, the upper transistor 820A can be used as a transistor in a pixel circuit that drives a light-emitting element, and the lower transistor 820B can be used as a transistor in a memory cell.

[0215] This configuration allows for a higher density of circuits located directly beneath the light-emitting elements, making it possible to miniaturize the display panel compared to cases where the drive circuits are located around the display area.

[0216] [Display devices 200C, 200D] Display device 200C, shown in Figure 18, is configured by adding an insulating layer 423 and a lens 424 to display device 200A. Display device 200D, shown in Figure 19, is configured by adding an insulating layer 423 and a lens 424 to display device 200B.

[0217] In one aspect of the present invention, it is preferable that the display device has a lens array (e.g., a microlens array) in a position overlapping with the light-emitting element. By providing the lens array in a position overlapping with the light-emitting element, the light emitted from the light-emitting element can be utilized efficiently. This makes it possible to realize a highly reliable display device.

[0218] Figure 18 shows an example in which lenses 424 are provided on light-emitting elements 410R, 410G, and 410B via a protective layer 421 and an insulating layer 423. By directly forming the lenses 424 on the substrate on which the light-emitting elements are formed, the alignment accuracy between the light-emitting elements and the lens array can be improved.

[0219] Figure 18 shows an example in which a layer having a planarization function is used as the insulating layer 423. For example, it is preferable to use an inorganic material for the protective layer 421 and an organic material for the insulating layer 423. Alternatively, the insulating layer 423 may not be used, and the lens 424 may be provided directly on the protective layer 421.

[0220] The lens 424 may have its convex surface facing the substrate 470 side, or it may face the light-emitting element side.

[0221] The lens 424 can be formed using at least one of an inorganic material and an organic material. For example, a material containing resin can be used for the lens. Alternatively, a material containing at least one of an oxide and a sulfide can be used for the lens. The lens 424 may be formed directly on a substrate or on a light-emitting element, or a separately formed lens array may be bonded to it.

[0222] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0223] (Embodiment 5) This embodiment describes an electronic device to which a display device according to one aspect of the present invention can be applied.

[0224] A display device according to one aspect of the present invention can be applied to the display unit of an electronic device. Therefore, it is possible to realize an electronic device with high display quality, or an extremely high-definition electronic device, or a highly reliable electronic device.

[0225] Electronic devices using a display device according to one aspect of the present invention include televisions, monitors and other display devices, lighting devices, desktop or notebook personal computers, word processors, and DVDs (Digital Versatile). Examples include image playback devices that play still images or videos stored on recording media such as discs, portable CD players, radios, tape recorders, headphone stereos, stereos, desk clocks, wall clocks, cordless telephone handsets, transceivers, car phones, mobile phones, personal digital assistants, tablet devices, portable game consoles, fixed game machines such as pachinko machines, calculators, electronic organizers, e-book readers, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air conditioning equipment such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Furthermore, industrial equipment such as guide lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and energy storage devices for power leveling and smart grids can also be included in the category of electronic equipment. In addition, mobile devices propelled by engines using fuel or electric motors using electricity from energy storage devices may also be included in the category of electronic equipment. Examples of such mobile devices include electric vehicles (EVs), hybrid vehicles (HVs) that combine internal combustion engines and electric motors, plug-in hybrid vehicles (PHVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, motorized bicycles including electric assist bicycles, motorcycles, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spacecraft.

[0226] An electronic device according to one aspect of the present invention may have a secondary battery, and it is preferable that the secondary battery can be charged using contactless power transmission.

[0227] Examples of secondary batteries include lithium-ion batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air batteries, nickel-zinc batteries, and silver-zinc batteries.

[0228] An electronic device according to one aspect of the present invention may have an antenna. By receiving signals with the antenna, the display unit can display images and information. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0229] An electronic device according to one aspect of the present invention may have a sensor (including a function for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0230] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0231] Furthermore, electronic devices having multiple display units may have functions such as displaying image information primarily on one part of the display unit and text information primarily on another part, or displaying a three-dimensional image by displaying images that take parallax into account on multiple display units. Furthermore, electronic devices having an image receiving unit may have functions such as capturing still images or moving images, automatically or manually correcting captured images, saving captured images to a recording medium (external or built into the electronic device), and displaying captured images on a display unit. It should be noted that the functions of an electronic device according to one aspect of the present invention are not limited to these, and it may have a variety of functions.

[0232] A display device according to one aspect of the present invention can display high-definition images. Therefore, it can be suitably used in portable electronic devices, wearable electronic devices, and e-book terminals. For example, it can be suitably used in xR devices such as VR devices or AR devices.

[0233] Figure 20A shows the external appearance of the head-mounted display 710. The head-mounted display 710 includes a mounting part 711, lenses 712, a main body 713, a display unit 714, a cable 715, etc. A battery 716 is also built into the mounting part 711. A display device according to one embodiment of the present invention can be applied to the display unit 714.

[0234] Cable 715 supplies power from battery 716 to main unit 713. The main unit 713 is equipped with a wireless receiver and can display received image data and other video information on the display unit 714. In addition, a camera provided on the main unit 713 captures the movement of the user's eyeballs and / or eyelids, and by calculating the user's gaze based on that information, the user's gaze can be used as an input means.

[0235] Furthermore, the attachment portion 711 may be provided with multiple electrodes in positions that come into contact with the user. The main body 713 may have a function to recognize the user's gaze by detecting the current flowing through the electrodes in accordance with the user's eye movements. It may also have a function to monitor the user's pulse by detecting the current flowing through the electrodes. The attachment portion 711 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function to display the user's biological information on the display unit 714. It may also detect the user's head movements and change the image displayed on the display unit 714 in accordance with those movements.

[0236] Figure 20B shows the external appearance of the head-mounted display 720. The head-mounted display 720 is a goggle-type information processing device.

[0237] The head-mounted display 720 has a housing 721, operation buttons 723, a band-shaped fixing device 724, and two display units 722. Having two display units 722 allows the user to view one display unit per eye. This enables the display of high-resolution images even when performing 3D display using parallax. A battery 725 is also provided on the fixing device 724. The battery 725 could also be provided on the housing 721, but providing it on the fixing device 724 is preferable because it allows the center of gravity of the head-mounted display 720 to be moved to the rear, improving the wearing comfort for the user. In addition to the battery 725, the fixing device 724 may also be provided with a drive circuit for operating the display units 722 to adjust the center of gravity of the head-mounted display 720.

[0238] The operation button 723 has functions such as a power button. The device may also have other buttons besides the operation button 723.

[0239] A display device according to one aspect of the present invention can be applied to the display unit 722. Because the display device according to one aspect of the present invention has extremely high resolution, pixels are difficult for the user to see, and a more realistic image can be displayed.

[0240] Figure 20C shows the external appearance of the camera 730 equipped with a viewfinder 740.

[0241] The camera 730 includes a housing 731, a display unit 732, operation buttons 733, a shutter button 734, and the like. The camera 730 is also fitted with a detachable lens 736.

[0242] In this example, the camera 730 is configured such that the lens 736 can be removed from the housing 731 and replaced; however, the lens 736 and the housing may be integrated.

[0243] The camera 730 can take an image by pressing the shutter button 734. The display unit 732 also functions as a touch panel, and an image can be taken by touching the display unit 732.

[0244] The housing 731 of the camera 730 has a mount with electrodes, and in addition to the viewfinder 740, a strobe device and the like can be connected to it.

[0245] The viewfinder 740 includes a housing 741, a display unit 742, buttons 743, etc.

[0246] The housing 741 has a mount that engages with the mount of the camera 730, allowing the viewfinder 740 to be attached to the camera 730. The mount also has electrodes, which allow images and other data received from the camera 730 to be displayed on the display unit 742.

[0247] Button 743 functions as a power button. Button 743 can be used to switch the display on and off of the display unit 742.

[0248] A display device according to one aspect of the present invention can be applied to the display unit 732 of the camera 730 and the display unit 742 of the viewfinder 740.

[0249] In Figure 20C, the camera 730 and the viewfinder 740 are shown as separate electronic devices and are configured to be detachable. However, the camera 730's housing 731 may also have a viewfinder equipped with a display device according to one aspect of the present invention built into it.

[0250] The information terminal 750 shown in Figure 20D includes a housing 751, a display unit 752, a microphone 757, a speaker unit 754, a camera 753, and an operation switch 755. A display device according to one embodiment of the present invention can be applied to the display unit 752. The display unit 752 also functions as a touch panel. The information terminal 750 also includes an antenna, battery, etc. inside the housing 751. The information terminal 750 can be used, for example, as a smartphone, mobile phone, tablet information terminal, tablet personal computer, e-book reader, etc.

[0251] Figure 20E shows an example of a wristwatch-type information terminal. The information terminal 760 includes a housing 761, a display unit 762, a band 763, a buckle 764, an operation switch 765, input / output terminals 766, etc. The information terminal 760 also includes an antenna and battery inside the housing 761. The information terminal 760 can run various applications such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games.

[0252] Furthermore, the display unit 762 is equipped with a touch sensor and can be operated by touching the screen with a finger or stylus. For example, an application can be launched by touching the icon 767 displayed on the display unit 762. The operation switch 765 can have various functions, including setting the time, turning the power on and off, turning wireless communication on and off, activating and deactivating silent mode, and activating and deactivating power saving mode. For example, the functions of the operation switch 765 can also be configured by the operating system built into the information terminal 760.

[0253] Furthermore, the information terminal 760 is capable of performing standardized short-range wireless communication. For example, it can communicate with a wireless headset to make hands-free calls. The information terminal 760 is also equipped with an input / output terminal 766, which can be used to send and receive data with other information terminals. It can also be charged via the input / output terminal 766. Note that charging may be performed by wireless power supply without using the input / output terminal 766.

[0254] Furthermore, in electronic devices to which the display device according to one aspect of the present invention shown in Figures 20A to 20E can be applied, the device may be connected to an external server via a network. Alternatively, the electronic device may not perform processing that requires high computing power, but rather the server connected via the network may perform such processing. Such processing is also called a thin client, and the user-side (client-side) terminal (in this case, the electronic device) executes only limited processing, while advanced processing such as application execution and management is performed on the server side, thereby reducing the scale of processing on the client-side terminal. As a result, there is no need to use a computing device with high computing power in the electronic device, making it easier to reduce costs, weight, and size. Furthermore, in electronic devices according to one aspect of the present invention, the above-mentioned thin client and processing that requires high computing power on the electronic device side may be combined to perform processing.

[0255] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0256] <Notes Regarding the Description in This Specification, etc.> The above embodiments and descriptions of each component in the embodiments are provided below.

[0257] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples can be appropriately combined.

[0258] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0259] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0260] Furthermore, a diagram (even if only a part) described in one embodiment can be combined with another part of that diagram, another diagram (even if only a part) described in the same embodiment, and / or a diagram (even if only a part) described in one or more other embodiments to form even more diagrams.

[0261] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification and can be appropriately rephrased.

[0262] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0263] In this specification and other documents, when describing the connections of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, etc.

[0264] Furthermore, in this specification, the terms "electrode" or "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0265] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0266] In this specification, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0267] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0268] In this specification, channel length refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of a transistor, or in the region where the channel is formed.

[0269] In this specification, channel width refers to, for example, the length of the portion where the source and drain face each other in the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the region where the channel is formed.

[0270] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be short-circuited. For example, in an n-channel transistor, the state in which the voltage between the gate and source is higher than the threshold voltage, or in a p-channel transistor, the state in which the voltage between the gate and source is lower than the threshold voltage, is called the "on state." The "on state" of a transistor is a state in which current can flow between the source and drain. Therefore, the state in which a transistor is "on" is sometimes referred to as the "conducting state" of the transistor.

[0271] In this specification, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered disconnected. For example, in an n-channel transistor, the state in which the voltage between the gate and source is lower than the threshold voltage, or in a p-channel transistor, the state in which the voltage between the gate and source is higher than the threshold voltage, is called the "off state." In some cases, the state of a transistor being in the "off state" is also referred to as the transistor being in a "non-conducting state."

[0272] In this specification, the voltage between the gate and source (gate-source) is sometimes referred to as the "gate voltage," the voltage between the drain and source (drain-source) is sometimes referred to as the "drain voltage," and the voltage between the back gate and source (back gate-source) is sometimes referred to as the "back gate voltage." In addition, the current flowing from the drain to the source is sometimes referred to as the "drain current."

[0273] In this specification, unless otherwise specified, the "off-current" of a transistor refers to the drain current when the transistor is in the off state. In this specification, the off-current, as well as the current flowing from the gate to the source and drain (also called gate leakage current), may be referred to as leakage current.

[0274] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship of circuit elements as a physical object, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" means, for example, that A and B are connected without the use of a circuit element (e.g., a transistor or a switch; however, wiring is not a circuit element) between them. On the other hand, "A and B are indirectly connected" means, for example, that A and B are connected through one or more circuit elements.

[0275] Here, when we define "A and B are indirectly connected," it refers to the following type of connection, as an example: That is, assuming the circuit is operating, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then such a circuit can be defined as having "A and B indirectly connected" as a physical object. Even if there are times when no electrical signals are exchanged or potential interactions occur between A and B, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined as having "A and B indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as a physical object. Therefore, for example, even if no power supply voltage is supplied to the circuit and the circuit is not operating, the circuit can still be defined as having "A and B indirectly connected" as a physical object (however, as an example, this is limited to cases where, when power supply voltage is supplied to the circuit and the circuit is operating, electrical signals are exchanged or potential interactions occur between A and B during the circuit's operation).

[0276] The following are specific examples of "indirect connections." First, an example of "A and B being indirectly connected" is when A and B are connected via the source and drain of one or more transistors. Another example of "A and B being indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming the circuit is operating, one transistor between A and B will be ON, conducting, or in a state where current can flow at least once. Note that "A and B are indirectly connected" includes cases where one transistor between A and B is OFF or non-conducting. When "A and B are indirectly connected" and multiple transistors are connected between A and B, assuming the circuit is operating, each of the multiple transistors between A and B will be ON, conducting, or in a state where current can flow at least once. In other words, when "A and B are indirectly connected," it is not necessary for all of the transistors to be in an ON state, a conducting state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it includes cases where the transistors between A and B are in an OFF state or a non-conducting state at the same time or at different times. As another example, when A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be discussed later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected," or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0277] Having shown examples of cases where a connection can be considered "indirect" and cases where it cannot, let's look at another example of a case where a connection cannot be considered "indirect." Even if electrical signals are exchanged or potential interactions occur between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of when A and B are connected via an insulator is when a capacitor is connected between A and B. Another example of when A and B are connected via an insulator is when a transistor gate insulating film is interposed between A and B. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0278] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. For example, if multiple transistors are connected via their sources and drains in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power source or GND, then it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected," or "B and V are indirectly connected." Furthermore, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power source or GND, then it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0279] As shown above, we have provided an example of "indirect connection." As an example, the provisions for "indirect connection" are included in the provisions for "electrical connection," so if "A and B are indirectly connected," then "A and B are electrically connected."

[0280] Next, let's look at specific examples of "direct connections." An example of "A and B being directly connected" is when A and B are connected without any circuit elements in between. If A and B are connected to a power source that supplies a constant potential V, or to GND, without any circuit elements in between, then we can say that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Even if A (or B) is connected to a constant potential V via the source and drain of a transistor, we can still say that "A and B are directly connected." However, since A and V, or B and V, are connected via the source and drain of a transistor, they cannot be considered directly connected, and we can say that "A and V are indirectly connected," or "B and V are indirectly connected."

[0281] As shown above, an example of "direct connection" has been given, but as an example, since the provisions for "direct connection" are included in the provisions for "electrical connection," if "A and B are directly connected," then "A and B are electrically connected."

[0282] GL: Gate line, IDATA: Data current, IMONI: Monitor current, ML: Monitor line, MOL: Monitor current line, SL: Source line, VDATA: Data voltage, VMONI: Correction signal, 20: Element layer, 21: Processor circuit, 22: Display driver circuit, 23: Signal conversion circuit, 25: Signal readout circuit section, 26: Signal readout circuit, 27: Integrator circuit, 28: Analog-to-digital conversion circuit, 29: Terminal section, 30: Element layer, 31: Display section, 32: Gate line driver circuit, 33: Source line driver circuit, 34: Digital-to-analog conversion circuit, 35: Amplifier circuit, 40: Encapsulated substrate, 51: Pixel circuit, 71: Memory circuit, 100: Display device

Claims

1. A display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor has a semiconductor layer having a channel formation region made of silicon, the second element layer has a second transistor, the second transistor has a semiconductor layer having a channel formation region made of oxide semiconductor, the first element layer is provided with a signal conversion circuit, a memory circuit, a processor circuit, and a display drive circuit, the second element layer is provided with a pixel circuit electrically connected to a monitor line and a signal readout circuit electrically connected to the signal conversion circuit via a monitor current line, the signal readout circuit has the function of transmitting the current flowing through the pixel circuit via the monitor line to the monitor current line, the signal conversion circuit has the function of converting the amount of analog current flowing through the monitor current line into digital correction data, the memory circuit has the function of storing the correction data, and the processor circuit has the function of correcting the data voltage supplied from the display drive circuit to the pixel circuit according to the correction data.

2. The display device according to claim 1, wherein the pixel circuit comprises a light-emitting element and a drive transistor that supplies a current to the light-emitting element according to the data voltage, and the current flowing through the monitor line is the current flowing through the drive transistor.

3. The display device according to claim 1 or 2, wherein the signal conversion circuit comprises an integrating circuit that converts the amount of current flowing through the monitor current line into an analog voltage value, and an analog-to-digital conversion circuit that converts the voltage value into correction data for the digital value.

4. The display device according to claim 1 or 2, wherein the monitor line is arranged in a direction parallel to the surfaces of the first element layer and the second element layer, and the monitor current line has a portion arranged in a direction perpendicular to the surfaces of the first element layer and the second element layer.

5. A display device according to claim 1 or 2, comprising a third element layer having the second transistor, wherein the third element layer is provided between the first element layer and the second element layer, and the third element layer has the memory circuit.

6. A display device according to claim 1 or 2, wherein the oxide semiconductor is indium oxide.

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