Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display apparatus. The display panel comprises a display area and a peripheral area located around the display area, wherein the peripheral area comprises a first peripheral area and a second peripheral area; the first peripheral area has a plurality of peripheral traces, and the peripheral traces form at least one first trace group; the first trace group comprises a first peripheral trace, a second peripheral trace and a third peripheral trace; in the same first trace group, the first peripheral trace has a first peripheral main trace, the second peripheral trace has a second peripheral main trace, and the third peripheral trace has a third peripheral main trace; the first peripheral main trace and the second peripheral main trace are arranged in the same layer and adjacent to each other, and are located in a different film layer from the third peripheral main trace; and the orthographic projection of a gap between the first peripheral main trace and the second peripheral main trace in a plane where the display panel is located, is located within the orthographic projection of the third peripheral main trace in the plane where the display panel is located. The present disclosure facilitates a narrow bezel of the display panel. (FIG. 8)

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] With the rapid iteration of electronic products (such as mobile phones and computers), the concept of partial refresh has emerged. Electronic products with partial refresh functionality require more drive signals than ordinary electronic products, which necessitates larger wiring space, increases the product's bezel width, and hinders the development of narrow bezels.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device to facilitate narrow bezels in the display panel.

[0005] According to one aspect of this disclosure, a display panel is provided, including a display area and a peripheral area surrounding the display area;

[0006] The peripheral area includes a first peripheral area located between the display area and the bonding end of the display panel, and a second peripheral area adjacent to the first peripheral area and provided with a gate driving circuit.

[0007] The second peripheral region has a plurality of gate drive circuit traces for loading drive signals to the gate drive circuit;

[0008] The first peripheral region has multiple peripheral traces, and the multiple peripheral traces form at least one first trace group; the first trace group includes a first peripheral trace, a second peripheral trace, and a third peripheral trace, and the first peripheral trace, the second peripheral trace, and the third peripheral trace are all used to apply a drive signal to the gate drive circuit trace;

[0009] In the same first routing group, the first peripheral routing has a first peripheral main routing, the second peripheral routing has a second peripheral main routing, and the third peripheral routing has a third peripheral main routing;

[0010] The first peripheral main trace and the second peripheral main trace are arranged in the same layer and adjacent to each other, and are located in different film layers from the third peripheral main trace; the orthographic projection of the gap between the first peripheral main trace and the second peripheral main trace on the plane where the display panel is located is located within the orthographic projection of the third peripheral main trace on the plane where the display panel is located.

[0011] In one embodiment of this disclosure, within the same first wiring group, the extension trajectories of the first peripheral main wiring, the second peripheral main wiring, and the third peripheral main wiring are consistent.

[0012] In one embodiment of this disclosure, within the same first wiring group, the orthographic projection of the third peripheral main wiring onto the plane where the display panel is located is within the orthographic projection of the overall structure formed by the first peripheral main wiring, the second peripheral main wiring, and the gap between the first peripheral main wiring and the second peripheral main wiring onto the plane where the display panel is located.

[0013] In one embodiment of this disclosure, within the same first wiring group, the first peripheral main wiring includes a first upper wiring and a first lower wiring; the first upper wiring and the first lower wiring are located in different film layers; the extension trajectory of the first upper wiring and the extension trajectory of the first lower wiring are the same;

[0014] The second peripheral main routing includes a second upper routing and a second lower routing; the second upper routing and the second lower routing are located in different film layers; the extension trajectory of the second upper routing and the extension trajectory of the second lower routing are the same.

[0015] In one embodiment of this disclosure, in at least one of the first trace groups, the first peripheral trace, the second peripheral trace, and the third peripheral trace are respectively used to load different power supply voltage signals.

[0016] In one embodiment of this disclosure, in at least one of the first trace groups, the first peripheral trace is used to apply a first low-level power supply voltage, the second peripheral trace is used to apply a second low-level power supply voltage, and the third peripheral trace is used to apply a third low-level power supply voltage.

[0017] In one embodiment of this disclosure, in at least one of the first trace groups, the first peripheral trace is used to apply a first high-level power supply voltage, the second peripheral trace is used to apply a second high-level power supply voltage, and the third peripheral trace is used to apply a third high-level power supply voltage.

[0018] In one embodiment of this disclosure, the display panel has at least one second wiring group in the first peripheral area; the second wiring group includes a fourth peripheral wiring, a fifth peripheral wiring, and a sixth peripheral wiring.

[0019] In at least one of the second wiring groups, one or two of the fourth peripheral wiring, the fifth peripheral wiring, and the sixth peripheral wiring are used to apply a drive signal to the gate drive circuit wiring;

[0020] In the same second routing group, the fourth peripheral routing has a fourth peripheral main routing, the fifth peripheral routing has a fifth peripheral main routing, and the sixth peripheral routing has a sixth peripheral main routing;

[0021] The fourth and fifth peripheral main traces are arranged in the same layer and adjacent to each other, and are located in different film layers from the sixth peripheral main trace; the orthographic projection of the gap between the fourth and fifth peripheral main traces on the plane of the display panel is located within the orthographic projection of the sixth peripheral main trace on the plane of the display panel.

[0022] In one embodiment of this disclosure, in at least one of the second trace groups, one of the fourth peripheral trace, the fifth peripheral trace, and the sixth peripheral trace is used to apply an initialization voltage.

[0023] In one embodiment of this disclosure, at least one of the traces in the first trace group is directly electrically connected to the corresponding gate drive circuit trace.

[0024] In one embodiment of this disclosure, the peripheral wiring includes a first connecting line; the display panel has adapter wiring in the display area that corresponds one-to-one with the first connecting line;

[0025] The first connection line is electrically connected to the corresponding gate drive circuit trace through the adapter trace.

[0026] In one embodiment of this disclosure, the display panel is provided with a plurality of first edge integrated traces extending along a first direction and a plurality of second edge integrated traces extending along a second direction; the transition traces include first transition traces and second transition traces.

[0027] The first adapter trace is part of the second edge integrated trace, and one end of the first adapter trace is electrically connected to the first edge integrated trace, and the other end is electrically connected to the first connecting line.

[0028] The second adapter trace is part of the first edge integrated trace, and one end of the second adapter trace is electrically connected to the second edge integrated trace, and the other end is electrically connected to the gate drive circuit trace.

[0029] In one embodiment of this disclosure, the display panel has at least one first connection line group in the first peripheral area; one gate drive circuit trace corresponds to one first connection line group, and the first connection line group has multiple first connection lines;

[0030] Each of the first connecting lines in the first connecting line group is electrically connected to the corresponding gate drive circuit line through the corresponding adapter line.

[0031] In one embodiment of this disclosure, the display panel is provided with second connecting lines that correspond one-to-one with at least a portion of the first connecting line groups, and the second connecting lines are part of the second edge integrated wiring;

[0032] The gate drive circuit traces corresponding to the first connection line group are electrically connected to the corresponding second connection line through the third connection line, and each of the first connection lines in the same first connection line group is electrically connected to the corresponding second connection line through the corresponding adapter trace.

[0033] According to another aspect of this disclosure, a display device is also provided, including the display panel described above.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0036] Figure 1 is a schematic diagram of a display panel in one embodiment of this disclosure.

[0037] Figure 2 is a schematic diagram of a display panel in one embodiment of this disclosure.

[0038] Figure 3 is a schematic diagram of a display panel in one embodiment of this disclosure.

[0039] Figure 4 is a schematic diagram of a display panel in one embodiment of this disclosure.

[0040] Figure 5 is a schematic diagram of the wiring of the gate drive circuit in one embodiment of this disclosure.

[0041] Figure 6 is a schematic diagram of a display panel in one embodiment of this disclosure.

[0042] Figure 7 is a schematic diagram of a display panel in one embodiment of this disclosure.

[0043] Figure 8 is a schematic diagram of the wiring of the gate drive circuit in one embodiment of this disclosure.

[0044] Figure 9 is a schematic diagram of the film layer of the first wiring group in one embodiment of this disclosure.

[0045] Figure 10 is a schematic diagram of the film layer of the second wiring group in one embodiment of this disclosure.

[0046] Figure 11 is a schematic diagram of the connection between the first connecting line and the adapter cable in Figure 7.

[0047] Figure 12 is a schematic diagram of a display panel in one embodiment of this disclosure.

[0048] Figure 13 is a schematic diagram of the connection between the first connecting line group and the adapter wiring in Figure 12, which is intended to illustrate the loading of a drive signal through two first connecting lines.

[0049] Figure 14 is a schematic diagram of a display panel in one embodiment of this disclosure.

[0050] Figure 15 is a schematic diagram of the first source / drain metal layer in one embodiment of this disclosure.

[0051] Figure 16 is a schematic diagram of the second source / drain metal layer in one embodiment of this disclosure. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0053] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0054] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0055] In this embodiment, the thin-film transistor includes an active layer, a gate insulating layer, and a gate, stacked together. The active layer is located within the semiconductor layer and includes a channel region and a source and a drain located on opposite sides of the channel region. The channel region maintains semiconductor characteristics, while both the source and drain are conductive. In this embodiment, the functions of the "source" and "drain" are sometimes interchanged when using transistors with opposite polarities or when the current direction changes during circuit operation. In this embodiment, for any given transistor, one of the "source" and "drain" is referred to as the first terminal of the transistor, and the other as the second terminal. In this embodiment, at least a portion of the signal has a high level and a low level; one of the high and low levels can serve as the gating level of the signal, which enables the controlled transistor to conduct; the other of the high and low levels can serve as the cutoff level of the signal, which enables the controlled transistor to cut off. For example, for a signal controlling a P-type transistor (that can be applied to the control terminal of the P-type transistor), its strobe level is low and its cutoff level is high. As another example, for a signal controlling an N-type transistor (that can be applied to the control terminal of the N-type transistor), its strobe level is high and its cutoff level is low.

[0056] Structural layer A is located on the side of structural layer B that faces away from the substrate. This can be understood as structural layer A being formed on the side of structural layer B that faces away from the substrate. When structural layer B is a patterned structure, some structures of structural layer A may also be located at the same physical height as structural layer B or at a lower physical height than structural layer B, where the substrate serves as the height reference.

[0057] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. For example, film layers located on the same layer can be film layers with a specific pattern formed using the same film-forming process. Of course, film layers with a specific pattern can also be located at different heights or have different thicknesses.

[0058] In one embodiment of this disclosure, the first direction and the second direction are perpendicular to each other. In one example, the first direction can be a row direction, and the second direction can be a column direction. In another example, the first direction can be a column direction, and the second direction can be a row direction.

[0059] This disclosure provides a display device. The display device includes a display panel. The display device can be a television screen, computer screen, smartphone screen, smartwatch screen, or other types of display device.

[0060] In one embodiment of this disclosure, referring to FIG1, a display panel PNL is provided with an array of display units in the display area AA. Each display unit includes a sub-pixel PIX and a pixel driving circuit that drives the sub-pixel PIX. The display panel PNL does not provide display units in the peripheral area BB, or the provided display units are not used for displaying images. Referring to FIG1, the display panel PNL provides multiple scan lines GL extending along a first direction DH in the display area AA, with each scan line GL corresponding to a row of display units. The pixel driving circuit of each display unit in each row of display units is electrically connected to the corresponding scan line GL. The display panel PNL also provides multiple data lines DL extending along a second direction DV in the display area AA, with each data line DL corresponding to a column of display units. The pixel driving circuit of each display unit in each column of display units is electrically connected to the corresponding data line DL. Thus, the pixel driving circuit of each display unit is connected to both the scan line GL and the data line DL. A scan signal is loaded onto the scan line GL to control the state of the pixel driving circuit. It is understood that the example in Figure 1 only illustrates one type of scan line GL corresponding to the display unit row; as needed, the display panel PNL can be configured with multiple different scan lines GL corresponding to the display unit row. A data voltage Vdata for driving the pixel driving circuit can be loaded onto the data line DL. The pixel driving circuit can drive the sub-pixel PIX according to the written data voltage Vdata, thereby controlling the brightness of the sub-pixel PIX. It is also understood that the pixel driving circuit can control the brightness of the sub-pixel PIX according to other signals.

[0061] Optionally, the pixel driving circuit includes at least a data writing transistor, a driving transistor, and a storage capacitor. The gate of the driving transistor can be electrically connected to one electrode plate of the storage capacitor. The source of the data writing transistor can be electrically connected to the data line DL, and the gate of the data writing transistor can be electrically connected to a write control line used to load a data writing signal (a scan signal). The pixel driving circuit is configured such that when a pass level of the data writing signal is applied to the write control line, the data writing transistor is turned on, thereby causing the driving voltage on the data line DL to be written to the gate of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It is understood that the pixel driving circuit of the present disclosure embodiment may also include other transistors or capacitors to give the pixel driving circuit better driving performance. For example, the pixel driving circuit can be a 7T1C (7 thin film transistors and one storage capacitor), an 8T1C (8 thin film transistors and one storage capacitor), or a pixel driving circuit with other architectures.

[0062] Optionally, the sub-pixel PIX can be a current-driven self-emissive element, such as any one of OLED, PLED, QLED, Micro LED, Mini LED, etc. In this embodiment, the sub-pixel PIX can include multiple sub-pixel PIXs of different colors, such as a red sub-pixel for emitting red light, a blue sub-pixel for emitting blue light, and a green sub-pixel for emitting green light. It is understood that in other embodiments of this disclosure, the sub-pixel PIX in the display area AA can also have sub-pixel PIXs of other colors (e.g., a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).

[0063] Referring to Figure 2, in this display panel PNL, a gate drive circuit GOA is provided in the peripheral area BB to provide scan signals to the pixel drive circuit. Depending on the needs of the pixel drive circuit, multiple gate drive circuits GOA can be provided in the peripheral area BB to provide different scan signals. Alternatively, some scan signals can share a single gate drive circuit GOA.

[0064] Optionally, depending on the needs of the pixel driving circuit, the scanning signal may include, but is not limited to, one or more of the following signals: a write control signal for controlling the data voltage to be written to the pixel driving circuit, a light emission control signal for controlling the output drive current of the pixel driving circuit, and a reset control signal for controlling the reset of the pixel driving circuit.

[0065] In one embodiment of this disclosure, referring to FIG2, a gate driving circuit GOA is disposed in the peripheral region BB, and the gate driving circuit GOA includes a plurality of shift registers SR connected in sequence. The shift registers SR can output the scan signals required by the respective pixel driving circuits in the corresponding pixel row. The input terminal of the Nth-stage shift register SR is electrically connected to the output terminal of the (NX)th-stage shift register SR, where N is an integer greater than 0, and X is an integer greater than 0 and less than N. For example, the input terminal of the third-stage shift register SR is electrically connected to the output terminal of the second-stage shift register SR. As another example, the input terminal of the third-stage shift register SR is electrically connected to the output terminal of the first-stage shift register SR. As yet another example, the input terminal of the fourth-stage shift register SR is electrically connected to the output terminal of the first-stage shift register SR.

[0066] Figure 3 is a schematic diagram illustrating the film layer structure of a display panel PNL according to an embodiment of the present disclosure. Referring to Figure 3, in some embodiments of the present disclosure, the display panel PNL includes a driving layer DRL and a pixel layer PIXL sequentially stacked on the substrate SBT;

[0067] Optionally, the substrate SBT can be an inorganic material substrate SBT or an organic material substrate SBT; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrate SBTs. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass.

[0068] In other embodiments of this disclosure, the substrate SBT may be made of polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT may also be a flexible substrate, for example, the material of the substrate SBT may include polyimide.

[0069] Optionally, in the driving layer DRL, any pixel driving circuit may include a thin-film transistor and a storage capacitor (not shown in the accompanying drawings). Further, the thin-film transistor may be selected from top-gate, bottom-gate, or dual-gate thin-film transistors; the material of the active layer of the thin-film transistor may be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin-film transistor may be an N-type or P-type thin-film transistor.

[0070] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. Exemplarily, in some embodiments, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in other embodiments, in a pixel driving circuit, the active layer material of some transistors can be low-temperature polycrystalline silicon (LTPS) semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor (MODS) semiconductor material. In some embodiments of this disclosure, the thin-film transistor is a LPS transistor. In other embodiments of this disclosure, some thin-film transistors are LPS transistors, and some thin-film transistors are MODS transistors.

[0071] Optionally, referring to FIG3, the driving layer DRL may include a buffer layer (e.g., the first buffer layer Buff1 and the second buffer layer Buff2 shown in FIG3) stacked on the substrate SBT, a metal light-shielding layer BSM disposed between the first buffer layer Buff1 and the substrate SBT, a semiconductor layer in the pixel layer PIXL (e.g., a low-temperature polysilicon semiconductor layer PSCL and a metal oxide semiconductor layer OSCL), a gate insulating layer (e.g., the first gate insulating layer GI1, the second gate insulating layer GI2 and the third gate insulating layer GI3 shown in FIG3), a gate layer (e.g., the first gate layer GT1 and the second gate layer GT2 shown in FIG3), an interlayer dielectric layer ILD, a source drain metal layer (e.g., the first source drain metal layer SD1 and the second source drain metal layer SD2 shown in FIG3), a planarization layer (e.g., the first planarization layer PLN1 and the second planarization layer PLN2 shown in FIG3), etc. Each thin-film transistor and storage capacitor (not specifically labeled in the accompanying drawings) can be formed from a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer (ILD), a source / drain metal layer, and other film layers; alternatively, other film layers can also be used. The positional relationship of each film layer can be determined based on the film layer structure of the thin-film transistor. Furthermore, the semiconductor layer can be used to form the active layer of the transistor (including the first electrode, second electrode, and channel region of the transistor), and can also be conductively formed to create partial traces or conductive structures when necessary. The first source / drain metal layer SD1 can be used to form scan signal traces; the gate layer can be used to form one or more gate layer traces such as reset control signal traces and light emission control signal traces, or it can be used to form the gate of the transistor, or it can be used to form part or all of the electrode plates of the storage capacitor. The source / drain metal layer can be used to form data lines, drive power supply voltage traces, or other source / drain metal layer traces, or it can be used to form part of the electrode plates of the storage capacitor.

[0072] Of course, in other embodiments of this disclosure, the driving layer DRL may also include other film layers as needed, such as a metal light-shielding layer BSM located between the semiconductor layer and the substrate SBT. As needed, any one of the aforementioned semiconductor layer, gate layer, source / drain metal layers, etc., may be multiple layers. For example, the driving layer DRL may include two different semiconductor layers, or two or three source / drain metal layers, or two or three gate layers. Correspondingly, the insulating film layers in the driving layer DRL (e.g., gate insulating layer, interlayer dielectric layer ILD, planarization layer, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0073] Optionally, the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes PE in the display area of ​​the display panel. The pixel definition layer PDL has multiple through-holes corresponding to the multiple pixel electrodes PE, with each pixel opening exposing at least a portion of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the internal area of ​​the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer EL), thereby defining the light-emitting area and light-emitting region of the sub-pixel. The common electrode layer COML covers the light-emitting functional layer EL as a common electrode. The pixel electrodes PE and the common electrode layer COML provide electrons, holes, and other charge carriers to the light-emitting functional layer EL, causing the light-emitting functional layer EL to emit light. The portion of the light-emitting functional layer EL located between the pixel electrodes and the common electrode layer COML can serve as the light-emitting functional unit of the sub-pixel. The pixel electrodes PE, the common electrode layer COML, and the light-emitting functional unit form the light-emitting element of the sub-pixel. In this design, one of the pixel electrode PE and the common electrode layer COML serves as the anode of the sub-pixel, and the other serves as the cathode of the sub-pixel.

[0074] In this example, the display panel is an OLED (Organic Light Emitting Diode) display panel. The light-emitting functional layer EL may include an organic light-emitting layer, and may include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. Furthermore, the organic light-emitting layer may include a host material and a guest material, wherein the guest material may be a fluorescent dopant or a phosphorescent dopant, and particularly may be a thermally activated delayed fluorescence material.

[0075] It is understandable that the display panel can also be other types of display panels, such as QLED display panels, QD-OLED display panels, or other types of display panels.

[0076] Referring to Figure 3, the display panel may further include a thin-film encapsulation layer (TFE). The TFE can be disposed on the surface of the pixel layer (PIXL) away from the substrate (SBT), and may include alternately stacked inorganic and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer (PIXL) and causing material aging. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer.

[0077] Exemplarily, the thin-film encapsulation layer (TFE) includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer (not specifically shown in this figure) sequentially stacked on the side of the pixel layer (PIXL) away from the substrate (SBT). The first inorganic encapsulation layer covers the display area and extends to the outside of the barrier; the organic encapsulation layer covers the display area and extends to the inside of the barrier; the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the barrier. On the outside of the barrier, the second inorganic encapsulation layer contacts the first inorganic encapsulation layer. In this way, the organic encapsulation layer is sealed by the first and second inorganic encapsulation layers, balancing the stress of the first and second inorganic encapsulation layers. The first and second inorganic encapsulation layers seal the organic encapsulation layer, isolating it from contact with water and oxygen. Of course, in other embodiments of this disclosure, the display panel may not have a thin-film encapsulation layer (TFE), but may use other methods to encapsulate and protect the pixel layer.

[0078] In some embodiments of this disclosure, the display panel may further include a touch metal layer (not specifically shown in the accompanying drawings), which may be disposed on the side of the thin-film transistor away from the pixel layer PIXL, so that the display panel has touch functionality.

[0079] In this embodiment, referring to FIG3, the driving layer DRL may further include a transistor layer TL, a first source / drain metal layer SD1, and a second source / drain metal layer SD2; the transistor layer TL is a combination of various film layers disposed between the substrate SBT and the first source / drain metal layer SD1, which can form various thin-film transistors required for the pixel driving circuit.

[0080] The bezel of the display panel PNL is limited by the driving circuit and packaging design. With the rise of electronic products with partial refresh functions, the driving signals required by the display panel PNL increase, leading to increased wiring space and hindering the narrowing of the display panel PNL bezel. For example, referring to Figure 4, in order to provide driving signals to the gate drive circuit (GOA, Gate Driven on Array), the gate drive circuit traces pass through the fanout area of ​​the display panel and the corner area located around the display area AA, and finally connect to the gate drive circuit. However, the more gate drive circuit traces there are, the larger the space required in the fanout area and corner area, thus increasing the bezel width of the display panel PNL (see Figures 4 and 5, where the various gate drive circuit traces are routed side by side, occupying a large space area).

[0081] To address the aforementioned problems, in one embodiment of this disclosure, referring to Figures 6-9, the peripheral region BB includes a first peripheral region BB1 located between the bonding ends of the display area AA and the display panel PNL, and a second peripheral region BB2 adjacent to the first peripheral region BB1 and provided with a gate drive circuit GOA. The second peripheral region BB2 has multiple gate drive circuit traces GOAL for loading drive signals to the gate drive circuit GOA; the first peripheral region BB1 has multiple peripheral traces TRL, which form at least one first trace group LS; the first trace group LS includes a first peripheral trace TRL1, a second peripheral trace TRL2, and a third peripheral trace TRL3, all of which are used to load drive signals to the gate drive circuit traces GOAL; within the same first trace group LS, the first peripheral... The trace TRL1 has a first peripheral main trace TRL1A, the second peripheral trace TRL2 has a second peripheral main trace TRL2A, and the third peripheral trace TRL3 has a third peripheral main trace TRL3A; wherein, the first peripheral main trace TRL1A and the second peripheral main trace TRL2A are arranged in the same layer and adjacent to each other, and are located in a different film layer from the third peripheral main trace TRL3A; the orthographic projection of the gap between the first peripheral main trace TRL1A and the second peripheral main trace TRL2A on the plane where the display panel PNL is located is within the orthographic projection of the third peripheral main trace TRL3A on the plane where the display panel PNL is located. Thus, in the same first trace group LS, from the perspective of film layer structure, the first peripheral main trace TRL1A and the second peripheral main trace TRL2A are located in the same film layer, and are located in a different film layer from the third peripheral main trace TRL3A. From the perspective of planar structure, the orthographic projection of the third peripheral main trace TRL3A on the plane where the display panel PNL is located covers the orthographic projection of the gap between the first peripheral main trace TRL1A and the second peripheral main trace TRL2A on the plane where the display panel PNL is located. Compared with the method of multiple gate driving circuit traces GOAL located in the same film layer and running side by side in related technologies, the overlapping wiring method of gate driving circuit traces GOAL in this disclosure can reduce the space area of ​​the first peripheral area BB1 occupied by the gate driving circuit traces GOAL, which is beneficial to reduce the bezel width of the display panel PNL and facilitates the narrow bezel of the display panel PNL.

[0082] In one embodiment of this disclosure, the display panel PNL may have a partial refresh function. In other embodiments of this disclosure, the display panel PNL may not have a partial refresh function.

[0083] In one embodiment of this disclosure, the corner shape of the corner area of ​​the display panel PNL can be a rounded corner, an elliptical corner, a square corner, or an irregularly shaped corner.

[0084] In one embodiment of this disclosure, the drive signal may include at least one of a high-level power supply voltage VGH (not shown in the figures), a low-level power supply voltage VGL (not shown in the figures), a start signal STV (not shown in the figures), and a reset signal CX (not shown in the figures). The high-level power supply voltage VGH may include a first high-level power supply voltage VGH1 (not shown in the figures), a second high-level power supply voltage VGH2 (not shown in the figures), a third high-level power supply voltage VGH3 (not shown in the figures), and a fourth high-level power supply voltage VGH4 (not shown in the figures). In one example, the first high-level power supply voltage VGH1, the second high-level power supply voltage VGH2, the third high-level power supply voltage VGH3, and the fourth high-level power supply voltage VGH4 may be the same high-level power supply voltage VGH. In another example, the first high-level power supply voltage VGH1, the second high-level power supply voltage VGH2, the third high-level power supply voltage VGH3, and the fourth high-level power supply voltage VGH4 may be different high-level power supply voltages VGH.

[0085] The low-level power supply voltage VGL may include a first low-level power supply voltage VGL1 (not shown in the figures), a second low-level power supply voltage VGL2 (not shown in the figures), a third low-level power supply voltage VGL3 (not shown in the figures), and a fourth low-level power supply voltage VGL4 (not shown in the figures), etc. In one example, the first low-level power supply voltage VGL1, the second low-level power supply voltage VGL2, the third low-level power supply voltage VGL3, and the fourth low-level power supply voltage VGL4 may be the same low-level power supply voltage VGL. In another example, the first low-level power supply voltage VGL1, the second low-level power supply voltage VGL2, the third low-level power supply voltage VGL3, and the fourth low-level power supply voltage VGL4 may be different low-level power supply voltages VGL.

[0086] The start signal STV (not shown in the attached diagram) may include a first start signal PSTV (not shown in the attached diagram), a second start signal ESTV (not shown in the attached diagram), and a third start signal NSTV (not shown in the attached diagram). The first start signal PSTV provides the start signal STV to the first gate drive circuit PGOA (not shown in the attached diagram). The second start signal ESTV provides the start signal STV to the second gate drive circuit EGOA (not shown in the attached diagram). The third start signal NSTV provides the start signal STV to the third gate drive circuit NGOA (not shown in the attached diagram). The first gate drive circuit PGOA provides a control signal to the gate of the P-type transistor in the pixel drive circuit, enabling the P-type transistor to turn on and off; for example, the P-type transistor may be a thin-film transistor such as a data write transistor or an electrode reset transistor in the pixel drive circuit. The second gate drive circuit EGOA provides a light emission control signal to the gate of the light emission control transistor in the pixel drive circuit, enabling the light emission control transistor to turn on and off. The third gate drive circuit NGOA is used to provide control signals to the gate of the N-type transistor in the pixel drive circuit, so that the N-type transistor in the pixel drive circuit can be turned on and off; for example, the N-type transistor can be a thin film transistor such as a threshold compensation transistor or a gate reset transistor in the pixel drive circuit.

[0087] The reset signal CX (not shown in the attached diagram) may include a second reset signal ECX (not shown in the attached diagram), a third reset signal NCX (not shown in the attached diagram), and a first reset signal PCX (not shown in the attached diagram). The second reset signal ECX provides the reset signal CX to the second gate drive circuit EGOA. The third reset signal NCX provides the reset signal CX to the third gate drive circuit NGOA. The first reset signal PCX provides the reset signal CX to the first gate drive circuit PGAA. The reset signal CX provides a reset control signal to the gate of the reset transistor in the gate drive circuit GOA, thereby resetting the gate drive circuit GOA.

[0088] In one embodiment of this disclosure, referring to FIG8, within the same first trace group LS, the extension trajectories of the first peripheral main trace TRL1A, the second peripheral main trace TRL2A, and the third peripheral main trace TRL3A are consistent. In other words, the first peripheral main trace TRL1A, the second peripheral main trace TRL2A, and the third peripheral main trace TRL3A are arranged side by side, and the first peripheral main trace TRL1A and the second peripheral main trace TRL2A are located in the same film layer, while the third peripheral main trace TRL3A is located in a different film layer than the first peripheral main trace TRL1A. For example, the first peripheral main trace TRL1A and the second peripheral main trace TRL2A may be located in the first gate layer, and the third peripheral main trace TRL3A may be located in the second gate layer. In this way, the first peripheral main trace TRL1A, the second peripheral main trace TRL2A, and the third peripheral main trace TRL3A can be arranged neatly, so as to further reduce the space area of ​​the first peripheral area BB1 occupied by the gate drive circuit trace GOAL, thereby further reducing the space area of ​​the first peripheral area BB1, which is beneficial to the narrow bezel of the display panel PNL.

[0089] In one embodiment of this disclosure, referring to Figures 8 and 9, within the same first wiring group LS, the orthographic projection of the third peripheral main wiring TRL3A onto the plane of the display panel PNL is located within the orthographic projection of the overall structure formed by the gaps between the first peripheral main wiring TRL1A, the second peripheral main wiring TRL2A, and the first and second peripheral main wiring TRL1A and TRL2A onto the plane of the display panel PNL. This arrangement allows the third peripheral main wiring TRL3A to overlap with the first and second peripheral main wiring TRL1A and TRL2A respectively, further reducing the spatial area of ​​the first peripheral region BB1.

[0090] In one embodiment of this disclosure, referring to FIG9, within the same first trace group LS, the first peripheral main trace TRL1A includes a first upper trace TRL1A1 and a first lower trace TRL1A2. The first upper trace TRL1A1 and the first lower trace TRL1A2 are located in different film layers; the extension trajectory of the first upper trace TRL1A1 is the same as the extension trajectory of the first lower trace TRL1A2. The second peripheral main trace TRL2A includes a second upper trace TRL2A1 and a second lower trace TRL2A2. The second upper trace TRL2A1 and the second lower trace TRL2A2 are located in different film layers; the extension trajectory of the second upper trace TRL2A1 is the same as the extension trajectory of the second lower trace TRL2A2. In other words, the first peripheral main trace TRL1A and the second peripheral main trace TRL2A are double-film-layer traces to increase the width of the first peripheral trace TRL1 and the second peripheral trace TRL2, and reduce the resistance of the first peripheral trace TRL1 and the second peripheral trace TRL2.

[0091] In one embodiment of this disclosure, from the perspective of the film structure, referring to FIG9, in the same first wiring group LS, the first peripheral main wiring TRL1A and the second peripheral main wiring TRL2A are both double film layer wirings, and the third peripheral main wiring TRL3A is stacked on the first peripheral main wiring TRL1A and the second peripheral main wiring TRL2A and interspersed in the gap between the first peripheral main wiring TRL1A and the second peripheral main wiring TRL2A.

[0092] For example, referring to Figure 9, a first gate layer GT1, a second gate layer GT2, and a third gate layer GT3 are sequentially stacked on the substrate SBT. A first upper trace TRL1A1 is disposed on the first gate layer GT1, and a first lower trace TRL1A2 is disposed on the second gate layer GT2. The orthographic projection of the first lower trace TRL1A2 onto the plane of the display panel PNL lies within the orthographic projection of the first upper trace TRL1A1 onto the plane of the display panel PNL. A second upper trace TRL2A1 is disposed on the first gate layer GT1, and a second lower trace TRL2A2 is disposed on the second gate layer GT2. The orthographic projection of the second lower trace TRL2A2 onto the plane of the display panel PNL lies within the orthographic projection of the second upper trace TRL2A1 onto the plane of the display panel PNL. The third peripheral main trace TRL3A has two first horizontal segments, one second horizontal segment, and two inclined segments. One of the first horizontal segments has its orthographic projection on the plane of the display panel PNL located within the orthographic projection of the first upper trace TRL1A1 on the plane of the display panel PNL; the other first horizontal segment has its orthographic projection on the plane of the display panel PNL located within the orthographic projection of the second upper trace TRL2A1 on the plane of the display panel PNL. The orthographic projection of the second horizontal segment on the plane of the display panel PNL is located within the orthographic projection of the gap between the first peripheral main trace TRL1A and the second peripheral main trace TRL2A on the plane of the display panel PNL, and the second horizontal segment is disposed on the third gate layer GT3. One of the first horizontal segments is electrically connected to the second horizontal segment through a tilted segment, and the other first horizontal segment is electrically connected to the second horizontal segment through another tilted segment, so that the two first horizontal segments, one second horizontal segment, and two tilted segments are electrically connected to each other. In other words, the third peripheral main trace TRL3A is disposed on the third gate layer GT3. Thus, by overlapping the third peripheral main trace TRL3A with the first peripheral main trace TRL1A and the second peripheral main trace TRL2A respectively, and when the first peripheral main trace TRL1A and the second peripheral main trace TRL2A are double-layer traces, the trace width of the third peripheral main trace TRL3A is much larger than the trace width of the first peripheral main trace TRL1A or the second peripheral main trace TRL2A (for example, the trace width of the third peripheral main trace TRL3A is twice the trace width of the first peripheral main trace TRL1A), which effectively reduces the resistance of the third peripheral main trace TRL3A.

[0093] It is understood that other film layers may be disposed between the substrate SBT, the first gate layer GT1, the second gate layer GT2, and the third gate layer GT3. For example, a gate insulating layer may be disposed between the first gate layer GT1 and the second gate layer GT2 to insulate the first gate layer GT1 and the second gate layer GT2.

[0094] In one embodiment of this disclosure, referring to FIG8, in the same first trace group LS, the first peripheral trace TRL1 further includes a first peripheral secondary trace TRL1B electrically connected to the first peripheral main trace TRL1A. The second peripheral trace TRL2 further includes a second peripheral secondary trace TRL2B electrically connected to the second peripheral main trace TRL2A. The third peripheral trace TRL3 further includes a third peripheral secondary trace TRL3B electrically connected to the third peripheral main trace TRL3A. The extension trajectories of the first peripheral secondary trace TRL1B, the second peripheral secondary trace TRL2B, and the third peripheral secondary trace TRL3B are consistent, so that the first peripheral secondary trace TRL1B, the second peripheral secondary trace TRL2B, and the third peripheral secondary trace TRL3B are arranged side by side, and the first peripheral secondary trace TRL1B, the second peripheral secondary trace TRL2B, and the third peripheral secondary trace TRL3B are used for electrical connection with the driver chip to realize the loading of the drive signal onto the peripheral trace TRL.

[0095] In one embodiment of this disclosure, in at least one first trace group LS, a first peripheral trace TRL1, a second peripheral trace TRL2, and a third peripheral trace TRL3 are respectively used to load different power supply voltage signals. The power supply voltage signals can be a high-level power supply voltage VGH or a low-level power supply voltage VGL, etc. In one example, in at least one first trace group LS, the first peripheral trace TRL1 is used to load a first low-level power supply voltage VGL1, the second peripheral trace TRL2 is used to load a second low-level power supply voltage VGL2, and the third peripheral trace TRL3 is used to load a third low-level power supply voltage VGL3. In another example, in at least one first trace group LS, the first peripheral trace TRL1 is used to load a first high-level power supply voltage VGH1, the second peripheral trace TRL2 is used to load a second high-level power supply voltage VGH2, and the third peripheral trace TRL3 is used to load a third high-level power supply voltage VGH3. In other examples, in at least one first trace group LS, a first peripheral trace TRL1 is used to load a first high-level power supply voltage VGH1, a second peripheral trace TRL2 is used to load a first low-level power supply voltage VGL1, and a third peripheral trace TRL3 is used to load a second high-level power supply voltage VGH2.

[0096] In one embodiment of this disclosure, referring to Figures 8 and 10, the display panel PNL has at least one second trace group LXS in the first peripheral region BB1. The second trace group LXS includes a fourth peripheral trace TRL4, a fifth peripheral trace TRL5, and a sixth peripheral trace TRL6. In at least one second trace group LXS, one or two of the fourth peripheral trace TRL4, the fifth peripheral trace TRL5, and the sixth peripheral trace TRL6 are used to load a drive signal to the gate drive circuit trace GOAL, and one or two of the fourth peripheral trace TRL4, the fifth peripheral trace TRL5, and the sixth peripheral trace TRL6 are used to load a signal from the pixel drive circuit. In the same second trace group LXS, the fourth peripheral trace TRL4 has a fourth peripheral main trace TRL4A, the fifth peripheral trace TRL5 has a fifth peripheral main trace TRL5A, and the sixth peripheral trace TRL6 has a sixth peripheral main trace TRL6A; wherein, the fourth peripheral main trace TRL4A and the fifth peripheral main trace TRL5A are arranged in the same layer and adjacent to each other, and are located in different film layers from the sixth peripheral main trace TRL6A; the gap between the fourth peripheral main trace TRL4A and the fifth peripheral main trace TRL5A is orthographically projected onto the plane where the display panel PNL is located, and is located within the orthographic projection of the sixth peripheral main trace TRL6A onto the plane where the display panel PNL is located. In one example, the fourth peripheral trace TRL4 is used to load a drive signal, and the fifth peripheral trace TRL5 and the sixth peripheral trace TRL6 can be used to load signals of the pixel drive circuit. In another example, the fourth peripheral trace TRL4 and the fifth peripheral trace TRL5 are used to load drive signals, and the sixth peripheral trace TRL6 can be used to load signals from the pixel drive circuit. The signals from the pixel drive circuit may include an initialization voltage Vinit (not shown in the figures), a reference voltage Vref (not shown in the figures), etc.; wherein, the initialization voltage Vinit may include a first initialization voltage Vinit1 (not shown in the figures), a second initialization voltage Vinit2 (not shown in the figures), and a third initialization voltage Vinit3 (not shown in the figures). For example, in at least one second trace group LXS, the fourth peripheral trace TRL4 is used to load a first high-level power supply voltage VGH1, the fifth peripheral trace TRL5 is used to load a first start signal PSTV, and the sixth peripheral trace TRL6 is used to load a third initialization voltage Vinit3. As another example, in at least one second trace group LXS, the fourth peripheral trace TRL4 is used to load a fourth low-level power supply voltage VGL4, the fifth peripheral trace TRL5 is used to load a second reset signal ECX, and the sixth peripheral trace TRL6 is used to load a first initialization voltage Vinit1.Thus, within the same second trace group LXS, on the one hand, by arranging the signals in the pixel driving circuit (such as the initialization voltage Vinit) with the driving signals of the gate driving circuit trace GOAL through film layer overlap, the spatial area of ​​the first peripheral area BB1 can be further reduced, which is beneficial for narrowing the bezel of the display panel PNL; on the other hand, since the start signal STV and the reset signal CX in the driving signals only change once, arranging them with other constant voltage DC signals (such as high-level power supply voltage VGH, low-level power supply voltage VGL, and initialization voltage Vinit) through film layer overlap further reduces the spatial area of ​​the first peripheral area BB1, making it easier to reduce the bezel width of the display panel PNL.

[0097] In one embodiment of this disclosure, referring to FIG10, within the same second wiring group LXS, the fourth peripheral main wiring TRL4A includes a fourth upper wiring TRL4A1 and a fourth lower wiring TRL4A2. The fourth upper wiring TRL4A1 and the fourth lower wiring TRL4A2 are located in different film layers; the extension trajectory of the fourth upper wiring TRL4A1 is the same as the extension trajectory of the fourth lower wiring TRL4A2. The fifth peripheral main wiring TRL5A includes a fifth upper wiring TRL5A1 and a fifth lower wiring TRL5A2. The fifth upper wiring TRL5A1 and the fifth lower wiring TRL5A2 are located in different film layers; the extension trajectory of the fifth upper wiring TRL5A1 is the same as the extension trajectory of the fifth lower wiring TRL5A2. In other words, the fourth peripheral main trace TRL4A and the fifth peripheral main trace TRL5A are double-layer traces to increase the width of the fourth peripheral trace TRL4 and the fifth peripheral trace TRL5 and reduce the resistance of the fourth peripheral trace TRL4 and the fifth peripheral trace TRL5.

[0098] From the perspective of the membrane structure, in the same second wiring group LXS, the fourth peripheral main wiring TRL4A and the fifth peripheral main wiring TRL5A are both double membrane layer wirings. The sixth peripheral main wiring TRL6A is stacked on top of the fourth peripheral main wiring TRL4A and the fifth peripheral main wiring TRL5A and is inserted in the gap between the fourth peripheral main wiring TRL4A and the fifth peripheral main wiring TRL5A.

[0099] For example, referring to Figure 10, a first gate layer GT1, a second gate layer GT2, and a third gate layer GT3 are sequentially stacked on the substrate SBT. A fourth upper trace TRL4A1 is disposed on the first gate layer GT1, and a fourth lower trace TRL4A2 is disposed on the second gate layer GT2. The orthographic projection of the fourth lower trace TRL4A2 onto the plane of the display panel PNL lies within the orthographic projection of the fourth upper trace TRL4A1 onto the plane of the display panel PNL. A fifth upper trace TRL5A1 is disposed on the first gate layer GT1, and a fifth lower trace TRL5A2 is disposed on the second gate layer GT2. The orthographic projection of the fifth lower trace TRL5A2 onto the plane of the display panel PNL lies within the orthographic projection of the fifth upper trace TRL5A1 onto the plane of the display panel PNL. A sixth peripheral main trace TRL6A has two third horizontal segments, one fourth horizontal segment, and two skew segments. One of the third horizontal segments has its orthographic projection on the plane of the display panel PNL located within the orthographic projection of the fourth upper trace TRL4A1 on the plane of the display panel PNL; the other third horizontal segment has its orthographic projection on the plane of the display panel PNL located within the orthographic projection of the fifth upper trace TRL5A1 on the plane of the display panel PNL. The orthographic projection of the fourth horizontal segment on the plane of the display panel PNL is located within the orthographic projection of the gap between the fourth peripheral main trace TRL4A and the fifth peripheral main trace TRL5A on the plane of the display panel PNL, and the fourth horizontal segment is disposed on the third gate layer GT3. One of the third horizontal segments is electrically connected to the fourth horizontal segment through a skew segment, and the other third horizontal segment is electrically connected to the fourth horizontal segment through another skew segment, so that the two third horizontal segments, one fourth horizontal segment, and two skew segments are electrically connected to each other. In other words, the sixth peripheral main trace TRL6A is disposed on the third gate layer GT3. Thus, by overlapping the sixth peripheral main trace TRL6A with the fourth peripheral main trace TRL4A and the fifth peripheral main trace TRL5A respectively, and when the fourth peripheral main trace TRL4A and the fifth peripheral main trace TRL5A are double-layer traces, the trace width of the sixth peripheral main trace TRL6A is much larger than the trace width of the fourth peripheral main trace TRL4A or the fifth peripheral main trace TRL5A (for example, the trace width of the sixth peripheral main trace TRL6A is twice the trace width of the fourth peripheral main trace TRL4A), effectively reducing the resistance of the sixth peripheral main trace TRL6A.

[0100] It is understood that other film layers may be disposed between the substrate SBT, the first gate layer GT1, the second gate layer GT2, and the third gate layer GT3. For example, a gate insulating layer may be disposed between the first gate layer GT1 and the second gate layer GT2 to insulate the first gate layer GT1 and the second gate layer GT2.

[0101] In one embodiment of this disclosure, referring to FIG8, in the same second trace group LXS, the fourth peripheral trace TRL4 further includes a fourth peripheral secondary trace TRL4B electrically connected to the fourth peripheral main trace TRL4A. The fifth peripheral trace TRL5 further includes a fifth peripheral secondary trace TRL5B electrically connected to the fifth peripheral main trace TRL5A. The sixth peripheral trace TRL6 further includes a sixth peripheral secondary trace TRL6B electrically connected to the sixth peripheral main trace TRL6A. The extension trajectories of the fourth peripheral secondary trace TRL4B, the fifth peripheral secondary trace TRL5B, and the sixth peripheral secondary trace TRL6B are consistent, so that the fourth peripheral secondary trace TRL4B, the fifth peripheral secondary trace TRL5B, and the sixth peripheral secondary trace TRL6B are arranged side by side, and the fourth peripheral secondary trace TRL4B, the fifth peripheral secondary trace TRL5B, and the sixth peripheral secondary trace TRL6B are used for electrical connection with the driver chip to load the drive signal onto the peripheral trace TRL.

[0102] In one embodiment of this disclosure, referring to Figures 7 and 14, the second peripheral region BB2 is provided with initialization voltage traces VIL corresponding one-to-one with the initialization voltage Vinit. The peripheral trace TRL that loads the initialization voltage Vinit is directly electrically connected to the corresponding initialization voltage trace VIL. For example, when the peripheral trace TRL loads the first initialization voltage Vinit1, this peripheral trace TRL is electrically connected to the first initialization voltage trace VIL1. When the peripheral trace TRL loads the second initialization voltage Vinit2, this peripheral trace TRL is electrically connected to the second initialization voltage trace VIL2. When the peripheral trace TRL loads the third initialization voltage Vinit3, this peripheral trace TRL is electrically connected to the third initialization voltage trace VIL3. In this way, the initialization voltage Vinit is provided to each pixel driving circuit.

[0103] In one embodiment of this disclosure, each trace in at least one first trace group LS is directly electrically connected to the corresponding gate drive circuit trace GOAL, so that the trace that provides the drive signal to the gate drive circuit GOA extends from the first peripheral region BB1 to the second peripheral region BB2, and is electrically connected to the corresponding gate drive circuit trace GOAL in the second peripheral region BB2, thereby realizing a reasonable layout of the traces in the peripheral region BB.

[0104] In one embodiment of this disclosure, referring to FIG7, the peripheral trace TRL includes a first connecting line LA. The display panel PNL has a transition trace LAB in the display area AA, corresponding one-to-one with the first connecting line LA; the first connecting line LA and the corresponding gate driving circuit trace GOAL are electrically connected through the transition trace LAB. Thus, by electrically connecting the first connecting line LA to the corresponding gate driving circuit trace GOAL through the transition trace LAB, the traces located in the peripheral area BB can be transferred into the display area AA and finally electrically connected to the corresponding gate driving circuit trace GOAL, thereby reducing the number of traces arranged in the corner area, which is beneficial for compressing the space area of ​​the first peripheral area BB1, and further reducing the bezel width of the display panel PNL. It should be noted that the peripheral trace TRL containing the first connecting line LA is not the peripheral trace TRL in the first trace group LS and the second trace group LXS.

[0105] In one embodiment of this disclosure, referring to Figures 7 and 11, the display panel PNL is provided with a plurality of first edge integrated traces (HSIPs) and a plurality of second edge integrated traces (VSIPs). The first edge integrated traces (HSIPs) extend along a first direction (DH), and the second edge integrated traces (VSIPs) extend along a second direction (DV). The transition traces (LABs) include a first transition trace (LAB1) and a second transition trace (LAB2). The first transition trace (LAB1) is part of the second edge integrated trace (VSIP), and one end of the first transition trace (LAB1) is electrically connected to the first edge integrated trace (HSIP), and the other end is electrically connected to the first connection line (LA). The second transition trace (LAB2) is part of the first edge integrated trace (HSIP), and one end of the second transition trace (LAB2) is electrically connected to the second edge integrated trace (VSIP), and the other end is electrically connected to the gate drive circuit trace (GOAL). The signal applied to the first connection line (LA) can be at least one of a high-level power supply voltage (VGH), a low-level power supply voltage (VGL), a start signal (STV), and a reset signal (CX). In this way, the second transition line LAB2 is electrically connected from the corner area to the corresponding gate drive circuit line GOAL. The drive signal can be loaded onto the corresponding gate drive circuit GOA through the first connection line LA, the first transition line LAB1, the second transition line LAB2, and the gate drive circuit line GOAL in sequence, so as to reduce the number of traces laid in the corner area and compress the space area of ​​the first peripheral area BB1.

[0106] In one embodiment of this disclosure, referring to Figures 12 and 13, the display panel PNL is provided with a second connection line LB that corresponds one-to-one with the gate drive circuit trace GOAL. The second connection line LB is part of the second edge integrated trace VSIP, and one end of the second connection line LB is electrically connected to the second transition trace LAB2, and the other end is electrically connected to the corresponding gate drive circuit trace GOAL.

[0107] In one embodiment of this disclosure, referring to Figures 12 and 13, the display panel PNL has at least one first connection line group LAS in the first peripheral area BB1. One gate drive circuit trace GOAL corresponds to one first connection line group LAS, and the first connection line group LAS has multiple first connection lines LA. Each first connection line LA in the first connection line group LAS is electrically connected to the corresponding gate drive circuit trace GOAL through a corresponding adapter trace LAB. For example, a first connection line group LAS has two first connection lines LA, and each of the two first connection lines LA has a corresponding adapter trace LAB. That is, each first connection line LA corresponds to a first adapter trace LAB1 and a second adapter trace LAB2. The two second adapter traces LAB2 corresponding to the same first connection line group LAS are both electrically connected to a gate drive circuit trace GOAL. The same drive signal can be applied to the gate drive circuit GOAL through the two traces, thereby reducing the resistance of the drive signal and improving the stability of the drive signal. For another example, a first connection line group LAS has three first connection lines LA, and each of the three first connection lines LA has a corresponding transition trace LAB. That is, each first connection line LA corresponds to a first transition trace LAB1 and a second transition trace LAB2. The three second transition traces LAB2 corresponding to the same first connection line group LAS are all electrically connected to a gate drive circuit trace GOAL. The same drive signal can be applied to the gate drive circuit GOA through the three traces, thereby further reducing the resistance of the drive signal and improving the stability of the drive signal.

[0108] In one embodiment of this disclosure, referring to FIG12, the display panel PNL is provided with second connection lines LB corresponding one-to-one with at least a portion of the first connection line groups LAS, the second connection lines LB being part of the second edge integrated trace VSIP; the gate drive circuit trace GOAL corresponding to the first connection line group LAS is electrically connected to the corresponding second connection line LB through a third connection line LC, and each of the first connection lines LA in the same first connection line group LAS is electrically connected to the corresponding second connection line LB through the corresponding adapter trace LAB. For example, a first connection line group LAS has two first connection lines LA, and each of the two first connection lines LA has a corresponding adapter trace LAB. That is, each first connection line LA corresponds to a first adapter trace LAB1 and a second adapter trace LAB2. The two second adapter traces LAB2 corresponding to the same first connection line group LAS are electrically connected to a second connection line LB. The second connection line LB is electrically connected to the corresponding gate drive circuit trace GOAL through a third connection line LC. The same drive signal can be applied to the gate drive circuit GOA through the two traces, thereby reducing the resistance of the drive signal and improving the stability of the drive signal. For another example, a first connection line group LAS has three first connection lines LA, and each of the three first connection lines LA has a corresponding adapter trace LAB. That is, each first connection line LA corresponds to a first adapter trace LAB1 and a second adapter trace LAB2. The three second adapter traces LAB2 corresponding to the same first connection line group LAS are all electrically connected to a second connection line LB. The second connection line LB is electrically connected to the corresponding gate drive circuit trace GOAL through a third connection line LC. The same drive signal can be applied to the gate drive circuit GOA through the three traces, thereby further reducing the resistance of the drive signal and improving the stability of the drive signal.

[0109] In one embodiment of this disclosure, when the first connection line LA is loaded with an initialization voltage Vinit, the transition line LAB or the third connection line LC is electrically connected to the corresponding initialization voltage line VIL. For example, when the first connection line LA is loaded with a first initialization voltage Vinit1, the transition line LAB or the third connection line LC is electrically connected to the corresponding first initialization voltage line VIL1. When the first connection line LA is loaded with a second initialization voltage Vinit2, the transition line LAB or the third connection line LC is electrically connected to the corresponding second initialization voltage line VIL2. When the first connection line LA is loaded with a third initialization voltage Vinit3, the transition line LAB or the third connection line LC is electrically connected to the corresponding third initialization voltage line VIL3.

[0110] In one embodiment of this disclosure, the drive signal may further include a clock signal CK (not shown in the figures). The clock signal CK includes a first clock signal CKA (not shown in the figures) and a second clock signal CKB (not shown in the figures), wherein the first clock signal CKA and the second clock signal CKB are a clock signal pair, and the first clock signal CKA and the second clock signal CKB are out of phase. The peripheral trace TRL used to load the clock signal CK can be directly electrically connected to the corresponding gate drive circuit trace GOAL, and the peripheral trace TRL used to load the clock signal CK does not belong to the trace in the first trace group LS or the second trace group LXS. Since the signal transition frequency of the clock signal CK is high, this arrangement can reduce the impact of the clock signal CK transition on other traces, thereby reducing crosstalk between drive signals.

[0111] In one embodiment of this disclosure, referring to FIG7, the gate drive circuit trace GOAL may include a high-level power supply voltage trace VHL, a low-level power supply voltage trace VLL, a clock signal trace CKL, a start signal trace STVL, a reset signal trace CXL, etc., to provide drive signals for the gate drive circuit GOA. The high-level power supply voltage trace VHL may include a first high-level power supply voltage trace VHL1 (not shown in the figures) for loading a first high-level power supply voltage VGH1, a second high-level power supply voltage trace VHL2 (not shown in the figures) for loading a second high-level power supply voltage VGH2, and a third high-level power supply voltage trace VHL3 (not shown in the figures) for loading a third high-level power supply voltage VGH3. The low-level power supply voltage trace VLL may include a first low-level power supply voltage trace VLL1 (not shown in the figure) for loading a first low-level power supply voltage VGL1, a second low-level power supply voltage trace VLL2 (not shown in the figure) for loading a second low-level power supply voltage VGL2, and a third low-level power supply voltage trace VLL3 (not shown in the figure) for loading a third low-level power supply voltage VGL3. The clock signal trace CKL may include a first clock signal trace CL1 (not shown in the figure) for loading a first clock signal CKA and a second clock signal trace CL2 (not shown in the figure) for loading a second clock signal CKB. The start signal trace STVL is used to load the start signal STV. The reset signal trace CXL is used to load the reset signal CX.

[0112] In one embodiment of this disclosure, referring to FIG7, the display panel PNL is further provided with at least one third trace group LFS; the same third trace group LFS includes a peripheral trace TRL7, a second edge integrated trace VSIP, a first edge integrated trace HSIP, and a data line DL connected in sequence. In this way, the driver chip can apply data voltage to the data line DL in sequence through the second edge integrated trace VSIP and the first edge integrated trace HSIP, thereby reducing the length of the trace used to apply data voltage in the first peripheral area BB1, compressing the wiring space in the first peripheral area BB1, and facilitating the narrowing of the bezel of the display panel PNL.

[0113] In one embodiment of this disclosure, referring to FIG7, the display panel PNL is further provided with a fourth trace group LVS for loading a reference power supply voltage VSS; the fourth trace group LVS includes multiple second edge integrated traces VSIP and multiple first edge integrated traces HSIP that are electrically connected to each other, so as to realize the gridding of the reference power supply voltage VSS and improve the uniformity of the display panel PNL.

[0114] In one embodiment of this disclosure, the display panel PNL is further provided with peripheral traces TRL8 in the first peripheral area BB1, which correspond one-to-one with the data lines DL. The peripheral traces TRL8 are directly electrically connected to the corresponding data lines DL.

[0115] In one embodiment of this disclosure, referring to FIG7, the first peripheral area BB1 has a bending region BEA, which allows the flexible circuit board to be folded behind the display area AA, thereby reducing the spatial area of ​​the first peripheral area BB1 and facilitating the narrowing of the bezel of the display panel PNL. Multiple fourth connection lines LD are provided in the bending region BEA, each corresponding to one of the first connection line groups LAS. Each first connection line LA in the same first connection line group LAS is electrically connected to its corresponding fourth connection line LD, enabling the driver chip to load driving signals or pixel driving circuit signals to the first connection line group LAS through the fourth connection line LD.

[0116] The following section provides a detailed explanation of the film structure of the first source / drain metal layer SD1 and the second source / drain metal layer SD2, using the distribution of signal traces in the corner region illustrated in Figures 14-16 as examples:

[0117] Figure 15 illustrates a schematic diagram of the first source / drain metal layer SD1 in one embodiment of this disclosure. Referring to Figure 15, the first source / drain metal layer SD1 has a first initialization voltage trace VIL1, a second initialization voltage trace VIL2, a third initialization voltage trace VIL3, a conductive portion MA, and a first connection portion XL1 disposed in the second peripheral region BB2. The first initialization voltage trace VIL1 is used to load the first initialization voltage Vinit1, the second initialization voltage trace VIL2 is used to load the second initialization voltage Vinit2, the third initialization voltage trace VIL3 is used to load the third initialization voltage Vinit3, and the first connection portion XL1 is used to load the high-level power supply voltage VGH. The first initialization voltage traces VIL1, VIL2, and VIL3 have the same extension trajectory. Along the second direction DV, the second initialization voltage trace VIL2 is located between the first initialization voltage trace VIL1 and the third initialization voltage trace VIL3. A first lower via region HA1 is provided on the first initialization voltage trace VIL1, a second lower via region HA2 is provided on the second initialization voltage trace VIL2, and a third lower via region HA3 is provided on the third initialization voltage trace VIL3. The conductive part MA is electrically connected to the first connecting part XL1; along the second direction DV, the first connecting part XL1 is located between the conductive part MA and the third initialization voltage trace VIL3. A fourth lower via region HA4 is provided on the conductive part MA.

[0118] Figure 16 illustrates a schematic diagram of the second source / drain metal layer SD2 in one embodiment of this disclosure. Referring to Figure 16, the second source / drain metal layer SD2 is provided with a second connection line LB1, a second connection line LB2, a second connection line LB3, a second connection line LB4, a second connection portion XL2, a high-level power supply voltage trace VHL, a reference power supply voltage trace VSSL, a plurality of first edge integrated traces HSIP, and a plurality of second edge integrated traces VSIP. Among them, the second connection line LB1, the second connection line LB2, the second connection line LB3, and the second connection line LB4 are part of the second edge integrated traces VSIP and extend along the second direction DV. The second connection line LB1, the second connection line LB2, the second connection line LB3, and the second connection line LB4 all extend from the display area AA to the second peripheral area BB2. The second connecting line LB1 is used to load the first initialization voltage Vinit1, the second connecting line LB2 is used to load the second initialization voltage Vinit2, the second connecting line LB2 is used to load the third initialization voltage Vinit3, the second connecting line LB4, the second connecting part XL2, and the high-level power supply voltage trace VHL are used to load the high-level power supply voltage VGH. The reference power supply voltage trace VSSL is used to load the reference power supply voltage VSS. The second connecting part XL2, the high-level power supply voltage trace VHL, and the reference power supply voltage trace VSSL are located in the second peripheral area BB2. Along the first direction DH, the second connecting line LB2 is located between the second connecting line LB1 and the second connecting line LB3, and the second connecting line LB1 is located between the second connecting line LB2 and the second connecting line LB4. The second connecting line LB1 has a first upper via area HB1, the second connecting line LB2 has a second upper via area HB2, and the second connecting line LB3 has a third upper via area HB3. The second connecting line LB4, the second connecting part XL2, and the high-level power supply voltage trace VHL are connected in sequence, and the high-level power supply voltage trace VHL is provided with a fourth upper via area HB4.

[0119] Referring to Figures 14-16, the first upper via region HB1 overlaps with the first lower via region HA1 and is electrically connected through a via; the second upper via region HB2 overlaps with the second lower via region HA2 and is electrically connected through a via; the third upper via region HB3 overlaps with the third lower via region HA3 and is electrically connected through a via; and the fourth upper via region HB4 overlaps with the fourth lower via region HA4 and is electrically connected through a via.

[0120] Thus, by leading the first initialization voltage Vinit1, the second initialization voltage Vinit2, the third initialization voltage Vinit3, and the high-level power supply voltage VGH from the display area AA to the second peripheral area BB2, the number of traces extending directly from the first peripheral area BB1 to the second peripheral area BB2 can be reduced. This helps to reduce the wiring space in the first peripheral area BB1 and facilitates the narrowing of the bezel of the display panel PNL. Furthermore, the high-level power supply voltage VGH can be applied to multiple traces through the first connection part XL1, thereby reducing the resistance of the high-level power supply voltage VGH.

[0121] Referring to Figure 16, the second source / drain metal layer SD2 has a fourth trace group LVS. The fourth trace group LVS includes multiple first edge integrated traces HSIP and multiple second edge integrated traces VSIP. The multiple first edge integrated traces HSIP and multiple second edge integrated traces VSIP are electrically connected to each other. The reference power supply voltage trace VSSL is electrically connected to the multiple second edge integrated traces VSIP to mesh the reference power supply voltage VSS and improve the uniformity of the display panel PNL.

[0122] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising a display area and a peripheral area surrounding the display area; in, The peripheral area includes a first peripheral area located between the display area and the bonding end of the display panel, and a second peripheral area adjacent to the first peripheral area and provided with a gate driving circuit. The second peripheral region has a plurality of gate drive circuit traces for loading drive signals to the gate drive circuit; The first peripheral region has multiple peripheral traces, and the multiple peripheral traces form at least one first trace group; the first trace group includes a first peripheral trace, a second peripheral trace, and a third peripheral trace, and the first peripheral trace, the second peripheral trace, and the third peripheral trace are all used to apply a drive signal to the gate drive circuit trace; In the same first routing group, the first peripheral routing has a first peripheral main routing, the second peripheral routing has a second peripheral main routing, and the third peripheral routing has a third peripheral main routing; The first peripheral main trace and the second peripheral main trace are arranged in the same layer and adjacent to each other, and are located in different film layers from the third peripheral main trace; the orthographic projection of the gap between the first peripheral main trace and the second peripheral main trace on the plane where the display panel is located is located within the orthographic projection of the third peripheral main trace on the plane where the display panel is located.

2. The display panel according to claim 1, wherein, Within the same first wiring group, the extension trajectories of the first outer main wiring, the second outer main wiring, and the third outer main wiring are consistent.

3. The display panel according to claim 1, wherein, Within the same first wiring group, the orthographic projection of the third peripheral main wiring onto the plane where the display panel is located is within the orthographic projection of the overall structure formed by the first peripheral main wiring, the second peripheral main wiring, and the gap between the first peripheral main wiring and the second peripheral main wiring onto the plane where the display panel is located.

4. The display panel according to claim 1, wherein, Within the same first wiring group, the first peripheral main wiring includes a first upper wiring and a first lower wiring; the first upper wiring and the first lower wiring are located in different film layers; the extension trajectory of the first upper wiring and the extension trajectory of the first lower wiring are the same; The second peripheral main routing includes a second upper routing and a second lower routing; the second upper routing and the second lower routing are located in different film layers; the extension trajectory of the second upper routing and the extension trajectory of the second lower routing are the same.

5. The display panel according to claim 1, wherein, In at least one of the first trace groups, the first peripheral trace, the second peripheral trace, and the third peripheral trace are respectively used to load different power supply voltage signals.

6. The display panel according to claim 5, wherein, In at least one of the first trace groups, the first peripheral trace is used to apply a first low-level power supply voltage, the second peripheral trace is used to apply a second low-level power supply voltage, and the third peripheral trace is used to apply a third low-level power supply voltage.

7. The display panel according to claim 5, wherein, In at least one of the first trace groups, the first peripheral trace is used to apply a first high-level power supply voltage, the second peripheral trace is used to apply a second high-level power supply voltage, and the third peripheral trace is used to apply a third high-level power supply voltage.

8. The display panel according to claim 1, wherein, The display panel has at least one second wiring group in the first peripheral area; the second wiring group includes a fourth peripheral wiring, a fifth peripheral wiring, and a sixth peripheral wiring; In at least one of the second wiring groups, one or two of the fourth peripheral wiring, the fifth peripheral wiring, and the sixth peripheral wiring are used to apply a drive signal to the gate drive circuit wiring; In the same second routing group, the fourth peripheral routing has a fourth peripheral main routing, the fifth peripheral routing has a fifth peripheral main routing, and the sixth peripheral routing has a sixth peripheral main routing; The fourth and fifth peripheral main traces are arranged in the same layer and adjacent to each other, and are located in different film layers from the sixth peripheral main trace; the orthographic projection of the gap between the fourth and fifth peripheral main traces on the plane of the display panel is located within the orthographic projection of the sixth peripheral main trace on the plane of the display panel.

9. The display panel according to claim 8, wherein, In at least one of the second trace groups, one of the fourth peripheral trace, the fifth peripheral trace, and the sixth peripheral trace is used to apply the initialization voltage.

10. The display panel according to claim 1, wherein, At least one of the traces in the first trace group is directly electrically connected to the corresponding gate drive circuit trace.

11. The display panel according to claim 1, wherein, The peripheral wiring includes a first connecting line; the display panel has adapter wiring in the display area that corresponds one-to-one with the first connecting line; The first connection line is electrically connected to the corresponding gate drive circuit trace through the adapter trace.

12. The display panel according to claim 11, wherein, The display panel is provided with a plurality of first edge integrated traces extending along a first direction and a plurality of second edge integrated traces extending along a second direction; the transition traces include first transition traces and second transition traces. The first adapter trace is part of the second edge integrated trace, and one end of the first adapter trace is electrically connected to the first edge integrated trace, and the other end is electrically connected to the first connecting line. The second adapter trace is part of the first edge integrated trace, and one end of the second adapter trace is electrically connected to the second edge integrated trace, and the other end is electrically connected to the gate drive circuit trace.

13. The display panel according to claim 12, wherein, The display panel has at least one first connection line group in the first peripheral area; One of the gate drive circuit traces corresponds to one of the first connection line groups, and the first connection line group has a plurality of the first connection lines; Each of the first connecting lines in the first connecting line group is electrically connected to the corresponding gate drive circuit line through the corresponding adapter line.

14. The display panel according to claim 13, wherein, The display panel is provided with second connecting lines that correspond one-to-one with at least a portion of the first connecting line groups, and the second connecting lines are part of the second edge integrated wiring; The gate drive circuit traces corresponding to the first connection line group are electrically connected to the corresponding second connection line through the third connection line, and each of the first connection lines in the same first connection line group is electrically connected to the corresponding second connection line through the corresponding adapter trace.

15. A display device comprising the display panel as described in any one of claims 1 to 14.

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