Driving method for display panel, and timing controller and display apparatus

Abstract

Provided in the embodiments of the present disclosure are a driving method for a display panel, and a timing controller and a display apparatus. The driving method comprises: acquiring original display data of one display frame, wherein the original display data comprises original data voltages corresponding to M rows and K columns of sub-pixels, and a display panel comprises N rows and K columns of sub-pixels, where N is P times M, M, N and K are positive integers, and P is a positive integer greater than 1; and charging the original data voltages into a sub-pixel in an a-th row and a sub-pixel in an (a+b)-th row among the same column of sub-pixels of the display panel, and charging a rendered data voltage into sub-pixels in an (a+c)-th row among the same column of sub-pixels of the display panel, wherein the rendered data voltage is determined on the basis of the original data voltages which are charged into the sub-pixel in the a-th row and the sub-pixel in the (a+b)-th row, where c<b, and a, b and c are positive integers.

Description

Driving method for display panel, timing controller and display device Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a driving method for a display panel, a timing controller and a display device. Background Art

[0002] With the development of the economy, people's pursuit of the specifications of display products is getting higher and higher. A higher and higher resolution has become the basic specification requirement for the development of future display products. Under a display panel with a high resolution, the requirement for the refresh frame rate of the display panel is also getting higher and higher. Then, under the display requirements of high resolution and high refresh rate, the hardware specifications of the system-on-chip (SOC) are extremely high. The hardware specifications of the current SOCs on the market may not support the full display of a display panel with a high resolution and a high refresh rate, resulting in a situation where only a part of the display panel can be displayed.

[0003] Moreover, with the increase in the resolution and refresh frame rate of the display panel, a problem of insufficient charging appears during the design of the display panel, which affects the trend of the display product towards high resolution. Summary of the Invention

[0004] The driving method for a display panel provided by an embodiment of the present disclosure includes:

[0005] Obtain the original display data of a display frame, where the original display data includes the original data voltages corresponding to M rows and K columns of sub-pixels, the display panel includes N rows and K columns of sub-pixels, N is P times of M, and M, N, K are positive integers, and P is a positive integer greater than 1;

[0006] Charge the original data voltage into the sub-pixels of the a-th row and the (a + b)-th row in the same column of the display panel, and charge the rendering data voltage into the sub-pixels of the (a + c)-th row. The rendering data voltage is determined according to the original data voltages charged into the sub-pixels of the a-th row and the (a + b)-th row, c < b, and a, b, c are positive integers.

[0007] In some examples, the rendering data voltage charged into the sub-pixels of the (a + c)-th row is equal to the average value of the sum of the original data voltages charged into the sub-pixels of the a-th row and the (a + b)-th row.

[0008] In some examples, the display frame is an odd frame, a and a + b are both odd numbers from 1 to N, and a + c is an even number from 1 to N.

[0009] In some examples, the display frame is an odd frame, a and a + b are both even numbers from 1 to N, and a + c is an odd number from 1 to N.

[0010] In some examples, the display frames are even-numbered frames, where a and a+b are both even numbers from 1 to N, and a+c is an odd number from 1 to N.

[0011] In some examples, the display frames are even-numbered frames, where a and a+b are both odd numbers from 1 to N, and a+c is an even number from 1 to N.

[0012] In some examples, a first rendering data voltage is applied to the first row of sub-pixels in the same column of the display panel, the second and fourth row sub-pixels are applied to the original data voltage, and the third row sub-pixels are applied to the rendering data voltage; wherein the first rendering data voltage is equal to half of the original data voltage applied to the second row sub-pixels.

[0013] In some examples, the original data voltage is applied to the N-3rd and N-1st row sub-pixels in the same column of the display panel, the rendering data voltage is applied to the N-2nd row sub-pixels, and the second rendering data voltage is applied to the Nth row sub-pixels; wherein the second rendering data voltage is equal to half of the original data voltage applied to the N-1th row sub-pixels.

[0014] In some examples, b = 2 and c = 1.

[0015] The timing controller provided in this embodiment includes: a memory storing a computer program; and a processor executing the computer program to implement the above-described display panel driving method.

[0016] The display device provided in this disclosure includes:

[0017] The display panel includes: N rows and K columns of sub-pixels, multiple data signal lines, and source drive circuitry;

[0018] The central control circuit, electrically connected to the timing controller, is configured to provide the timing controller with the original data voltage corresponding to the M rows and K columns of the original display data; where N is P times M, M, N, and K are positive integers, and P is a positive integer greater than 1.

[0019] The aforementioned timing controller, electrically connected to the central control circuit, is configured to determine the rendering data voltage charged into the (a+c)th row sub-pixel based on the original data voltage charged into the (a)th row sub-pixel and the (a+b)th row sub-pixel in the same column of sub-pixels.

[0020] The source drive circuit is electrically connected to the timing controller and is configured to, under the control of the timing controller, charge the original data voltage to the sub-pixels in the a-th row and the (a+b-th row) of the same column of sub-pixels in the display panel through the data signal line, and charge the rendering data voltage to the (a+c-th row) of sub-pixels.

[0021] In some examples, the plurality of data signal lines includes: K first data signal lines and K second data signal lines;

[0022] The sub-pixels in the a-th row and the a+b-th row of the k-th sub-pixels are electrically connected to the k-th first data signal line, and the sub-pixels in the a+c-th row of the k-th sub-pixels are electrically connected to the k-th second data signal line.

[0023] Alternatively, the sub-pixels in the a-th row and the a+b-th row of the k-th sub-pixels are electrically connected to the k-th second data signal line, and the sub-pixels in the a+c-th row of the k-th sub-pixels are electrically connected to the k-th first data signal line; where k is a positive integer.

[0024] In some examples, the display panel further includes: multiple gate lines, with a row of subpixels electrically connected to a gate line;

[0025] Valid signals are sequentially and alternately applied to the first data signal line and the second data signal line.

[0026] In some examples, the display panel further includes: multiple gate lines, with adjacent rows of sub-pixels electrically connected to the same gate line;

[0027] Simultaneously, a valid signal is applied to the first data signal line and a valid signal is applied to the second data signal line.

[0028] In some examples, the source driving circuit includes: a first source driving circuit and a second source driving circuit; the first source driving circuit and the second source driving circuit are respectively disposed on both sides of the display panel;

[0029] The first source drive circuit is electrically connected to the K first data signal lines;

[0030] The second source drive circuit is electrically connected to the K second data signal lines.

[0031] In some examples, P = 2. Attached Figure Description

[0032] Figure 1 is a schematic diagram of the structure of the display device provided in an embodiment of this disclosure;

[0033] Figure 2 is a schematic diagram of some structures of the display panel provided in the embodiments of this disclosure;

[0034] Figure 3 is a schematic diagram of some other structures of the display panel provided in the embodiments of this disclosure;

[0035] Figure 4 is a flowchart of the driving method for the display panel provided in an embodiment of this disclosure;

[0036] Figure 5 is a schematic diagram of the original display data provided in an embodiment of this disclosure;

[0037] Figure 6 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0038] Figure 7 is a timing signal diagram provided in the embodiments of this disclosure;

[0039] Figure 8 shows some other timing signal diagrams provided in the embodiments of this disclosure;

[0040] Figure 9 shows some more timing signal diagrams provided in the embodiments of this disclosure;

[0041] Figure 10 shows some more timing signal diagrams provided in the embodiments of this disclosure;

[0042] Figure 11 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0043] Figure 12 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0044] Figure 13 shows some more timing signal diagrams provided in the embodiments of this disclosure;

[0045] Figure 14 shows some more timing signal diagrams provided in the embodiments of this disclosure;

[0046] Figure 15 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0049] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0050] The display device provided in this embodiment of the present disclosure, as shown in FIG1, may include: a display panel 100, wherein the display panel 100 includes: N rows and K columns of sub-pixels, multiple data signal lines DA, and a source driving circuit 120;

[0051] The central control circuit 300 is electrically connected to the timing controller 200 and is configured to provide the timing controller 200 with the original data voltage corresponding to the M rows and K columns of the original display data; where N is P times M, M, N, and K are positive integers, and P is a positive integer greater than 1.

[0052] The timing controller 200, electrically connected to the central control circuit 300, is configured to determine the rendering data voltage charged into the sub-pixel of the (a+c)th row based on the original data voltage charged into the sub-pixels of the (a)th row and the (a+b)th row in the same column of sub-pixels.

[0053] The source drive circuit 120 is electrically connected to the timing controller 200 and is configured to, under the control of the timing controller 200, charge the original data voltage to the sub-pixels in the a-th row and the a+b-th row of the same column of sub-pixels in the display panel through the data signal line DA, and charge the rendering data voltage to the sub-pixels in the a+c-th row.

[0054] For example, the central control circuit can be a system-on-a-chip (SOC).

[0055] In some embodiments of this disclosure, P = 2.

[0056] In some embodiments of this disclosure, as shown in Figures 2 and 3, the display panel 100 further includes: a plurality of gate lines (GA1, GA2, GA3, GA4...GA(n-3), GA(n-2), GA(n-1), GAn in Figures 2 and 3), wherein a row of sub-pixels spx is electrically connected to a gate line (GA1, GA2, GA3, GA4...GA(n-3), GA(n-2), GA(n-1), GAn in Figures 2 and 3);

[0057] For example, the sub-pixel spx in the first row is electrically connected to the gate line GA1, the sub-pixel spx in the second row is electrically connected to the gate line GA2, the sub-pixel spx in the third row is electrically connected to the gate line GA3, the sub-pixel spx in the fourth row is electrically connected to the gate line GA4, ... the sub-pixel spx in the (n-3)th row is electrically connected to the gate line GA(n-3), the sub-pixel spx in the (n-2)th row is electrically connected to the gate line GA(n-2), the sub-pixel spx in the (n-1)th row is electrically connected to the gate line GA(n-1), and the sub-pixel spx in the nth row is electrically connected to the gate line GAn.

[0058] In some embodiments of this disclosure, as shown in Figures 2 and 3, the multiple data signal lines include: K first data signal lines (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figures 2 and 3) and K second data signal lines (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figures 2 and 3); wherein, the sub-pixels in the a-th row and the (a+b-th row) of the k-th column sub-pixels are electrically connected to the k-th first data signal line, and the sub-pixels in the (a+c-th row) of the k-th column sub-pixels are electrically connected to the k-th second data signal line; or, the sub-pixels in the a-th row and the (a+b-th row) of the k-th column sub-pixels are electrically connected to the k-th second data signal line, and the sub-pixels in the (a+c-th row) of the k-th column sub-pixels are electrically connected to the k-th first data signal line; wherein, k is a positive integer.

[0059] For example, as shown in Figure 2, the sub-pixels in the first row, the third row, ..., the (n-3)th row, and the (n-1)th row of the first column of sub-pixels are electrically connected to the first first data signal line DA1; the sub-pixels in the second row, the fourth row, ..., the (n-2)th row, and the nth row of the first column of sub-pixels are electrically connected to the first second data signal line DA2; and the sub-pixels in the second column, the first row, the third row, ..., the (n-3)th row, and the (n-1)th row of sub-pixels are electrically connected to the second first data signal line DA3. The sub-pixels in the second column of sub-pixels, specifically the sub-pixels in the second row, fourth row, ..., (n-2)th row, and nth row, are electrically connected to the second second data signal line DA4; the sub-pixels in the third column of sub-pixels, specifically the sub-pixels in the first row, third row, ..., (n-3)th row, and (n-1)th row, are electrically connected to the third first data signal line DA5; the sub-pixels in the fifth column of sub-pixels, specifically the sub-pixels in the second row, fourth row, ..., (n-2)th row, and nth row, are electrically connected to the third second data signal line DA6; ... in the (k-2)th column of sub-pixels... The sub-pixels in the first row, the third row, ..., the (n-3)th row, and the (n-1)th row are electrically connected to the (k-2)th first data signal line DA2k-5. The sub-pixels in the (k-2)th column, the second row, the fourth row, ..., the (n-2)th row, and the nth row are electrically connected to the (k-2)th second data signal line DA2k-4. The sub-pixels in the (k-1)th column, the first row, the third row, ..., the (n-3)th row, and the (n-1)th row are electrically connected to the (k-1)th first data signal line DA2k-3. Then, the sub-pixels in the second row, the fourth row, ..., the (n-2)th row, and the nth row of the sub-pixels in the (k-1)th column are electrically connected to the second data signal line DA2k-2; the sub-pixels in the first row, the third row, ..., the (n-3)th row, and the (n-1)th row of the sub-pixels in the kth column are electrically connected to the first data signal line DA2k-1; and the sub-pixels in the second row, the fourth row, ..., the (n-2)th row, and the nth row of the sub-pixels in the kth column are electrically connected to the second data signal line DA2k.

[0060] For example, as shown in Figure 3, the sub-pixels in the first row, the third row, ..., the (n-3)th row, and the (n-1)th row of the first column of sub-pixels are electrically connected to the first second data signal line DA2; the sub-pixels in the second row, the fourth row, ..., the (n-2)th row, and the nth row of the first column of sub-pixels are electrically connected to the first first data signal line DA1; and the sub-pixels in the second column, the first row, the third row, ..., the (n-3)th row, and the (n-1)th row of sub-pixels are electrically connected to the second second data signal line DA4. The sub-pixels in the second column of sub-pixels, specifically the sub-pixels in the second row, fourth row, ..., (n-2)th row, and nth row, are electrically connected to the second first data signal line DA3; the sub-pixels in the third column of sub-pixels, specifically the sub-pixels in the first row, third row, ..., (n-3)th row, and (n-1)th row, are electrically connected to the third second data signal line DA6; the sub-pixels in the third column of sub-pixels, specifically the sub-pixels in the second row, fourth row, ..., (n-2)th row, and nth row, are electrically connected to the third first data signal line DA5; ... the sub-pixels in the (k-2)th column... The sub-pixels in the first row, the third row, ..., the (n-3)th row, and the (n-1)th row are electrically connected to the (k-2)th second data signal line DA2k-4. The sub-pixels in the (k-2)th column, the second row, the fourth row, ..., the (n-2)th row, and the nth row are electrically connected to the (k-2)th first data signal line DA2k-5. The sub-pixels in the (k-1)th column, the first row, the third row, ..., the (n-3)th row, and the (n-1)th row are electrically connected to the (k-1)th second data signal line DA2k-2. Then, the sub-pixels in the second row, the fourth row, ..., the (n-2)th row, and the nth row of the sub-pixels in the (k-1)th column are electrically connected to the first data signal line DA2k-3; the sub-pixels in the first row, the third row, ..., the (n-3)th row, and the (n-1)th row of the sub-pixels in the kth column are electrically connected to the second data signal line DA2k; and the sub-pixels in the second row, the fourth row, ..., the (n-2)th row, and the nth row of the sub-pixels in the kth column are electrically connected to the first data signal line DA2k-1.

[0061] In some embodiments of this disclosure, as shown in Figures 2 and 3, valid signals are sequentially and alternately applied to the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figures 2 and 3) and valid signals (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figures 2 and 3) and the second data signal line.

[0062] It should be noted that the valid signal can be either the rendering data voltage or the raw data voltage.

[0063] As exemplarily shown in Figures 1 to 3, the display panel 100 may further include a gate driving circuit 110. The gate driving circuit 110 is electrically connected to the gate lines GA (GA1, GA2, GA3, GA4...GA(n-3), GA(n-2), GA(n-1), GAn in Figures 2 and 3). The timing controller 200 can input signals to the gate driving circuit 110 via a level shift circuit, thereby driving the gate lines GA (GA1, GA2, GA3, GA4...GA(n-3), GA(n-2), GA(n-1), GAn in Figures 2 and 3). The timing controller 200 inputs a signal to the source drive circuit 120, so that the source drive circuit 120 inputs the original data voltage or rendering data voltage to the data signal line DA (DA1, DA2, DA3, DA4, DA5, DA6, DA7...DA2k-5, DA2k-4, DA2k-3, DA2k-2, DA2k-1, DA2k in Figures 2 and 3), thereby charging the sub-pixel spx, so that the sub-pixel spx inputs the corresponding original data voltage or rendering data voltage, and the display panel realizes the image display function.

[0064] For example, as shown in Figures 2 and 3, each sub-pixel spx includes a transistor 01 and a pixel electrode 02. The gate of transistor 01 is electrically connected to the corresponding gate lines (GA1, GA2, GA3, GA4...GA(n-3), GA(n-2), GA(n-1), GAn in Figure 2), the source of transistor 01 is electrically connected to the corresponding data signal lines DA (DA1, DA2, DA3, DA4, DA5, DA6, DA7...DA2k-5, DA2k-4, DA2k-3, DA2k-2, DA2k-1, DA2k in Figure 2), and the drain of transistor 01 is electrically connected to the pixel electrode 02.

[0065] For example, as shown in Figures 2 and 3, each pixel unit includes multiple sub-pixels (spx). For instance, a pixel unit may include red, green, and blue sub-pixels, allowing for color mixing to achieve a color display. Alternatively, a pixel unit may include red, green, blue, and white sub-pixels, also allowing for color mixing to achieve a color display. Of course, in practical applications, the emission color of the sub-pixels within a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0066] It should be noted that the hardware specifications of the system-on-chip (SOC) currently available on the market can only support display panels with a resolution of 7680*3840 and a refresh rate of 60Hz, or display panels with a resolution of 7680*1920 and a refresh rate of 120Hz for display; when the resolution of the display panel is 7680*3840 and the refresh rate is 120Hz, the hardware specifications of the system-on-chip (SOC) are required to be relatively high; while the maximum resolution and data volume provided by the current system-on-chip (SOC) are 7680*1920 and a refresh rate of 120Hz, and this data volume cannot support the display panel with a resolution of 7680*3840 and a refresh rate of 120Hz to perform full-screen display, resulting in only half of the picture being displayed on the display panel and the display effect being poor.

[0067] Based on the above problems, the driving method of the display panel provided by the embodiments of the present invention determines the rendering data voltage according to the original data voltages charged into the a-th row sub-pixels and the (a + b)-th row sub-pixels in the same column of sub-pixels of the display panel, and charges the rendering data voltage into the (a + c)-th row sub-pixels. The rendering data voltage is determined according to the original data voltages charged into the a-th row sub-pixels and the (a + b)-th row sub-pixels. In this way, the rendering data voltage can be determined according to the original data voltage, avoiding the problem that the sub-pixels in the display panel cannot be displayed due to no corresponding original data voltage being charged, that is, solving the problem that the hardware specifications of the system-on-chip (SOC) are relatively low and cannot support the display panel to perform full-screen display, improving the display effect, and reducing costs, and ensuring that the display panel can be normally displayed by a system-on-chip with relatively low hardware specifications.

[0068] As shown in FIG. 4, the driving method of the display panel provided by the embodiments of the present disclosure may include the following steps:

[0069] S100. Obtain the original display data of a display frame. The original display data includes the original data voltages corresponding to M rows and K columns of sub-pixels. The display panel includes N rows and K columns of sub-pixels, and N is P times of M; M, N, and K are positive integers, and P is a positive integer greater than 1;

[0070] S200. Charge the original data voltage into the a-th row sub-pixels and the (a + b)-th row sub-pixels in the same column of sub-pixels of the display panel, and charge the rendering data voltage into the (a + c)-th row sub-pixels. The rendering data voltage is determined according to the original data voltages charged into the a-th row sub-pixels and the (a + b)-th row sub-pixels. c < b, and a, b, and c are positive integers.

[0071] This embodiment of the disclosure applies original data voltage to the sub-pixels in the a-th row and the (a+b)-th row of sub-pixels in the same column of the display panel, and applies rendering data voltage to the (a+c)-th row of sub-pixels. The rendering data voltage is determined based on the original data voltage applied to the sub-pixels in the a-th row and the (a+b)-th row. That is, rendering can expand the data rows of the original display data to twice their original size, and the rendering data voltage is determined based on the original data voltage applied to the sub-pixels in the a-th row and the (a+b)-th row. Therefore, the transition between the rendering data voltage of the (a+c)-th row of sub-pixels and the original data voltage of the sub-pixels in the a-th row and the (a+b)-th row is smoother, further improving the display effect.

[0072] For example, M=1920, K=7680, N=3840, P=2, as shown in Figure 5, the original display data includes the original data voltages corresponding to 1920 rows * 7680 columns of sub-pixels. As shown in Figure 6, the display panel includes 3840 rows * 7680 columns of sub-pixels.

[0073] For example, as shown in Figures 5 and 6, the original data voltage corresponding to the first row of sub-pixels in the original display data is applied to the first row of sub-pixels in the display panel; the original data voltage corresponding to the second row of sub-pixels in the original display data is applied to the third row of sub-pixels in the display panel; the original data voltage corresponding to the third row of sub-pixels in the original display data is applied to the fifth row of sub-pixels in the display panel; the original data voltage corresponding to the fourth row of sub-pixels in the original display data is applied to the seventh row of sub-pixels in the display panel; ... the original data voltage corresponding to the 1917th row of sub-pixels in the original display data is applied to the 3833rd row of sub-pixels in the display panel; the original data voltage corresponding to the 1918th row of sub-pixels in the original display data is applied to the 3835th row of sub-pixels in the display panel; the original data voltage corresponding to the 1919th row of sub-pixels in the original display data is applied to the 3837th row of sub-pixels in the display panel; and the original data voltage corresponding to the 1920th row of sub-pixels in the original display data is applied to the 3839th row of sub-pixels in the display panel.

[0074] For example, as shown in Figures 5 and 6, the original data voltage corresponding to the first row of sub-pixels in the original display data is applied to the second row of sub-pixels in the display panel; the original data voltage corresponding to the second row of sub-pixels in the original display data is applied to the fourth row of sub-pixels in the display panel; the original data voltage corresponding to the third row of sub-pixels in the original display data is applied to the sixth row of sub-pixels in the display panel; the original data voltage corresponding to the fourth row of sub-pixels in the original display data is applied to the eighth row of sub-pixels in the display panel; ... the original data voltage corresponding to the 1917th row of sub-pixels in the original display data is applied to the 3834th row of sub-pixels in the display panel; the original data voltage corresponding to the 1918th row of sub-pixels in the original display data is applied to the 3836th row of sub-pixels in the display panel; the original data voltage corresponding to the 1919th row of sub-pixels in the original display data is applied to the 3838th row of sub-pixels in the display panel; and the original data voltage corresponding to the 1920th row of sub-pixels in the original display data is applied to the 3840th row of sub-pixels in the display panel.

[0075] In some embodiments of this disclosure, the rendering data voltage charged to the sub-pixels in the (a+c)th row is equal to the average of the sum of the original data voltages charged to the sub-pixels in the (a)th row and the (a+b)th row.

[0076] In some embodiments of this disclosure, a first rendering data voltage is applied to the first row of sub-pixels in the same column of the display panel, the second and fourth row of sub-pixels are applied to the original data voltage, and the third row of sub-pixels is applied to the rendering data voltage; wherein, the first rendering data voltage is equal to half of the original data voltage applied to the second row of sub-pixels.

[0077] For example, as shown in Figure 6, for the same column of sub-pixels, the first rendering data voltage charged to the sub-pixels in the first row is equal to half of the original data voltage charged to the second row; the rendering data voltage charged to the sub-pixels in the third row is equal to the average of the sum of the original data voltages charged to the sub-pixels in the second and fourth rows; the rendering data voltage charged to the sub-pixels in the fifth row is equal to the average of the sum of the original data voltages charged to the sub-pixels in the fourth and sixth rows; the rendering data voltage charged to the sub-pixels in the seventh row is equal to the average of the sum of the original data voltages charged to the sub-pixels in the sixth and eighth rows; ... the rendering data voltage charged to the sub-pixels in the 3833rd row is equal to the average of the sum of the original data voltages charged to the sub-pixels in the sixth and eighth rows; ... The rendering data voltage is equal to the average of the sum of the original data voltages charged into the sub-pixels in rows 3832 and 3834; the rendering data voltage charged into the sub-pixels in row 3835 is equal to the average of the sum of the original data voltages charged into the sub-pixels in rows 3834 and 3836; the rendering data voltage charged into the sub-pixels in row 3837 is equal to the average of the sum of the original data voltages charged into the sub-pixels in rows 3836 and 3838; and the rendering data voltage charged into the sub-pixels in row 3839 is equal to the average of the sum of the original data voltages charged into the sub-pixels in rows 3838 and 3840.

[0078] In some embodiments of this disclosure, the original data voltage is applied to the N-3rd row and the N-1st row of sub-pixels in the same column of the display panel, the rendering data voltage is applied to the N-2nd row of sub-pixels, and the second rendering data voltage is applied to the Nth row of sub-pixels; wherein the second rendering data voltage is equal to half of the original data voltage applied to the N-1st row of sub-pixels.

[0079] For example, as shown in Figure 6, for the same column of sub-pixels, the rendering data voltage charged to the sub-pixels in the 2nd row is equal to the average of the sum of the original data voltages charged to the sub-pixels in the 1st and 3rd rows; the rendering data voltage charged to the sub-pixels in the 4th row is equal to the average of the sum of the original data voltages charged to the sub-pixels in the 3rd and 5th rows; the rendering data voltage charged to the sub-pixels in the 6th row is equal to the average of the sum of the original data voltages charged to the sub-pixels in the 5th and 7th rows; the rendering data voltage charged to the sub-pixels in the 8th row is equal to the average of the sum of the original data voltages charged to the sub-pixels in the 7th and 9th rows; ... The rendering data voltage charged to the sub-pixel in row 3834 is equal to the average of the sum of the original data voltages charged to the sub-pixels in rows 3833 and 3835; the rendering data voltage charged to the sub-pixel in row 3836 is equal to the average of the sum of the original data voltages charged to the sub-pixels in rows 3835 and 3837; the rendering data voltage charged to the sub-pixel in row 3838 is equal to the average of the sum of the original data voltages charged to the sub-pixels in rows 3837 and 3839; and the second rendering data voltage charged to the sub-pixel in row 3840 is equal to half of the original data voltage charged to the sub-pixel in row 3839.

[0080] In some embodiments of this disclosure, b = 2 and c = 1, that is, the sub-pixel of the (a+c)th row is located between the sub-pixel of the (a)th row and the sub-pixel of the (a+b)th row.

[0081] In some embodiments of this disclosure, the display frame is an odd-numbered frame, where a and a+b are both odd numbers from 1 to N, and a+c is an even number from 1 to N.

[0082] The following will use the structural schematic diagrams of the display panel shown in Figures 1 and 2 as examples, combined with the timing signal diagram shown in Figure 7, for further explanation;

[0083] For example, as shown in Figure 7, STV represents the frame start signal loaded by the timing controller onto the gate drive circuit, CLK1 represents the first clock signal loaded by the timing controller onto the gate drive circuit, CLK2 represents the second clock signal loaded by the timing controller onto the gate drive circuit, CLK3 represents the third clock signal loaded by the timing controller onto the gate drive circuit, CLK4 represents the fourth clock signal loaded by the timing controller onto the gate drive circuit, G1 represents the gate scan signal loaded by the gate drive circuit onto gate line GA1, and G2 represents the gate scan signal loaded by the gate drive circuit onto gate line GA2. The signals are as follows: G3 represents the gate scan signal loaded onto the gate line GA3 by the gate drive circuit; G4 represents the gate scan signal loaded onto the gate line GA4 by the gate drive circuit; G5 represents the gate scan signal loaded onto the gate line GA5 by the gate drive circuit; Gn-1 represents the gate scan signal loaded onto the gate line GA(n-1) by the gate drive circuit; Gn represents the gate scan signal loaded onto the gate line GAn by the gate drive circuit; S1 represents the original data voltage loaded onto the first data signal line by the source drive circuit; and S2 represents the rendered data voltage loaded onto the second data signal line by the source drive circuit.

[0084] For example, as shown in Figure 7, the time when the original data voltage S1 is applied to the first data signal line does not overlap with the time when the rendered data voltage S2 is applied to the second data signal line.

[0085] For example, the following will provide a detailed description of the same column of sub-pixels;

[0086] When the display frame is an odd number of frames, the gate drive circuit loads the gate scan signal G1 onto the gate line GA1. Transistor O1 in the first row of sub-pixels is turned on under the control of the high level of the gate scan signal G1. The original data voltage on the first data signal lines (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is then charged into the first row of sub-pixels, and the voltage value of the original data voltage charged into the first row of sub-pixels is V1. The gate drive circuit then loads the gate scan signal G2 onto the gate line GA2. Transistor O1 in the second row of sub-pixels is turned on under the control of the high level of the gate scan signal G2. The second data signal lines (DA2, DA4, DA5, DA6, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) are then charged into the first row of sub-pixels. The rendering data voltage on A6……DA2k-4, DA2k-2, DA2k) is charged into the second row of sub-pixels, and the voltage value of the rendering data voltage charged into the second row of sub-pixels is (V1+V3) / 2; the transistor O1 in the third row of sub-pixels is turned on under the control of the high level of the gate scan signal G3, so the original data voltage on the first data signal line (DA1, DA3, DA5, DA7……DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the third row of sub-pixels, and the voltage value of the original data voltage charged into the third row of sub-pixels is V3; the transistor O1 in the fourth row of sub-pixels is turned on under the control of the high level of the gate scan signal G4, so the original data voltage on the second ...) is charged In Figure 2, the rendering data voltage on DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k) is charged into the 4th row sub-pixel, and the voltage value of the rendering data voltage charged into the 4th row sub-pixel is (V3+V5) / 2; when the transistor O1 in the 5th row sub-pixel is turned on under the control of the high level of the gate scan signal G5, the original data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the 5th row sub-pixel, and the voltage value of the original data voltage charged into the 5th row sub-pixel is V5; when the transistor O1 in the (n-1)th row sub-pixel is turned on under the control of the high level of the gate scan signal Gn-1 ...) is charged into the 5th row sub-pixel, and the voltage value of the original data voltage charged into the 5th row sub-pixel is V5; when the transistor O1 in the (n-1)th row sub-pixel is turned on under the control of the high level of the gate scan signal Gn-1, the original data voltage on the first data signal line ( When the transistor 01 in the nth row of sub-pixels is turned on under the control of the high level of the gate scan signal Gn, the original data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the (n-1)th row of sub-pixels, and the voltage value of the original data voltage charged into the (n-1)th row of sub-pixels is V(n-1); when the transistor 01 in the nth row of sub-pixels is turned on under the control of the high level of the gate scan signal Gn, the second rendering data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the nth row of sub-pixels, and the voltage value of the second rendering data voltage charged into the nth row of sub-pixels is V(n-1) / 2.

[0087] In some embodiments of this disclosure, the display frame is an even-numbered frame, where a and a+b are both even numbers from 1 to N, and a+c is an odd number from 1 to N.

[0088] The following will use the structural schematic diagrams of the display panel shown in Figures 1 and 2 as examples, combined with the timing signal diagram shown in Figure 8, for further explanation;

[0089] For example, as shown in Figure 8, STV represents the frame start signal loaded by the timing controller onto the gate drive circuit, CLK1 represents the first clock signal loaded by the timing controller onto the gate drive circuit, CLK2 represents the second clock signal loaded by the timing controller onto the gate drive circuit, CLK3 represents the third clock signal loaded by the timing controller onto the gate drive circuit, CLK4 represents the fourth clock signal loaded by the timing controller onto the gate drive circuit, G1 represents the gate scan signal loaded by the gate drive circuit onto gate line GA1, G2 represents the gate scan signal loaded by the gate drive circuit onto gate line GA2, and G3 represents the gate drive circuit... The gate scan signal loaded onto gate line GA3, G4 represents the gate scan signal loaded onto gate line GA4 by the gate drive circuit, G5 represents the gate scan signal loaded onto gate line GA5 by the gate drive circuit, G6 represents the gate scan signal loaded onto gate line GA6 by the gate drive circuit, Gn-1 represents the gate scan signal loaded onto gate line GA(n-1) by the gate drive circuit, Gn represents the gate scan signal loaded onto gate line GAn by the gate drive circuit, S1 represents the rendering data voltage loaded onto the first data signal line by the source drive circuit, and S2 represents the original data voltage loaded onto the second data signal line by the source drive circuit.

[0090] For example, as shown in Figure 8, the time for loading the rendering data voltage S1 on the first data signal line does not overlap with the time for loading the original data voltage S2 on the second data signal line.

[0091] For example, the following will provide a detailed description of the same column of sub-pixels;

[0092] When the displayed frame is an even-numbered frame, the gate drive circuit loads the gate scan signal G1 onto the gate line GA1. Transistor O1 in the first row of sub-pixels is turned on under the control of the high level of the gate scan signal G1. Then, the first rendering data voltage on the first data signal lines (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the first row of sub-pixels, and the voltage value of the first rendering data voltage charged into the first row of sub-pixels is V2 / 2. The gate drive circuit loads the gate scan signal G2 onto the gate line GA2. Transistor O1 in the second row of sub-pixels is turned on under the control of the high level of the gate scan signal G2. Then, the second row of sub-pixels... The original data voltage on the signal lines (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the second row of sub-pixels, and the voltage value of the original data voltage charged into the second row of sub-pixels is V2. The gate drive circuit loads the gate scan signal G3 onto the gate line GA3. Under the control of the high level of the gate scan signal G3, the transistor O1 in the third row of sub-pixels is turned on, and the rendering data voltage on the first data signal lines (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the third row of sub-pixels, and the voltage value of the rendering data voltage charged into the third row of sub-pixels is V2. The gate drive circuit applies a gate scan signal G4 to the gate line GA4. Transistor 01 in the 4th row sub-pixel is turned on under the control of the high level of the gate scan signal G4. The original data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is then charged into the 4th row sub-pixel, and the voltage value of the original data voltage charged into the 4th row sub-pixel is V4. The gate drive circuit applies a gate scan signal G5 to the gate line GA5. Transistor 01 in the 5th row sub-pixel is turned on under the control of the high level of the gate scan signal G5. The voltage value of the first data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is then charged into the 4th row sub-pixel. 1. The rendering data voltage on DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1) is charged into the 5th row sub-pixel, and the voltage value of the rendering data voltage charged into the 5th row sub-pixel is (V4+V6) / 2; the gate drive circuit loads the gate scan signal G6 onto the gate line GA6, and the transistor 01 in the 6th row sub-pixel is turned on under the control of the high level of the gate scan signal G6. Then the original data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the 6th row sub-pixel, and the voltage value of the original data voltage charged into the 6th row sub-pixel is V6;The gate driving circuit loads the gate scan signal Gn-1 onto the gate line GAn-1. Transistor O1 in the (n-1)th row of sub-pixels is turned on under the control of the high level of the gate scan signal Gn-1. Therefore, the rendering data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the (n-1)th row of sub-pixels, and the voltage value of the rendering data voltage charged into the (n-1)th row of sub-pixels is (Vn + V(n-2)) / 2. The gate driving circuit also loads the gate scan signal Gn onto the gate line GAn. Transistor O1 in the nth row of sub-pixels is turned on under the control of the high level of the gate scan signal Gn. Therefore, the original data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the nth row of sub-pixels, and the voltage value of the original data voltage charged into the nth row of sub-pixels is Vn.

[0093] In some embodiments of this disclosure, the display frame is an odd-numbered frame, where a and a+b are both even numbers from 1 to N, and a+c is an odd number from 1 to N.

[0094] The following will use the structural schematic diagrams of the display panel shown in Figures 1 and 3 as examples, combined with the timing signal diagram shown in Figure 9, for further explanation;

[0095] For example, as shown in Figure 9, STV represents the frame start signal loaded by the timing controller onto the gate drive circuit, CLK1 represents the first clock signal loaded by the timing controller onto the gate drive circuit, CLK2 represents the second clock signal loaded by the timing controller onto the gate drive circuit, CLK3 represents the third clock signal loaded by the timing controller onto the gate drive circuit, CLK4 represents the fourth clock signal loaded by the timing controller onto the gate drive circuit, G1 represents the gate scan signal loaded by the gate drive circuit onto gate line GA1, G2 represents the gate scan signal loaded by the gate drive circuit onto gate line GA2, and G3 represents the gate drive circuit... The gate scan signal loaded onto gate line GA3, G4 represents the gate scan signal loaded onto gate line GA4 by the gate drive circuit, G5 represents the gate scan signal loaded onto gate line GA5 by the gate drive circuit, G6 represents the gate scan signal loaded onto gate line GA6 by the gate drive circuit, Gn-1 represents the gate scan signal loaded onto gate line GA(n-1) by the gate drive circuit, Gn represents the gate scan signal loaded onto gate line GAn by the gate drive circuit, S1 represents the original data voltage loaded onto the first data signal line by the source drive circuit, and S2 represents the rendering data voltage loaded onto the second data signal line by the source drive circuit.

[0096] For example, as shown in Figure 9, the time when the original data voltage S1 is applied to the first data signal line does not overlap with the time when the rendered data voltage S2 is applied to the second data signal line.

[0097] For example, the following will provide a detailed description of the same column of sub-pixels;

[0098] When the display frame is an odd number of frames, the gate drive circuit loads the gate scan signal G1 onto the gate line GA1. Transistor O1 in the first row of sub-pixels is turned on under the control of the high level of the gate scan signal G1. Then, the first rendering data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 3) is charged into the first row of sub-pixels, and the voltage value of the first rendering data voltage charged into the first row of sub-pixels is V2 / 2. The gate drive circuit loads the gate scan signal G2 onto the gate line GA2. Transistor O1 in the second row of sub-pixels is turned on under the control of the high level of the gate scan signal G2. Then, the first data signal line (Figure 3...DA2k-4, DA2k-2, DA2k in Figure 3) is charged into the first row of sub-pixels. The original data voltage on the DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 3 is charged into the second row of sub-pixels, and the voltage value of the original data voltage charged into the second row of sub-pixels is V2; the gate drive circuit loads the gate scan signal G3 onto the gate line GA3, and the transistor O1 in the third row of sub-pixels is turned on under the control of the high level of the gate scan signal G3. Then the rendering data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 3) is charged into the third row of sub-pixels, and the voltage value of the rendering data voltage charged into the third row of sub-pixels is (V2 + V). 4) / 2; The gate drive circuit loads the gate scan signal G4 onto the gate line GA4. Transistor O1 in the 4th row sub-pixel is turned on under the control of the high level of the gate scan signal G4. The original data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 3) is then charged into the 4th row sub-pixel. The voltage value of the original data voltage charged into the 4th row sub-pixel is V4. The gate drive circuit loads the gate scan signal G5 onto the gate line GA5. Transistor O1 in the 5th row sub-pixel is turned on under the control of the high level of the gate scan signal G5. The second data signal line (DA...DA2k-5, DA2k-3, DA2k-1 in Figure 3) is then charged into the 4th row sub-pixel. 2. The rendering data voltage on DA4, DA6...DA2k-4, DA2k-2, DA2k) is charged into the 5th row sub-pixel, and the voltage value of the rendering data voltage charged into the 5th row sub-pixel is (V4+V6) / 2; the gate drive circuit loads the gate scan signal G6 onto the gate line GA6, and the transistor 01 in the 6th row sub-pixel is turned on under the control of the high level of the gate scan signal G6. Then the original data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 3) is charged into the 6th row sub-pixel, and the voltage value of the original data voltage charged into the 6th row sub-pixel is V6;The gate driving circuit loads the gate scan signal Gn-1 onto the gate line GAn-1. Transistor O1 in the (n-1)th row of sub-pixels is turned on under the control of the high level of the gate scan signal Gn-1. Then, the rendering data voltage on the second data signal lines (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 3) is charged into the (n-1)th row of sub-pixels, and the voltage value of the rendering data voltage charged into the (n-1)th row of sub-pixels is (Vn + V(n-2)) / 2. The gate driving circuit also loads the gate scan signal Gn onto the gate line GAn. Transistor O1 in the nth row of sub-pixels is turned on under the control of the high level of the gate scan signal Gn. Then, the original data voltage on the first data signal lines (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 3) is charged into the nth row of sub-pixels, and the voltage value of the original data voltage charged into the nth row of sub-pixels is Vn.

[0099] In some embodiments of this disclosure, the display frame is an even-numbered frame, where a and a+b are both odd numbers from 1 to N, and a+c is an even number from 1 to N.

[0100] The following will use the structural schematic diagrams of the display panel shown in Figures 1 and 3 as examples, combined with the timing signal diagram shown in Figure 10, for further explanation;

[0101] For example, as shown in Figure 10, STV represents the frame start signal loaded by the timing controller onto the gate drive circuit, CLK1 represents the first clock signal loaded by the timing controller onto the gate drive circuit, CLK2 represents the second clock signal loaded by the timing controller onto the gate drive circuit, CLK3 represents the third clock signal loaded by the timing controller onto the gate drive circuit, CLK4 represents the fourth clock signal loaded by the timing controller onto the gate drive circuit, G1 represents the gate scan signal loaded by the gate drive circuit onto gate line GA1, and G2 represents the gate scan signal loaded by the gate drive circuit onto gate line GA2. The signal is defined as follows: G3 represents the gate scan signal loaded onto the gate line GA3 by the gate drive circuit; G4 represents the gate scan signal loaded onto the gate line GA4 by the gate drive circuit; G5 represents the gate scan signal loaded onto the gate line GA5 by the gate drive circuit; Gn-1 represents the gate scan signal loaded onto the gate line GA(n-1) by the gate drive circuit; Gn represents the gate scan signal loaded onto the gate line GAn by the gate drive circuit; S1 represents the rendering data voltage loaded onto the first data signal line by the source drive circuit; and S2 represents the original data voltage loaded onto the second data signal line by the source drive circuit.

[0102] For example, as shown in Figure 10, the time for loading the rendering data voltage S1 on the first data signal line does not overlap with the time for loading the original data voltage S2 on the second data signal line.

[0103] For example, the following will provide a detailed description of the same column of sub-pixels;

[0104] When the displayed frame is an even-numbered frame, the gate drive circuit loads the gate scan signal G1 onto the gate line GA1. Transistor O1 in the first row of sub-pixels is turned on under the control of the high level of the gate scan signal G1. The original data voltage on the second data signal lines (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 3) is then charged into the first row of sub-pixels, and the voltage value of the original data voltage charged into the first row of sub-pixels is V1. The gate drive circuit then loads the gate scan signal G2 onto the gate line GA2. Transistor O1 in the second row of sub-pixels is turned on under the control of the high level of the gate scan signal G2. The first data signal lines (DA1, DA3, DA5, DA6...DA2k-4, DA2k-2, DA2k in Figure 3) are then charged into the first row of sub-pixels. The rendering data voltage on lines 7...DA2k-5, DA2k-3, DA2k-1) is charged into the second row of sub-pixels, and the voltage value of the rendering data voltage charged into the second row of sub-pixels is (V1+V3) / 2; when transistor 01 in the third row of sub-pixels is turned on under the control of the high level of the gate scan signal G3, the original data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 3) is charged into the third row of sub-pixels, and the voltage value of the original data voltage charged into the third row of sub-pixels is V3; when transistor 01 in the fourth row of sub-pixels is turned on under the control of the high level of the gate scan signal G4, the original data voltage on the first .... The rendering data voltage on the DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1) lines is charged into the 4th row sub-pixel, and the voltage value of the rendering data voltage charged into the 4th row sub-pixel is (V3+V5) / 2; the transistor O1 in the 5th row sub-pixel is turned on under the control of the high level of the gate scan signal G5, and the original data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 3) is charged into the 5th row sub-pixel, and the voltage value of the original data voltage charged into the 5th row sub-pixel is V5; the transistor O1 in the (n-1)th row sub-pixel is turned on under the control of the high level of the gate scan signal Gn-1. When transistor 01 in the nth row of sub-pixels is turned on under the control of the high level of the gate scan signal Gn, the original data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 3) is charged into the (n-1)th row of sub-pixels, and the voltage value of the original data voltage charged into the (n-1)th row of sub-pixels is V(n-1); when transistor 01 in the nth row of sub-pixels is turned on under the control of the high level of the gate scan signal Gn, the second rendering data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 3) is charged into the nth row of sub-pixels, and the voltage value of the second rendering data voltage charged into the nth row of sub-pixels is V(n-1) / 2.

[0105] This disclosure provides other structural schematic diagrams of a display device, as shown in Figures 10 and 11, which are modifications of the embodiments described above. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0106] In some embodiments of this disclosure, as shown in Figures 11 and 12, the display panel further includes: multiple gate lines (GA1, GA2...GA(n-1), GAn in Figures 11 and 12), and adjacent rows of sub-pixels spx are electrically connected to the same gate line (GA1, GA2...GA(n-1), GAn in Figures 11 and 12).

[0107] For example, the sub-pixels spx in the first row and the second row are electrically connected to the gate line GA1, the sub-pixels spx in the third row and the fourth row are electrically connected to the gate line GA2, ... the sub-pixels spx in the (n-3)th row and the (n-2)th row are electrically connected to the gate line GA(n-1), and the sub-pixels spx in the (n-1)th row and the nth row are electrically connected to the gate line GAn.

[0108] This embodiment of the invention doubles the charging time of sub-pixels in the display panel by electrically connecting two adjacent rows of sub-pixels to the same gate line, thus avoiding insufficient charging time of sub-pixels in high-resolution display panels and improving the display effect.

[0109] In some embodiments of this disclosure, a valid signal is simultaneously loaded onto a first data signal line and a valid signal is simultaneously loaded onto a second data signal line.

[0110] It should be noted that the valid signal can be either the rendering data voltage or the raw data voltage.

[0111] The following will use the structural schematic diagrams of the display panel shown in Figures 1 and 11 as examples, combined with the timing signal diagram shown in Figure 13, for further explanation;

[0112] For example, as shown in Figure 13, STV represents the frame start signal loaded by the timing controller onto the gate drive circuit, CLK1 represents the first clock signal loaded by the timing controller onto the gate drive circuit, CLK2 represents the second clock signal loaded by the timing controller onto the gate drive circuit, CLK3 represents the third clock signal loaded by the timing controller onto the gate drive circuit, CLK4 represents the fourth clock signal loaded by the timing controller onto the gate drive circuit, G1 represents the gate scan signal loaded by the gate drive circuit onto gate line GA1, G2 represents the gate scan signal loaded by the gate drive circuit onto gate line GA2, Gn-1 represents the gate scan signal loaded by the gate drive circuit onto gate line GA(n-1), Gn represents the gate scan signal loaded by the gate drive circuit onto gate line GAn, S1 represents the original data voltage loaded by the source drive circuit onto the first data signal line, and S2 represents the rendered data voltage loaded by the source drive circuit onto the second data signal line.

[0113] For example, as shown in Figure 13, the time when the original data voltage S1 is applied to the first data signal line overlaps with the time when the rendered data voltage S2 is applied to the second data signal line.

[0114] For example, the following will provide a detailed description of the same column of sub-pixels;

[0115] When the display frame is an odd number of frames, the gate drive circuit loads the gate scan signal G1 onto the gate line GA1. The transistors 01 in the first and second row sub-pixels are turned on under the control of the high level of the gate scan signal G1. Then, the original data voltage on the first data signal line (DA1, DA3, DA5, DA7…DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the first row sub-pixel, and the rendering voltage on the second data signal line (DA2, DA4, DA6…DA2k-4, DA2k-2, DA2k in Figure 2) is... The rendering data voltage is applied to the second row of sub-pixels. The voltage value of the original data voltage applied to the first row of sub-pixels is V1, and the voltage value of the rendering data voltage applied to the second row of sub-pixels is (V1+V3) / 2. The gate drive circuit applies the gate scan signal G2 to the gate line GA2. Transistors O1 in the third and fourth row of sub-pixels are turned on under the control of the high level of the gate scan signal G2. Therefore, the original data voltage on the first data signal line (DA1, DA3, DA5, DA7…DA2k-5, DA2k-3, DA2k-1 in Figure 2) is applied. The voltage is applied to the third row of sub-pixels, and the rendering data voltage on the second data signal lines (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is applied to the fourth row of sub-pixels. The original data voltage applied to the third row of sub-pixels has a value of V3, and the rendering data voltage applied to the fourth row of sub-pixels has a value of (V3+V5) / 2. The gate drive circuit applies the gate scan signal G3 to the gate line GA3. The transistors 01 in the fifth and sixth row of sub-pixels are controlled by the high level of the gate scan signal G3. When the bottom conduction is turned on, the original data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the 5th row sub-pixel, and the rendering data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the 6th row sub-pixel. The voltage value of the original data voltage charged into the 5th row sub-pixel is V5, and the voltage value of the rendering data voltage charged into the 6th row sub-pixel is (V5+V7) / 2.The gate driving circuit loads the gate scan signal G4 onto the gate line GA4. Transistors 01 in the 7th and 8th row sub-pixels are turned on under the control of the high level of the gate scan signal G4. Therefore, the original data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the 7th row sub-pixel, and the rendering data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the 8th row sub-pixel. The voltage value of the original data voltage charged into the 7th row sub-pixel is V7, and the voltage value of the rendering data voltage charged into the 8th row sub-pixel is (V7+V9) / 2. When a gate scan signal Gn is applied to the gate line GAn, transistors 01 in the (n-1)th row and the nth row of sub-pixels are turned on under the control of the high level of the gate scan signal Gn. Then, the original data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the (n-1)th row of sub-pixels, and the second rendering data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the nth row of sub-pixels. The voltage value of the original data voltage charged into the (n-1)th row of sub-pixels is V(n-1), and the voltage value of the second rendering data voltage charged into the nth row of sub-pixels is V(n-1) / 2.

[0116] The following will take the structural schematic diagram of the display panel shown in Figures 1 and 11 as an example, and further explain it in conjunction with the timing signal diagram shown in Figure 14;

[0117] For example, as shown in Figure 14, STV represents the frame start signal loaded by the timing controller onto the gate drive circuit, CLK1 represents the first clock signal loaded by the timing controller onto the gate drive circuit, CLK2 represents the second clock signal loaded by the timing controller onto the gate drive circuit, CLK3 represents the third clock signal loaded by the timing controller onto the gate drive circuit, CLK4 represents the fourth clock signal loaded by the timing controller onto the gate drive circuit, G1 represents the gate scan signal loaded by the gate drive circuit onto gate line GA1, G2 represents the gate scan signal loaded by the gate drive circuit onto gate line GA2, Gn-1 represents the gate scan signal loaded by the gate drive circuit onto gate line GA(n-1), Gn represents the gate scan signal loaded by the gate drive circuit onto gate line GAn, S1 represents the rendered data voltage loaded by the source drive circuit onto the first data signal line, and S2 represents the original data voltage loaded by the source drive circuit onto the second data signal line.

[0118] For example, as shown in Figure 14, the time when the rendering data voltage S1 is applied to the first data signal line overlaps with the time when the original data voltage S2 is applied to the second data signal line.

[0119] For example, the following will provide a detailed description of the same column of sub-pixels;

[0120] When the displayed frame is an even-numbered frame, the gate drive circuit loads the gate scan signal G1 onto the gate line GA1. Transistors O1 in the first and second row sub-pixels are turned on under the control of the high level of the gate scan signal G1. Then, the first rendering data voltage on the first data signal line (DA1, DA3, DA5, DA7…DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the first row sub-pixel, and the voltage on the second data signal line (DA2, DA4, DA6…DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the second data signal line. The original data voltage is charged into the second row of sub-pixels, where the voltage value of the first rendering data voltage charged into the first row of sub-pixels is V2 / 2, and the voltage value of the original data voltage charged into the second row of sub-pixels is V2; the gate drive circuit loads the gate scan signal G2 onto the gate line GA2, and the transistors 01 in the third and fourth row of sub-pixels are turned on under the control of the high level of the gate scan signal G2, so the first rendering on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is activated. The data voltage is applied to the third row of sub-pixels, and the original data voltage on the second data signal lines (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is applied to the fourth row of sub-pixels. The voltage value of the rendering data voltage applied to the third row of sub-pixels is (V2+V4) / 2, and the voltage value of the original data voltage applied to the fourth row of sub-pixels is V4. The gate drive circuit applies the gate scan signal G3 to the gate line GA3. The transistors 01 in the fifth and sixth row of sub-pixels are controlled by the high level of the gate scan signal G3. When the bottom conduction is turned on, the rendering data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the 5th row sub-pixel, and the original data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the 6th row sub-pixel. The voltage value of the rendering data voltage charged into the 5th row sub-pixel is (V4+V6) / 2, and the voltage value of the original data voltage charged into the 6th row sub-pixel is V6.The gate drive circuit applies the gate scan signal G4 to the gate line GA4. Transistors 01 in the 7th and 8th row sub-pixels are turned on under the control of the high level of the gate scan signal G4. Therefore, the rendering data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the 7th row sub-pixel, and the original data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the 8th row sub-pixel. The voltage value of the rendering data voltage charged into the 7th row sub-pixel is (V6+V8) / 2, and the voltage value of the original data voltage charged into the 8th row sub-pixel is V8. When the gate scan signal Gn is applied to the path gate line GAn, the transistors 01 in the (n-1)th row sub-pixel and the nth row sub-pixel are turned on under the control of the high level of the gate scan signal Gn. Then, the rendering data voltage on the first data signal line (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 2) is charged into the (n-1)th row sub-pixel, and the original data voltage on the second data signal line (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 2) is charged into the nth row sub-pixel. The voltage value of the rendering data voltage charged into the (n-1)th row sub-pixel is (Vn + V(n-2)) / 2, and the voltage value of the original data voltage charged into the nth row sub-pixel is Vn.

[0121] This disclosure provides further structural schematic diagrams of a display device, as shown in FIG15, which are modifications of the embodiments described above. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0122] In this embodiment of the disclosure, as shown in FIG15, the source driving circuit includes: a first source driving circuit 121 and a second source driving circuit 122; the first source driving circuit 121 and the second source driving circuit 122 are respectively disposed on both sides of the display panel 100.

[0123] The first source drive circuit 121 is electrically connected to K first data signal lines (DA1, DA3, DA5, DA7...DA2k-5, DA2k-3, DA2k-1 in Figure 15);

[0124] The second source drive circuit 122 is electrically connected to K second data signal lines (DA2, DA4, DA6...DA2k-4, DA2k-2, DA2k in Figure 15).

[0125] This embodiment of the present disclosure, by having the first source driving circuit and the second source driving circuit respectively disposed on both sides of the display panel; the first source driving circuit being electrically connected to K first data signal lines; and the second source driving circuit being electrically connected to K second data signal lines, can avoid the situation where one side of a display panel with high resolution and small size is insufficient to place the source driving circuit. By disposing of the first source driving circuit and the second source driving circuit on both sides of the display panel, the placement space for the source driving circuit can be increased.

[0126] The timing controller provided in this embodiment includes: a memory storing a computer program; and a processor executing the computer program to implement the above-described display panel driving method.

[0127] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0128] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0129] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0130] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0131] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0132] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for driving a display panel, wherein, Comprising: Obtain the original display data of a display frame, the original display data includes the original data voltages corresponding to sub-pixels of M rows and K columns, the display panel includes sub-pixels of N rows and K columns, N is P times of M, M, N, and K are positive integers, and P is a positive integer greater than 1; Charge the original data voltages into the a-th row sub-pixels and the (a + b)-th row sub-pixels in the same column of sub-pixels of the display panel, and charge the rendering data voltage into the (a + c)-th row sub-pixels, the rendering data voltage is determined according to the original data voltages charged into the a-th row sub-pixels and the (a + b)-th row sub-pixels, c < b, and a, b, c are positive integers.

2. The driving method for the display panel as described in claim 1, wherein, The rendering data voltage charged into the (a + c)-th row sub-pixels is equal to the average value of the sum of the original data voltages charged into the a-th row sub-pixels and the (a + b)-th row sub-pixels.

3. The driving method for the display panel as described in claim 2, wherein, The display frame is an odd frame, a and a + b are both odd numbers from 1 to N, and a + c is an even number from 1 to N.

4. The driving method for the display panel as described in claim 2, wherein, The display frame is an odd frame, a and a + b are both even numbers from 1 to N, and a + c is an odd number from 1 to N.

5. The driving method for a display panel as described in claim 2, wherein, The display frame is an even frame, a and a + b are both even numbers from 1 to N, and a + c is an odd number from 1 to N.

6. The driving method for a display panel as described in claim 2, wherein, The display frame is an even frame, a and a + b are both odd numbers from 1 to N, and a + c is an even number from 1 to N.

7. The driving method for a display panel as described in claim 4 or 5, wherein, Charge the first rendering data voltage into the 1st row sub-pixels in the same column of sub-pixels of the display panel, charge the original data voltages into the 2nd row sub-pixels and the 4th row sub-pixels, and charge the rendering data voltage into the 3rd row sub-pixels; wherein, the first rendering data voltage is equal to half of the original data voltage charged into the 2nd row sub-pixels.

8. The driving method for a display panel as described in claim 3 or 6, wherein, Charge the original data voltages into the (N - 3)-th row sub-pixels and the (N - 1)-th row sub-pixels in the same column of sub-pixels of the display panel, charge the rendering data voltage into the (N - 2)-th row sub-pixels, and charge the second rendering data voltage into the N-th row sub-pixels; wherein, the second rendering data voltage is equal to half of the original data voltage charged into the (N - 1)-th row sub-pixels.

9. The driving method for a display panel as described in any one of claims 1-6, wherein, The b = 2, c = 1.

10. A timing controller, wherein, Comprising: A memory, in which a computer program is stored; A processor, which is configured to implement the driving method of the display panel as described in any one of claims 1-9 when executing the computer program.

11. A display device, wherein, Comprising: A display panel, including: sub-pixels of N rows and K columns, multiple data signal lines, and a source driver circuit; A central control circuit, electrically connected to the timing controller, and configured to provide the original data voltages corresponding to sub-pixels of M rows and K columns in the original display data to the timing controller; wherein, N is P times of M, M, N, and K are positive integers, and P is a positive integer greater than ​ The source drive circuit is electrically connected to the timing controller and is configured to, under the control of the timing controller, charge the original data voltage to the sub-pixels in the a-th row and the (a+b-th row) of the same column of sub-pixels in the display panel through the data signal line, and charge the rendering data voltage to the (a+c-th row) of sub-pixels.

12. The display device as claimed in claim 11, wherein, The multiple data signal lines include: K first data signal lines and K second data signal lines; The sub-pixels in the a-th row and the a+b-th row of the k-th sub-pixels are electrically connected to the k-th first data signal line, and the sub-pixels in the a+c-th row of the k-th sub-pixels are electrically connected to the k-th second data signal line. Alternatively, the sub-pixels in the a-th row and the a+b-th row of the k-th sub-pixels are electrically connected to the k-th second data signal line, and the sub-pixels in the a+c-th row of the k-th sub-pixels are electrically connected to the k-th first data signal line; where k is a positive integer.

13. The display device as claimed in claim 12, wherein, The display panel also includes: multiple grid lines, with one row of sub-pixels electrically connected to one grid line; Valid signals are sequentially and alternately applied to the first data signal line and the second data signal line.

14. The display device as claimed in claim 12, wherein, The display panel further includes: multiple grid lines, with adjacent rows of sub-pixels electrically connected to the same grid line; Simultaneously, a valid signal is applied to the first data signal line and a valid signal is applied to the second data signal line.

15. The display device as claimed in claim 12, wherein, The source drive circuit includes: a first source drive circuit and a second source drive circuit; the first source drive circuit and the second source drive circuit are respectively disposed on both sides of the display panel; The first source drive circuit is electrically connected to the K first data signal lines; The second source drive circuit is electrically connected to the K second data signal lines.

16. The display device according to any one of claims 11-15, wherein, P＝2。

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