Heterojunction solar cell and manufacturing method therefor, and device

Abstract

A heterojunction solar cell and a manufacturing method therefor, and a device. The cell has at least one front passivation layer (11) and at least one front doped layer (12), which are located on the front face of a silicon substrate (10); and at least one rear passivation layer (21) and at least one rear doped layer (22), which are located on the rear face of the silicon substrate (10). In the cell manufacturing method, the deposition of passivation layers on the front face and the rear face of the silicon substrate (10) is performed in the same deposition chain, such that the at least one front passivation layer (11) and the at least one rear passivation layer (21) are respectively deposited on the front face and the rear face of the silicon substrate (10), and at least one side-edge passivation layer (31) is also formed on a side edge of the heterojunction solar cell and in an edge region of the silicon substrate (10).

Description

A heterojunction solar cell and its fabrication method and equipment Technical Field

[0001] This invention relates to a heterojunction solar cell and its fabrication method and apparatus. Background Technology

[0002] Heterojunction solar cells combine the advantages of monocrystalline silicon and amorphous silicon solar cells, boasting simple manufacturing processes, high efficiency, low temperature coefficient, and high conversion efficiency, making them a hot topic in photovoltaic industry research and development. The heterojunction solar cell manufacturing process includes four main steps: cleaning and texturing, PECVD thin film deposition, PVD thin film deposition, and electrode metallization. Among these, the PECVD thin film deposition step is particularly critical, being the core process for forming the heterojunction ninip or nipin structure.

[0003] In the PECVD thin film deposition process, four layers need to be deposited: a front passivation layer (intrinsic layer), a back passivation layer (intrinsic layer), a front doped layer, and a back doped layer. Using four deposition chains results in the highest cost. However, using a single-sided co-deposition chain for the passivation and doped layers reduces the need for only two or three chains, significantly lowering equipment costs. But depositing both the passivation and doped layers on the same side and reusing the carrier substrate can contaminate the process chamber, affecting the passivation layer preparation and consequently the passivation effect.

[0004] In addition, the front and back intrinsic layers of both schemes are not deposited in the same deposition chain. The substrate and the previously deposited intrinsic layer are repeatedly heated and come into contact with the atmosphere to form a natural oxide layer on the surface, which further affects the performance of the solar cell. Summary of the Invention

[0005] The purpose of this invention is to provide a heterojunction solar cell and its manufacturing method and apparatus.

[0006] To achieve the objective of this invention, a method for fabricating a heterojunction solar cell is proposed. The heterojunction solar cell includes: a silicon substrate doped with a first conductivity type; at least one front passivation layer, at least one front doped layer, at least one transparent front conductive layer, and at least one front electrode located on the front side of the silicon substrate; at least one back passivation layer, at least one back doped layer, at least one transparent back conductive layer, and at least one back electrode located on the back side of the silicon substrate; wherein, in the front doped layer and the back doped layer, one doping type is the first conductivity type, and the other doping type is a second conductivity type opposite to the first conductivity type; the method includes the following steps: providing a silicon substrate doped with the first conductivity type; forming at least one front passivation layer and at least one back passivation layer made of an intrinsic amorphous silicon-based material on the front and back sides of the silicon substrate, respectively, in the same deposition chain; and forming at least one front doped layer and at least one back doped layer on the at least one front passivation layer and the at least one back passivation layer, respectively.

[0007] In a preferred embodiment, the method forms at least one side-edge passivation layer on the side edge of the heterojunction solar cell, in the edge region of the silicon substrate.

[0008] In a preferred embodiment, the method involves simultaneously depositing a front passivation layer and a back passivation layer to form the side edge passivation layer; or, depositing a front passivation layer first and then a back passivation layer to form the side edge passivation layer; or, depositing a back passivation layer first and then a front passivation layer to form the side edge passivation layer.

[0009] In a preferred embodiment, the front doped layer and / or the back doped layer are composed of microcrystalline silicon-based materials or nanocrystalline silicon-based materials.

[0010] In a preferred embodiment, the silicon substrate is an N-type textured silicon wafer, the first conductivity type is N-type, and the second conductivity type is P-type; or, the silicon substrate is a P-type textured silicon wafer, the first conductivity type is P-type, and the second conductivity type is N-type.

[0011] In a preferred embodiment, the method further includes: forming at least one transparent back conductive layer on at least one back doped layer; forming at least one transparent front conductive layer on at least one front doped layer; forming a back electrode on at least one transparent back conductive layer; and forming a front electrode on at least one transparent front conductive layer.

[0012] The present invention also proposes a heterojunction solar cell, the solar cell comprising: a silicon substrate doped with a first conductivity type; at least one front passivation layer formed on the front side of the silicon substrate, which is made of an intrinsic amorphous silicon-based material; at least one front doped layer formed on the at least one front passivation layer; at least one back passivation layer formed on the back side of the silicon substrate, which is made of an intrinsic amorphous silicon-based material; at least one back doped layer formed on the at least one back passivation layer; wherein, in the front doped layer and the back doped layer, one doping type is a first conductivity type and the other doping type is a second conductivity type opposite to the first conductivity type; at least one transparent front conductive layer formed on the at least one front doped layer; at least one transparent back conductive layer formed on the at least one back doped layer; a front electrode formed on the at least one transparent front conductive layer; a back electrode formed on the at least one transparent back conductive layer; and at least one side edge passivation layer formed on the side edge of the heterojunction solar cell, in the edge region of the silicon substrate.

[0013] In a preferred embodiment, at least one front passivation layer and at least one back passivation layer are deposited on the front and back sides of the silicon substrate in the same deposition chain to form at least one side edge passivation layer on the side edge of the heterojunction solar cell.

[0014] In one preferred embodiment, a front passivation layer and a back passivation layer are deposited simultaneously to form the side edge passivation layer; or, a front passivation layer is deposited first, followed by a back passivation layer, to form the side edge passivation layer; or, a back passivation layer is deposited first, followed by a front passivation layer, to form the side edge passivation layer.

[0015] The present invention also proposes an apparatus for manufacturing heterojunction solar cells, the apparatus being used to deposit at least one front passivation layer and at least one back passivation layer on the front and back sides of a silicon substrate, respectively; to deposit at least one front doped layer on the at least one front passivation layer, and to deposit at least one back doped layer on the at least one back passivation layer; the apparatus having no more than three deposition chains, the apparatus comprising: a first deposition chain for depositing at least one front passivation layer and at least one back passivation layer on the front side of the silicon substrate; a second deposition chain for depositing at least one front doped layer on the front passivation layer; a third deposition chain for depositing at least one back doped layer on the back passivation layer; and a silicon substrate driving and flipping mechanism including between the second and third deposition chains.

[0016] In a preferred embodiment, the first deposition chain in the apparatus includes at least one process cavity that simultaneously deposits at least one front passivation layer and at least one back passivation layer on the front and back sides of the silicon substrate.

[0017] In a preferred embodiment, the first deposition chain in the device includes at least one first process chamber for depositing a front passivation layer and at least one second process chamber for depositing a back passivation layer, which are connected together.

[0018] In a preferred embodiment, the first process cavity is located upstream of the second process cavity in the carrier board transport direction; or, in the carrier board transport direction, the second process cavity is located upstream of the first process cavity.

[0019] Compared with the prior art, the significant advantages of this invention are:

[0020] (1) In the fabrication of the cell, the present invention deposits at least one front passivation layer and at least one back passivation layer on the front and back sides of the silicon substrate in the same deposition chain. Depositing the front passivation layer and the back passivation layer in the same deposition chain can avoid the formation of a natural oxide layer on the surface of the supporting silicon substrate and the previously deposited intrinsic layer, thereby avoiding affecting the performance of the solar cell.

[0021] (2) In the device described in this invention, the front intrinsic layer and the back intrinsic layer are deposited in the same deposition chain, which can reduce the number of wafer flipping times and simplify the device. Compared with the prior art, which deposits the intrinsic layer and the doped layer in the same deposition chain and reuses the carrier plate that carries the silicon wafer, this avoids the doped components attached to the carrier plate affecting the film quality of the passivation layer during the recycling process, thereby affecting the passivation effect.

[0022] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0023] Figure 1 is a schematic diagram of the solar cell structure shown in an embodiment of the present invention.

[0024] Figure 2 is a schematic diagram of a solar cell structure according to another embodiment of the present invention.

[0025] Figure 3 is a schematic diagram of a solar cell structure according to another embodiment of the present invention.

[0026] Figure 4 is a schematic diagram of one embodiment of the process cavity in the first deposition chain of the solar cell manufacturing equipment shown in the embodiment of the present invention.

[0027] Figure 5 is a schematic diagram of another embodiment of the process cavity in the first deposition chain of the solar cell manufacturing equipment shown in the embodiment of the present invention.

[0028] Figure 6 is a schematic diagram of another embodiment of the process cavity in the first deposition chain of the solar cell manufacturing equipment shown in the embodiment of the present invention.

[0029] Figure 7 is a schematic diagram of one embodiment of the process cavity in the second or third deposition chain of the solar cell manufacturing equipment shown in the embodiment of the present invention;

[0030] Explanation of reference numerals in the attached figures: 10-Silicon substrate; 11-Front-side passivation layer; 12-Front-side doped layer; 21-Back-side passivation layer; 22-Back-side doped layer; 30-Carrier plate; 31-Side edge passivation layer; 41-Process cavity; 411, 511-Upper plate electrode; 412, 512-Lower plate electrode; 413-Gas source; 414-RF power system; 416-Roller; 417-Pump; 51-First process cavity; 52-Second process cavity. Detailed Implementation

[0031] It is readily understood that, based on the technical solution of this invention, various embodiments of the invention can be conceived by those skilled in the art without altering the essential spirit of the invention. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative examples of the technical solution of this invention and should not be considered as the entirety of the invention or as limitations or restrictions on the technical solution of this invention. Rather, these embodiments are provided to enable those skilled in the art to gain a more thorough understanding of the invention. Preferred embodiments of the invention are described below in conjunction with the accompanying drawings, which form part of this application and, together with the embodiments of the invention, serve to illustrate the innovative concept of the invention.

[0032] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0033] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0034] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0035] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0036] This invention proposes a method for fabricating a heterojunction solar cell, the structure of which is shown in Figure 1. The heterojunction solar cell includes: a silicon substrate 10 doped with a first conductivity type; at least one front passivation layer 11, at least one front doped layer 12, at least one transparent front conductive layer, and at least one front electrode (not shown) located on the front side of the silicon substrate 10; at least one back passivation layer 21, at least one back doped layer 22, at least one transparent back conductive layer, and at least one back electrode (not shown) located on the back side of the silicon substrate 10; in the front doped layer 12 and the back doped layer 22, one doping type is the first conductivity type, and the other doping type is a second conductivity type opposite to the first conductivity type. Furthermore, at least one side edge passivation layer 31 is located on the side edge of the heterojunction solar cell, in the edge region of the silicon substrate 10. Thus, a side edge passivation layer 31 is formed on the edge region of the silicon substrate 10. The side edge passivation layer 31, the front passivation layer 11, and the back passivation layer 21 located on the side edge wrap around the silicon substrate 10, forming a good passivation protection effect for the sidewall of the battery.

[0037] It should be noted that the aforementioned front and back conductive layers and front and back electrodes are conventional structures of heterojunction solar cells, and will not be further explained here.

[0038] As a preferred embodiment, the front doped layer 12 and / or the back doped layer 22 are composed of microcrystalline silicon-based materials or nanocrystalline silicon-based materials. Compared with traditional amorphous silicon-based materials, microcrystalline silicon-based materials or nanocrystalline silicon-based materials have good light transmittance and excellent doping efficiency, which can improve the performance of heterojunction solar cells.

[0039] The fabrication of the heterojunction solar cell described in the foregoing embodiments includes the following steps: providing a silicon substrate 10 doped with a first conductivity type; forming at least one front passivation layer 11 and at least one back passivation layer 21 made of intrinsic amorphous silicon on the front and back sides of the silicon substrate 10, respectively; and forming at least one front doped layer 12 and at least one back doped layer 22 on the at least one front passivation layer 11 and the at least one back passivation layer 21, respectively. Based on the structure on the edge region of the silicon substrate 10 in the aforementioned heterojunction solar cell, the present invention allows for the deposition of at least one front passivation layer 11 and at least one back passivation layer 21 on the front and back sides of the silicon substrate 10 in the same deposition chain during cell fabrication. By depositing a front passivation layer 11 and a back passivation layer 21 in the same deposition chain, the formation of a natural oxide layer between the front and back passivation layers is avoided. Consequently, a side edge passivation layer 31 with better passivation effect is formed on the edge region of the silicon substrate 10, achieving a better passivation protection effect. At the same time, compared with the prior art of depositing passivation layers and doped layers in the same deposition chain and recycling the carrier plate that carries the silicon wafer, this avoids the impact of dopants attached to the carrier plate on the film quality of the passivation layer during the recycling process, which in turn affects the passivation effect and thus avoids affecting the performance of the solar cell.

[0040] When depositing the front passivation layer 11 and the back passivation layer 21 in the same depositional chain, the deposition order of the front passivation layer 11 and the back passivation layer 21 is not restricted. The front passivation layer 11 and the back passivation layer 21 can be deposited in the same depositional chain in the following different ways.

[0041] For example, as shown in Figure 1, a front passivation layer 11 and a back passivation layer 21 are deposited simultaneously to form the side edge passivation layer 31 on the edge region of the silicon substrate 10. This not only avoids the formation of a natural oxide layer between the front and back passivation layers due to the formation of the front and back passivation layers in different deposition chains in the prior art, but also improves the deposition efficiency.

[0042] For example, as shown in Figure 2, a back passivation layer 21 is deposited first, followed by a front passivation layer 11, to form the side edge passivation layer 31 on the edge region of the silicon substrate 10. In this case, the side edge passivation layer 31 is formed by stacking the back passivation layer 21 and the front passivation layer 11. Alternatively, as shown in Figure 3, the front passivation layer 11 can be deposited first, followed by a back passivation layer 21, to form the side edge passivation layer 31 on the edge region of the silicon substrate 10. In this case, the side edge passivation layer 31 is formed by stacking the front passivation layer 11 and the back passivation layer 21. Compared to depositing the front passivation layer 11 and the back passivation layer 21 simultaneously, depositing the front passivation layer 11 first, or the back passivation layer 21 first, can simplify the deposition equipment and reduce the complexity of the process while avoiding the formation of a natural oxide layer between the front and back passivation layers.

[0043] Of course, whether the front passivation layer 11 and the back passivation layer 21 are deposited simultaneously, or the front passivation layer 11 is deposited first, or the back passivation layer 21 is deposited first, in this invention, the front passivation layer 11 and the back passivation layer 21 are deposited in the same deposition chain, so as to avoid the formation of a natural oxide layer between the front and back passivation layers on the sidewall of the silicon substrate 10, and further improve the effect of the side edge passivation layer 31 on the passivation protection of the battery sidewall.

[0044] In this invention, the silicon substrate 10 is doped with a first conductivity type; in the front doped layer 12 and the back doped layer 22, one doping type is the first conductivity type, and the other doping type is a second conductivity type opposite to the first conductivity type. For example, the silicon substrate 10 is an N-type textured silicon wafer, the first conductivity type is N-type, and the second conductivity type is P-type. Alternatively, the silicon substrate 10 is a P-type textured silicon wafer, the first conductivity type is P-type, and the second conductivity type is N-type. That is, the heterojunction solar cell of this invention can be either a front-emitter solar cell or a back-emitter solar cell.

[0045] For the different heterojunction solar cell fabrication methods shown in the foregoing embodiments, preferably, the conductive layers and electrodes on the front and back sides of the silicon substrate 10 are formed in the following sequence: forming at least one transparent back conductive layer on at least one back doped layer 22; forming at least one transparent front conductive layer on at least one front doped layer 12; forming a back electrode on at least one transparent back conductive layer; and forming a front electrode on at least one transparent front conductive layer. During solar cell manufacturing, the substrate absorbs moisture from the air, and this moisture also provides oxygen during each deposition step. However, the incident light front side of the solar cell is sensitive to oxygen and requires high oxygen control. Therefore, this invention first deposits the conductive layer on the back side of the silicon substrate 10, and then deposits the conductive layer on the front side. This facilitates further control of moisture during the front side deposition process of the solar cell.

[0046] Based on various embodiments of the heterojunction solar cell fabrication method described above in this invention, heterojunction solar cells with the following structures can be prepared.

[0047] The solar cell includes: a silicon substrate 10 doped with a first conductivity type; at least one front passivation layer 11 formed on the front side of the silicon substrate 10, made of an intrinsic amorphous silicon-based material; at least one front doped layer 12 formed on the at least one front passivation layer 11; at least one back passivation layer 21 formed on the back side of the silicon substrate 10, made of an intrinsic amorphous silicon-based material; at least one back doped layer 22 formed on the at least one back passivation layer 21; wherein one of the front doped layer 12 and the back doped layer 22 is doped with a first conductivity type and the other is doped with a second conductivity type opposite to the first conductivity type; at least one transparent front conductive layer formed on the at least one front doped layer 12; at least one transparent back conductive layer formed on the at least one back doped layer 22; a front electrode formed on the at least one transparent front conductive layer; and a back electrode formed on the at least one transparent back conductive layer. Furthermore, on the side edge of the heterojunction solar cell, in the edge region of the silicon substrate 10, at least one side edge passivation layer 31, the side edge passivation layer 31 located on the side edge, and the front passivation layer 11 and the back passivation layer 21 wrap the silicon substrate 10, forming a good passivation protection effect for the sidewall of the cell.

[0048] It should be noted that the aforementioned front and back conductive layers and front and back electrodes are conventional structures of heterojunction solar cells, and will not be further explained here.

[0049] The present invention also proposes an apparatus for manufacturing heterojunction solar cells applicable to the aforementioned fabrication method and cell structure. The apparatus is used to deposit at least one front passivation layer 11 and at least one back passivation layer 21 on the front and back sides of a silicon substrate 10, respectively; to deposit at least one front doped layer 12 on the at least one front passivation layer 21, and to deposit at least one back doped layer 22 on the at least one back passivation layer 21. The apparatus has no more than three deposition chains, wherein a first deposition chain is used to deposit at least one front passivation layer 11 and at least one back passivation layer 21 on the front side of the silicon substrate 10; a second deposition chain is used to deposit at least one front doped layer 12 on the front passivation layer 11; a third deposition chain is used to deposit at least one back doped layer 23 on the back passivation layer 21; and a silicon substrate driving and flipping mechanism is included between the second and third deposition chains. Using this equipment, the front intrinsic layer and the back intrinsic layer are deposited in the same deposition chain, avoiding the formation of a natural oxide layer on the silicon wafer due to the deposition of the front passivation layer and the back passivation layer in different deposition chains, which would affect the passivation effect. At the same time, it can reduce the number of wafer flipping times and simplify the equipment.

[0050] Furthermore, since the front and back passivation layers are formed in the same deposition chain, only the front doped layer and the back doped layer need to be deposited in the second and third deposition chains. Compared with the prior art, which forms the front passivation layer and the front doped layer in one deposition chain, or forms the back passivation layer and the back doped layer in one deposition chain, in the recycling process of the carrier plate, the carrier plate carrying the silicon wafer substrate 10 is only used in the first deposition chain. There is no issue of the doping components attached to the carrier plate affecting the film quality of the passivation layer, thereby affecting the passivation effect and thus affecting the performance of the solar cell.

[0051] As a preferred approach, as shown in FIG4, the first deposition chain includes at least one process cavity 41 for simultaneously depositing at least one front passivation layer 11 and at least one back passivation layer 21 on both the front and back sides of the silicon substrate 10. The process cavity 41 includes an upper planar electrode 411 located above the carrier plate 30 and a lower planar electrode 412 located below the carrier plate 30, as well as a gas source 413, an RF power supply system 414, a roller 416, and a pump 417. That is, in the first deposition chain, the front passivation layer 11 and the back passivation layer 21 are deposited simultaneously in the same process cavity.

[0052] Alternatively, the first deposition chain includes at least one first process cavity 51 for depositing the front passivation layer 11 and at least one second process cavity 52 for depositing the back passivation layer 21, which are connected together. The first process cavity 51 includes an upper plate electrode 511 located above the carrier plate 30, and the second process cavity 52 includes a lower plate electrode 512 located below the carrier plate 30. In this case, the upstream and downstream positions of the first process cavity 51 and the second process cavity 52 can also be set differently depending on the situation. For example, as shown in FIG. 5, in the transport direction of the carrier plate 30, the first process cavity 51 is located upstream of the second process cavity 52. ​​In this case, both the first process cavity 51 and the second process cavity 52 include a gas source 413, an RF power supply system 414, a roller 416, and a pump 417. The difference is that the first process cavity 51 includes the upper plate electrode 511 located above the carrier plate 30, and the second process cavity 52 includes the lower plate electrode 512 located below the carrier plate 30. In this configuration, within the same deposition chain, a front passivation layer is deposited first in the first process cavity 51, followed by a back passivation layer 21 in the second process cavity 52. ​​Furthermore, as shown in FIG6, in the transport direction of the carrier 30, the first process cavity 51 is located downstream of the second process cavity 52. ​​Both the first and second process cavities 51 and 52 include a gas source 413, an RF power system 414, a roller 416, and a pump 417. The difference lies in that the second process cavity 52 includes a lower plate electrode 512 located below the carrier 30, while the first process cavity 51 includes an upper plate electrode 511 located above the carrier 30. In this configuration, within the same deposition chain, a back passivation layer 21 is deposited first in the second process cavity 52, followed by a front passivation layer in the first process cavity 51.

[0053] As another preferred approach, a second deposition chain is used to deposit at least one front-side doped layer 12 on the front-side passivation layer 11; a third deposition chain is used to deposit at least one back-side doped layer 22 on the back-side passivation layer 21, and a silicon substrate driving and flipping mechanism is provided between the second and third deposition chains. As shown in FIG. 7, the second and third deposition chains, in the transport direction of the carrier 30, are used to form at least one front-side doped layer 12 on the front-side passivation layer 11, or at least one back-side doped layer 22 on the back-side passivation layer 21.

[0054] In addition, it should be noted that the number of the first and second process cavities in the first deposition chain, as well as the number of doping process cavities in the second and third deposition chains, can be set according to the production cycle, such as one, two, or more than or equal to three, and the number is not further limited.

[0055] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

[0056] It should be understood that, in order to simplify the present invention and help those skilled in the art understand its various aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes described in a single embodiment or with reference to a single figure. However, the present invention should not be construed as including all features in the exemplary embodiments as essential technical features of the claims of this patent.

Claims

A method for fabricating a heterojunction solar cell. The heterojunction solar cell includes: A silicon substrate (10) doped with a first conductivity type, At least one front passivation layer (11), at least one front doped layer (12), at least one transparent front conductive layer, and at least one front electrode are located on the front side of the silicon substrate (10); At least one back passivation layer (21), at least one back doped layer (22), at least one transparent back conductive layer, and at least one back electrode are located on the back side of the silicon substrate (10). In the front doped layer (12) and the back doped layer (22), one of the doping types is a first conductivity type, and the other doping type is a second conductivity type opposite to the first conductivity type; The method is characterized by comprising the following steps: A silicon substrate (10) with doping of a first conductivity type is provided; In the same deposition chain, at least one front passivation layer (11) made of intrinsic amorphous silicon-based material and at least one back passivation layer (21) made of intrinsic amorphous silicon-based material are formed on the front and back sides of the silicon substrate (10), respectively. At least one front doped layer (12) and at least one back doped layer (22) are formed on the at least one front passivation layer (11) and the at least one back passivation layer (21), respectively. The method according to claim 1, characterized in that, The method enables the formation of at least one side edge passivation layer (31) on the side edge of the heterojunction solar cell. The method according to claim 2, characterized in that, Simultaneously deposit a front passivation layer (11) and a back passivation layer (21) to form the side edge passivation layer (31); or, First, deposit the front passivation layer (11), then deposit the back passivation layer (21) to form the side edge passivation layer (31); or, First, a back passivation layer (21) is deposited, followed by a front passivation layer (11) to form the side edge passivation layer (31). The method according to claim 1, characterized in that, The front doped layer (12) and / or the back doped layer (22) are composed of microcrystalline silicon-based material or nanocrystalline silicon-based material. The method according to claim 1, characterized in that, The silicon substrate (10) is an N-type textured silicon wafer, the first conductivity type is N-type, and the second conductivity type is P-type, or... The silicon substrate (10) is a P-type textured silicon wafer, with the first conductivity type being P-type and the second conductivity type being N-type. The method according to claim 1, characterized in that, The method further includes: At least one transparent back conductive layer is formed on at least one back doped layer (22); At least one transparent front conductive layer is formed on at least one front doped layer (12); A back electrode is formed on at least one transparent back conductive layer; A front electrode is formed on at least one transparent front conductive layer. A heterojunction solar cell, the solar cell comprising: A silicon substrate (10) doped with a first conductivity type; At least one front passivation layer (11) made of intrinsic amorphous silicon-based material is formed on the front side of the silicon substrate (10). At least one front-side doped layer (12) is formed on the at least one front-side passivation layer (11); At least one back passivation layer (21) made of intrinsic amorphous silicon-based material is formed on the back side of the silicon substrate (10); At least one back-side doped layer (22) is formed on the at least one back-side passivation layer (21); In the front doped layer (12) and the back doped layer (22), one of the doping types is a first conductivity type, and the other doping type is a second conductivity type opposite to the first conductivity type; At least one transparent front conductive layer is formed on at least one front doped layer (12); At least one transparent back conductive layer is formed on at least one back doped layer (22); A front electrode is formed on at least one transparent front conductive layer; A back electrode is formed on at least one transparent back conductive layer; At least one side edge passivation layer (31) is formed on the side edge of the heterojunction solar cell. The solar cell according to claim 7 is characterized in that, In the same deposition chain, at least one front passivation layer (11) and at least one back passivation layer (21) are deposited on the front and back sides of the silicon substrate (10) to form at least one side edge passivation layer (31) on the side edge of the heterojunction solar cell. The solar cell according to claim 8 is characterized in that, Simultaneously deposit a front passivation layer (11) and a back passivation layer (21) to form the side edge passivation layer (31); or, First, deposit the front passivation layer (11), then deposit the back passivation layer (21) to form the side edge passivation layer (31); or, First, a back passivation layer (21) is deposited, followed by a front passivation layer (11) to form the side edge passivation layer (31). The solar cell according to claim 7 is characterized in that, The front doped layer (12) and / or the back doped layer (22) are composed of microcrystalline silicon-based material or nanocrystalline silicon-based material. The solar cell according to claim 7 is characterized in that, The silicon substrate (10) is an N-type textured silicon wafer, the first conductivity type is N-type, and the second conductivity type is P-type; or, The silicon substrate (10) is a P-type textured silicon wafer, with the first conductivity type being P-type and the second conductivity type being N-type. An apparatus for manufacturing a heterojunction solar cell, the apparatus being used to deposit at least one front passivation layer (11) and at least one back passivation layer (21) on the front and back sides of a silicon substrate (10), respectively; to deposit at least one front doped layer (12) on the at least one front passivation layer (21) and at least one back doped layer (22) on the at least one back passivation layer (21). Its features are, The device has no more than three deposition chains, and the device includes: The first deposition chain is used to deposit at least one front passivation layer (11) and at least one back passivation layer (21) on the front side of the silicon substrate (10); The second deposition chain is used to deposit at least one front doped layer (12) on the front passivation layer (11); The third deposition chain is used to deposit at least one back-side doped layer (22) on the back-side passivation layer (21); And a silicon substrate drive and flipping mechanism included between the second and third deposition chains. The device according to claim 12 is characterized in that, The first deposition chain includes at least one process cavity (41) that simultaneously deposits at least one front passivation layer (11) and at least one back passivation layer (21) on the front and back sides of the silicon substrate (10). The device according to claim 12 is characterized in that, The first deposition chain includes at least one first process chamber (51) for depositing a front passivation layer (11) and at least one second process chamber (52) for depositing a back passivation layer (21) connected together. The device according to claim 14, characterized in that, In the carrier plate transport direction, the first process cavity (51) is located upstream of the second process cavity (52); or, In the carrier transfer direction, the second process cavity (52) is located upstream of the first process cavity (51).

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