Reference counting method and related apparatus
By establishing multiple counters for each CPU core in the storage space, the problem of frequent cache line invalidation caused by reference counting was solved, the speed of Pin/Unpin operations on multi-core CPUs was improved, and system performance was enhanced.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2025-06-23
- Publication Date
- 2026-06-04
Smart Images
Figure CN2025102737_04062026_PF_FP_ABST
Abstract
Description
A reference counting method and related apparatus
[0001] This application claims priority to Chinese Patent Application No. 202411750962.9, filed with the State Intellectual Property Office of China on November 30, 2024, entitled “A Reference Counting Method and Related Apparatus”, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of resource management technology, and in particular to a reference counting method and related apparatus. Background Technology
[0003] Reference counting is a management method for shared resources (such as memory) in computers. It determines whether a resource is still in use by tracking its references (or the number of references). This method has been applied in various scenarios, including pin / unpin operations in database buffer pools and garbage collection in the Java Virtual Machine. Reference counting allows multiple readers to access the same shared resource simultaneously, but writers can only access it if the reference count is 0. This method ensures that multiple readers can access the same shared resource at the same time, while preventing simultaneous access by both readers and writers. It increases the concurrency of the entire system while maintaining correctness, thereby improving performance.
[0004] The underlying implementation of reference counting methods typically uses an atomic variable. The increment operation is performed atomically when the reference count is incremented, and the decrement operation is performed atomically when the reference count is decremented. In database resource management, pin / unpin operations in high-concurrency scenarios cause the atomic variable to continuously switch between the corresponding caches of multiple cores of the Central Processing Unit (CPU). Each switch of the atomic variable involves a cache loading process and incurs synchronization overhead on the corresponding cache line.
[0005] Therefore, how to provide a reference counting method that avoids frequent loading of memory data and improves the speed of Pin / Unpin on multi-core CPUs is a technical problem that urgently needs to be solved in this field. Summary of the Invention
[0006] This application provides a reference counting method and related apparatus to improve the speed of Pin / Unpin on a multi-core CPU, thereby improving the overall system performance.
[0007] The first aspect of this application provides a reference counting method, including:
[0008] Obtain a free target data block from the storage space;
[0009] Multiple counters are established in the target data block, and the number of counters corresponds to the grouping of multiple cores of the central processing unit (CPU).
[0010] In response to a Pin / Unpin operation performed on a target data block, the target core corresponding to the Pin / Unpin operation is determined, and the target core belongs to multiple cores;
[0011] The target counter is determined based on the target core, and the target counter belongs to multiple counters;
[0012] The reference count corresponding to the Pin / Unpin operation is performed using the target counter.
[0013] In this embodiment, by establishing multiple counters corresponding to multiple CPU cores in the data block of the storage space, each reference count corresponds to a set of counters instead of an atomic variable. The Pin / Unpin operation only increments / decrements the counter corresponding to the CPU core where the current thread is located, which greatly reduces the number of cache line invalidations caused by reference counting operations, thereby avoiding the throughput reduction problem caused by frequent loading of memory data and improving the overall performance of the system.
[0014] In one possible implementation, after establishing multiple counters in the target data block, the method further includes:
[0015] The sum of the counts of multiple counters in the target data block is detected to obtain the total value;
[0016] If the total value is 0, the target data block is determined to be a discardable data block.
[0017] In this embodiment of the application, when detecting whether a certain data block is allowed to be eliminated, it is necessary to add up the count values of all the different group number counters corresponding to the same data block, and determine whether it can be eliminated by whether the result is 0.
[0018] In one possible implementation, after determining the free target data block in the storage space, the method further includes:
[0019] Create a lock in the target data block;
[0020] If the total value is 0, the target data block is determined to be a data block that can be evicted, specifically including:
[0021] If the total value is 0, then the target data block is locked using a locker.
[0022] The sum of the counts of multiple counters in the target data block is checked again to obtain the total value of the re-check;
[0023] If the total value of the re-inspection is 0, the target data block is determined to be a discardable data block.
[0024] In this embodiment, in addition to the counter, the data block also includes a lock, which requires exclusive access to the cache line. During the process of determining whether a target cache line can be evicted, a secondary check is required to ensure that the current data block is definitely a free data block and that the currently accessed buffer will not be evicted.
[0025] In one possible implementation, in response to a Pin / Unpin operation performed on a target data block, the target core corresponding to the Pin / Unpin operation is determined, specifically including:
[0026] In response to a Pin / Unpin operation on the target data block, determine whether the target data block is locked;
[0027] If it is not locked, then the target core corresponding to the Pin / Unpin operation is determined.
[0028] In this embodiment of the application, when a lock is established, before performing a Pin / Unpin operation on the target data block, it is necessary to first determine whether the target data block is locked. If it is locked, the operation cannot be performed; if it is not locked, subsequent steps can be performed.
[0029] In one possible implementation, the storage space includes multiple data blocks, and the target data block belongs to multiple data blocks;
[0030] The data number of the target data block in the storage space corresponds to the first index of multiple counters;
[0031] The group numbers of multiple cores correspond to the second subscripts of multiple counters;
[0032] Based on the target core, the corresponding target counter is determined, specifically including:
[0033] The value of the first index is determined by the buffer number of the target data block;
[0034] The value of the second subscript is determined by the group number of the target core;
[0035] The target counter is determined based on the value of the first target and the value of the second subscript.
[0036] In this embodiment of the application, the data block number and the corresponding core group number can be used as two dimensions to determine the counter. Based on these two numbers, the target counter can be located relatively easily.
[0037] In one possible implementation, the target core corresponding to the Pin / Unpin operation is determined, specifically including:
[0038] The target core is identified using the restartable sequence RSEQ.
[0039] In this embodiment of the application, the CPU core ID can be obtained in the range of ~1ns through a restartable sequence.
[0040] A second aspect of this application provides a reference counting device, comprising:
[0041] The acquisition module is used to acquire free target data blocks in the storage space;
[0042] The module is used to establish multiple counters in the target data block, with the number of counters corresponding to the grouping of multiple CPU cores;
[0043] The positioning module is used to respond to the Pin / Unpin operation performed on the target data block, and to determine the target core corresponding to the Pin / Unpin operation. The target core belongs to multiple cores.
[0044] The determination module is used to determine the corresponding target counter based on the target core. The target counter belongs to multiple counters.
[0045] The counting module is used to perform reference counting corresponding to Pin / Unpin operations via a target counter.
[0046] One possible implementation also includes:
[0047] The elimination module is used to detect the sum of the count values of multiple counters of the target data block and obtain the total value; if the total value is 0, the target data block is determined to be an elimination data block.
[0048] In one possible implementation, the module is also used to create a lock in the target data block;
[0049] The elimination module is specifically used to lock the target data block by means of a locker if the total value is 0; to check the sum of the count values of multiple counters of the target data block again to obtain the re-check total value; if the re-check total value is 0, the target data block is determined as a data block that can be eliminated.
[0050] In one possible implementation, the positioning module is specifically used to determine whether the target data block is locked in response to a Pin / Unpin operation performed on the target data block; if it is not locked, the target core corresponding to the Pin / Unpin operation is determined.
[0051] In one possible implementation, the storage space includes multiple data blocks, and the target data block belongs to multiple data blocks; the buffer number of the target data block in the storage space corresponds to the first index of multiple counters; the group numbers of multiple cores correspond to the second index of multiple counters respectively;
[0052] The determination module is specifically used to determine the value of the first index by using the buffer number of the target data block; determine the value of the second index by using the group number of the target core; and determine the target counter based on the value of the first target and the value of the second index.
[0053] A third aspect of this application provides a computing device, including a processor;
[0054] The processor is used to execute computer programs or computer instructions in memory to perform the methods described in the first aspect above.
[0055] In one possible implementation, memory is also included.
[0056] The fourth aspect of this application provides a computer program product containing instructions that, when executed on a computer, cause the computer to perform the implementation as described in the first aspect.
[0057] The fifth aspect of this application provides a computer-readable storage medium including computer instructions that, when executed on a computer, cause the computer to perform the implementation as described in the first aspect.
[0058] The beneficial effects of the technical solutions provided in the second to fifth aspects above can be referred to the beneficial effects of the technical solutions in the first aspect, and will not be repeated here. Attached Figure Description
[0059] Figure 1 is a flowchart of the reference counting method provided in an embodiment of this application;
[0060] Figure 2 is a schematic diagram of the CPU cache hierarchy;
[0061] Figure 3 is a schematic diagram of the underlying memory structure of the counter in the reference counting method provided in the embodiments of this application;
[0062] Figure 4 is a supplementary method flowchart of the reference counting method provided in the embodiments of this application;
[0063] Figure 5 is a flowchart of the reference counting method provided in an embodiment of this application;
[0064] Figure 6 is a schematic diagram of the reference counting device provided in an embodiment of this application;
[0065] Figure 7 is a schematic diagram of the structure of the computing device provided in the embodiment of this application. Detailed Implementation
[0066] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
[0067] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps appearing in this application does not imply that the steps in the method flow must be performed in the chronological / logical order indicated by the naming or numbering. The execution order of named or numbered process steps can be changed according to the desired technical purpose, as long as the same or similar technical effect is achieved. The division of units in this application is a logical division. In practical applications, there may be other division methods. For example, multiple units may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the shown or discussed mutual coupling, direct coupling, or communication connection may be through some interface, and the indirect coupling or communication connection between units may be electrical or other similar forms, none of which are limited in this application. Furthermore, the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed among multiple circuit units. Some or all of the units can be selected to achieve the purpose of the solution in this application according to actual needs.
[0068] In concurrent systems, when accessing the same shared resource, if the access does not modify the content of the shared resource, the user is called a reader; otherwise, they are called a writer. Atomic variables are a mechanism in computers for concurrent access. Atomic variables support a series of atomic operations, such as atomic addition, atomic subtraction, and compare-and-swap (CAS). Atomic operations ensure that multiple concurrent operations do not interfere with each other due to mechanisms such as caching and CPU registers, guaranteeing the correctness of atomic variable data.
[0069] Reference counting is a management method for shared resources (such as memory) in computers. It determines whether a resource is still in use by tracking its references (or the number of references). This method has been applied in various scenarios, including pin / unpin operations in database buffer pools and garbage collection in the Java Virtual Machine. Reference counting allows multiple readers to access the same shared resource simultaneously, but writers can only access it if the reference count is 0. This method ensures that multiple readers can access the same shared resource at the same time, while preventing simultaneous access by both readers and writers. It increases the concurrency of the entire system while maintaining correctness, thereby improving performance.
[0070] Computer caches are managed in units of cache lines. On modern CPUs, a cache line is typically 64 or 128 bytes. Each time the CPU reads data from memory, even if the required data is only 1 bit, it must read at least the size of a cache line. Operations on atomic variables also need to be performed in units of cache lines. When two atomic variables reside in the same cache line, due to cache coherency protocols, even if they are completely unrelated, performing atomic operations requires each cache line to be exclusively used. The operation on one atomic variable must be completed first, followed by the operation on the other. In other words, multi-threaded concurrent operations on them are equivalent to single-threaded operations, thus reducing system concurrency and performance. This phenomenon is commonly referred to as false sharing.
[0071] The underlying implementation of reference counting methods typically uses an atomic variable. Incrementing the reference count by one is performed atomically, and decrementing it by one is performed atomically. Since reference counting is generally used in high-concurrency scenarios, to avoid false sharing issues, each atomic variable used for reference counting needs to occupy its own cache line.
[0072] Taking a database scenario as an example, the buffer pool is a module in the database used to accelerate access to disk data. It consists of multiple buffers. Each buffer is generally the same size. When accessing disk data, a free buffer needs to be allocated from the buffer pool first, and the data is loaded from the disk into that buffer before being accessed through the buffer.
[0073] When the amount of data accessed exceeds the memory space, the buffer pool needs to evict buffers and reallocate unused buffers. Pin / Unpin operations are used to confirm whether a buffer is in use. The pin operation increments the reference count of the buffer, and the unpin operation decrements the reference count. Only buffers with a reference count of 0 can be evicted, ensuring the correctness of the buffer pool.
[0074] In database buffer pool management, even without the false sharing problem, Pin / Unpin operations can become a bottleneck in high-concurrency scenarios. The fundamental reason is that atomic operations cause atomic variables to switch continuously between multiple CPU caches. Each switch of an atomic variable involves a cache loading process and incurs synchronization overhead on the corresponding cache line.
[0075] For example, modern CPUs are much faster at computing than they are at loading data from memory. To mitigate the impact of this, the CPU doesn't directly read data from memory. Instead, it first reads the data from memory into the CPU's cache and then interacts with the cache. This leverages the principle of data locality, meaning that data adjacent to currently accessed data is more likely to be accessed in the future. Faster caches are more expensive. To reduce costs, modern CPUs typically maintain three levels of cache: L1, L2, and L3. L1 is the fastest, usually dedicated to one core per CPU core; L3 is the slowest, typically shared by all CPUs. Typical data shows that L1 cache access speed is ~1ns, L2 ~3ns, L3 ~10ns, and memory access speed is ~100ns. Under high concurrency, if a CPU core needs to load a failed cache line into L1, it requires a read from L2 / L3, which can result in a performance difference of up to 10 times.
[0076] Therefore, how to provide a reference counting method that avoids frequent loading of memory data and improves the speed of Pin / Unpin on multi-core CPUs is a technical problem that urgently needs to be solved in this field.
[0077] To address the aforementioned issues, this application provides a reference counting method and related apparatus. By establishing multiple counters corresponding to multiple CPU cores in the data blocks of the storage space, each reference count corresponds to a set of counters rather than an atomic variable. The Pin / Unpin operation only increments / decrements the counter corresponding to the CPU core where the current thread resides, significantly reducing the number of cache line misses caused by reference counting operations. This avoids the throughput reduction problem caused by frequent loading of memory data and improves the overall system performance.
[0078] The reference counting method provided in the embodiments of this application will be described below. Please refer to Figure 1, which is a flowchart of the reference counting method provided in the embodiments of this application, including:
[0079] 101. Obtain a free target data block in the storage space.
[0080] It is understood that, in the embodiments of this application, storage space refers to an area composed of a series of data blocks. In a database scenario, storage space corresponds to a buffer pool, and data blocks correspond to each buffer in the buffer pool; in a Java Virtual Machine garbage collection scenario, storage space corresponds to allocated memory, and data blocks correspond to single-allocation memory within the allocated memory.
[0081] Taking a buffer pool as an example, when accessing hard disk data, a free buffer needs to be allocated from the buffer pool first, and the data needs to be loaded from the hard disk into the buffer before accessing it through the buffer. In this embodiment, a free buffer needs to be obtained first and determined as the target buffer.
[0082] 102. Establish multiple counters in the target data block, with the number of counters corresponding to the grouping of multiple CPU cores.
[0083] In this embodiment of the application, after determining the target data block, multiple counters are established in the target data block, and the number of counters corresponds to the grouping of multiple cores of the CPU.
[0084] For example, please refer to Figure 2, which is a schematic diagram of the CPU cache hierarchy.
[0085] CPU cache levels typically include L1, L2, and L3. In the L1 level, CPU cores are grouped one CPU core per group. In the L2 and L3 levels, multiple CPU cores are grouped together.
[0086] The number of counters corresponds to the grouping of CPU cores. Specifically, the number of counters can be the same as the number of CPU cores; for example, if there are 128 CPU cores, the number of counters for each data block in the storage space is also 128. In memory-sensitive scenarios, CPU cores sharing the same L2 or L3 cache can be grouped together, meaning the number of CPU cores is 128. At the L2 level, if two CPU cores share the same L2 cache, meaning the CPU cores are divided into 64 groups, then the number of counters is 64. Similarly, in more memory-sensitive scenarios, if four CPU cores share the same L3 cache, then the number of counters is 32. In other words, by sacrificing some computation time for memory space, a balance between time and space can be achieved.
[0087] It is understandable that the rules for establishing counters are only introduced based on target data blocks. It is also understandable that all data blocks in the storage space can be target data blocks. In other words, the counters in each data block should also be created according to the same rules. Taking one counter corresponding to one CPU core as an example, each data block includes multiple counters corresponding to multiple CPU cores. That is, one CPU core has a corresponding counter in each data block.
[0088] Please refer to Figure 3, which is a schematic diagram of the underlying memory structure of the counter in the reference counting method provided in the embodiment of this application.
[0089] Taking data blocks as buffers as an example, as shown in Figure 3, buf 1counter refers to the counter in buffer number 1, and buf 2counter refers to the counter in buffer number 2. Group refers to the CPU core group number. It can be understood that each buffer includes a counter corresponding to the CPU core group. For ease of subsequent description, the counters corresponding to the same CPU core group are defined as a group.
[0090] 103. In response to a Pin / Unpin operation performed on a target data block, determine the target core corresponding to the Pin / Unpin operation, where the target core belongs to multiple cores.
[0091] Based on the counter creation rules provided in step 102 above, when performing Pin / Unpin operations on data blocks, since each counter corresponds to a different CPU core, it is necessary to determine the target core corresponding to the Pin / Unpin operation in order to facilitate subsequent counting operations.
[0092] 104. Determine the corresponding target counter based on the target core; the target counter belongs to multiple counters.
[0093] Once the target core is identified, the corresponding target counter can be determined based on the group to which the target core belongs. When the number of counters matches the number of CPU cores, the core number can be used as the counter index, and the target counter can be determined using the target core number.
[0094] In one possible implementation, the storage space includes multiple data blocks, and the target data block belongs to multiple data blocks;
[0095] The buffer number of the target data block in the storage space corresponds to the first index of multiple counters;
[0096] The group numbers of multiple cores correspond to the second subscripts of multiple counters;
[0097] At this point, step 104 specifically includes:
[0098] 1041. Determine the value of the first index by the data number of the target data block;
[0099] 1042. Determine the value of the second subscript by using the group number of the target core;
[0100] 1043. Determine the target counter based on the value of the first target and the value of the second subscript.
[0101] It is understandable that the storage space consists of multiple data blocks, and the target data block belongs to the storage space; therefore, the target data block is one of these multiple data blocks. The data number of each data block in the storage space, i.e., when the data block is a buffer, is the buffer ID. The memory structure of the counters is shown in Figure 3. That is, each data block includes multiple counters corresponding to the number of core groups. Therefore, the buffer ID can be used as the first index of the counter, and the first index of counters within the same data block is consistent. Similarly, the number of counters in each group is the same as the number of data blocks, so the core group number can be used as the second index of the counter, and the second index of counters within the same group is consistent.
[0102] When the number of counters and CPU cores are the same, the CPU core ID (i.e., the core number of the CPU core) can be used as the second index of the counter. When performing Pin / Unpin operations on the target data block, the CPU core ID (i.e., the number of the CPU core where the current thread is located) can be obtained first, and used together with the data number of the target data block as an index to retrieve the target counter from the two-dimensional array shown in Figure 3.
[0103] It is understandable that the CPU ID needs to be obtained every time a pin / unpin is performed, making its efficiency crucial. If obtaining the CPU core ID takes too long, exceeding the impact of cache migration, then the method provided in this embodiment will be meaningless. Therefore, this application provides several methods for obtaining the CPU core ID, including:
[0104] Obtain the target kernel ID through the getcpu() function: The specific implementation of this function depends on the environment. It may be in the form of a system call, in which case its time consumption is on the order of ~100ns; in some environments, it may be implemented through vdso.
[0105] By modifying the kernel or eBPF, the target kernel ID is exposed to a specified address during thread scheduling.
[0106] In a preferred method, the target core ID is determined by Restartable Sequences (RSEQ): RSEQ is a feature supported by Linux since version 4.18, which can obtain the CPU core ID in the order of ~1ns.
[0107] 105. Perform reference counting corresponding to Pin / Unpin operations using the target counter.
[0108] Understandably, once the target counter is determined, a reference count corresponding to the Pin / Unpin operation can be performed on the target counter, that is, the corresponding atomic increment or atomic decrement can be performed.
[0109] The reference counting method provided in this application, by grouping counters corresponding to the same CPU core group in the storage space, eliminates the need for exclusive cache lines between counters with the same group number. Compared to traditional solutions, it can be simply understood that in traditional solutions, there is only one group of counters in the storage space, while in this application embodiment, the number of groups increases to the number of CPU core groups. However, it should be noted that the memory usage in the method provided in this application embodiment does not balloon to an unacceptable level because the memory structure of the counters in this application embodiment is more compact, and multiple counters in the same group do not need to occupy exclusive cache lines.
[0110] For example, assuming the counter occupies 2 bytes, the cache line is 64 bytes, and the CPU core count is 128, the corresponding counter count is also 128. Therefore, the memory usage in the method provided in this embodiment is actually 128 / (64 / 2) = 4 times that of the traditional scheme, not the intuitively 128 times. Thus, the reference counting method provided in this embodiment can significantly reduce the number of cache line misses caused by reference counting operations, thereby avoiding the throughput decrease problem caused by frequent loading of memory data.
[0111] It is understood that idle data blocks can be evicted and reclaimed to storage space. Based on this, this application embodiment further supplements the data block eviction process based on steps 101 to 105 corresponding to the embodiment shown in Figure 1.
[0112] Please refer to Figure 4, which is a supplementary method flowchart of the reference counting method provided in the embodiments of this application, including:
[0113] 401. Detect the sum of the count values of multiple counters in the target data block to obtain the total value;
[0114] 402. If the total value is 0, then the target data block is determined as a discardable data block.
[0115] Understandably, when checking whether a data block is eligible for eviction, the counts of all group counters corresponding to the same data block need to be summed, and the result is used to determine whether eviction is possible. It's also understandable that thread scheduling might occur between Pin and Unpin, causing an increment operation on one counter while a decrement operation on the other, leading to non-zero counters or overflows, but this doesn't compromise correctness. For example, if core 1 accesses a data block and a Pin operation is performed on its corresponding counter 1, and then thread scheduling occurs, moving from core 1 to core 2 and ending the access, an Unpin operation will be performed on the corresponding counter 2 on core 2, causing its value to decrement. Since counters 1 and 2 are on the same data block, their sum will still be 0, preventing any issues with correctness. When eviction of the data block is required, the counters of all groups for that data block need to be traversed and summed. Therefore, regardless of thread scheduling, the total sum will always be 0. Overflow also doesn't require additional handling. Assuming the counter is 2 bytes, the overflow result is a congruence class in the sense of mod 65536, and the final sum is congruent to 0, so it is still 0.
[0116] In one possible implementation, to ensure the correctness of the elimination, after step 101 corresponding to Figure 1, the following is also included:
[0117] Establish a lock in the target data block;
[0118] Correspondingly, step 402 specifically includes:
[0119] 4021. If the total value is 0, then the target data block is locked by the locking device;
[0120] 4022. The sum of the count values of the plurality of counters of the target data block is detected again to obtain the total value of the re-inspection;
[0121] 4023. If the total value of the re-inspection is 0, then the target data block is determined as a data block that can be eliminated.
[0122] In this embodiment of the application, in addition to the counter, the data block also includes a lock, which needs to exclusively occupy the cache line.
[0123] In determining whether a target cache line can be evicted, a secondary check is required. Specifically: if the first check determines it cannot be evicted (total value greater than 0), the check process can end directly; if the first check determines it can be evicted (total value is 0), the data block needs to be locked to ensure that no further pin operations will be performed afterward; to avoid pin operations occurring during the period between the first check and locking, a second check is performed to obtain the total value of the second check in the current state. It's understandable that since the total values of the counters are both 0, and the target data block is locked, the counter value is guaranteed not to change, thus ensuring that the current data block is definitely a free data block, and the currently accessed buffer will definitely not be evicted.
[0124] In one possible implementation, step 103 corresponding to Figure 1 specifically includes:
[0125] 1031. In response to a Pin / Unpin operation performed on the target data block, determine whether the target data block is locked;
[0126] 1032. If not locked, determine the target core corresponding to the Pin / Unpin operation.
[0127] Understandably, when a lock is established, before a Pin / Unpin operation can be performed on the target data block, it is necessary to first determine whether the target data block is locked. If it is locked, the operation cannot be performed; if it is not locked, subsequent steps can be performed.
[0128] In most cases, Pin / Unpin will not trigger cache migration without replacement. The shared resources accessed by Pin / Unpin include locks and their corresponding counters. Since no replacement is triggered, the state of the locks remains unchanged, and therefore their cache in L1 will not be invalidated. When the number of counters corresponds to the number of cores, when retrieving the target counter, because the CPU core ID is used as the index, counters from different groups will be cached in the L1 cache of different cores, without migration or cross-core access. Therefore, Pin / Unpin operations can be completed in L1 without triggering cache migration. It is understandable that even if cache replacement generates a large amount of cache migration, the access speed of secondary storage is relatively slow, and the bottleneck during replacement is mainly in input / output (IO). Therefore, the impact of cache migration is relatively small, and in actual testing, it can still bring performance improvements.
[0129] Please refer to Figure 5, which is a flowchart of the reference counting method provided in an embodiment of this application, including:
[0130] 501. Obtain a free target data block in the storage space;
[0131] 502. Establish a lock and multiple counters in the target data block, with the number of counters corresponding to the grouping of multiple cores of the central processing unit (CPU).
[0132] 503. In response to a Pin / Unpin operation on the target data block, determine whether the target data block is locked;
[0133] 504. If not locked, determine the target core corresponding to the Pin / Unpin operation;
[0134] 505. Determine the corresponding target counter based on the target core; the target counter belongs to multiple counters.
[0135] 506. Perform reference counting corresponding to Pin / Unpin operations using the target counter;
[0136] 507. Detect the sum of the count values of multiple counters in the target data block and obtain the total value;
[0137] 508. If the total value is 0, then the target data block is locked using a locker.
[0138] 509. Detect the sum of the count values of multiple counters in the target data block again to obtain the total retest value;
[0139] 510. If the total value of the re-inspection is 0, then the target data block is determined as a data block that can be discarded;
[0140] 511. Release the obsolete data blocks to the storage space.
[0141] It is understood that steps 501 to 510 combine the key contents of the corresponding embodiments in Figures 1 and 4, and the relevant descriptions can be found above, so they will not be repeated here. In this embodiment of the application, a batch eviction method can be used to share all data blocks of a cache line at once, reducing the impact of large-scale cache migration during eviction.
[0142] The reference counting method provided in this application uses multiple counters as the underlying structure of reference counting in the data block. This solves the problem that reference counting modifications cause the underlying atomic variables to switch frequently between different cache lines, becoming a performance bottleneck. This ensures that Pin / Unpin will not cause cache line invalidation and avoids concurrent programs from degenerating into serial execution. At the same time, the method of secondary detection and batch eviction alleviates the cache line invalidation caused by eviction and does not lead to new performance bottlenecks in the entire system.
[0143] In summary, the method provided in this application embodiment can effectively improve the speed of Pin / Unpin on multi-core CPUs, eliminate bottlenecks, and ultimately improve overall performance. It also has good compatibility with the operating system's thread scheduling. When the kernel version supports it, there is no need to modify, adapt, or bind the kernel, and it will not lead to a decrease in multi-core performance.
[0144] This application also provides a reference counting device. Please refer to Figure 6, which is a schematic diagram of the structure of the reference counting device provided in this application, including:
[0145] The acquisition module 601 is used to acquire free target data blocks in the storage space;
[0146] Module 602 is used to establish multiple counters in the target data block, the number of which corresponds to the grouping of multiple CPU cores;
[0147] The positioning module 603 is used to respond to the Pin / Unpin operation performed on the target data block, and to determine the target core corresponding to the Pin / Unpin operation, wherein the target core belongs to multiple cores;
[0148] The determination module 604 is used to determine the corresponding target counter based on the target core. The target counter belongs to multiple counters.
[0149] The counting module 605 is used to perform reference counting corresponding to Pin / Unpin operations via a target counter.
[0150] The reference counting device provided in this application establishes multiple counters in the data blocks of the storage space corresponding to multiple CPU cores, so that each reference count corresponds to a set of counters instead of an atomic variable. The Pin / Unpin operation only adds / subtracts the counter corresponding to the CPU core where the current thread is located, which greatly reduces the number of cache line invalidations caused by reference counting operations, thereby avoiding the problem of decreased throughput caused by frequent loading of memory data and improving the overall performance of the system.
[0151] One possible implementation also includes:
[0152] The elimination module 606 is used to detect the sum of the count values of multiple counters of the target data block and obtain the total value; if the total value is 0, the target data block is determined as an elimination data block.
[0153] In one possible implementation, module 602 is also used to establish a lock in the target data block;
[0154] The elimination module 606 is specifically used to lock the target data block through a locker if the total value is 0; to detect the sum of the count values of multiple counters of the target data block again to obtain the re-inspection total value; if the re-inspection total value is 0, the target data block is determined as an elimination data block.
[0155] In one possible implementation, the positioning module 603 is specifically used to determine whether the target data block is locked in response to a Pin / Unpin operation performed on the target data block; if it is not locked, the target core corresponding to the Pin / Unpin operation is determined.
[0156] In one possible implementation, the storage space includes multiple data blocks, and the target data block belongs to multiple data blocks; the buffer number of the target data block in the storage space corresponds to the first index of multiple counters; the group numbers of multiple cores correspond to the second index of multiple counters respectively;
[0157] The determination module 604 is specifically used to determine the value of the first index by the buffer number of the target data block; determine the value of the second index by the group number of the target core; and determine the target counter based on the value of the first target and the value of the second index.
[0158] In one possible implementation, the positioning module 603 is specifically used to determine the target core via a restartable sequence RSEQ.
[0159] It is understood that the reference counting device provided in this application corresponds to the reference counting method corresponding to Figures 1, 4 and 5 above. Please refer to the above description for relevant details, which will not be repeated here.
[0160] This application also provides a computing device. Please refer to Figure 7, which is a schematic diagram of the structure of the computing device provided in an embodiment of this application. The computing device can be used to execute computer programs or computer instructions stored in memory to perform the methods shown in the embodiments of Figures 1, 4, and 5. Refer to the relevant descriptions in the above method embodiments.
[0161] The computing device includes a processor 1101. Optionally, the computing device may also include a memory 1102 and a transceiver 1103.
[0162] This application also provides a computer program product including instructions that, when run on a computer, cause the computer to perform the methods of the embodiments shown in Figures 1, 4 and 5 above.
[0163] This application also provides a computer-readable storage medium including computer instructions that, when executed on a computer, cause the computer to perform the methods of the embodiments shown in Figures 1, 4, and 5 above.
[0164] This application also provides a chip device, including a processor for connection to a memory, and for calling a program stored in the memory so that the processor executes the method of the embodiments shown in FIG1, FIG4 and FIG5 above.
[0165] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of a program for controlling the methods of the embodiments shown in Figures 1, 4, and 5. The memory mentioned above can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).
[0166] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0167] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.
[0168] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0169] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0170] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
Claims
A reference counting method, characterized in that, include: Obtain a free target data block from the storage space; Multiple counters are established in the target data block, and the number of the multiple counters corresponds to the grouping of multiple cores of the central processing unit (CPU). In response to a Pin / Unpin operation performed on the target data block, the target core corresponding to the Pin / Unpin operation is determined, and the target core belongs to the plurality of cores; Based on the target core, a corresponding target counter is determined, and the target counter belongs to the plurality of counters; The target counter is used to perform a reference count corresponding to the Pin / Unpin operation. The method according to claim 1, characterized in that, After establishing multiple counters in the target data block, the method further includes: The sum of the count values of the plurality of counters of the target data block is detected to obtain a total value; If the total value is 0, then the target data block is determined to be a discardable data block. The method according to claim 2, characterized in that, After determining the free target data block in the storage space, the method further includes: Establish a lock in the target data block; If the total value is 0, then the target data block is determined as a data block that can be discarded, specifically including: If the total value is 0, then the target data block is locked by the locker; The sum of the count values of the multiple counters of the target data block is detected again to obtain the total value of the re-inspection; If the total value of the re-inspection is 0, then the target data block is determined as a data block that can be eliminated. The method according to claim 3, characterized in that, The step of determining the target core corresponding to the Pin / Unpin operation in response to the target data block specifically includes: In response to a Pin / Unpin operation performed on the target data block, determine whether the target data block is locked; If it is not locked, then the target core corresponding to the Pin / Unpin operation is determined. The method according to any one of claims 1 to 4, characterized in that, The storage space includes multiple data blocks, and the target data block belongs to the multiple data blocks; The data number of the target data block in the storage space corresponds to the first index of the plurality of counters; The group numbers of the multiple cores respectively correspond to the second subscripts of the multiple counters; The step of determining the corresponding target counter based on the target core specifically includes: The value of the first index is determined by the buffer number of the target data block; The value of the second subscript is determined by the group number of the target core; The target counter is determined based on the value of the first target and the value of the second subscript. The method according to any one of claims 1 to 5, characterized in that, The determination of the target core corresponding to the Pin / Unpin operation specifically includes: The target core is determined by the restartable sequence RSEQ. A reference counting device, characterized in that, include: The acquisition module is used to acquire free target data blocks in the storage space; A module is established to establish multiple counters in the target data block, the number of which corresponds to the grouping of multiple cores of the central processing unit (CPU). A positioning module is used to determine the target core corresponding to the Pin / Unpin operation in response to the Pin / Unpin operation of the target data block, wherein the target core belongs to the plurality of cores; A determination module is used to determine a corresponding target counter based on the target core, wherein the target counter belongs to the plurality of counters; The counting module is used to perform reference counting corresponding to the Pin / Unpin operation through the target counter. A computing device, characterized in that, Including the processor; The processor is configured to execute computer programs or computer instructions stored in memory to perform the method as described in any one of claims 1 to 6. The computing device according to claim 8, characterized in that, It also includes the memory. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing device, the computing device performs the method as described in any one of claims 1 to 6. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a computing device, cause the computing device to perform the method as described in any one of claims 1 to 6.