Communication method and apparatus in wireless local area network, and readable storage medium

Abstract

The present application relates to the technical field of wireless communications, and in particular to a communication method and apparatus in a wireless local area network, and a readable storage medium. The method comprises: a sending end acquiring an information bit sequence, and encoding the information bit sequence on the basis of a check matrix of an LDPC code so as to obtain a codeword, wherein the LDPC code has a code length of 3,888 bits, and the check matrix of the LDPC code is as shown in embodiments; and sending the codeword. Use of the present application can achieve stronger error control performance, and can reduce implementation complexity. The present application supports IEEE series protocols such as an IEEE 802.11bn / UHR protocol, an IEEE 802.15 / UWB protocol, an IEEE 802.11bf / sensing protocol, or an integrated millimeter wave / IMMW protocol. The present application can also support SparkLink / NearLink standard protocols.

Description

Communication methods, devices and readable storage media in wireless local area networks

[0001] This application claims priority to Chinese Patent Application No. 202411717974.1, filed on November 27, 2024, with the State Intellectual Property Office of China, entitled "Communication Method, Apparatus and Readable Storage Medium in Wireless Local Area Network", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of wireless communication technology, and in particular to a communication method, apparatus and readable storage medium in a wireless local area network. Background Technology

[0003] The IEEE 802.11n / ac / ax / be wireless local area network (WLAN) standards primarily focus on improving user experience in high-bandwidth scenarios such as 60GHz. This includes increasing average user throughput and energy efficiency of battery-powered devices. This requires achieving high-speed and reliable transmission of data, video, and other services on limited frequency and power resources, thus necessitating highly reliable and efficient channel coding and decoding schemes.

[0004] To date, in the field of channel coding, Turbo codes and low-density parity-check (LDPC) codes are the two most commonly used channel coding schemes. Both offer performance close to the Shannon limit and have been widely applied in the communications field. Compared to Turbo codes, LDPC codes have significant advantages, such as: achieving good error performance without deep interleaving, better frame error rate performance, significantly reduced error floor, support for parallel decoding, and low decoding latency. Therefore, LDPC codes have become the standard channel coding scheme for low-frequency, short-range WLAN communication systems such as 802.11n / ac / ax.

[0005] To improve the transmission reliability of wireless transmission systems, LDPC codes have been widely used in WLAN standards. Next-generation WLAN standards, such as the IEEE 802.11bn standard, are considering using LDPC codes with even longer code lengths. Currently, how to design LDPC codes suitable for the 802.11bn standard is a problem being studied by those skilled in the art. Summary of the Invention

[0006] This application provides a communication method, apparatus, and readable storage medium in a wireless local area network, which can achieve stronger error control performance and reduce implementation complexity.

[0007] The present application is described below from different aspects. It should be understood that the different implementation methods and beneficial effects described below can be referenced from each other.

[0008] In a first aspect, this application provides a communication method in a wireless local area network (WLAN). The method includes: a first communication device (as a transmitter or encoder) acquiring an information bit sequence and encoding the information bit sequence based on a parity-check matrix of the LDPC code provided in this application to obtain a codeword; the first communication device then transmitting the codeword. The LDPC code provided in this application has a code length of 3888 bits. The parity-check matrix of the LDPC code provided in this application can be found in the description of the method embodiments below, and will not be detailed here.

[0009] The information bit sequence in this application may refer to the information bits before channel coding, or the information bits input to the channel coding module. For example, the information bit sequence may be payload bits, or the information bit sequence may include payload bits and cyclic redundancy check (CRC) bits, and this application does not impose any limitations.

[0010] It is understood that generally, the longer the code length, the better the error control performance. Therefore, this application uses a longer LDPC code to encode the information bit sequence, which can achieve stronger error control performance. In addition, since the LDPC code provided in this application is designed based on the parity check matrix of the existing 1944-bit LDPC code, this application can reuse the encoding modules (such as encoding chips, encoding circuits, or basic encoding operation units, etc.) and / or decoding modules (such as decoding chips, decoding circuits, or basic decoding operation units, etc.) of existing LDPC codes in wireless local area networks as much as possible, thereby reducing its implementation complexity.

[0011] Secondly, this application provides a communication method in a wireless local area network. The method includes: a second communication device (as a receiver or decoder) receiving a codeword and decoding the codeword based on the parity-check matrix of the LDPC code provided in this application to obtain an information bit sequence. The LDPC code provided in this application has a code length of 3888 bits. The parity-check matrix of the LDPC code provided in this application can be found in the description of the method embodiments below, and will not be detailed here.

[0012] For example, the decoding process at the receiving end can be understood as the reverse process of the encoding process at the sending end.

[0013] It is understandable that, in order for the decoding end to decode correctly, encoding and decoding can be based on the same LDPC code, or in other words, the parity check matrix of the LDPC code involved in encoding and decoding is the same matrix.

[0014] In any possible implementation of any of the above aspects, the code rate of the LDPC code is any of the following values:

[0015] or

[0016] In any possible implementation of any of the above aspects, when the code rate of the LDPC code is 5 / 6, the size of the parent matrix corresponding to the parity check matrix of the LDPC code is 4×24, and each element in the parent matrix represents a z×z square matrix, where z equals 162.

[0017] For example, the parent matrix corresponding to the parity-check matrix of this LDPC code is:

[0018] It is understandable that, for ease of description, the parity check matrix of an LDPC code can be represented using a parent matrix. In practical applications (the actual encoding process), the parity check matrix of an LDPC code can be the form of the parent matrix expanded according to predetermined rules. For example, the non-zero element "A (A is a positive integer)" in the above parent matrix can be replaced with a cyclic shift matrix obtained by shifting a z×z identity matrix to the right by A bits, and the element "0" in the above parent matrix can be replaced with a z×z identity matrix. z = N / 24 = 3888 / 24 = 162. N is the code length of the LDPC code.

[0019] In any possible implementation of any of the above aspects, when the code rate of the LDPC code is 5 / 6, the size of the parent matrix corresponding to the parity check matrix of the LDPC code is 8×48, and each element in the parent matrix represents a z×z square matrix, where z equals 81.

[0020] For example, each element block in the parent matrix corresponding to the parity-check matrix of this LDPC code is obtained by diagonally expanding each element in the parent matrix corresponding to the initial parity-check matrix. This element block is a 2×2 square matrix. The initial parity-check matrix can be the parity-check matrix of an LDPC code with a code length of 1944 bits and a code rate of 5 / 6 in a WLAN.

[0021] For example, the position of element 1 in the parity check matrix of the LDPC code can be represented by a concatenation index, which can be Table 2 or Table 3 in the method embodiments below, and will not be described in detail here.

[0022] In any possible implementation of any of the above aspects, when the code rate of the LDPC code is 3 / 4, the size of the parent matrix corresponding to the parity check matrix of the LDPC code is 12×48, and each element in the parent matrix represents a z×z square matrix, where z equals 81.

[0023] For example, the position of element 1 in the parity check matrix of the LDPC code can be represented by a concatenation index, which can be Table 4 in the method embodiments below, and will not be described in detail here.

[0024] In any possible implementation of any of the above aspects, when the code rate of the LDPC code is 2 / 3, the size of the parent matrix corresponding to the parity check matrix of the LDPC code is 16×48, and each element in the parent matrix represents a z×z square matrix, where z equals 81.

[0025] For example, the position of element 1 in the parity check matrix of the LDPC code can be represented by a concatenation index, which can be Table 5 in the method embodiments below, and will not be described in detail here.

[0026] Thirdly, this application provides a communication device for performing the method in the first aspect or any possible implementation thereof. The communication device includes modules for performing the method in the first aspect or any possible implementation thereof.

[0027] Fourthly, this application provides a communication device for performing the method in the second aspect or any possible implementation thereof. The communication device includes modules for performing the method in the second aspect or any possible implementation thereof.

[0028] In the third or fourth aspect, the aforementioned communication device may include a transceiver module and a processing module. For a detailed description of the transceiver module and the processing module, please refer to the device embodiments shown below. The beneficial effects of the third to fourth aspects described above can be referred to the relevant descriptions of the first and second aspects above, and will not be repeated here.

[0029] Fifthly, this application provides a communication device including a processor for executing the methods shown in any possible implementation of the first aspect, the second aspect, or any of the above-described aspects. Alternatively, the processor is configured to execute a program stored in a memory, wherein when the program is executed, the methods shown in any possible implementation of the first aspect, the second aspect, or any of the above-described aspects are executed.

[0030] In conjunction with the fifth aspect, in one possible implementation, the memory is located outside the aforementioned communication device.

[0031] In conjunction with the fifth aspect, in one possible implementation, the memory is located within the aforementioned communication device.

[0032] In this application, the processor and memory can also be integrated into a single device, that is, the processor and memory can be integrated together.

[0033] In conjunction with the fifth aspect, in one possible implementation, the communication device further includes a transceiver for sending or receiving codewords.

[0034] Sixthly, this application provides a communication device that may include logic circuitry and an interface coupled together. The interface is used for exchanging (or sending / receiving or inputting / outputting) information or data, and the logic circuitry is used for executing program instructions to cause the communication device to perform the methods described in the first aspect, the second aspect, or any possible implementation thereof. The interface may be a communication interface or a transceiver. The transceiver may be a radio frequency module in the communication device, or a combination of a radio frequency module and an antenna, or an input / output interface of a chip or circuit.

[0035] In a seventh aspect, this application provides a readable storage medium storing program instructions that, when run on a computer, cause the computer to perform the method described in the first aspect, or the second aspect, or any possible implementation thereof.

[0036] Eighthly, this application provides a computer program product containing program instructions that, when run, causes the method described in any possible implementation of the first aspect, the second aspect, or any of the aspects to be executed.

[0037] Ninthly, this application provides a communication system, which includes a first communication device and a second communication device; the first communication device is used to perform the method described in the first aspect or any possible implementation of the first aspect, and the second communication device is used to perform the method described in the second aspect or any possible implementation of the second aspect.

[0038] The technical effects achieved in the above aspects can be referred to each other or to the beneficial effects in the method embodiments shown below, and will not be repeated here. Attached Figure Description

[0039] Figure 1 is a network architecture diagram of a wireless communication system provided in an embodiment of this application;

[0040] Figure 2a is a schematic diagram of a parity check matrix of an LDPC code provided in an embodiment of this application;

[0041] Figure 2b is a Tanner diagram of the LDPC code provided in an embodiment of this application;

[0042] Figure 3a is a schematic diagram of an LDPC code parity check matrix with a code rate of 5 / 6 and a code length of 1944 bits provided in an embodiment of this application;

[0043] Figure 3b shows the cyclic shift matrix P provided in the embodiment of this application. i A schematic diagram;

[0044] Figure 4 is a schematic diagram of the encoding process of LDPC code in WLAN provided in the embodiments of this application;

[0045] Figure 5 is a schematic diagram of the parity check matrix of an LDPC code with a code length of 1944 bits provided in an embodiment of this application;

[0046] Figure 6 is a flowchart illustrating a communication method provided in an embodiment of this application;

[0047] Figure 7 is a structural schematic diagram of a communication device provided in an embodiment of this application;

[0048] Figure 8 is another structural schematic diagram of the communication device provided in an embodiment of this application;

[0049] Figure 9 is another structural schematic diagram of the communication device provided in the embodiments of this application. Detailed Implementation

[0050] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0051] In the description of this application, the terms "first," "second," etc., are used only to distinguish different objects and do not limit the quantity or order of execution, nor do they imply that they are necessarily different. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0052] In the description of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one item", "one or more of the following", or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent: a, b, c; a and b; a and c; b and c; or a and b and c. Here, a, b, and c can be single or multiple.

[0053] In the description of this application, the words "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design that is described as "exemplary," "for example," or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of the words "exemplary," "for example," or "for example" is intended to present the relevant concepts in a specific manner.

[0054] It is understood that in the description of this application, "when," "if," and "if" all refer to the device making a corresponding action under certain objective circumstances, and are not time-limited, nor do they require the device to make a judgment action when it is implemented, nor do they mean that there are other limitations.

[0055] In this application, the use of singular designations for elements is intended to represent "one or more" rather than "one and only one," unless otherwise specified.

[0056] It is understood that in the various embodiments of this application, "B corresponding to A", "A corresponds to B" or similar expressions indicate that B is associated with A, or that B can be determined based on A. However, it should also be understood that determining B based on (or on) A does not mean that B is determined solely based on (or on) A; B can also be determined based on (or on) A and / or other information.

[0057] The technical solutions of this application can be applied to various communication systems, such as: wireless local area network (WLAN) systems using the 802.11 series protocols, long term evolution (LTE) systems, 5th generation (5G) systems, such as new radio access technology (NR), networks integrating multiple systems, Internet of Things (IoT) systems, vehicle-to-everything (V2X) systems, open-radio access network (O-RAN) systems, and future communication systems, such as 6th generation (6G) systems. The 802.11 series protocols include, but are not limited to: 802.11a / b / g protocols, 802.11n protocols, 802.11ac protocols, 802.11ax protocols, 802.11be protocols, Wi-Fi 7 or next-generation protocols, such as Wi-Fi 8 / ultra-high reliability (UHR) / 802.11bn protocols, etc., which are not listed here.

[0058] The technical solutions provided in this application can also be applied to wireless personal area networks (WPANs) based on millimeter wave (MMW) and ultra-wideband (UWB) technologies. For example, the technical solutions provided in this application can be applied to IEEE 802.15 series protocols, such as 802.15.4a, 802.15.4z, or 802.15.4ab, or a future generation of UWB WPAN protocols, etc., and will not be listed exhaustively. The technical solutions provided in this application can also be applied to sensing systems, such as the 802.11bf series standards. The technical solutions provided in this application can also be applied to communication systems using Spark Link / NearLink standard protocols.

[0059] The technical solutions of this application can be applied to communication scenarios between access points and stations, such as communication between an access point and a station, or communication between an access point and multiple stations simultaneously. Simultaneous communication between an access point and multiple stations can be further divided into one access point simultaneously sending signals to multiple stations for downlink transmission, and multiple stations simultaneously sending signals to the access point for uplink transmission. The technical solutions of this application can also be applied to communication scenarios between access points, and also to communication scenarios between stations. In this application, the term "communication" can also be described as "data transmission," "information transmission," or "transmission."

[0060] Referring to Figure 1, Figure 1 is a network architecture diagram of a wireless communication system provided in an embodiment of this application. As shown in Figure 1, the wireless communication system may include one or more access point (AP) type stations (STAs) and one or more non-access point type stations (non-AP STAs). For ease of description, access point type stations (AP STAs) are simply referred to as access points (APs), and non-access point type stations (non-AP STAs) are simply referred to as stations (STAs). APs and STAs support WLAN communication protocols, which may include 802.11bn (or UHR), and may also include protocols such as 802.11be, 802.11ax, and 802.11ac. Of course, with the continuous evolution and development of communication technologies, the communication protocol may also include next-generation protocols of 802.11bn, etc. Taking WLAN as an example, the apparatus for implementing the method of this application may be an AP and / or STA in a WLAN, or a chip or processing system installed in an AP and / or STA.

[0061] In this system, the AP can communicate with one or more STAs, and multiple STAs can also communicate with each other. As shown in Figure 1(a), it illustrates a system in which an AP communicates with one STA; as shown in Figure 1(b), it illustrates a system in which an AP communicates with multiple STAs.

[0062] It is understood that the use of STA as a mobile phone and AP as a router in Figure 1 is merely an example and does not imply a limitation on the types of APs and STAs in the embodiments of this application. Furthermore, the number of APs and STAs shown in Figure 1 is only an example; in practical applications, the number of APs and STAs included in the wireless communication system may be more or less. This application does not limit the number of APs and STAs in the wireless communication system.

[0063] In one possible implementation, the access point (AP as shown in Figure 1) can be a device with wireless communication capabilities, supporting communication using the WLAN protocol and having the ability to communicate with other devices (such as stations or other access points) in the WLAN network. This wireless communication device can be a complete device, or it can be a chip or processing system installed within a complete device. Devices with these chips or processing systems can implement the methods and functions of the embodiments of this application under the control of the chip or processing system. Access points can be deployed in homes, buildings, and parks, with a coverage radius of tens to hundreds of meters; they can also be deployed outdoors. An access point can be understood as a bridge connecting wired and wireless networks, its main function being to connect various wireless network clients together and then connect the wireless network to the Ethernet. For example, an access point can be a terminal device (such as a mobile phone) or a network device (such as a communication server, router, switch, bridge, etc.) with a wireless-fidelity (Wi-Fi) chip.

[0064] The access point in this application can be a device that supports the 802.11bn standard. Of course, the access point can also support various WLAN standards from the 802.11 family, such as 802.11be, 802.11ax, 802.11ac, 802.11n, 802.11g, 802.11b, 802.11ad, 802.11ay, and 802.11a. In one possible implementation, the access point can also support the IEEE Integrated mmWave / IMMW standard, or the IEEE 802.11bf / sensing standard, or the UWB standard, or the Spark Link / NearLink standard, etc.

[0065] In one possible implementation, a station (as shown in any of the stations in Figure 1) can be a device with wireless communication capabilities, supporting communication using the WLAN protocol and having the ability to communicate with other stations or access points in the WLAN network. This wireless communication device can be a complete device, or a chip or processing system installed within a complete device. Devices with these chips or processing systems can implement the methods and functions of the embodiments of this application under the control of the chip or processing system. A station can also be a wireless communication chip, a wireless sensor, or a wireless communication terminal, and can also be referred to as a user. For example, a station can be a mobile phone supporting Wi-Fi communication, a tablet computer supporting Wi-Fi communication, a set-top box supporting Wi-Fi communication, a smart TV supporting Wi-Fi communication, a smart wearable device supporting Wi-Fi communication, an in-vehicle communication device supporting Wi-Fi communication, or a computer supporting Wi-Fi communication, etc.

[0066] The site in this application can also be a device that supports the 802.11bn standard. Of course, the site can also support various WLAN standards of the 802.11 family, such as 802.11be, 802.11bf, 802.11ax, 802.11ac, 802.11n, 802.11g, 802.11b, 802.11ad, 802.11ay, and 802.11a. In one possible implementation, the site can also support the IEEE Integrated mmWave / IMMW standard, or the IEEE 802.11bf / sensing standard, or the UWB standard, or the Spark Link / NearLink standard.

[0067] WLAN systems can provide high-speed, low-latency transmission. As WLAN application scenarios continue to evolve, WLAN systems will be applied to more scenarios or industries, such as the Internet of Things industry, the Internet of Vehicles industry, the banking industry, enterprise offices, stadiums and exhibition halls, concert halls, hotel rooms, dormitories, hospital wards, classrooms, shopping malls, squares, streets, production workshops and warehouses, etc. Of course, devices supporting WLAN communication (such as access points or sites) can be sensor nodes in smart cities (e.g., smart water meters, smart electricity meters, smart air quality monitoring nodes), smart devices in smart homes (e.g., smart cameras, projectors, displays, televisions, speakers, refrigerators, washing machines, etc.), nodes in the Internet of Things (IoT), entertainment terminals (e.g., augmented reality (AR), virtual reality (VR), and other wearable devices), smart devices in smart offices (e.g., printers, projectors, loudspeakers, speakers, etc.), vehicle-to-everything (V2X) devices, infrastructure in daily life scenarios (e.g., vending machines, supermarket self-service navigation kiosks, self-checkout machines, self-ordering machines, etc.), and equipment in large sports and music venues, etc. The specific forms of sites and access points in this application embodiment are not limited; they are merely illustrative examples.

[0068] In some embodiments, the AP in the wireless communication system shown in Figure 1 can be replaced by an Access Point Multi-Link Device (AP MLD), and the STA can be replaced by a Non-Access Point Multi-Link Device (non-AP MLD). That is, the technical solutions provided in this application can also be applied to scenarios where multi-link devices (MLDs) communicate with each other. A multi-link device is a wireless communication device that supports parallel transmission across multiple links. Compared to devices that only support single-link transmission, multi-link devices have higher transmission efficiency and higher throughput. A multi-link device includes one or more affiliated STAs. An affiliated STA is a logical site that can operate on a single link. The affiliated site can be an access point (AP) or a non-access point STA. A multi-link device whose affiliated site is an AP can be called an AP MLD, and a multi-link device whose affiliated site is a non-AP STA can be called a non-AP MLD.

[0069] In one possible implementation, the multi-link device (which can be either a non-AP MLD or an AP MLD) involved in the embodiments of this application is a device with wireless communication function. This device can be a complete device or a chip or processing system installed in the complete device. The device with these chips or processing systems installed can implement the methods and functions of the embodiments of this application under the control of these chips or processing systems.

[0070] Although the embodiments in this application are primarily illustrated using a network deploying IEEE 802.11 as an example, those skilled in the art will readily understand that the various aspects of this application can be extended to other networks employing various standards or protocols. For example, personal area networks (PANs), Bluetooth, high-performance radio LANs (HIPERLANs) (a wireless standard similar to IEEE 802.11, primarily used in Europe), and wide area networks (WANs) or other networks now known or developed in the future. Therefore, regardless of the coverage area and wireless access protocol used, the various aspects provided in this application can be applied to any suitable wireless network.

[0071] The following is a brief introduction to some of the terms or nouns used in this application.

[0072] I. LDPC code

[0073] LDPC codes are linear block codes that can map a sequence of information bits into codewords using a generator matrix G. For the generator matrix G, there exists an equivalent parity-check matrix H, and all the codewords C constitute the null space of the parity-check matrix H, i.e., H*C. T =0 (i.e., a matrix consisting entirely of zeros). C T This represents the transpose of the generating matrix G.

[0074] The parity-check matrix H of an LDPC code is a sparse matrix, meaning the number of non-zero elements is much smaller than the number of zero elements, or the ratio of row weight to code length and the ratio of column weight to code length are both very small. The LDPC code's bipartite graph (also called a Tanner graph) corresponds one-to-one with the parity-check matrix H, and it can be composed of two types of nodes: the first type represents code symbols, called variable nodes; the second type represents parity constraints, called parity nodes, with each parity node representing a parity constraint.

[0075] For example, referring to Figures 2a and 2b, Figure 2a is a schematic diagram of a parity check matrix of an LDPC code provided in an embodiment of this application; Figure 2b is a Tanner diagram of an LDPC code provided in an embodiment of this application. In Figures 2a and 2b, {V i} represents the set of variable nodes, {C i} represents the set of check nodes, where i takes the value of a positive integer. As shown in Figure 2a, each row in the check matrix H of the LDPC code represents a check equation, which corresponds to a check node C. i Each column represents a variable node V. i If a variable node is included in the corresponding parity check equation, then a line connects the involved variable node and the parity check node. Therefore, the number of lines in the Tanner diagram of the LDPC code is the same as the number of "1"s in the parity check matrix H. As shown in Figure 2b, variable nodes in the Tanner diagram are represented by circular nodes, and parity check nodes are represented by square nodes.

[0076] The LDPC code used in the 802.11ac / ax standard is a quasi-cyclic LDPC (QC-LDPC) code. QC-LDPC codes are a widely used type of structured LDPC code. Due to the unique structure of its parity-check matrix, encoding can be implemented using a simple feedback shift register, thus effectively solving the encoding complexity problem of LDPC codes. See Figure 3a, which is a schematic diagram of the parity-check matrix of an LDPC code with a code rate of 5 / 6 and a code length of 1944 bits provided in this embodiment. As shown in Figure 3a, each element in the parity-check matrix of the LDPC code with a code length N = 1944 and a code rate R = 5 / 6 represents a square matrix of order Z = N / 24 (e.g., N equals 1944, Z equals 81), where "0" represents a Z×Z identity matrix and "-" represents a Z×Z matrix of all zeros. For example, in Figure 3a, element "13" represents a Z×Z identity matrix P cyclically shifted 13 bits to the right to obtain a cyclic shift matrix P. 13 The other non-zero elements in Figure 3a are similar to element "13" and will not be described in detail. Among them, P i Let i represent the cyclic shift matrix, and i (0≤i≤Z-1) represent the cyclic shift value.

[0077] Taking a 4×4 cyclic shift matrix as an example, see Figure 3b. Figure 3b is a cyclic shift matrix P provided in an embodiment of this application. i A schematic diagram is shown in Figure 3b. P0 represents a 4×4 identity matrix, P1 represents a 4×4 identity matrix shifted 1 position to the right, P2 represents a 4×4 identity matrix shifted 2 positions to the right, and P3 represents a 4×4 identity matrix shifted 3 positions to the right.

[0078] It is understandable that, for ease of description, Figure 3a above represents the parity check matrix of the LDPC code in the form of a parent matrix. In actual applications (the actual encoding process), the parity check matrix can be the form of the parent matrix expanded according to predetermined rules. For example, in Figure 3a, the element "0" can be replaced with a Z×Z identity matrix, the element "-" can be replaced with a Z×Z matrix of all zeros, and the non-zero element "i" (where i is a positive integer) can be replaced with a cyclic shift matrix P obtained by cyclically shifting the Z×Z identity matrix P to the right by i positions. i In some embodiments, for ease of description, the parity check matrix of the LDPC code is also represented in the form of a parent matrix, which will not be elaborated further.

[0079] II. Encoding process of LDPC code in WLAN

[0080] The encoding process of LDPC codes can be implemented using matrix multiplication. Suppose we want to encode a data block using LDPC, we first multiply the data block by the generator matrix G of the LDPC code to obtain the encoded data block. The generator matrix G is a special matrix in LDPC codes, which can be used to convert information bits into codewords. The decoding process of LDPC codes can be implemented using the parity-check matrix H. The decoding algorithm usually employs an iterative decoding algorithm, such as the Belief Propagation algorithm. The parity-check matrix H and the generator matrix G of the LDPC code satisfy GH T =0 (i.e., a matrix with all elements being 0).

[0081] The following example illustrates the encoding process of LDPC codes in a wireless local area network (WLAN). Existing WLAN standards (such as 802.11n / ac) employ orthogonal frequency division multiplexing (OFDM) technology. The LDPC encoding module needs to encode the data bits (which can also be understood as payload bits) and place them into an integer number of OFDM symbols. These encoded bits must also fit exactly into an integer number of LDPC codewords. Therefore, before transmission, the minimum number of OFDM symbols N required for this transmission needs to be calculated. SYM Then according to N SYM Calculate the total number of coded bits N that can be stored in all OFDM symbols using the current coding and modulation scheme. TCB =N CBPS ×N SYM , where N CBPS This represents the number of coded bits that can be stored in each OFDM symbol. Then, based on the total number of coded bits N... TCB Determine the LDPC code length L used in the current transmission. LDPC and the required number of codewords NCW For most data bit lengths and coding modulation schemes, there are not enough data bits to fill all the information bit positions in the LDPC codeword. Therefore, a shortening operation is required before generating parity bits. This shortening operation involves filling a certain number of "0"s into the information bit positions of the LDPC codeword before generating the parity bits, and then deleting these "0"s after the parity bits are generated.

[0082] Referring to Figure 4, which is a schematic diagram of the encoding process of LDPC code in WLAN provided in this application embodiment, the encoding process of LDPC code in WLAN includes at least steps 1 to 6. Specifically, step 1 is the data bits to be encoded, such as payload bits. Step 2 determines the length L of the LDPC codeword. LDPC And the number of codewords N CW The specific determination method is detailed in existing technology and will not be elaborated here. Step 3 shortens the data bits to be encoded by inserting shortened zero bits after the data bits to be encoded. Step 4 encodes the data bits to be encoded and the shortened zero bits in each LDPC codeword according to the parity check matrix H of the LDPC code to generate parity bits, and then deletes these shortened zero bits. Step 5 repeats some of the data bits to be encoded in the LDPC codeword or punctures the parity bits in the LDPC codeword so that the processed (punctured or repeated) codeword bits exactly fill the OFDM symbol to be transmitted. That is, the number of processed (punctured or repeated) codeword bits is equal to the number of bits that the OFDM symbol can carry. Step 6 concatenates multiple codewords and performs stream parsing.

[0083] In this application, "LDPC code length" refers to the length of an LDPC codeword. "LDPC code length", "LDPC code length", and "LDPC codeword length" can be used interchangeably.

[0084] It is understood that Figure 4 above is merely an example. LDPC codes can be applied not only to WLAN systems but also to other communication systems, such as 5G or 6G. When LDPC codes are applied to different communication systems, their encoding and / or decoding processes may differ. The embodiments of this application do not limit the specific encoding and decoding processes of LDPC codes in each communication system.

[0085] III. Check Matrix of LDPC Code in WLAN

[0086] Existing WLAN standards (such as 802.11n / ac / ax) specify multiple LDPC code parity check matrices, with three code lengths: 648 bits, 1296 bits, and 1944 bits. Each code length supports four different code rates, such as 1 / 2 (half), 2 / 3 (two-thirds), 3 / 4 (three-quarters), and 5 / 6 (five-sixths). The code rate is determined by the system's adaptive modulation and coding scheme (MCS) based on the link. In WLAN, LDPC codes can be selected from multiple parity check matrices based on the chosen code length and code rate; therefore, the parity check matrices can be different for each code length and code rate.

[0087] Referring to Figure 5, Figure 5 is a schematic diagram of the parity-check matrix of an LDPC code with a code length of 1944 bits provided in an embodiment of this application. As shown in Figure 5, it illustrates the parity-check matrix (represented by a parent matrix) of an LDPC code with a code length N of 1944 bits and coding rates R of 1 / 2, 2 / 3, 3 / 4, and 5 / 6. Each element in the parity-check matrix of this LDPC code represents a square matrix of order Z = N / 24 (e.g., N equals 1944, Z equals 81), where "0" represents a Z×Z identity matrix and "-" represents a Z×Z matrix of all zeros. The "non-zero values" in Figure 5 represent the cyclic shift matrix P obtained by cyclically shifting the Z×Z identity matrix P. i , i (0≤i≤Z-1) represents the cyclic shift value.

[0088] In summary, the longest LDPC code length in existing WLANs is 1944 bits. To further improve the transmission reliability of wireless transmission systems, next-generation WLAN standards, such as the IEEE 802.11bn standard, are considering using LDPC codes with longer code lengths. However, how to design LDPC codes suitable for the 802.11bn standard remains to be explored.

[0089] This application provides a communication method, apparatus, and readable storage medium in a wireless local area network, which not only achieves stronger error control performance but also reduces implementation complexity.

[0090] In this application, unless otherwise specified, the same or similar parts between various embodiments or implementations can be referred to each other. In the various embodiments of this application, and in the various implementation methods / methods / implementations within each embodiment, unless otherwise specified or logically conflicting, the terminology and / or descriptions between different embodiments and between the various implementation methods / methods / implementations within each embodiment are consistent and can be mutually referenced. The technical features in different embodiments and the various implementation methods / methods / implementations within each embodiment can be combined according to their inherent logical relationships to form new embodiments, implementation methods, methods, or implementation approaches. The embodiments described below do not constitute a limitation on the scope of protection of this application.

[0091] In one possible implementation, the first communication device in this application can be an AP (Access Point) and the second communication device can be a non-AP STA (Standard Operating System) (STA for short); or, the first communication device is a non-AP STA and the second communication device is an AP. Of course, both the first and second communication devices in this application can be non-AP STAs, or both can be APs. This application does not limit the specific form of the first and second communication devices.

[0092] Referring to Figure 6, which is a schematic flowchart of a communication method provided in an embodiment of this application, the first communication device in this method can be understood as a transmitting end or an encoding end, and the second communication device can be understood as a receiving end or a decoding end. As shown in Figure 6, the communication method includes, but is not limited to, the following steps:

[0093] S101, the first communication device acquires the information bit sequence.

[0094] S102, the first communication device encodes the information bit sequence based on the LDPC code check matrix to obtain codewords.

[0095] S103, the first communication device sends the codeword.

[0096] Correspondingly, the second communication device receives the codeword.

[0097] In one possible implementation, the information bit sequence in this embodiment may refer to the information bits before channel coding, or the information bits input to the channel coding module. For example, the information bit sequence may be payload bits, or it may include payload bits and cyclic redundancy check (CRC) bits; this embodiment does not impose any limitations.

[0098] In one possible implementation, the first communication device (as a transmitter or encoder) can acquire the information bit sequence and encode it based on the parity-check matrix of the LDPC code provided in this embodiment to obtain codewords. For example, the first communication device can use the generator matrix G corresponding to the parity-check matrix H of the LDPC code provided in this embodiment to encode the information bit sequence to obtain codewords. It can be understood that the parity-check matrix H and the generator matrix G of the LDPC code are in one-to-one correspondence and satisfy GH... T =0 (i.e., a matrix with all elements equal to 0), where H T This represents the transpose of the parity-check matrix H. Therefore, the generator matrix G of the LDPC code can be determined from the parity-check matrix H.

[0099] In this embodiment, the process by which the first communication device encodes the information bit sequence based on the parity check matrix of the LDPC code can be referred to existing technology and will not be elaborated here. This embodiment does not limit the specific encoding process. For example, the first communication device can perform matrix multiplication between the information bit sequence and the generator matrix G of the LDPC code to obtain the encoded information bit sequence. Then, it can perform various processing on the encoded information bit sequence (e.g., generating parity bits, repetition, or puncturing) to obtain a codeword. The first communication device can then transmit the codeword. For example, the first communication device can output the codeword to the radio frequency module for transmission, or it can perform other processing on the codeword (e.g., modulation, or stream parsing) before outputting it to the radio frequency module for transmission. This embodiment does not limit this approach.

[0100] S104, the second communication device decodes the received codeword based on the parity check matrix of the LDPC code to obtain the information bit sequence.

[0101] In one possible implementation, after receiving the codeword, the second communication device (as a receiver or decoder) can decode the codeword based on the parity check matrix of the LDPC code provided in this application embodiment to obtain the information bit sequence. The decoding process at the receiver can be understood as the reverse of the encoding process at the sender. This application embodiment does not limit the specific decoding process. For example, the second communication device can use an iterative decoding algorithm (such as the Belief Propagation algorithm) based on the parity check matrix H of the LDPC code to decode the received codeword to obtain the information bit sequence. It is understood that, in order for the decoder to decode correctly, encoding and decoding can be based on the same LDPC code, or in other words, the parity check matrix H used for decoding and the generator matrix G used for encoding satisfy GH. T =0 (i.e., a matrix with all elements equal to 0), or in other words, the parity check matrix H of the LDPC code involved in encoding and decoding is the same matrix.

[0102] The LDPC code provided in the embodiments of this application will be described below. The LDPC code in the embodiments of this application can be characterized by the parity check matrix of the LDPC code.

[0103] In one possible implementation, the code length of the LDPC code provided in this application embodiment is greater than 1944 bits. For example, the code length of the LDPC code in this application embodiment can be twice 1944 bits, i.e., 3888 (1944 × 2 = 3888) bits. The code rate of this LDPC code can be any of the following values: 2 / 3, 3 / 4, or 5 / 6. It can be understood that the code rate can refer to the ratio of the effective number of information bits to the total number of transmitted bits, or in other words, the code rate can be equal to the ratio of the length of the information bit sequence to the length of the codeword.

[0104] In one possible implementation, an element in the parent matrix corresponding to the parity check matrix of the LDPC code provided in this application represents a z×z square matrix, where z can be equal to 81 or 162.

[0105] For example, when the code rate of the LDPC code is 5 / 6, the size of the parent matrix corresponding to the parity-check matrix of the LDPC code can be 4×24, in which case z equals 162; or, the size of the parent matrix corresponding to the parity-check matrix of the LDPC code can be 8×48, in which case z equals 81. Therefore, the size of the parity-check matrix of the LDPC code is 648×3888.

[0106] For another example, when the code rate of the LDPC code is 3 / 4, the size of the parent matrix corresponding to the parity-check matrix of the LDPC code can be 12×48, and z equals 81. Therefore, the size of the parity-check matrix of the LDPC code is 972×3888.

[0107] For another example, when the code rate of the LDPC code is 2 / 3, the size of the parent matrix corresponding to the parity-check matrix of the LDPC code can be 16×48, and z equals 81. Therefore, the size of the parity-check matrix of the LDPC code is 1296×3888.

[0108] The following is a brief description of the parity check matrix of the LDPC code provided in the embodiments of this application and its design concept.

[0109] Generally, longer code lengths result in better error control performance, but also higher implementation complexity. Therefore, this application embodiment considers using parts of the existing 1944-bit LDPC code design to design / construct a 3888-bit LDPC code. This aims to reuse existing LDPC code encoding modules (such as encoding chips, encoding circuits, or basic encoding operation units) and / or decoding modules (such as decoding chips, decoding circuits, or basic decoding operation units) in WLANs as much as possible, thereby reducing implementation complexity and enabling the 3888-bit LDPC code to achieve stronger error control performance and better decoding performance. In other words, this application embodiment considers the trade-off between the performance of the LDPC code and the reusability of the encoding and decoding modules in the LDPC code within the WLAN.

[0110] In this application, LDPC codes with a code length of 1944 bits and code rates of 2 / 3, 3 / 4, and 5 / 6 (five-sixths) in WLAN are used as the base matrix for expansion to obtain LDPC codes with a code length of 3888 bits for the corresponding code rates. Three possible implementation methods are described below.

[0111] Implementation method 1:

[0112] This application embodiment addresses the parity-check matrix (PCM) of a 1944-bit LDPC code in existing WLAN standards (as shown in Figure 5 above), and modifies the cyclic shift matrix P in the PCM PCM parity-check matrix (when represented by a parent matrix). i The size of the parity-check matrix (PCM) is doubled from 81×81 to 162×162 to obtain a double-length PCM PCM parity-check matrix, i.e., a PCM PCM parity-check matrix with a code length of 3888 bits (=1944×2). For example, the value of each element (i.e., the cyclic shift value i) in the PCM PCM parity-check matrix (when represented as a parent matrix) with a code length of 3888 bits can be the same as the element value at the corresponding position in the PCM PCM parity-check matrix (when represented as a parent matrix) with a code length of 1944 bits. Of course, embodiments of this application can also optimize the value of the elements (i.e., the cyclic shift value i) in the PCM PCM parity-check matrix (when represented as a parent matrix) with a code length of 3888 bits to further improve the performance of the PCM PCM with a code length of 3888 bits.

[0113] Implementation method 2:

[0114] This application embodiment addresses the parity-check matrix (PCM) of a 1944-bit LDPC code in existing WLAN standards (as shown in Figure 5 above), maintaining the cyclic shift matrix P in the PCM PCM parity-check matrix (when represented by a parent matrix). iThe size (i.e., 81×81) remains unchanged, and the parity check matrix of the LDPC code (when represented by the parent matrix) is block-extended using a permutation matrix of size 2×2, thereby obtaining the parity check matrix of the LDPC code with a code length of 3888 bits.

[0115] For example, taking an LDPC code with a code rate of 5 / 6 (five-sixths) as an example, we will introduce the basic principle of extending the code length in implementation method 2. Here, the extension can be the cyclic shift matrix P in the parity-check matrix (when represented by the parent matrix) of the existing LDPC code with a code length of 1944 bits and a code rate of 5 / 6. i The size (i.e., 81×81) remains unchanged, and the parity-check matrix (when represented by the parent matrix) of the LDPC code is expanded to twice its original size. That is, the parent matrix size corresponding to the parity-check matrix of the LDPC code with a code rate R = 5 / 6 and a code length of 1944 bits is 4×24, and the parent matrix size corresponding to the parity-check matrix of the LDPC code with a code rate R = 5 / 6 and a code length of 3888 bits is 8×48. In this way, the code rate remains unchanged (R = 5 / 6), and the code length N = 1944×2 = 3888. In order to reuse the various modules in the existing WLAN LDPC decoder as much as possible (such as the basic operation unit of the decoder, or the logic gate design, etc.), the embodiments of this application perform diagonal expansion on each item in the parity-check matrix (when represented by the parent matrix) of the LDPC code with a code length of 1944 bits and a code rate of 5 / 6, such as positive diagonal expansion or negative diagonal expansion. Here, we take the first item (i.e., the cyclic shift value "13") in the parity check matrix (represented by the parent matrix) of the LDPC code with a code length of 1944 bits and a code rate of 5 / 6 shown in Figure 5 above as an example. Its diagonal expansion is as follows (1-1), and its anti-diagonal expansion is as follows (1-2).

[0116] In (1-1) and (1-2) above, the "-" represents an 81×81 all-zero matrix, and the non-zero elements represent the cyclically shifted matrix P obtained by cyclically shifting the 81×81 identity matrix P. i , where i represents the cyclic shift value. Therefore, it can be seen that each item in the parity-check matrix (represented by the parent matrix) of the LDPC code with a code length of 1944 bits and a code rate of 5 / 6, as shown in Figure 5 above, is expanded into a 2×2 square matrix. Thus, the code rate of the LDPC code obtained by diagonal expansion remains unchanged (i.e., the code rate is still 5 / 6), while the code length increases from 1944 bits to 3888 bits.

[0117] It is understood that, in the embodiments of this application, different diagonal expansions can be performed on different items in the parity check matrix (represented by the parent matrix) of an LDPC code with a code length of 1944 bits and a code rate of 5 / 6. For example, the first item can be expanded diagonally, and the second item can be expanded diagonally.

[0118] In other words, each element block in the parent matrix corresponding to the parity-check matrix of a 3888-bit LDPC code is obtained by diagonally expanding each element in the parent matrix corresponding to the initial parity-check matrix. This diagonal expansion includes positive diagonal expansion and / or negative diagonal expansion, as shown in formulas (1-1) and (1-2) above. The initial parity-check matrix is ​​the parity-check matrix of a 1944-bit LDPC code in the existing WLAN standard. The element block is a 2×2 square matrix. In other words, by replacing each element in the parent matrix corresponding to the initial parity-check matrix with a 2×2 square matrix diagonally expanded from that element, the parent matrix corresponding to the parity-check matrix of the 3888-bit LDPC code can be obtained.

[0119] It can also be understood that the cyclic shift values ​​in the parity-check matrix (represented by the parent matrix) of the LDPC code with a code rate R = 5 / 6 and a code length of 3888 bits obtained by diagonal expansion can be different from the cyclic shift values ​​in the parity-check matrix (represented by the parent matrix) of the existing LDPC code with a code rate R = 5 / 6 and a code length of 1944 bits; of course, they can also be the same. In other words, the cyclic shift values ​​in the parity-check matrix (represented by the parent matrix) of the LDPC code with a code rate R = 5 / 6 and a code length of 3888 bits can be redesigned to further improve the performance of the 3888-bit LDPC code.

[0120] Implementation method 3:

[0121] This application embodiment uses the cyclic shift matrix P i The size is set to 81×81, and the parity check matrix of the LDPC code with a code length of 3888 bits is redesigned. It can be understood that in implementation 3, this embodiment retains the cyclic shift matrix P in the parity check matrix of the LDPC code with a code length of 3888 bits (when represented by the parent matrix). i The size of the matrix is ​​the same as the size of the cyclic shift matrix in the parity-check matrix (when represented by the parent matrix) of a 1944-bit LDPC code. This allows for the reuse of basic operational units in existing WLAN LDPC codecs, reducing their implementation complexity.

[0122] Based on the above three implementation methods, this application provides several LDPC codes with a code length of 3888 bits as examples.

[0123] It is understood that the parity-check matrix of an LDPC code contains only two types of elements: element 1 and element 0. For simplicity, the embodiments of this application can be described by the position of element 1 in the parity-check matrix of the LDPC code, with all other positions being element 0.

[0124] For example, based on the above implementation method 1, the position of element 1 in the parity check matrix of an LDPC code with a code rate of 5 / 6 (five-sixths) and a code length of 3888 bits can be shown in Table 1a below. In the parity check matrix of this LDPC code, except for the position of element 1 shown in Table 1a below, all other positions are elements 0.

[0125] Table 1a

[0126] In Table 1a, the values ​​in row (i+1) represent the column index of element 1 in row (i×z) of the LDPC code parity check matrix, where i takes the values ​​0, 1, 2, and 3, and z equals 162. For example, the values ​​in row 1 (i.e., i=0) (row number 1) of Table 1a represent the column index of element 1 in row 0 of the LDPC code parity check matrix; the values ​​in row 2 (i.e., i=1) (row number 2) of Table 1a represent the column index of element 1 in row 162 of the LDPC code parity check matrix; the values ​​in row 3 (i.e., i=2) (row number 3) of Table 1a represent the column index of element 1 in row 324 of the LDPC code parity check matrix; and the values ​​in row 4 (i.e., i=3) (row number 4) of Table 1a represent the column index of element 1 in row 486 of the LDPC code parity check matrix. In the parity-check matrix of this LDPC code, the column index of element 1 in the ((i×z)+j)th row is equal to ((162×X+Y+j)mod 162), where Y is the column index of element 1 in the (i×z)th row of the LDPC code parity-check matrix. The value of j is 1, 2, 3, 4, ..., (z-1). This indicates rounding down, which will not be elaborated further below. For example, taking the first value "26" in the first row of Table 1a as an example, it represents the column index of the first element 1 in the 0th row of the LDPC code parity check matrix. Then, the column index of the first element 1 in the 1st (j=1) row of the LDPC code parity check matrix is ​​"27"; the column index of the first element 1 in the 2nd (j=2) row of the LDPC code parity check matrix is ​​"28"; and so on, the column index of the first element 1 in the 161st (j=161) row of the LDPC code parity check matrix is ​​"25". These are not listed individually here.

[0127] The column labels in Table 1a above are arranged in ascending order starting from 0, i.e., 0, 1, 2, 3, ..., 3887.

[0128] It is understandable that the parity check matrix of the LDPC code corresponding to Table 1a above can also be represented by a parent matrix, as shown in Table 1b below. The size of the parent matrix shown in Table 1b can be 4×24.

[0129] Table 1b

[0130] In the parent matrix shown in Table 1b, each element represents a 162×162 square matrix. In the parent matrix shown in Table 1b, element "0" represents a 162×162 identity matrix, and non-zero elements represent cyclic shift matrices of the 162×162 identity matrix. For example, the first element "26" in the parent matrix shown in Table 1b represents a cyclic shift matrix obtained by shifting the 162×162 identity matrix 26 bits to the right. Tables 1b and 1a are two representations of the parity-check matrix of the same LDPC code.

[0131] For another example, based on the above implementation method 2, the position of element 1 in the parity check matrix of an LDPC code with a code rate of 5 / 6 (five-sixths) and a code length of 3888 bits can be shown in Table 2 below. In the parity check matrix of this LDPC code, except for the position of element 1 shown in Table 2 below, all other positions are elements 0.

[0132] Table 2

[0133] In Table 2, the values ​​in row (i+1) represent the column index of element 1 in row (i×z) of the LDPC code parity check matrix, where i takes the values ​​0, 1, 2, 3, 4, 5, 6, 7, and z equals 81. For example, the values ​​in row 1 (i=0) of Table 2 represent the column index of element 1 in row 0 of the LDPC code parity check matrix, the values ​​in row 2 (i=1) represent the column index of element 1 in row 81 of the LDPC code parity check matrix, the values ​​in row 3 (i=2) represent the column index of element 1 in row 162 of the LDPC code parity check matrix, and the values ​​in row 4 (i=3) represent the column index of element 1 in row 243 of the LDPC code parity check matrix. The column index of element 1 in the ((i×z)+j)th row of the parity-check matrix of this LDPC code is equal to ((81×X+Y+j)mod 81), where Y is the column index of element 1 in the (i×z)th row of the parity-check matrix of this LDPC code. The value of j is 1, 2, 3, 4, ..., (z-1). For example, taking the first value "145" in the first row of Table 2 as an example, it represents the column index of the first element 1 in the 0th row of the LDPC code parity check matrix. Then, the column index of the first element 1 in the 1st (j=1) row of the LDPC code parity check matrix is ​​"65"; the column index of the first element 1 in the 2nd (j=2) row of the LDPC code parity check matrix is ​​"66"; and so on, the column index of the first element 1 in the 80th (j=80) row of the LDPC code parity check matrix is ​​"63". These are not listed individually here.

[0134] For another example, based on the above implementation method 3, the position of element 1 in the parity check matrix of an LDPC code with a code rate of 5 / 6 (five-sixths) and a code length of 3888 bits can be shown in Table 3 below. In the parity check matrix of this LDPC code, except for the position of element 1 shown in Table 3 below, all other positions are elements 0.

[0135] Table 3

[0136] In Table 3, the values ​​in row (i+1) represent the column index of element 1 in row (i×z) of the LDPC code's parity-check matrix, where i takes values ​​of 0, 1, 2, 3, 4, 5, 6, 7, and z equals 81. The column index of element 1 in row ((i×z)+j) of the LDPC code's parity-check matrix is ​​equal to ((81×X+Y+j)mod81), where Y is the column index of element 1 in row (i×z) of the LDPC code's parity-check matrix. The value of j is 1, 2, 3, 4, ..., (z-1). The column indices in Table 3 are sorted in ascending order starting from 0, i.e., 0, 1, 2, 3, ..., 3887.

[0137] For example, based on the above implementation method 3, the position of element 1 in the parity check matrix of an LDPC code with a code rate of 3 / 4 (three-quarters) and a code length of 3888 bits can be shown in Table 4 below. In the parity check matrix of this LDPC code, except for the position of element 1 shown in Table 4 below, all other positions are elements 0.

[0138] Table 4

[0139] In Table 4, the values ​​in row (i+1) represent the column index of element 1 in row (i×z) of the LDPC code's parity-check matrix, where i takes values ​​of 0, 1, 2, 3, ..., 11, and z equals 81. The column index of element 1 in row ((i×z)+j) of the LDPC code's parity-check matrix is ​​equal to ((81×X+Y+j)mod81), where Y is the column index of element 1 in row (i×z) of the LDPC code's parity-check matrix. The value of j is 1, 2, 3, 4, ..., (z-1). The column indices in Table 4 above are sorted in ascending order starting from 0, i.e., 0, 1, 2, 3, ..., 3887.

[0140] For example, based on the above implementation method 3, the position of element 1 in the parity check matrix of an LDPC code with a code rate of 2 / 3 (two-thirds) and a code length of 3888 bits can be shown in Table 5 below. In the parity check matrix of this LDPC code, except for the position of element 1 shown in Table 5 below, all other positions are elements 0.

[0141] Table 5

[0142] In Table 5, the values ​​in row (i+1) represent the column index of element 1 in row (i×z) of the LDPC code's parity-check matrix, where i takes values ​​of 0, 1, 2, 3, ..., 15, and z equals 81. The column index of element 1 in row ((i×z)+j) of the LDPC code's parity-check matrix is ​​equal to ((81×X+Y+j)mod81), where Y is the column index of element 1 in row (i×z) of the LDPC code's parity-check matrix. The value of j is 1, 2, 3, 4, ..., (z-1). The column indices in Table 5 above are sorted in ascending order starting from 0, i.e., 0, 1, 2, 3, ..., 3887.

[0143] It is understood that the check matrices shown in Tables 1a, 1b, and 2 to 5 above are merely examples. Another check matrix can be obtained by performing row permutations and / or column permutations on any of the check matrices shown in Tables 1a, 1b, and 2 to 5 above, and these check matrices are all within the scope of protection of this application.

[0144] It is understood that generally, the longer the code length, the better the error control performance. Therefore, the embodiments of this application can achieve stronger error control performance. In addition, since the embodiments of this application are based on the existing 1944-bit LDPC code parity check matrix, the 3888-bit LDPC code parity check matrix is ​​designed. Therefore, the embodiments of this application can reuse the existing LDPC code encoding modules (such as encoding chips, encoding circuits, or basic encoding operation units, etc.) and / or decoding modules (such as decoding chips, decoding circuits, or basic decoding operation units, etc.) in WLAN as much as possible, thereby reducing its implementation complexity.

[0145] The foregoing details the method provided in this application. To facilitate the implementation of the above-described solutions in the embodiments of this application, corresponding apparatus or devices are also provided in the embodiments of this application.

[0146] This application divides the communication device into functional modules according to the above method embodiments. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware or as software functional modules. It should be noted that the module division in this application is illustrative and only represents one logical functional division; other division methods may be used in actual implementation. The communication device of the embodiments of this application will be described in detail below with reference to Figures 7 to 9.

[0147] Referring to Figure 7, which is a schematic diagram of a communication device provided in an embodiment of this application, the communication device includes a transceiver module 10 and a processing module 20. The transceiver module 10 can implement corresponding communication functions, and the processing module 20 is used for data processing. The transceiver module 10 may also be referred to as a communication interface or a communication module, etc.

[0148] In some embodiments of this application, the communication device may be the first communication device shown above. That is, the communication device shown in FIG7 may be used to perform the steps or functions performed by the first communication device in the above method embodiments. For example, the communication device may be the first communication device or a chip or functional module configured in the first communication device, etc., and this application embodiment does not limit this. The transceiver module 10 is used to perform the transceiver-related operations of the first communication device in the above method embodiments, and the processing module 20 is used to perform the processing-related operations of the first communication device in the above method embodiments.

[0149] The processing module 20 is used to acquire the information bit sequence; the processing module 20 is also used to encode the information bit sequence based on the parity check matrix of the LDPC code to obtain a codeword; the transceiver module 10 is used to transmit the codeword. The codeword of the LDPC code is 3888 bits long.

[0150] Understandably, transceiver module 10 can send codewords to other communication devices, or it can output the codewords from processing module 20 to other components or functional modules in the communication device. The explanations for other information output by the transceiver module are similar and will not be detailed below.

[0151] In this embodiment of the application, the description of the first communication device, LDPC code and its parity check matrix, etc. can be found in the above method embodiment (as shown in Figure 6), and will not be described in detail here.

[0152] It is understood that the specific descriptions of the transceiver module and processing module shown in the embodiments of this application are merely examples. For the specific functions or execution steps of the transceiver module and processing module, please refer to the above method embodiments (as shown in Figure 6), which will not be described in detail here. In addition, the technical effects of the embodiments of this application are the same as those in the foregoing method embodiments, and for the sake of brevity, they will not be repeated here.

[0153] Reusing Figure 7, in some other embodiments of this application, the communication device may be the second communication device shown above. That is, the communication device shown in Figure 7 may be used to perform the steps or functions performed by the second communication device in the above method embodiments. For example, the communication device may be the second communication device or a chip or functional module configured in the second communication device, etc., and this application embodiment does not limit this. The transceiver module 10 is used to perform the transceiver-related operations of the second communication device in the above method embodiments, and the processing module 20 is used to perform the processing-related operations of the second communication device in the above method embodiments.

[0154] The transceiver module 10 is used to receive codewords; the processing module 20 is used to decode the codewords based on the parity check matrix of the LDPC code to obtain the information bit sequence. The code length of the LDPC code is 3888 bits.

[0155] It is understood that the transceiver module 10 can receive codewords from other communication devices, or the transceiver module 10 can input the codewords from other components or other functional modules in the communication device. The explanations regarding the input of other information by the transceiver module are similar and will not be detailed below.

[0156] In this embodiment of the application, the description of the second communication device, LDPC code and its parity check matrix, etc. can be found in the above method embodiment (as shown in Figure 6), and will not be described in detail here.

[0157] It is understood that the specific descriptions of the transceiver module and processing module shown in the embodiments of this application are merely examples. For the specific functions or execution steps of the transceiver module and processing module, please refer to the above method embodiments (as shown in Figure 6), which will not be described in detail here. In addition, the technical effects of the embodiments of this application are the same as those in the foregoing method embodiments, and for the sake of brevity, they will not be repeated here.

[0158] The communication device according to embodiments of this application has been described above. The following describes possible product forms of the communication device. It should be understood that any product possessing the functions of the communication device described in FIG. 7 falls within the protection scope of the embodiments of this application. It should also be understood that the following description is merely illustrative and does not limit the product form of the communication device according to the embodiments of this application to this extent.

[0159] In one possible implementation, in the communication device shown in FIG7, the processing module 20 can be one or more processors, the transceiver module 10 can be a transceiver, or the transceiver module 10 can also be a transmitting module and a receiving module. The transmitting module can be a transmitter, and the receiving module can be a receiver. The transmitting module and the receiving module are integrated into one device, such as a transceiver. In the embodiments of this application, the processor and the transceiver can be coupled, etc., and the connection method of the processor and the transceiver is not limited in the embodiments of this application. In the process of executing the above method, the process of sending information (such as sending codewords) in the above method can be understood as the process of the processor outputting the above information. When outputting the above information, the processor outputs the above information to the transceiver so that the transceiver can transmit it. After the above information is output by the processor, it may need to undergo other processing before reaching the transceiver. Similarly, the process of receiving information (such as receiving codewords) in the above method can be understood as the process of the processor receiving the input above information. When the processor receives the input information, the transceiver receives the above information and inputs it into the processor. Furthermore, after the transceiver receives the aforementioned information, the information may need to undergo further processing before being input into the processor.

[0160] Referring to Figure 8, which is another structural schematic diagram of the communication device provided in an embodiment of this application, the communication device may be a first communication device or a second communication device, or a chip therein. Figure 8 only shows the main components of the communication device. In addition to the processor 1001, the communication device may further include a transceiver 1002, a memory 1003, and input / output devices (not shown in Figure 8).

[0161] The processor 1001 is mainly used to process communication protocols and communication data, control the entire communication device, execute software programs, and process the data of the software programs. The memory 1003 is mainly used to store software programs and data. The transceiver 1002 may include control circuitry and an antenna. The control circuitry is mainly used for converting baseband signals to radio frequency signals and processing radio frequency signals. The antenna is mainly used for transmitting and receiving radio frequency signals in the form of electromagnetic waves. Input / output devices, such as touchscreens, displays, and keyboards, are mainly used to receive user input data and output data to the user.

[0162] When the communication device is powered on, the processor 1001 can read the software program in the memory 1003, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1001 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1001. The processor 1001 converts the baseband signal into data and processes the data.

[0163] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0164] The processor 1001, transceiver 1002, and memory 1003 can be connected via a communication bus.

[0165] For example, when the communication device is used to perform the steps, methods, or functions performed by the first communication device in the method embodiment shown in FIG6, the processor 1001 may be used to perform steps S101 and S102 in FIG6, and / or to perform other processes of the technology described herein; the transceiver 1002 may be used to perform step S103 in FIG6, and / or to perform other processes of the technology described herein.

[0166] For example, when the communication device is used to perform the steps, methods, or functions performed by the second communication device in the method embodiment shown in FIG6, the processor 1001 may be used to perform step S104 in FIG6, and / or to perform other processes of the technology described herein; the transceiver 1002 may be used to receive codewords, and / or to perform other processes of the technology described herein.

[0167] In any of the above designs, the processor 1001 may include a transceiver for implementing receiving and transmitting functions. For example, the transceiver may be a transceiver circuit, an interface, or an interface circuit. The transceiver circuit, interface, or interface circuit for implementing receiving and transmitting functions may be separate or integrated. The aforementioned transceiver circuit, interface, or interface circuit may be used for reading and writing code / data, or it may be used for transmitting or relaying signals.

[0168] In any of the above designs, the processor 1001 may store instructions, which may be computer programs. These computer programs, running on the processor 1001, cause the communication device to perform the methods described in the above method embodiments. The computer program may be embedded in the processor 1001; in this case, the processor 1001 may be implemented in hardware.

[0169] In one implementation, the communication device may include circuitry that performs the functions of transmitting, receiving, or communicating as described in the foregoing method embodiments. The processor and transceiver described in this application can be implemented on integrated circuits (ICs), analog ICs, radio frequency integrated circuits (RFICs), mixed-signal ICs, application-specific integrated circuits (ASICs), printed circuit boards (PCBs), electronic devices, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductors (CMOS), n-metal-oxide-semiconductor (NMOS), positive channel metal oxide semiconductors (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0170] It is understood that the communication device shown in the embodiments of this application may have more components than those in FIG8, and the embodiments of this application do not limit this. The methods executed by the processor and transceiver shown above are only examples, and the specific steps executed by the processor and transceiver can be referred to the description of the method embodiments above.

[0171] In another possible implementation, in the communication device shown in FIG7, the processing module 20 can be one or more logic circuits, and the transceiver module 10 can be an input / output interface, or a communication interface, or an interface circuit, or an interface, etc. Alternatively, the transceiver module 10 can also be a sending module and a receiving module. The sending module can be an output interface, and the receiving module can be an input interface. The sending module and the receiving module are integrated into one module, such as an input / output interface. Referring to FIG9, FIG9 is another structural schematic diagram of the communication device provided in the embodiments of this application. As shown in FIG9, the communication device shown in FIG9 includes a logic circuit 901 and an interface 902. That is, the above-mentioned processing module 20 can be implemented by the logic circuit 901, and the transceiver module 10 can be implemented by the interface 902. Among them, the logic circuit 901 can be a chip, a processing circuit, an integrated circuit, or a system on chip (SoC) chip, etc., and the interface 902 can be a communication interface, an input / output interface, a pin, etc. For example, FIG9 shows the above-mentioned communication device as a chip, which includes a logic circuit 901 and an interface 902.

[0172] In this embodiment, the logic circuit and the interface can also be coupled to each other. The specific connection method between the logic circuit and the interface is not limited in this embodiment.

[0173] For example, when the communication device is used to execute the method or function or step executed by the first communication device in the aforementioned method embodiment, the logic circuit 901 is used to generate an information bit sequence; the logic circuit 901 is also used to encode the information bit sequence based on the LDPC code check matrix to obtain a codeword; the interface 902 is used to output the codeword.

[0174] For example, when the communication device is used to perform the method, function or step performed by the second communication device in the aforementioned method embodiment, the interface 902 is used to input a codeword; the logic circuit 901 is used to decode the codeword based on the LDPC code check matrix to obtain an information bit sequence.

[0175] In this application embodiment, the specific description of the LDPC code and its parity check matrix can be found in the method embodiment shown in Figure 6 above, and will not be described in detail here.

[0176] It is understood that the communication device shown in the embodiments of this application can implement the method provided in the embodiments of this application in hardware form or in software form, etc., and the embodiments of this application do not limit it in this way.

[0177] For specific implementations of the embodiment shown in Figure 9, please refer to the above embodiments, which will not be described in detail here.

[0178] This application also provides a communication system, which includes a first communication device and a second communication device, which can be used to execute the methods in the foregoing method embodiments.

[0179] In addition, this application also provides a computer program for implementing the operations and / or processes performed by the first communication device in the method provided in this application.

[0180] This application also provides a computer program for implementing the operations and / or processes performed by the second communication device in the method provided in this application.

[0181] This application also provides a computer-readable storage medium storing computer code that, when executed on a computer, causes the computer to perform the operations and / or processes performed by the first communication device in the method provided in this application.

[0182] This application also provides a computer-readable storage medium storing computer code that, when executed on a computer, causes the computer to perform the operations and / or processes performed by the second communication device in the method provided in this application.

[0183] This application also provides a computer program product, which includes computer code or a computer program that, when run on a computer, causes the operations and / or processes performed by the first communication device in the method provided in this application to be executed.

[0184] This application also provides a computer program product, which includes computer code or a computer program that, when run on a computer, causes the operations and / or processes performed by the second communication device in the method provided in this application to be executed.

[0185] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, or it may be an electrical, mechanical, or other form of connection.

[0186] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the technical effects of the solutions provided in the embodiments of this application.

[0187] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0188] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0189] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A communication method in a wireless local area network, characterized in that, include: Obtain the information bit sequence; The information bit sequence is encoded using the parity check matrix of a low-density parity-check (LDPC) code to obtain codewords. The LDPC code has a code length of 3888 bits, and the parity check matrix of the LDPC code is as shown in Tables 1a, 1b, and any of the matrices in Tables 2 to 5 of the embodiments. Send the codeword.

2. A communication method in a wireless local area network, characterized in that, include: Receive codewords; The codeword is decoded based on the parity check matrix of the low-density parity check (LDPC) code to obtain the information bit sequence; wherein the code length of the LDPC code is 3888 bits, and the parity check matrix of the LDPC code is as shown in Tables 1a, 1b, and any of the matrices described in Tables 2 to 5 of the embodiments.

3. The method according to claim 1 or 2, characterized in that, The code rate of the LDPC code is any of the following values: or 4. The method according to any one of claims 1 to 3, characterized in that, The code rate of the LDPC code is The size of the parent matrix corresponding to the parity check matrix of the LDPC code is 4×24. Each element in the parent matrix represents a z×z square matrix, where z equals 162.

5. The method of claim 4, wherein, The parent matrix corresponding to the parity check matrix of the LDPC code is:

6. The method according to any one of claims 1 to 3, characterized in that, The code rate of the LDPC code is The size of the parent matrix corresponding to the parity check matrix of the LDPC code is 8×48. Each element in the parent matrix represents a z×z square matrix, where z equals 81.

7. The method according to claim 6, characterized in that, The parity check matrix of the LDPC code is a 2×2 square matrix. Each element block in the parent matrix is ​​obtained by diagonally expanding each element in the parent matrix corresponding to the initial parity check matrix. The initial parity check matrix is ​​a parity check matrix of an LDPC code with a code length of 1944 bits.

8. The method according to claim 7, characterized in that, The position of element 1 in the parity-check matrix of the LDPC code is indicated by a concatenation index, which is: Wherein, the (i+1)th row of the connection index represents the column index of element 1 in the (i×z)th row of the LDPC code check matrix, and the value of i is 0, 1, 2, 3, 4, 5, 6, 7; The column index of element 1 in the ((i×z)+j)th row of the LDPC code's parity-check matrix is ​​equal to ((81×X+Y+j)mod 81), where Y is the column index of element 1 in the (i×z)th row of the LDPC code's parity-check matrix. The value of j is 1, 2, 3, 4, ..., (z-1).

9. The method according to claim 6, characterized in that, The position of element 1 in the parity-check matrix of the LDPC code is indicated by a concatenation index, which is: Wherein, the (i+1)th row of the link index represents the column index of element 1 in the (i×z)th row of the LDPC code's parity-check matrix, where i takes values ​​of 0, 1, 2, 3, 4, 5, 6, 7; the column index of element 1 in the ((i×z)+j)th row of the LDPC code's parity-check matrix is ​​equal to ((81×X+Y+j)mod 81), where Y is the column index of element 1 in the (i×z)th row of the LDPC code's parity-check matrix. The value of j is 1, 2, 3, 4, ..., (z-1).

10. The method according to any one of claims 1 to 3, characterized in that, The code rate of the LDPC code is The size of the parent matrix corresponding to the parity check matrix of the LDPC code is 12×48. Each element in the parent matrix represents a z×z square matrix, where z equals 81.

11. The method according to claim 10, characterized in that, The position of element 1 in the parity-check matrix of the LDPC code is indicated by a concatenation index, which is: Wherein, the (i+1)th row of the connection index represents the column index of element 1 in the (i×z)th row of the LDPC code's parity-check matrix, where i takes values ​​of 0, 1, 2, 3, ..., 11; the column index of element 1 in the ((i×z)+j)th row of the LDPC code's parity-check matrix is ​​equal to ((81×X+Y+j)mod 81), where Y is the column index of element 1 in the (i×z)th row of the LDPC code's parity-check matrix. The value of j is 1, 2, 3, 4, ..., (z-1).

12. The method according to any one of claims 1 to 3, characterized in that, The code rate of the LDPC code is The size of the parent matrix corresponding to the parity check matrix of the LDPC code is 16×48. Each element in the parent matrix represents a z×z square matrix, where z equals 81.

13. The method according to claim 12, characterized in that, The position of element 1 in the parity-check matrix of the LDPC code is indicated by a concatenation index, which is: Wherein, the (i+1)th row of the connection index represents the column index of element 1 in the (i×z)th row of the LDPC code's parity-check matrix, where i takes values ​​of 0, 1, 2, 3, ..., 15; the column index of element 1 in the ((i×z)+j)th row of the LDPC code's parity-check matrix is ​​equal to ((81×X+Y+j)mod 81), where Y is the column index of element 1 in the (i×z)th row of the LDPC code's parity-check matrix. The value of j is 1, 2, 3, 4, ..., (z-1).

14. A communication device, characterized in that, Includes modules for performing the method according to any one of claims 1 to 13.

15. A communication device, characterized in that, include: One or more processors, said one or more processors being coupled to one or more memories; The one or more memories are used to store computer programs, and the one or more processors are used to execute the computer programs stored in the one or more memories, so that the communication device performs the method as described in any one of claims 1 to 13.

16. A communication device, characterized in that, Includes logic circuits and interfaces, wherein the logic circuits and interfaces are coupled; The interface is used for inputting and / or outputting information, and the logic circuit is used to cause the communication device to perform the method as described in any one of claims 1 to 13.

17. A readable storage medium, characterized in that, The device is used to store a program, which is executed by one or more processors, such that a device including the one or more processors performs the method as described in any one of claims 1 to 13.

18. A computer program product, characterized in that, When the computer program product is executed, it causes the apparatus containing the computer program product to perform the method as described in any one of claims 1 to 13.

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